MLK-14938-9 imx8: bootaux: Add i.MX8 M4 boot support

1. Implement bootaux for the M4 boot on i.MX8QM and QXP. Users need to download M4 image to any DDR address first. Then use the "bootaux <M4 download DDR address> [M4 core id]" to boot CM4_0 or CM4_1, the default core id is 0 for CM4_0. Since current M4 only supports running in TCM. The bootaux will copy the M4 image from DDR to its TCML. 2. Implment bootaux for HIFI on QXP command: bootaux 0x81000000 1 Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 778606204b84ce6646fe58d752e2abda67600cf2) (cherry picked from commit e4a3fcc6fd357502d61687659b9cd7d2808b3fd4)

MLK-14938-9 imx8: bootaux: Add i.MX8 M4 boot support
1. Implement bootaux for the M4 boot on i.MX8QM and QXP. Users need to download M4 image to any DDR address first. Then use the "bootaux <M4 download DDR address> [M4 core id]" to boot CM4_0 or CM4_1, the default core id is 0 for CM4_0. Since current M4 only supports running in TCM. The bootaux will copy the M4 image from DDR to its TCML. 2. Implment bootaux for HIFI on QXP command: bootaux 0x81000000 1 Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 778606204b84ce6646fe58d752e2abda67600cf2) (cherry picked from commit e4a3fcc6fd357502d61687659b9cd7d2808b3fd4)
Ye Li · Eric Lee
1 parent 1ac777e595
Showing 5 changed files with 245 additions and 6 deletions Side-by-side Diff
arch/arm/include/asm/mach-imx/sys_proto.h
arch/arm/mach-imx/Kconfig
arch/arm/mach-imx/Makefile
arch/arm/mach-imx/imx8/cpu.c
arch/arm/mach-imx/imx_bootaux.c
@@ -182,6 +182,9 @@
 int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
 int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
  
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data);
+int arch_auxiliary_core_check_up(u32 core_id);
+
 unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
 			   unsigned long reg1, unsigned long reg2,
 			   unsigned long reg3);
@@ -23,7 +23,7 @@
  
 config IMX_BOOTAUX
 	bool "Support boot auxiliary core"
-	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610
+	depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8
 	help
 	  bootaux [addr] to boot auxiliary core.
  
@@ -58,6 +58,11 @@
 obj-y += ddrmc-vf610.o
 obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o
 endif
+ifeq ($(SOC),$(filter $(SOC),imx8))
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
+endif
+endif
 ifneq ($(CONFIG_SPL_BUILD),y)
 obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
 obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
@@ -15,6 +15,8 @@
 #include <errno.h>
 #include <thermal.h>
 #include <asm/arch/sci/sci.h>
+#include <power-domain.h>
+#include <elf.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch-imx/cpu.h>
 #include <asm/armv8/cpu.h>
@@ -78,6 +80,228 @@
  
 	return 0;
 }
+
+#ifdef CONFIG_IMX_BOOTAUX
+
+#ifdef CONFIG_IMX8QM
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
+{
+	sc_rsrc_t core_rsrc, mu_rsrc;
+	sc_faddr_t tcml_addr;
+	u32 tcml_size = SZ_128K;
+	ulong addr;
+
+
+	switch (core_id) {
+	case 0:
+		core_rsrc = SC_R_M4_0_PID0;
+		tcml_addr = 0x34FE0000;
+		mu_rsrc = SC_R_M4_0_MU_1A;
+		break;
+	case 1:
+		core_rsrc = SC_R_M4_1_PID0;
+		tcml_addr = 0x38FE0000;
+		mu_rsrc = SC_R_M4_1_MU_1A;
+		break;
+	default:
+		printf("Not support this core boot up, ID:%u\n", core_id);
+		return -EINVAL;
+	}
+
+	addr = (sc_faddr_t)boot_private_data;
+
+	if (addr >= tcml_addr && addr <= tcml_addr + tcml_size) {
+		printf("Wrong image address 0x%lx, should not in TCML\n",
+			addr);
+		return -EINVAL;
+	}
+
+	printf("Power on M4 and MU\n");
+
+	if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+		return -EIO;
+
+	if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+		return -EIO;
+
+	printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr);
+
+	if (addr != tcml_addr)
+		memcpy((void *)tcml_addr, (void *)addr, tcml_size);
+
+	printf("Start M4 %u\n", core_id);
+	if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE)
+		return -EIO;
+
+	printf("bootaux complete\n");
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_IMX8QXP
+static unsigned long load_elf_image_shdr(unsigned long addr)
+{
+	Elf32_Ehdr *ehdr; /* Elf header structure pointer */
+	Elf32_Shdr *shdr; /* Section header structure pointer */
+	unsigned char *strtab = 0; /* String table pointer */
+	unsigned char *image; /* Binary image pointer */
+	int i; /* Loop counter */
+
+	ehdr = (Elf32_Ehdr *)addr;
+
+	/* Find the section header string table for output info */
+	shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
+			     (ehdr->e_shstrndx * sizeof(Elf32_Shdr)));
+
+	if (shdr->sh_type == SHT_STRTAB)
+		strtab = (unsigned char *)(addr + shdr->sh_offset);
+
+	/* Load each appropriate section */
+	for (i = 0; i < ehdr->e_shnum; ++i) {
+		shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
+				     (i * sizeof(Elf32_Shdr)));
+
+		if (!(shdr->sh_flags & SHF_ALLOC) ||
+		    shdr->sh_addr == 0 || shdr->sh_size == 0) {
+			continue;
+		}
+
+		if (strtab) {
+			debug("%sing %s @ 0x%08lx (%ld bytes)\n",
+			      (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load",
+			       &strtab[shdr->sh_name],
+			       (unsigned long)shdr->sh_addr,
+			       (long)shdr->sh_size);
+		}
+
+		if (shdr->sh_type == SHT_NOBITS) {
+			memset((void *)(uintptr_t)shdr->sh_addr, 0,
+			       shdr->sh_size);
+		} else {
+			image = (unsigned char *)addr + shdr->sh_offset;
+			memcpy((void *)(uintptr_t)shdr->sh_addr,
+			       (const void *)image, shdr->sh_size);
+		}
+		flush_cache(shdr->sh_addr, shdr->sh_size);
+	}
+
+	return ehdr->e_entry;
+}
+
+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
+{
+	sc_rsrc_t core_rsrc, mu_rsrc = -1;
+	sc_faddr_t aux_core_ram;
+	u32 size;
+	ulong addr;
+
+	switch (core_id) {
+	case 0:
+		core_rsrc = SC_R_M4_0_PID0;
+		aux_core_ram = 0x34FE0000;
+		mu_rsrc = SC_R_M4_0_MU_1A;
+		size = SZ_128K;
+		break;
+	case 1:
+		core_rsrc = SC_R_DSP;
+		aux_core_ram = 0x596f8000;
+		size = SZ_2K;
+		break;
+	default:
+		printf("Not support this core boot up, ID:%u\n", core_id);
+		return -EINVAL;
+	}
+
+	addr = (sc_faddr_t)boot_private_data;
+
+	if (addr >= aux_core_ram && addr <= aux_core_ram + size) {
+		printf("Wrong image address 0x%lx, should not in aux core ram\n",
+			addr);
+		return -EINVAL;
+	}
+
+	printf("Power on aux core %d\n", core_id);
+
+	if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+		return -EIO;
+
+	if (mu_rsrc != -1) {
+		if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
+			return -EIO;
+	}
+
+	if (core_id == 1) {
+		struct power_domain pd;
+
+		if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) {
+			printf("Error enable clock\n");
+			return -EIO;
+		}
+
+		if (!power_domain_lookup_name("audio_sai0", &pd)) {
+			if (power_domain_on(&pd)) {
+				printf("Error power on SAI0\n");
+				return -EIO;
+			}
+		}
+
+		if (!power_domain_lookup_name("audio_ocram", &pd)) {
+			if (power_domain_on(&pd)) {
+				printf("Error power on HIFI RAM\n");
+				return -EIO;
+			}
+		}
+	}
+
+	printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram);
+	if (core_id == 0) {
+		/* M4 use bin file */
+		memcpy((void *)aux_core_ram, (void *)addr, size);
+	} else {
+		/* HIFI use elf file */
+		if (!valid_elf_image(addr))
+			return -1;
+		addr = load_elf_image_shdr(addr);
+	}
+
+	printf("Start %s\n", core_id == 0 ? "M4" : "HIFI");
+
+	if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE)
+		return -EIO;
+
+	printf("bootaux complete\n");
+	return 0;
+}
+#endif
+
+int arch_auxiliary_core_check_up(u32 core_id)
+{
+	sc_rsrc_t core_rsrc;
+	sc_pm_power_mode_t power_mode;
+
+	switch (core_id) {
+	case 0:
+		core_rsrc = SC_R_M4_0_PID0;
+		break;
+#ifdef CONFIG_IMX8QM
+	case 1:
+		core_rsrc = SC_R_M4_1_PID0;
+		break;
+#endif
+	default:
+		printf("Not support this core, ID:%u\n", core_id);
+		return 0;
+	}
+
+	if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE)
+		return 0;
+
+	if (power_mode != SC_PM_PW_MODE_OFF)
+		return 1;
+
+	return 0;
+}
+#endif
  
 int print_bootinfo(void)
 {
@@ -12,7 +12,7 @@
 #include <linux/compiler.h>
 #include <cpu_func.h>
  
-#ifndef CONFIG_IMX8M
+#if !defined(CONFIG_IMX8M) && !defined(CONFIG_IMX8)
 const __weak struct rproc_att hostmap[] = { };
  
 static const struct rproc_att *get_host_mapping(unsigned long auxcore)
@@ -76,6 +76,7 @@
 }
 #endif
  
+#ifndef CONFIG_IMX8
 int arch_auxiliary_core_up(u32 core_id, ulong addr)
 {
 	ulong stack, pc;
@@ -142,7 +143,7 @@
 	return 1;
 #endif
 }
-
+#endif
 /*
  * To i.MX6SX and i.MX7D, the image supported by bootaux needs
  * the reset vector at the head for the image, with SP and PC
  
@@ -160,11 +161,15 @@
 {
 	ulong addr;
 	int ret, up;
+	u32 core = 0;
  
 	if (argc < 2)
 		return CMD_RET_USAGE;
  
-	up = arch_auxiliary_core_check_up(0);
+	if (argc > 2)
+		core = simple_strtoul(argv[2], NULL, 10);
+
+	up = arch_auxiliary_core_check_up(core);
 	if (up) {
 		printf("## Auxiliary core is already up\n");
 		return CMD_RET_SUCCESS;
@@ -175,7 +180,7 @@
 	if (!addr)
 		return CMD_RET_FAILURE;
  
-	ret = arch_auxiliary_core_up(0, addr);
+	ret = arch_auxiliary_core_up(core, addr);
 	if (ret)
 		return CMD_RET_FAILURE;
  
@@ -185,6 +190,8 @@
 U_BOOT_CMD(
 	bootaux, CONFIG_SYS_MAXARGS, 1,	do_bootaux,
 	"Start auxiliary core",
-	""
+	"<address> [<core>]\n"
+	"   - start auxiliary core [<core>] (default 0),\n"
+	"     at address <address>\n"
 );
...	...	@@ -182,6 +182,9 @@
182	182	int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
183	183	int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
184	184
	185	+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data);
	186	+int arch_auxiliary_core_check_up(u32 core_id);
	187	+
185	188	unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
186	189	unsigned long reg1, unsigned long reg2,
187	190	unsigned long reg3);
...	...	@@ -23,7 +23,7 @@
23	23
24	24	config IMX_BOOTAUX
25	25	bool "Support boot auxiliary core"
26		- depends on ARCH_MX7 \|\| ARCH_MX6 \|\| ARCH_VF610
	26	+ depends on ARCH_MX7 \|\| ARCH_MX6 \|\| ARCH_VF610 \|\| ARCH_IMX8
27	27	help
28	28	bootaux [addr] to boot auxiliary core.
29	29
...	...	@@ -58,6 +58,11 @@
58	58	obj-y += ddrmc-vf610.o
59	59	obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o
60	60	endif
	61	+ifeq ($(SOC),$(filter $(SOC),imx8))
	62	+ifneq ($(CONFIG_SPL_BUILD),y)
	63	+obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o
	64	+endif
	65	+endif
61	66	ifneq ($(CONFIG_SPL_BUILD),y)
62	67	obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
63	68	obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
...	...	@@ -15,6 +15,8 @@
15	15	#include <errno.h>
16	16	#include <thermal.h>
17	17	#include <asm/arch/sci/sci.h>
	18	+#include <power-domain.h>
	19	+#include <elf.h>
18	20	#include <asm/arch/sys_proto.h>
19	21	#include <asm/arch-imx/cpu.h>
20	22	#include <asm/armv8/cpu.h>
...	...	@@ -78,6 +80,228 @@
78	80
79	81	return 0;
80	82	}
	83	+
	84	+#ifdef CONFIG_IMX_BOOTAUX
	85	+
	86	+#ifdef CONFIG_IMX8QM
	87	+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
	88	+{
	89	+ sc_rsrc_t core_rsrc, mu_rsrc;
	90	+ sc_faddr_t tcml_addr;
	91	+ u32 tcml_size = SZ_128K;
	92	+ ulong addr;
	93	+
	94	+
	95	+ switch (core_id) {
	96	+ case 0:
	97	+ core_rsrc = SC_R_M4_0_PID0;
	98	+ tcml_addr = 0x34FE0000;
	99	+ mu_rsrc = SC_R_M4_0_MU_1A;
	100	+ break;
	101	+ case 1:
	102	+ core_rsrc = SC_R_M4_1_PID0;
	103	+ tcml_addr = 0x38FE0000;
	104	+ mu_rsrc = SC_R_M4_1_MU_1A;
	105	+ break;
	106	+ default:
	107	+ printf("Not support this core boot up, ID:%u\n", core_id);
	108	+ return -EINVAL;
	109	+ }
	110	+
	111	+ addr = (sc_faddr_t)boot_private_data;
	112	+
	113	+ if (addr >= tcml_addr && addr <= tcml_addr + tcml_size) {
	114	+ printf("Wrong image address 0x%lx, should not in TCML\n",
	115	+ addr);
	116	+ return -EINVAL;
	117	+ }
	118	+
	119	+ printf("Power on M4 and MU\n");
	120	+
	121	+ if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
	122	+ return -EIO;
	123	+
	124	+ if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
	125	+ return -EIO;
	126	+
	127	+ printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr);
	128	+
	129	+ if (addr != tcml_addr)
	130	+ memcpy((void )tcml_addr, (void )addr, tcml_size);
	131	+
	132	+ printf("Start M4 %u\n", core_id);
	133	+ if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE)
	134	+ return -EIO;
	135	+
	136	+ printf("bootaux complete\n");
	137	+ return 0;
	138	+}
	139	+#endif
	140	+
	141	+#ifdef CONFIG_IMX8QXP
	142	+static unsigned long load_elf_image_shdr(unsigned long addr)
	143	+{
	144	+ Elf32_Ehdr ehdr; / Elf header structure pointer */
	145	+ Elf32_Shdr shdr; / Section header structure pointer */
	146	+ unsigned char strtab = 0; / String table pointer */
	147	+ unsigned char image; / Binary image pointer */
	148	+ int i; /* Loop counter */
	149	+
	150	+ ehdr = (Elf32_Ehdr *)addr;
	151	+
	152	+ /* Find the section header string table for output info */
	153	+ shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
	154	+ (ehdr->e_shstrndx * sizeof(Elf32_Shdr)));
	155	+
	156	+ if (shdr->sh_type == SHT_STRTAB)
	157	+ strtab = (unsigned char *)(addr + shdr->sh_offset);
	158	+
	159	+ /* Load each appropriate section */
	160	+ for (i = 0; i < ehdr->e_shnum; ++i) {
	161	+ shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
	162	+ (i * sizeof(Elf32_Shdr)));
	163	+
	164	+ if (!(shdr->sh_flags & SHF_ALLOC) \|\|
	165	+ shdr->sh_addr == 0 \|\| shdr->sh_size == 0) {
	166	+ continue;
	167	+ }
	168	+
	169	+ if (strtab) {
	170	+ debug("%sing %s @ 0x%08lx (%ld bytes)\n",
	171	+ (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load",
	172	+ &strtab[shdr->sh_name],
	173	+ (unsigned long)shdr->sh_addr,
	174	+ (long)shdr->sh_size);
	175	+ }
	176	+
	177	+ if (shdr->sh_type == SHT_NOBITS) {
	178	+ memset((void *)(uintptr_t)shdr->sh_addr, 0,
	179	+ shdr->sh_size);
	180	+ } else {
	181	+ image = (unsigned char *)addr + shdr->sh_offset;
	182	+ memcpy((void *)(uintptr_t)shdr->sh_addr,
	183	+ (const void *)image, shdr->sh_size);
	184	+ }
	185	+ flush_cache(shdr->sh_addr, shdr->sh_size);
	186	+ }
	187	+
	188	+ return ehdr->e_entry;
	189	+}
	190	+
	191	+int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data)
	192	+{
	193	+ sc_rsrc_t core_rsrc, mu_rsrc = -1;
	194	+ sc_faddr_t aux_core_ram;
	195	+ u32 size;
	196	+ ulong addr;
	197	+
	198	+ switch (core_id) {
	199	+ case 0:
	200	+ core_rsrc = SC_R_M4_0_PID0;
	201	+ aux_core_ram = 0x34FE0000;
	202	+ mu_rsrc = SC_R_M4_0_MU_1A;
	203	+ size = SZ_128K;
	204	+ break;
	205	+ case 1:
	206	+ core_rsrc = SC_R_DSP;
	207	+ aux_core_ram = 0x596f8000;
	208	+ size = SZ_2K;
	209	+ break;
	210	+ default:
	211	+ printf("Not support this core boot up, ID:%u\n", core_id);
	212	+ return -EINVAL;
	213	+ }
	214	+
	215	+ addr = (sc_faddr_t)boot_private_data;
	216	+
	217	+ if (addr >= aux_core_ram && addr <= aux_core_ram + size) {
	218	+ printf("Wrong image address 0x%lx, should not in aux core ram\n",
	219	+ addr);
	220	+ return -EINVAL;
	221	+ }
	222	+
	223	+ printf("Power on aux core %d\n", core_id);
	224	+
	225	+ if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
	226	+ return -EIO;
	227	+
	228	+ if (mu_rsrc != -1) {
	229	+ if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE)
	230	+ return -EIO;
	231	+ }
	232	+
	233	+ if (core_id == 1) {
	234	+ struct power_domain pd;
	235	+
	236	+ if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) {
	237	+ printf("Error enable clock\n");
	238	+ return -EIO;
	239	+ }
	240	+
	241	+ if (!power_domain_lookup_name("audio_sai0", &pd)) {
	242	+ if (power_domain_on(&pd)) {
	243	+ printf("Error power on SAI0\n");
	244	+ return -EIO;
	245	+ }
	246	+ }
	247	+
	248	+ if (!power_domain_lookup_name("audio_ocram", &pd)) {
	249	+ if (power_domain_on(&pd)) {
	250	+ printf("Error power on HIFI RAM\n");
	251	+ return -EIO;
	252	+ }
	253	+ }
	254	+ }
	255	+
	256	+ printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram);
	257	+ if (core_id == 0) {
	258	+ /* M4 use bin file */
	259	+ memcpy((void )aux_core_ram, (void )addr, size);
	260	+ } else {
	261	+ /* HIFI use elf file */
	262	+ if (!valid_elf_image(addr))
	263	+ return -1;
	264	+ addr = load_elf_image_shdr(addr);
	265	+ }
	266	+
	267	+ printf("Start %s\n", core_id == 0 ? "M4" : "HIFI");
	268	+
	269	+ if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE)
	270	+ return -EIO;
	271	+
	272	+ printf("bootaux complete\n");
	273	+ return 0;
	274	+}
	275	+#endif
	276	+
	277	+int arch_auxiliary_core_check_up(u32 core_id)
	278	+{
	279	+ sc_rsrc_t core_rsrc;
	280	+ sc_pm_power_mode_t power_mode;
	281	+
	282	+ switch (core_id) {
	283	+ case 0:
	284	+ core_rsrc = SC_R_M4_0_PID0;
	285	+ break;
	286	+#ifdef CONFIG_IMX8QM
	287	+ case 1:
	288	+ core_rsrc = SC_R_M4_1_PID0;
	289	+ break;
	290	+#endif
	291	+ default:
	292	+ printf("Not support this core, ID:%u\n", core_id);
	293	+ return 0;
	294	+ }
	295	+
	296	+ if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE)
	297	+ return 0;
	298	+
	299	+ if (power_mode != SC_PM_PW_MODE_OFF)
	300	+ return 1;
	301	+
	302	+ return 0;
	303	+}
	304	+#endif
81	305
82	306	int print_bootinfo(void)
83	307	{
...	...	@@ -12,7 +12,7 @@
12	12	#include <linux/compiler.h>
13	13	#include <cpu_func.h>
14	14
15		-#ifndef CONFIG_IMX8M
	15	+#if !defined(CONFIG_IMX8M) && !defined(CONFIG_IMX8)
16	16	const __weak struct rproc_att hostmap[] = { };
17	17
18	18	static const struct rproc_att *get_host_mapping(unsigned long auxcore)
...	...	@@ -76,6 +76,7 @@
76	76	}
77	77	#endif
78	78
	79	+#ifndef CONFIG_IMX8
79	80	int arch_auxiliary_core_up(u32 core_id, ulong addr)
80	81	{
81	82	ulong stack, pc;
...	...	@@ -142,7 +143,7 @@
142	143	return 1;
143	144	#endif
144	145	}
145		-
	146	+#endif
146	147	/*
147	148	* To i.MX6SX and i.MX7D, the image supported by bootaux needs
148	149	* the reset vector at the head for the image, with SP and PC
149	150
...	...	@@ -160,11 +161,15 @@
160	161	{
161	162	ulong addr;
162	163	int ret, up;
	164	+ u32 core = 0;
163	165
164	166	if (argc < 2)
165	167	return CMD_RET_USAGE;
166	168
167		- up = arch_auxiliary_core_check_up(0);
	169	+ if (argc > 2)
	170	+ core = simple_strtoul(argv[2], NULL, 10);
	171	+
	172	+ up = arch_auxiliary_core_check_up(core);
168	173	if (up) {
169	174	printf("## Auxiliary core is already up\n");
170	175	return CMD_RET_SUCCESS;
...	...	@@ -175,7 +180,7 @@
175	180	if (!addr)
176	181	return CMD_RET_FAILURE;
177	182
178		- ret = arch_auxiliary_core_up(0, addr);
	183	+ ret = arch_auxiliary_core_up(core, addr);
179	184	if (ret)
180	185	return CMD_RET_FAILURE;
181	186
...	...	@@ -185,6 +190,8 @@
185	190	U_BOOT_CMD(
186	191	bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux,
187	192	"Start auxiliary core",
188		- ""
	193	+ "<address> [<core>]\n"
	194	+ " - start auxiliary core [<core>] (default 0),\n"
	195	+ " at address <address>\n"
189	196	);