Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 1626308797ac4184e73e56d275a1b8da11a62d5b

Authored by Mike Williams
Committed by Wolfgang Denk
1 parent 2469c4b2db
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

cleanup: Fix typos and misspellings in various files. 

Recieve/Receive
recieve/receive
Interupt/Interrupt
interupt/interrupt
Addres/Address
addres/address

Signed-off-by: Mike Williams <mike@mikebwilliams.com>

Showing 48 changed files with 57 additions and 57 deletions Side-by-side Diff

arch/arm/cpu/arm720t/lpc2292/mmc_hw.c
Diff comments   View file @ 1626308
... ... @@ -148,7 +148,7 @@
148 148 /* Command 16 to read aBlocks from the MMC/SD - caed */
149 149 unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF};
150 150  
151   - /* The addres on the MMC/SD-card is in bytes,
  151 + /* The address on the MMC/SD-card is in bytes,
152 152 addr is transformed from blocks to bytes and the result is
153 153 placed into the command */
154 154  
... ... @@ -173,7 +173,7 @@
173 173 /* Command 24 to write a block to the MMC/SD - card */
174 174 unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF};
175 175  
176   - /* The addres on the MMC/SD-card is in bytes,
  176 + /* The address on the MMC/SD-card is in bytes,
177 177 addr is transformed from blocks to bytes and the result is
178 178 placed into the command */
179 179  
arch/arm/cpu/arm720t/start.S
Diff comments   View file @ 1626308
... ... @@ -274,7 +274,7 @@
274 274  
275 275 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
276 276  
277   -/* Interupt-Controller base addresses */
  277 +/* Interrupt-Controller base addresses */
278 278 INTMR1: .word 0x80000280 @ 32 bit size
279 279 INTMR2: .word 0x80001280 @ 16 bit size
280 280 INTMR3: .word 0x80002280 @ 8 bit size
arch/arm/cpu/arm920t/at91/timer.c
Diff comments   View file @ 1626308
... ... @@ -59,7 +59,7 @@
59 59 when the value in TC_RC is reached */
60 60 writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr);
61 61  
62   - writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interupts */
  62 + writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */
63 63 writel(TIMER_LOAD_VAL, &tc->tc[0].rc);
64 64  
65 65 writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr);
arch/arm/cpu/arm920t/start.S
Diff comments   View file @ 1626308
... ... @@ -142,11 +142,11 @@
142 142  
143 143 # if defined(CONFIG_S3C2400)
144 144 # define pWTCON 0x15300000
145   -# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
  145 +# define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
146 146 # define CLKDIVN 0x14800014 /* clock divisor register */
147 147 #else
148 148 # define pWTCON 0x53000000
149   -# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
  149 +# define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
150 150 # define INTSUBMSK 0x4A00001C
151 151 # define CLKDIVN 0x4C000014 /* clock divisor register */
152 152 # endif
arch/arm/cpu/ixp/npe/IxQMgrDispatcher.c
Diff comments   View file @ 1626308
... ... @@ -386,7 +386,7 @@
386 386 &dispatchQInfo[qId].statusMask);
387 387  
388 388  
389   - /* Set the interupt source is this queue is in the range 0-31 */
  389 + /* Set the interrupt source is this queue is in the range 0-31 */
390 390 if (qId < IX_QMGR_MIN_QUEUPP_QID)
391 391 {
392 392 ixQMgrAqmIfIntSrcSelWrite (qId, srcSel);
arch/arm/cpu/ixp/npe/include/IxEthAcc_p.h
Diff comments   View file @ 1626308
... ... @@ -279,7 +279,7 @@
279 279 BOOL portInitialized;
280 280 UINT32 npeId; /**< NpeId for this port */
281 281 IxEthAccTxDataInfo ixEthAccTxData; /**< Transmit data control structures */
282   - IxEthAccRxDataInfo ixEthAccRxData; /**< Recieve data control structures */
  282 + IxEthAccRxDataInfo ixEthAccRxData; /**< Receive data control structures */
283 283 } IxEthAccPortDataInfo;
284 284  
285 285 extern IxEthAccPortDataInfo ixEthAccPortData[];
arch/arm/cpu/ixp/npe/include/IxNpeA.h
Diff comments   View file @ 1626308
... ... @@ -717,7 +717,7 @@
717 717 */
718 718 typedef struct
719 719 {
720   - UINT32 rxBitField; /**< Recieved bit field */
  720 + UINT32 rxBitField; /**< Received bit field */
721 721 UINT32 atmCellHeader; /**< ATM Cell Header */
722 722 UINT32 rsvdWord0; /**< Reserved field */
723 723 UINT16 currMbufLen; /**< Mbuf Length */
arch/arm/cpu/ixp/npe/include/IxQMgr.h
Diff comments   View file @ 1626308
... ... @@ -570,7 +570,7 @@
570 570 * @brief Queue interrupt source select.
571 571 *
572 572 * This enum defines the different source conditions on a queue that result in
573   - * an interupt being fired by the AQM. Interrupt source is configurable for
  573 + * an interrupt being fired by the AQM. Interrupt source is configurable for
574 574 * queues 0-31 only. The interrupt source for queues 32-63 is hardwired to the
575 575 * NE(Nearly Empty) status flag.
576 576 *
arch/arm/cpu/ixp/npe/include/IxQueueAssignments.h
Diff comments   View file @ 1626308
... ... @@ -404,7 +404,7 @@
404 404 *
405 405 * @def IX_ETH_ACC_RX_FRAME_ETH_Q
406 406 *
407   -* @brief Eth0/Eth1 NPE Frame Recieve Q.
  407 +* @brief Eth0/Eth1 NPE Frame Receive Q.
408 408 *
409 409 * @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
410 410 *
arch/arm/cpu/lh7a40x/start.S
Diff comments   View file @ 1626308
... ... @@ -124,7 +124,7 @@
124 124 msr cpsr,r0
125 125  
126 126 #define pWDTCTL 0x80001400 /* Watchdog Timer control register */
127   -#define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
  127 +#define pINTENC 0x8000050C /* Interrupt-Controller enable clear register */
128 128 #define pCLKSET 0x80000420 /* clock divisor register */
129 129  
130 130 /* disable watchdog, set watchdog control register to
arch/arm/cpu/sa1100/start.S
Diff comments   View file @ 1626308
... ... @@ -263,7 +263,7 @@
263 263 */
264 264  
265 265  
266   -/* Interupt-Controller base address */
  266 +/* Interrupt-Controller base address */
267 267 IC_BASE: .word 0x90050000
268 268 #define ICMR 0x04
269 269  
arch/m68k/include/asm/fec.h
Diff comments   View file @ 1626308
... ... @@ -39,7 +39,7 @@
39 39 uint cbd_bufaddr; /* Buffer address in host memory */
40 40 } cbd_t;
41 41  
42   -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
  42 +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
43 43 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
44 44 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
45 45 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
arch/powerpc/include/asm/cpm_8260.h
Diff comments   View file @ 1626308
... ... @@ -117,7 +117,7 @@
117 117 uint cbd_bufaddr; /* Buffer address in host memory */
118 118 } cbd_t;
119 119  
120   -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
  120 +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
121 121 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
122 122 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
123 123 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
arch/powerpc/include/asm/cpm_85xx.h
Diff comments   View file @ 1626308
... ... @@ -110,7 +110,7 @@
110 110 uint cbd_bufaddr; /* Buffer address in host memory */
111 111 } cbd_t;
112 112  
113   -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
  113 +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
114 114 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
115 115 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
116 116 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
arch/powerpc/include/asm/ppc440ep_gr.h
Diff comments   View file @ 1626308
... ... @@ -182,7 +182,7 @@
182 182 #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
183 183  
184 184 #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
185   -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
  185 +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
186 186 #define PRADV_MASK 0x07000000 /* Primary Divisor A */
187 187 #define PRBDV_MASK 0x07000000 /* Primary Divisor B */
188 188 #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
... ... @@ -192,7 +192,7 @@
192 192 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
193 193 #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
194 194 #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
195   -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
  195 +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
196 196 #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
197 197 #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
198 198 #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
arch/powerpc/include/asm/ppc440epx_grx.h
Diff comments   View file @ 1626308
... ... @@ -398,7 +398,7 @@
398 398 #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
399 399  
400 400 #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
401   -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
  401 +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
402 402 #define PRADV_MASK 0x07000000 /* Primary Divisor A */
403 403 #define PRBDV_MASK 0x07000000 /* Primary Divisor B */
404 404 #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
... ... @@ -408,7 +408,7 @@
408 408 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
409 409 #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
410 410 #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
411   -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
  411 +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
412 412 #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
413 413 #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
414 414 #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
arch/powerpc/include/asm/ppc440gx.h
Diff comments   View file @ 1626308
... ... @@ -71,7 +71,7 @@
71 71 #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
72 72  
73 73 #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
74   -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
  74 +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
75 75 #define PRADV_MASK 0x07000000 /* Primary Divisor A */
76 76 #define PRBDV_MASK 0x07000000 /* Primary Divisor B */
77 77 #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
... ... @@ -81,7 +81,7 @@
81 81 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
82 82 #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
83 83 #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
84   -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
  84 +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
85 85 #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
86 86 #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
87 87 #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
arch/powerpc/include/asm/ppc440sp.h
Diff comments   View file @ 1626308
... ... @@ -67,7 +67,7 @@
67 67 #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
68 68  
69 69 #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
70   -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
  70 +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
71 71 #define PRADV_MASK 0x07000000 /* Primary Divisor A */
72 72 #define PRBDV_MASK 0x07000000 /* Primary Divisor B */
73 73 #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
... ... @@ -77,7 +77,7 @@
77 77 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
78 78 #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
79 79 #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
80   -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
  80 +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
81 81 #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
82 82 #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
83 83 #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
arch/powerpc/include/asm/ppc440spe.h
Diff comments   View file @ 1626308
... ... @@ -83,7 +83,7 @@
83 83 #define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */
84 84  
85 85 #define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */
86   -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */
  86 +#define PERDV_MASK 0x07000000 /* Peripheral Clock Divisor */
87 87 #define PRADV_MASK 0x07000000 /* Primary Divisor A */
88 88 #define PRBDV_MASK 0x07000000 /* Primary Divisor B */
89 89 #define SPCID_MASK 0x03000000 /* Sync PCI Divisor */
... ... @@ -93,7 +93,7 @@
93 93 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
94 94 #define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */
95 95 #define PLLSYS1_RW_MASK 0x00300000 /* ROM width */
96   -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */
  96 +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Address reset vector */
97 97 #define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */
98 98 #define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */
99 99 #define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */
arch/sparc/cpu/leon3/usb_uhci.c
Diff comments   View file @ 1626308
... ... @@ -70,7 +70,7 @@
70 70 *
71 71 * Interrupt Transfers.
72 72 * --------------------
73   - * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
  73 + * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
74 74 * will be inserted after the appropriate (depending the interval setting) skeleton TD.
75 75 * If an interrupt has been detected the dev->irqhandler is called. The status and number
76 76 * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
arch/x86/cpu/start.S
Diff comments   View file @ 1626308
... ... @@ -66,7 +66,7 @@
66 66 movw %ax, %es
67 67 movw %ax, %ss
68 68  
69   - /* Clear the interupt vectors */
  69 + /* Clear the interrupt vectors */
70 70 lidt blank_idt_ptr
71 71  
72 72 /* Early platform init (setup gpio, etc ) */
arch/x86/include/asm/interrupt.h
Diff comments   View file @ 1626308
... ... @@ -32,7 +32,7 @@
32 32 /* arch/x86/cpu/interrupts.c */
33 33 void set_vector(u8 intnum, void *routine);
34 34  
35   -/* arch/x86/lib/interupts.c */
  35 +/* arch/x86/lib/interrupts.c */
36 36 void disable_irq(int irq);
37 37 void enable_irq(int irq);
38 38  
board/Marvell/common/bootseq.txt
Diff comments   View file @ 1626308
... ... @@ -62,7 +62,7 @@
62 62 remap gt regs?
63 63 map PCI mem/io
64 64 map device space
65   - clear out interupts
  65 + clear out interrupts
66 66 init_timebase
67 67 env_init
68 68 serial_init
board/Marvell/common/i2c.c
Diff comments   View file @ 1626308
... ... @@ -420,7 +420,7 @@
420 420 status = i2c_get_data (data, len);
421 421 if (status) {
422 422 #ifdef DEBUG_I2C
423   - printf ("Data not recieved: 0x%02x\n", status);
  423 + printf ("Data not received: 0x%02x\n", status);
424 424 #endif
425 425 return status;
426 426 }
board/Marvell/common/ns16550.h
Diff comments   View file @ 1626308
... ... @@ -51,7 +51,7 @@
51 51 #define dlm ier
52 52  
53 53 #define FCR_FIFO_EN 0x01 /*fifo enable*/
54   -#define FCR_RXSR 0x02 /*reciever soft reset*/
  54 +#define FCR_RXSR 0x02 /*receiver soft reset*/
55 55 #define FCR_TXSR 0x04 /*transmitter soft reset*/
56 56  
57 57  
board/Marvell/include/mv_gen_reg.h
Diff comments   View file @ 1626308
... ... @@ -2237,7 +2237,7 @@
2237 2237 #define CHANNEL2_REGISTER10 0x9070
2238 2238 #define CHANNEL2_REGISTER11 0x9074
2239 2239  
2240   -/* MPSCs Interupts */
  2240 +/* MPSCs Interrupts */
2241 2241  
2242 2242 #define MPSC0_CAUSE 0xb824
2243 2243 #define MPSC0_MASK 0xb8a4
... ... @@ -37,7 +37,7 @@
37 37 #define afr iirfcrafr
38 38  
39 39 #define FCR_FIFO_EN 0x01 /*fifo enable */
40   -#define FCR_RXSR 0x02 /*reciever soft reset */
  40 +#define FCR_RXSR 0x02 /*receiver soft reset */
41 41 #define FCR_TXSR 0x04 /*transmitter soft reset */
42 42 #define FCR_DMS 0x08 /* DMA Mode Select */
43 43  
board/evb64260/bootseq.txt
Diff comments   View file @ 1626308
... ... @@ -62,7 +62,7 @@
62 62 remap gt regs?
63 63 map PCI mem/io
64 64 map device space
65   - clear out interupts
  65 + clear out interrupts
66 66 init_timebase
67 67 env_init
68 68 serial_init
board/evb64260/i2c.c
Diff comments   View file @ 1626308
... ... @@ -306,7 +306,7 @@
306 306 status = i2c_get_data(data, len);
307 307 if (status) {
308 308 #ifdef DEBUG_I2C
309   - printf("Data not recieved: 0x%02x\n", status);
  309 + printf("Data not received: 0x%02x\n", status);
310 310 #endif
311 311 return status;
312 312 }
board/freescale/mpc8266ads/mpc8266ads.c
Diff comments   View file @ 1626308
... ... @@ -392,7 +392,7 @@
392 392 The 11th column addre will still be mucxed correctly onto the bus.
393 393  
394 394 Also be aware that the MPC8266ADS board Rev B has not connected
395   - Row addres 13 to anything.
  395 + Row address 13 to anything.
396 396  
397 397 The fix is to connect ADD16 (from U37-47) to SADDR12 (U28-126)
398 398 */
board/intercontrol/digsy_mtc/eeprom.h
Diff comments   View file @ 1626308
... ... @@ -27,7 +27,7 @@
27 27 #define EEPROM_ADDR_IDENT 0 /* identification word offset */
28 28 #define EEPROM_ADDR_LEN_SYS 2 /* system area lenght offset */
29 29 #define EEPROM_ADDR_LEN_SYSCFG 4 /* system config area length offset */
30   -#define EEPROM_ADDR_ETHADDR 23 /* ethernet addres offset */
  30 +#define EEPROM_ADDR_ETHADDR 23 /* ethernet address offset */
31 31  
32 32 #endif
board/mpl/common/usb_uhci.c
Diff comments   View file @ 1626308
... ... @@ -67,7 +67,7 @@
67 67 *
68 68 * Interrupt Transfers.
69 69 * --------------------
70   - * For Interupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
  70 + * For Interrupt transfers USB_MAX_TEMP_INT_TD Transfer descriptor are available. They
71 71 * will be inserted after the appropriate (depending the interval setting) skeleton TD.
72 72 * If an interrupt has been detected the dev->irqhandler is called. The status and number
73 73 * of transfered bytes is stored in dev->irq_status resp. dev->irq_act_len. If the
... ... @@ -139,7 +139,7 @@
139 139 } /* bank */
140 140 }
141 141 if (!found) {
142   - /* error, addres not in flash */
  142 + /* error, address not in flash */
143 143 printf("Error: end address (0x%08lx) not in flash!\n", *addr);
144 144 return 1;
145 145 }
... ... @@ -786,7 +786,7 @@
786 786 ZM_DEBUG (zm_dprintf ("Engaging cleanup mode...\n"));
787 787 /*
788 788 * Consume any trailing crap left in the inbuffer from
789   - * previous recieved blocks. Since very few files are an exact multiple
  789 + * previous received blocks. Since very few files are an exact multiple
790 790 * of the transfer block size, there will almost always be some gunk here.
791 791 * If we don't eat it now, RedBoot will think the user typed it.
792 792 */
... ... @@ -111,7 +111,7 @@
111 111 CONFIG_SYS_INIT_RAM_ADDR
112 112 -- defines the base address of the MCF5272 internal SRAM
113 113 CONFIG_SYS_ENET_BD_BASE
114   - -- defines the base addres of the FEC buffer descriptors
  114 + -- defines the base address of the FEC buffer descriptors
115 115  
116 116 CONFIG_SYS_SCR -- defines the contents of the System Configuration Register
117 117 CONFIG_SYS_SPR -- defines the contents of the System Protection Register
... ... @@ -138,7 +138,7 @@
138 138 CONFIG_SYS_INT_FLASH_BASE
139 139 -- defines the base address of the MCF5282 internal Flash memory
140 140 CONFIG_SYS_ENET_BD_BASE
141   - -- defines the base addres of the FEC buffer descriptors
  141 + -- defines the base address of the FEC buffer descriptors
142 142  
143 143 CONFIG_SYS_MFD
144 144 -- defines the PLL Multiplication Factor Devider
doc/README.qemu_mips
Diff comments   View file @ 1626308
... ... @@ -24,7 +24,7 @@
24 24  
25 25 #config to build the kernel
26 26 qemu_mips_defconfig
27   -#patch to fix mips interupt init on 2.6.24.y kernel
  27 +#patch to fix mips interrupt init on 2.6.24.y kernel
28 28 qemu_mips_kernel.patch
29 29 initrd.gz
30 30 vmlinux
drivers/net/4xx_enet.c
Diff comments   View file @ 1626308
... ... @@ -1704,7 +1704,7 @@
1704 1704 rc = 0;
1705 1705 }
1706 1706  
1707   - /* handle MAL RX EOB interupt from a receive */
  1707 + /* handle MAL RX EOB interrupt from a receive */
1708 1708 /* check for EOB on valid channels */
1709 1709 if (uic_mal & UIC_MAL_RXEOB) {
1710 1710 mal_eob = mfdcr(MAL0_RXEOBISR);
... ... @@ -576,7 +576,7 @@
576 576 GRETH_REGORIN(&regs->control, GRETH_RXEN);
577 577 }
578 578 done:
579   - /* return positive length of packet or 0 if non recieved */
  579 + /* return positive length of packet or 0 if non received */
580 580 return len;
581 581 }
582 582  
drivers/net/natsemi.c
Diff comments   View file @ 1626308
... ... @@ -282,7 +282,7 @@
282 282 * ready to send and receive packets.
283 283 *
284 284 * Side effects:
285   - * leaves the natsemi initialized, and ready to recieve packets.
  285 + * leaves the natsemi initialized, and ready to receive packets.
286 286 *
287 287 * Returns: struct eth_device *: pointer to NIC data structure
288 288 */
drivers/net/ns8382x.c
Diff comments   View file @ 1626308
... ... @@ -299,7 +299,7 @@
299 299 * Description: Retrieves the MAC address of the card, and sets up some
300 300 * globals required by other routines, and initializes the NIC, making it
301 301 * ready to send and receive packets.
302   - * Side effects: initializes ns8382xs, ready to recieve packets.
  302 + * Side effects: initializes ns8382xs, ready to receive packets.
303 303 * Returns: int: number of cards found
304 304 */
305 305  
drivers/pci/fsl_pci_init.c
Diff comments   View file @ 1626308
... ... @@ -316,7 +316,7 @@
316 316 hose->current_busno = hose->first_busno;
317 317  
318 318 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
319   - out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except
  319 + out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except
320 320 * - Master abort (pci)
321 321 * - Master PERR (pci)
322 322 * - ICCA (PCIe)
drivers/rtc/mpc5xxx.c
Diff comments   View file @ 1626308
... ... @@ -44,7 +44,7 @@
44 44 volatile ulong aier; /* MBAR+0x80C: alarm and interrupt enable register */
45 45 volatile ulong ctr; /* MBAR+0x810: current time register */
46 46 volatile ulong cdr; /* MBAR+0x814: current data register */
47   - volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interupt register */
  47 + volatile ulong asir; /* MBAR+0x818: alarm and stopwatch interrupt register */
48 48 volatile ulong piber; /* MBAR+0x81C: periodic interrupt and bus error register */
49 49 volatile ulong trdr; /* MBAR+0x820: test register/divides register */
50 50 } RTC5200;
... ... @@ -108,7 +108,7 @@
108 108 uint cbd_bufaddr; /* Buffer address in host memory */
109 109 } cbd_t;
110 110  
111   -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
  111 +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
112 112 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
113 113 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
114 114 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
include/configs/NETTA.h
Diff comments   View file @ 1626308
... ... @@ -589,7 +589,7 @@
589 589 +------+----------------+------------------------------------------------------------
590 590 | # | Name | Comment
591 591 +------+----------------+------------------------------------------------------------
592   - | IRQ1 | UINTER_3V | S interupt chips interrupt (common)
  592 + | IRQ1 | UINTER_3V | S interrupt chips interrupt (common)
593 593 | IRQ3 | IRQ_DSP | DSP interrupt
594 594 | IRQ4 | IRQ_DSP1 | Extra DSP interrupt
595 595 +------+----------------+------------------------------------------------------------
include/configs/TQM834x.h
Diff comments   View file @ 1626308
... ... @@ -39,7 +39,7 @@
39 39  
40 40 #define CONFIG_SYS_TEXT_BASE 0x80000000
41 41  
42   -/* IMMR Base Addres Register, use Freescale default: 0xff400000 */
  42 +/* IMMR Base Address Register, use Freescale default: 0xff400000 */
43 43 #define CONFIG_SYS_IMMR 0xff400000
44 44  
45 45 /* System clock. Primary input clock when in PCI host mode */
include/galileo/gt64260R.h
Diff comments   View file @ 1626308
... ... @@ -1182,7 +1182,7 @@
1182 1182 #define CHANNEL2_REGISTER10 0x9070
1183 1183 #define CHANNEL2_REGISTER11 0x9074
1184 1184  
1185   -/* MPSCs Interupts */
  1185 +/* MPSCs Interrupts */
1186 1186  
1187 1187 #define MPSC0_CAUSE 0xb824
1188 1188 #define MPSC0_MASK 0xb8a4
include/mpc5xxx_sdma.h
Diff comments   View file @ 1626308
... ... @@ -82,11 +82,11 @@
82 82 sdma->IntPend = (1 << tasknum); \
83 83 }
84 84  
85   -/* get interupt pending bit of a task */
  85 +/* get interrupt pending bit of a task */
86 86 #define SDMA_GET_PENDINGBIT(tasknum) \
87 87 ((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum)))
88 88  
89   -/* get interupt mask bit of a task */
  89 +/* get interrupt mask bit of a task */
90 90 #define SDMA_GET_MASKBIT(tasknum) \
91 91 ((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum)))
92 92  
... ... @@ -258,7 +258,7 @@
258 258 #define PLTR 0x8000000d /* PCI Latancy Timer Register */
259 259 #define PHTR 0x8000000e /* PCI Header Type Register */
260 260 #define BISTCTRL 0x8000000f /* BIST Control */
261   -#define LMBAR 0x80000010 /* Local Base Addres Register */
  261 +#define LMBAR 0x80000010 /* Local Base Address Register */
262 262 #define PCSRBAR 0x80000014 /* PCSR Base Address Register */
263 263 #define ILR 0x8000003c /* PCI Interrupt Line Register */
264 264 #define IPR 0x8000003d /* Interrupt Pin Register */