Commit 1860d101964d6ea77e5411e62e3b42a64dc94865

Authored by Lokesh Vutla
Committed by Tom Rini
1 parent 802bb57a58

ARM: DRA7-evm: DDR3: Update leveling values

Update the software leveling parameters.
This fixes the random crash seen on DRA7-evm.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Showing 1 changed file with 30 additions and 30 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap5/sdram.c
... ... @@ -152,10 +152,10 @@
152 152 .emif_ddr_phy_ctlr_1_init = 0x0E24400A,
153 153 .emif_ddr_phy_ctlr_1 = 0x0E24400A,
154 154 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
155   - .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
156   - .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
157   - .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
158   - .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
  155 + .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  156 + .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  157 + .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  158 + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
159 159 .emif_rd_wr_lvl_rmp_win = 0x00000000,
160 160 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
161 161 .emif_rd_wr_lvl_ctl = 0x00000000,
... ... @@ -177,10 +177,10 @@
177 177 .emif_ddr_phy_ctlr_1_init = 0x0E24400A,
178 178 .emif_ddr_phy_ctlr_1 = 0x0E24400A,
179 179 .emif_ddr_ext_phy_ctrl_1 = 0x10040100,
180   - .emif_ddr_ext_phy_ctrl_2 = 0x00BB00BB,
181   - .emif_ddr_ext_phy_ctrl_3 = 0x00BB00BB,
182   - .emif_ddr_ext_phy_ctrl_4 = 0x00BB00BB,
183   - .emif_ddr_ext_phy_ctrl_5 = 0x00BB00BB,
  180 + .emif_ddr_ext_phy_ctrl_2 = 0x00910091,
  181 + .emif_ddr_ext_phy_ctrl_3 = 0x00950095,
  182 + .emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
  183 + .emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
184 184 .emif_rd_wr_lvl_rmp_win = 0x00000000,
185 185 .emif_rd_wr_lvl_rmp_ctl = 0x00000000,
186 186 .emif_rd_wr_lvl_ctl = 0x00000000,
187 187  
... ... @@ -423,22 +423,22 @@
423 423  
424 424 const u32
425 425 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
426   - 0x00BB00BB,
427   - 0x00440044,
428   - 0x00440044,
429   - 0x00440044,
430   - 0x00440044,
431   - 0x00440044,
  426 + 0x00980098,
  427 + 0x00340034,
  428 + 0x00350035,
  429 + 0x00340034,
  430 + 0x00310031,
  431 + 0x00340034,
432 432 0x007F007F,
433 433 0x007F007F,
434 434 0x007F007F,
435 435 0x007F007F,
436 436 0x007F007F,
437   - 0x00600060,
438   - 0x00600060,
439   - 0x00600060,
440   - 0x00600060,
441   - 0x00600060,
  437 + 0x00480048,
  438 + 0x004A004A,
  439 + 0x00520052,
  440 + 0x00550055,
  441 + 0x00500050,
442 442 0x00000000,
443 443 0x00600020,
444 444 0x40010080,
445 445  
... ... @@ -452,22 +452,22 @@
452 452  
453 453 const u32
454 454 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
455   - 0x00BB00BB,
456   - 0x00440044,
457   - 0x00440044,
458   - 0x00440044,
459   - 0x00440044,
460   - 0x00440044,
  455 + 0x00980098,
  456 + 0x00330033,
  457 + 0x00330033,
  458 + 0x002F002F,
  459 + 0x00320032,
  460 + 0x00310031,
461 461 0x007F007F,
462 462 0x007F007F,
463 463 0x007F007F,
464 464 0x007F007F,
465 465 0x007F007F,
466   - 0x00600060,
467   - 0x00600060,
468   - 0x00600060,
469   - 0x00600060,
470   - 0x00600060,
  466 + 0x00520052,
  467 + 0x00520052,
  468 + 0x00470047,
  469 + 0x00490049,
  470 + 0x00500050,
471 471 0x00000000,
472 472 0x00600020,
473 473 0x40010080,