Commit 802bb57a584db2202a47d41ac730fe76ddeb4f33
Committed by
Tom Rini
Tom Rini
1 parent
aa8ac43645
Exists in
v2017.01-smarct4x
and in
37 other branches
ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value
The value in SDRAM_REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value corresponding to 500us delay before starting DDR initialization sequence, and configure proper value at the end of sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Showing 4 changed files with 14 additions and 6 deletions Side-by-side Diff
arch/arm/cpu/armv7/omap-common/emif-common.c
| ... | ... | @@ -252,6 +252,8 @@ |
| 252 | 252 | { |
| 253 | 253 | struct emif_reg_struct *emif = (struct emif_reg_struct *)base; |
| 254 | 254 | |
| 255 | + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); | |
| 256 | + writel(regs->sdram_config_init, &emif->emif_sdram_config); | |
| 255 | 257 | /* |
| 256 | 258 | * Set SDRAM_CONFIG and PHY control registers to locked frequency |
| 257 | 259 | * and RL =7. As the default values of the Mode Registers are not |
| ... | ... | @@ -265,7 +267,6 @@ |
| 265 | 267 | writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); |
| 266 | 268 | writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); |
| 267 | 269 | |
| 268 | - writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); | |
| 269 | 270 | writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); |
| 270 | 271 | |
| 271 | 272 | /* |
| ... | ... | @@ -274,6 +275,7 @@ |
| 274 | 275 | */ |
| 275 | 276 | if (is_dra7xx()) { |
| 276 | 277 | do_ext_phy_settings(base, regs); |
| 278 | + writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl); | |
| 277 | 279 | writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config); |
| 278 | 280 | writel(regs->sdram_config_init, &emif->emif_sdram_config); |
| 279 | 281 | } else { |
arch/arm/cpu/armv7/omap5/sdram.c
| ... | ... | @@ -141,7 +141,8 @@ |
| 141 | 141 | .sdram_config_init = 0x61851ab2, |
| 142 | 142 | .sdram_config = 0x61851ab2, |
| 143 | 143 | .sdram_config2 = 0x08000000, |
| 144 | - .ref_ctrl = 0x00001035, | |
| 144 | + .ref_ctrl = 0x000040F1, | |
| 145 | + .ref_ctrl_final = 0x00001035, | |
| 145 | 146 | .sdram_tim1 = 0xCCCF36B3, |
| 146 | 147 | .sdram_tim2 = 0x308F7FDA, |
| 147 | 148 | .sdram_tim3 = 0x027F88A8, |
| ... | ... | @@ -165,7 +166,8 @@ |
| 165 | 166 | .sdram_config_init = 0x61851B32, |
| 166 | 167 | .sdram_config = 0x61851B32, |
| 167 | 168 | .sdram_config2 = 0x08000000, |
| 168 | - .ref_ctrl = 0x00001035, | |
| 169 | + .ref_ctrl = 0x000040F1, | |
| 170 | + .ref_ctrl_final = 0x00001035, | |
| 169 | 171 | .sdram_tim1 = 0xCCCF36B3, |
| 170 | 172 | .sdram_tim2 = 0x308F7FDA, |
| 171 | 173 | .sdram_tim3 = 0x027F88A8, |
| ... | ... | @@ -189,7 +191,8 @@ |
| 189 | 191 | .sdram_config_init = 0x61862B32, |
| 190 | 192 | .sdram_config = 0x61862B32, |
| 191 | 193 | .sdram_config2 = 0x08000000, |
| 192 | - .ref_ctrl = 0x0000144A, | |
| 194 | + .ref_ctrl = 0x0000493E, | |
| 195 | + .ref_ctrl_final = 0x0000144A, | |
| 193 | 196 | .sdram_tim1 = 0xD113781C, |
| 194 | 197 | .sdram_tim2 = 0x308F7FE3, |
| 195 | 198 | .sdram_tim3 = 0x009F86A8, |
arch/arm/include/asm/emif.h
board/ti/beagle_x15/board.c
| ... | ... | @@ -47,7 +47,8 @@ |
| 47 | 47 | .sdram_config_init = 0x61851b32, |
| 48 | 48 | .sdram_config = 0x61851b32, |
| 49 | 49 | .sdram_config2 = 0x00000000, |
| 50 | - .ref_ctrl = 0x00001035, | |
| 50 | + .ref_ctrl = 0x000040F1, | |
| 51 | + .ref_ctrl_final = 0x00001035, | |
| 51 | 52 | .sdram_tim1 = 0xceef266b, |
| 52 | 53 | .sdram_tim2 = 0x328f7fda, |
| 53 | 54 | .sdram_tim3 = 0x027f88a8, |
| ... | ... | @@ -103,7 +104,8 @@ |
| 103 | 104 | .sdram_config_init = 0x61851b32, |
| 104 | 105 | .sdram_config = 0x61851b32, |
| 105 | 106 | .sdram_config2 = 0x00000000, |
| 106 | - .ref_ctrl = 0x00001035, | |
| 107 | + .ref_ctrl = 0x000040F1, | |
| 108 | + .ref_ctrl_final = 0x00001035, | |
| 107 | 109 | .sdram_tim1 = 0xceef266b, |
| 108 | 110 | .sdram_tim2 = 0x328f7fda, |
| 109 | 111 | .sdram_tim3 = 0x027f88a8, |