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Commit 18936ee2ad8bf92f8219026b6b93fdcf58baeb61

Authored by Jason Liu
Committed by Albert ARIBAUD
1 parent 393cb36199
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

i.mx: introduce the armv7/imx-common folder 

In order to support the coming MX6 platform and to reducde
the duplicated code, we had better move some common files
or functions to the imx-common folder for sharing.

This patch does the following:
- move speed.c file from armv7/mx5/speed.c to armv7/imx-common/speed.c
- move armv7/mx5/timer.c to armv7/imx-common/timer.c, no any new feature
  added but just fix the checkpatch errors in the old file and remove
  the CONFIG_SYS_MX5_CLK32 reference in the file
- create one new file cpu.c file to store the common function with i.mx5/6

Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc:Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>

Showing 9 changed files with 315 additions and 228 deletions Side-by-side Diff

... ... @@ -296,6 +296,14 @@
296 296 ifneq ($(CONFIG_AM335X)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
297 297 LIBS += $(CPUDIR)/omap-common/libomap-common.o
298 298 endif
  299 +
  300 +ifeq ($(SOC),mx5)
  301 +LIBS += $(CPUDIR)/imx-common/libimx-common.o
  302 +endif
  303 +ifeq ($(SOC),mx6)
  304 +LIBS += $(CPUDIR)/imx-common/libimx-common.o
  305 +endif
  306 +
299 307 ifeq ($(SOC),s5pc1xx)
300 308 LIBS += $(CPUDIR)/s5p-common/libs5p-common.o
301 309 endif
arch/arm/cpu/armv7/imx-common/Makefile
Diff comments   View file @ 18936ee
  1 +#
  2 +# (C) Copyright 2000-2006
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# (C) Copyright 2011 Freescale Semiconductor, Inc.
  6 +#
  7 +# See file CREDITS for list of people who contributed to this
  8 +# project.
  9 +#
  10 +# This program is free software; you can redistribute it and/or
  11 +# modify it under the terms of the GNU General Public License as
  12 +# published by the Free Software Foundation; either version 2 of
  13 +# the License, or (at your option) any later version.
  14 +#
  15 +# This program is distributed in the hope that it will be useful,
  16 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 +# GNU General Public License for more details.
  19 +#
  20 +# You should have received a copy of the GNU General Public License
  21 +# along with this program; if not, write to the Free Software
  22 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 +# MA 02111-1307 USA
  24 +#
  25 +
  26 +include $(TOPDIR)/config.mk
  27 +
  28 +LIB = $(obj)libimx-common.o
  29 +
  30 +COBJS = timer.o cpu.o speed.o
  31 +
  32 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  33 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
  34 +
  35 +all: $(obj).depend $(LIB)
  36 +
  37 +$(LIB): $(OBJS)
  38 + $(call cmd_link_o_target, $(OBJS))
  39 +
  40 +#########################################################################
  41 +
  42 +# defines $(obj).depend target
  43 +include $(SRCTREE)/rules.mk
  44 +
  45 +sinclude $(obj).depend
  46 +
  47 +#########################################################################
arch/arm/cpu/armv7/imx-common/cpu.c
Diff comments   View file @ 18936ee
  1 +/*
  2 + * (C) Copyright 2007
  3 + * Sascha Hauer, Pengutronix
  4 + *
  5 + * (C) Copyright 2009 Freescale Semiconductor, Inc.
  6 + *
  7 + * See file CREDITS for list of people who contributed to this
  8 + * project.
  9 + *
  10 + * This program is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License as
  12 + * published by the Free Software Foundation; either version 2 of
  13 + * the License, or (at your option) any later version.
  14 + *
  15 + * This program is distributed in the hope that it will be useful,
  16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 + * GNU General Public License for more details.
  19 + *
  20 + * You should have received a copy of the GNU General Public License
  21 + * along with this program; if not, write to the Free Software
  22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 + * MA 02111-1307 USA
  24 + */
  25 +
  26 +#include <common.h>
  27 +#include <asm/errno.h>
  28 +#include <asm/io.h>
  29 +#include <asm/arch/imx-regs.h>
  30 +#include <asm/arch/clock.h>
  31 +#include <asm/arch/sys_proto.h>
  32 +
  33 +#ifdef CONFIG_FSL_ESDHC
  34 +#include <fsl_esdhc.h>
  35 +#endif
  36 +
  37 +static char *get_reset_cause(void)
  38 +{
  39 + u32 cause;
  40 + struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  41 +
  42 + cause = readl(&src_regs->srsr);
  43 + writel(cause, &src_regs->srsr);
  44 +
  45 + switch (cause) {
  46 + case 0x00001:
  47 + return "POR";
  48 + case 0x00004:
  49 + return "CSU";
  50 + case 0x00008:
  51 + return "IPP USER";
  52 + case 0x00010:
  53 + return "WDOG";
  54 + case 0x00020:
  55 + return "JTAG HIGH-Z";
  56 + case 0x00040:
  57 + return "JTAG SW";
  58 + case 0x10000:
  59 + return "WARM BOOT";
  60 + default:
  61 + return "unknown reset";
  62 + }
  63 +}
  64 +
  65 +#if defined(CONFIG_DISPLAY_CPUINFO)
  66 +int print_cpuinfo(void)
  67 +{
  68 + u32 cpurev;
  69 +
  70 + cpurev = get_cpu_rev();
  71 + printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
  72 + (cpurev & 0xFF000) >> 12,
  73 + (cpurev & 0x000F0) >> 4,
  74 + (cpurev & 0x0000F) >> 0,
  75 + mxc_get_clock(MXC_ARM_CLK) / 1000000);
  76 + printf("Reset cause: %s\n", get_reset_cause());
  77 + return 0;
  78 +}
  79 +#endif
  80 +
  81 +int cpu_eth_init(bd_t *bis)
  82 +{
  83 + int rc = -ENODEV;
  84 +
  85 +#if defined(CONFIG_FEC_MXC)
  86 + rc = fecmxc_initialize(bis);
  87 +#endif
  88 +
  89 + return rc;
  90 +}
  91 +
  92 +/*
  93 + * Initializes on-chip MMC controllers.
  94 + * to override, implement board_mmc_init()
  95 + */
  96 +int cpu_mmc_init(bd_t *bis)
  97 +{
  98 +#ifdef CONFIG_FSL_ESDHC
  99 + return fsl_esdhc_mmc_init(bis);
  100 +#else
  101 + return 0;
  102 +#endif
  103 +}
  104 +
  105 +void reset_cpu(ulong addr)
  106 +{
  107 + __raw_writew(4, WDOG1_BASE_ADDR);
  108 +}
arch/arm/cpu/armv7/imx-common/speed.c
Diff comments   View file @ 18936ee
  1 +/*
  2 + * (C) Copyright 2000-2003
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6 + * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +#include <common.h>
  28 +#include <asm/arch/imx-regs.h>
  29 +#include <asm/arch/clock.h>
  30 +
  31 +#ifdef CONFIG_FSL_ESDHC
  32 +DECLARE_GLOBAL_DATA_PTR;
  33 +#endif
  34 +
  35 +int get_clocks(void)
  36 +{
  37 +#ifdef CONFIG_FSL_ESDHC
  38 + gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
  39 +#endif
  40 + return 0;
  41 +}
arch/arm/cpu/armv7/imx-common/timer.c
Diff comments   View file @ 18936ee
  1 +/*
  2 + * (C) Copyright 2007
  3 + * Sascha Hauer, Pengutronix
  4 + *
  5 + * (C) Copyright 2009 Freescale Semiconductor, Inc.
  6 + *
  7 + * See file CREDITS for list of people who contributed to this
  8 + * project.
  9 + *
  10 + * This program is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License as
  12 + * published by the Free Software Foundation; either version 2 of
  13 + * the License, or (at your option) any later version.
  14 + *
  15 + * This program is distributed in the hope that it will be useful,
  16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 + * GNU General Public License for more details.
  19 + *
  20 + * You should have received a copy of the GNU General Public License
  21 + * along with this program; if not, write to the Free Software
  22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 + * MA 02111-1307 USA
  24 + */
  25 +
  26 +#include <common.h>
  27 +#include <asm/io.h>
  28 +#include <asm/arch/imx-regs.h>
  29 +
  30 +/* General purpose timers registers */
  31 +struct mxc_gpt {
  32 + unsigned int control;
  33 + unsigned int prescaler;
  34 + unsigned int status;
  35 + unsigned int nouse[6];
  36 + unsigned int counter;
  37 +};
  38 +
  39 +static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
  40 +
  41 +/* General purpose timers bitfields */
  42 +#define GPTCR_SWR (1 << 15) /* Software reset */
  43 +#define GPTCR_FRR (1 << 9) /* Freerun / restart */
  44 +#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
  45 +#define GPTCR_TEN 1 /* Timer enable */
  46 +#define CLK_32KHZ 32768 /* 32Khz input */
  47 +
  48 +DECLARE_GLOBAL_DATA_PTR;
  49 +
  50 +#define timestamp (gd->tbl)
  51 +#define lastinc (gd->lastinc)
  52 +
  53 +int timer_init(void)
  54 +{
  55 + int i;
  56 + ulong val;
  57 +
  58 + /* setup GP Timer 1 */
  59 + __raw_writel(GPTCR_SWR, &cur_gpt->control);
  60 +
  61 + /* We have no udelay by now */
  62 + for (i = 0; i < 100; i++)
  63 + __raw_writel(0, &cur_gpt->control);
  64 +
  65 + __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
  66 +
  67 + /* Freerun Mode, PERCLK1 input */
  68 + i = __raw_readl(&cur_gpt->control);
  69 + __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
  70 +
  71 + val = __raw_readl(&cur_gpt->counter);
  72 + lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ);
  73 + timestamp = 0;
  74 +
  75 + return 0;
  76 +}
  77 +
  78 +ulong get_timer_masked(void)
  79 +{
  80 + ulong val = __raw_readl(&cur_gpt->counter);
  81 + val /= (CLK_32KHZ / CONFIG_SYS_HZ);
  82 + if (val >= lastinc)
  83 + timestamp += (val - lastinc);
  84 + else
  85 + timestamp += ((0xFFFFFFFF / (CLK_32KHZ / CONFIG_SYS_HZ))
  86 + - lastinc) + val;
  87 + lastinc = val;
  88 + return timestamp;
  89 +}
  90 +
  91 +ulong get_timer(ulong base)
  92 +{
  93 + return get_timer_masked() - base;
  94 +}
  95 +
  96 +/* delay x useconds AND preserve advance timestamp value */
  97 +void __udelay(unsigned long usec)
  98 +{
  99 + unsigned long now, start, tmo;
  100 + tmo = usec * (CLK_32KHZ / 1000) / 1000;
  101 +
  102 + if (!tmo)
  103 + tmo = 1;
  104 +
  105 + now = start = readl(&cur_gpt->counter);
  106 +
  107 + while ((now - start) < tmo)
  108 + now = readl(&cur_gpt->counter);
  109 +
  110 +}
arch/arm/cpu/armv7/mx5/Makefile
Diff comments   View file @ 18936ee
... ... @@ -27,7 +27,7 @@
27 27  
28 28 LIB = $(obj)lib$(SOC).o
29 29  
30   -COBJS = soc.o clock.o iomux.o timer.o speed.o
  30 +COBJS = soc.o clock.o iomux.o
31 31 SOBJS = lowlevel_init.o
32 32  
33 33 SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
arch/arm/cpu/armv7/mx5/soc.c
Diff comments   View file @ 18936ee
... ... @@ -31,10 +31,6 @@
31 31 #include <asm/errno.h>
32 32 #include <asm/io.h>
33 33  
34   -#ifdef CONFIG_FSL_ESDHC
35   -#include <fsl_esdhc.h>
36   -#endif
37   -
38 34 #if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
39 35 #error "CPU_TYPE not defined"
40 36 #endif
41 37  
... ... @@ -75,62 +71,7 @@
75 71 return system_rev;
76 72 }
77 73  
78   -static char *get_reset_cause(void)
79   -{
80   - u32 cause;
81   - struct src *src_regs = (struct src *)SRC_BASE_ADDR;
82   -
83   - cause = readl(&src_regs->srsr);
84   - writel(cause, &src_regs->srsr);
85   -
86   - switch (cause) {
87   - case 0x00001:
88   - return "POR";
89   - case 0x00004:
90   - return "CSU";
91   - case 0x00008:
92   - return "IPP USER";
93   - case 0x00010:
94   - return "WDOG";
95   - case 0x00020:
96   - return "JTAG HIGH-Z";
97   - case 0x00040:
98   - return "JTAG SW";
99   - case 0x10000:
100   - return "WARM BOOT";
101   - default:
102   - return "unknown reset";
103   - }
104   -}
105   -
106   -#if defined(CONFIG_DISPLAY_CPUINFO)
107   -int print_cpuinfo(void)
108   -{
109   - u32 cpurev;
110   -
111   - cpurev = get_cpu_rev();
112   - printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
113   - (cpurev & 0xFF000) >> 12,
114   - (cpurev & 0x000F0) >> 4,
115   - (cpurev & 0x0000F) >> 0,
116   - mxc_get_clock(MXC_ARM_CLK) / 1000000);
117   - printf("Reset cause: %s\n", get_reset_cause());
118   - return 0;
119   -}
120   -#endif
121   -
122   -int cpu_eth_init(bd_t *bis)
123   -{
124   - int rc = -ENODEV;
125   -
126 74 #if defined(CONFIG_FEC_MXC)
127   - rc = fecmxc_initialize(bis);
128   -#endif
129   -
130   - return rc;
131   -}
132   -
133   -#if defined(CONFIG_FEC_MXC)
134 75 void imx_get_mac_from_fuse(unsigned char *mac)
135 76 {
136 77 int i;
... ... @@ -144,19 +85,6 @@
144 85 }
145 86 #endif
146 87  
147   -/*
148   - * Initializes on-chip MMC controllers.
149   - * to override, implement board_mmc_init()
150   - */
151   -int cpu_mmc_init(bd_t *bis)
152   -{
153   -#ifdef CONFIG_FSL_ESDHC
154   - return fsl_esdhc_mmc_init(bis);
155   -#else
156   - return 0;
157   -#endif
158   -}
159   -
160 88 void set_chipselect_size(int const cs_size)
161 89 {
162 90 unsigned int reg;
... ... @@ -186,10 +114,5 @@
186 114 }
187 115  
188 116 writel(reg, &iomuxc_regs->gpr1);
189   -}
190   -
191   -void reset_cpu(ulong addr)
192   -{
193   - __raw_writew(4, WDOG1_BASE_ADDR);
194 117 }
arch/arm/cpu/armv7/mx5/speed.c
View file @ 18936ee
1   -/*
2   - * (C) Copyright 2000-2003
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6   - * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7   - *
8   - * See file CREDITS for list of people who contributed to this
9   - * project.
10   - *
11   - * This program is free software; you can redistribute it and/or
12   - * modify it under the terms of the GNU General Public License as
13   - * published by the Free Software Foundation; either version 2 of
14   - * the License, or (at your option) any later version.
15   - *
16   - * This program is distributed in the hope that it will be useful,
17   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
18   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19   - * GNU General Public License for more details.
20   - *
21   - * You should have received a copy of the GNU General Public License
22   - * along with this program; if not, write to the Free Software
23   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24   - * MA 02111-1307 USA
25   - */
26   -
27   -#include <common.h>
28   -#include <asm/arch/imx-regs.h>
29   -#include <asm/arch/clock.h>
30   -
31   -#ifdef CONFIG_FSL_ESDHC
32   -DECLARE_GLOBAL_DATA_PTR;
33   -#endif
34   -
35   -int get_clocks(void)
36   -{
37   -#ifdef CONFIG_FSL_ESDHC
38   - gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
39   -#endif
40   - return 0;
41   -}
arch/arm/cpu/armv7/mx5/timer.c
View file @ 18936ee
1   -/*
2   - * (C) Copyright 2007
3   - * Sascha Hauer, Pengutronix
4   - *
5   - * (C) Copyright 2009 Freescale Semiconductor, Inc.
6   - *
7   - * See file CREDITS for list of people who contributed to this
8   - * project.
9   - *
10   - * This program is free software; you can redistribute it and/or
11   - * modify it under the terms of the GNU General Public License as
12   - * published by the Free Software Foundation; either version 2 of
13   - * the License, or (at your option) any later version.
14   - *
15   - * This program is distributed in the hope that it will be useful,
16   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
17   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18   - * GNU General Public License for more details.
19   - *
20   - * You should have received a copy of the GNU General Public License
21   - * along with this program; if not, write to the Free Software
22   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23   - * MA 02111-1307 USA
24   - */
25   -
26   -#include <common.h>
27   -#include <asm/io.h>
28   -#include <asm/arch/imx-regs.h>
29   -
30   -/* General purpose timers registers */
31   -struct mxc_gpt {
32   - unsigned int control;
33   - unsigned int prescaler;
34   - unsigned int status;
35   - unsigned int nouse[6];
36   - unsigned int counter;
37   -};
38   -
39   -static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
40   -
41   -/* General purpose timers bitfields */
42   -#define GPTCR_SWR (1<<15) /* Software reset */
43   -#define GPTCR_FRR (1<<9) /* Freerun / restart */
44   -#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
45   -#define GPTCR_TEN (1) /* Timer enable */
46   -
47   -DECLARE_GLOBAL_DATA_PTR;
48   -
49   -#define timestamp (gd->tbl)
50   -#define lastinc (gd->lastinc)
51   -
52   -int timer_init(void)
53   -{
54   - int i;
55   - ulong val;
56   -
57   - /* setup GP Timer 1 */
58   - __raw_writel(GPTCR_SWR, &cur_gpt->control);
59   -
60   - /* We have no udelay by now */
61   - for (i = 0; i < 100; i++)
62   - __raw_writel(0, &cur_gpt->control);
63   -
64   - __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
65   -
66   - /* Freerun Mode, PERCLK1 input */
67   - i = __raw_readl(&cur_gpt->control);
68   - __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
69   -
70   - val = __raw_readl(&cur_gpt->counter);
71   - lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
72   - timestamp = 0;
73   -
74   - return 0;
75   -}
76   -
77   -ulong get_timer_masked(void)
78   -{
79   - ulong val = __raw_readl(&cur_gpt->counter);
80   - val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ);
81   - if (val >= lastinc)
82   - timestamp += (val - lastinc);
83   - else
84   - timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ))
85   - - lastinc) + val;
86   - lastinc = val;
87   - return timestamp;
88   -}
89   -
90   -ulong get_timer(ulong base)
91   -{
92   - return get_timer_masked() - base;
93   -}
94   -
95   -/* delay x useconds AND preserve advance timestamp value */
96   -void __udelay(unsigned long usec)
97   -{
98   - unsigned long now, start, tmo;
99   - tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000;
100   -
101   - if (!tmo)
102   - tmo = 1;
103   -
104   - now = start = readl(&cur_gpt->counter);
105   -
106   - while ((now - start) < tmo)
107   - now = readl(&cur_gpt->counter);
108   -
109   -}