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Commit 198cafbf2cab9851ee5dd8d24d268d0ccc0fe3bd

Authored by Alison Wang
Committed by Jason
1 parent a4110eecf2
Exists in master and in 57 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ColdFire: Clean up checkpatch warnings for MCF54451 and MCF54455 

Signed-off-by: Alison Wang <b18965@freescale.com>

Showing 7 changed files with 267 additions and 243 deletions Side-by-side Diff

arch/m68k/cpu/mcf5445x/cpu.c
Diff comments   View file @ 198cafb
... ... @@ -3,7 +3,7 @@
3 3 * (C) Copyright 2000-2003
4 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 5 *
6   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 8 *
9 9 * See file CREDITS for list of people who contributed to this
10 10  
11 11  
... ... @@ -31,14 +31,15 @@
31 31 #include <netdev.h>
32 32  
33 33 #include <asm/immap.h>
  34 +#include <asm/io.h>
34 35  
35 36 DECLARE_GLOBAL_DATA_PTR;
36 37  
37 38 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
38 39 {
39   - volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
  40 + rcm_t *rcm = (rcm_t *) (MMAP_RCM);
40 41 udelay(1000);
41   - rcm->rcr |= RCM_RCR_SOFTRST;
  42 + setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
42 43  
43 44 /* we don't return! */
44 45 return 0;
45 46  
... ... @@ -46,14 +47,14 @@
46 47  
47 48 int checkcpu(void)
48 49 {
49   - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
  50 + ccm_t *ccm = (ccm_t *) MMAP_CCM;
50 51 u16 msk;
51 52 u16 id = 0;
52 53 u8 ver;
53 54  
54 55 puts("CPU: ");
55   - msk = (ccm->cir >> 6);
56   - ver = (ccm->cir & 0x003f);
  56 + msk = (in_be16(&ccm->cir) >> 6);
  57 + ver = (in_be16(&ccm->cir) & 0x003f);
57 58 switch (msk) {
58 59 case 0x48:
59 60 id = 54455;
arch/m68k/cpu/mcf5445x/cpu_init.c
Diff comments   View file @ 198cafb
... ... @@ -3,7 +3,7 @@
3 3 * (C) Copyright 2000-2003
4 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 5 *
6   - * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
  6 + * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
7 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 8 *
9 9 * See file CREDITS for list of people who contributed to this
... ... @@ -30,6 +30,7 @@
30 30 #include <asm/immap.h>
31 31 #include <asm/processor.h>
32 32 #include <asm/rtc.h>
  33 +#include <asm/io.h>
33 34  
34 35 #if defined(CONFIG_CMD_NET)
35 36 #include <config.h>
36 37  
37 38  
38 39  
39 40  
40 41  
41 42  
42 43  
43 44  
... ... @@ -46,64 +47,64 @@
46 47 */
47 48 void cpu_init_f(void)
48 49 {
49   - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
50   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
51   - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  50 + scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
  51 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  52 + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
52 53  
53   - scm1->mpr = 0x77777777;
54   - scm1->pacra = 0;
55   - scm1->pacrb = 0;
56   - scm1->pacrc = 0;
57   - scm1->pacrd = 0;
58   - scm1->pacre = 0;
59   - scm1->pacrf = 0;
60   - scm1->pacrg = 0;
  54 + out_be32(&scm1->mpr, 0x77777777);
  55 + out_be32(&scm1->pacra, 0);
  56 + out_be32(&scm1->pacrb, 0);
  57 + out_be32(&scm1->pacrc, 0);
  58 + out_be32(&scm1->pacrd, 0);
  59 + out_be32(&scm1->pacre, 0);
  60 + out_be32(&scm1->pacrf, 0);
  61 + out_be32(&scm1->pacrg, 0);
61 62  
62 63 /* FlexBus */
63   - gpio->par_be =
64   - GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 | GPIO_PAR_BE_BE1_BE1 |
65   - GPIO_PAR_BE_BE0_BE0;
66   - gpio->par_fbctl =
67   - GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA | GPIO_PAR_FBCTL_RW_RW |
68   - GPIO_PAR_FBCTL_TS_TS;
  64 + out_8(&gpio->par_be,
  65 + GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
  66 + GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
  67 + out_8(&gpio->par_fbctl,
  68 + GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
  69 + GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
69 70  
70 71 #if !defined(CONFIG_CF_SBF)
71 72 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
72   - fbcs->csar0 = CONFIG_SYS_CS0_BASE;
73   - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
74   - fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
  73 + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  74 + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  75 + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
75 76 #endif
76 77 #endif
77 78  
78 79 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
79 80 /* Latch chipselect */
80   - fbcs->csar1 = CONFIG_SYS_CS1_BASE;
81   - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
82   - fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
  81 + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  82 + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  83 + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
83 84 #endif
84 85  
85 86 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
86   - fbcs->csar2 = CONFIG_SYS_CS2_BASE;
87   - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
88   - fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
  87 + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  88 + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  89 + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
89 90 #endif
90 91  
91 92 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
92   - fbcs->csar3 = CONFIG_SYS_CS3_BASE;
93   - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
94   - fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
  93 + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  94 + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  95 + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
95 96 #endif
96 97  
97 98 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
98   - fbcs->csar4 = CONFIG_SYS_CS4_BASE;
99   - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
100   - fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
  99 + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  100 + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  101 + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
101 102 #endif
102 103  
103 104 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
104   - fbcs->csar5 = CONFIG_SYS_CS5_BASE;
105   - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
106   - fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
  105 + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  106 + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  107 + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
107 108 #endif
108 109  
109 110 /*
... ... @@ -115,7 +116,8 @@
115 116 setvbr(CONFIG_SYS_CS0_BASE);
116 117  
117 118 #ifdef CONFIG_FSL_I2C
118   - gpio->par_feci2c = GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA;
  119 + out_be16(&gpio->par_feci2c,
  120 + GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
119 121 #endif
120 122  
121 123 icache_enable();
122 124  
... ... @@ -127,11 +129,11 @@
127 129 int cpu_init_r(void)
128 130 {
129 131 #ifdef CONFIG_MCFRTC
130   - volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
131   - volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
  132 + rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
  133 + rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
132 134  
133   - rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
134   - rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
  135 + out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
  136 + out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
135 137 #endif
136 138  
137 139 return (0);
138 140  
139 141  
140 142  
141 143  
142 144  
... ... @@ -139,40 +141,40 @@
139 141  
140 142 void uart_port_conf(int port)
141 143 {
142   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  144 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
143 145  
144 146 /* Setup Ports: */
145 147 switch (port) {
146 148 case 0:
147   - gpio->par_uart &=
148   - ~(GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
149   - gpio->par_uart |=
150   - (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
  149 + clrbits_8(&gpio->par_uart,
  150 + GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
  151 + setbits_8(&gpio->par_uart,
  152 + GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
151 153 break;
152 154 case 1:
153 155 #ifdef CONFIG_SYS_UART1_PRI_GPIO
154   - gpio->par_uart &=
155   - ~(GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
156   - gpio->par_uart |=
157   - (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
  156 + clrbits_8(&gpio->par_uart,
  157 + GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
  158 + setbits_8(&gpio->par_uart,
  159 + GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
158 160 #elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
159   - gpio->par_ssi &=
160   - (GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK);
161   - gpio->par_ssi |=
162   - (GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
  161 + clrbits_be16(&gpio->par_ssi,
  162 + ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
  163 + setbits_be16(&gpio->par_ssi,
  164 + GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
163 165 #endif
164 166 break;
165 167 case 2:
166 168 #if defined(CONFIG_SYS_UART2_ALT1_GPIO)
167   - gpio->par_timer &=
168   - (GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK);
169   - gpio->par_timer |=
170   - (GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
  169 + clrbits_8(&gpio->par_timer,
  170 + ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
  171 + setbits_8(&gpio->par_timer,
  172 + GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
171 173 #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
172   - gpio->par_timer &=
173   - (GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK);
174   - gpio->par_timer |=
175   - (GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
  174 + clrbits_8(&gpio->par_timer,
  175 + ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
  176 + setbits_8(&gpio->par_timer,
  177 + GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
176 178 #endif
177 179 break;
178 180 }
179 181  
180 182  
181 183  
182 184  
183 185  
184 186  
185 187  
186 188  
187 189  
188 190  
... ... @@ -181,43 +183,43 @@
181 183 #if defined(CONFIG_CMD_NET)
182 184 int fecpin_setclear(struct eth_device *dev, int setclear)
183 185 {
184   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  186 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
185 187 struct fec_info_s *info = (struct fec_info_s *)dev->priv;
186 188  
187 189 if (setclear) {
188 190 #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
189 191 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
190   - gpio->par_feci2c |=
191   - (GPIO_PAR_FECI2C_MDC0_MDC0 |
192   - GPIO_PAR_FECI2C_MDIO0_MDIO0);
  192 + setbits_be16(&gpio->par_feci2c,
  193 + GPIO_PAR_FECI2C_MDC0_MDC0 |
  194 + GPIO_PAR_FECI2C_MDIO0_MDIO0);
193 195 else
194   - gpio->par_feci2c |=
195   - (GPIO_PAR_FECI2C_MDC1_MDC1 |
196   - GPIO_PAR_FECI2C_MDIO1_MDIO1);
  196 + setbits_be16(&gpio->par_feci2c,
  197 + GPIO_PAR_FECI2C_MDC1_MDC1 |
  198 + GPIO_PAR_FECI2C_MDIO1_MDIO1);
197 199 #else
198   - gpio->par_feci2c |=
199   - (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
  200 + setbits_be16(&gpio->par_feci2c,
  201 + GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
200 202 #endif
201 203  
202 204 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
203   - gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
  205 + setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
204 206 else
205   - gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
  207 + setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
206 208 } else {
207   - gpio->par_feci2c &=
208   - ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
  209 + clrbits_be16(&gpio->par_feci2c,
  210 + GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
209 211  
210 212 if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
211 213 #ifdef CONFIG_SYS_FEC_FULL_MII
212   - gpio->par_fec |= GPIO_PAR_FEC_FEC0_MII;
  214 + setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
213 215 #else
214   - gpio->par_fec &= GPIO_PAR_FEC_FEC0_UNMASK;
  216 + clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
215 217 #endif
216 218 } else {
217 219 #ifdef CONFIG_SYS_FEC_FULL_MII
218   - gpio->par_fec |= GPIO_PAR_FEC_FEC1_MII;
  220 + setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
219 221 #else
220   - gpio->par_fec &= GPIO_PAR_FEC_FEC1_UNMASK;
  222 + clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
221 223 #endif
222 224 }
223 225 }
224 226  
225 227  
226 228  
227 229  
228 230  
229 231  
230 232  
231 233  
232 234  
... ... @@ -228,43 +230,45 @@
228 230 #ifdef CONFIG_CF_DSPI
229 231 void cfspi_port_conf(void)
230 232 {
231   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  233 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
232 234  
233   - gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
234   - GPIO_PAR_DSPI_SCK_SCK;
  235 + out_8(&gpio->par_dspi,
  236 + GPIO_PAR_DSPI_SIN_SIN |
  237 + GPIO_PAR_DSPI_SOUT_SOUT |
  238 + GPIO_PAR_DSPI_SCK_SCK);
235 239 }
236 240  
237 241 int cfspi_claim_bus(uint bus, uint cs)
238 242 {
239   - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
240   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  243 + dspi_t *dspi = (dspi_t *) MMAP_DSPI;
  244 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
241 245  
242   - if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
  246 + if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
243 247 return -1;
244 248  
245 249 /* Clear FIFO and resume transfer */
246   - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
  250 + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
247 251  
248 252 switch (cs) {
249 253 case 0:
250   - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
251   - gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
  254 + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
  255 + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
252 256 break;
253 257 case 1:
254   - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
255   - gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1;
  258 + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
  259 + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
256 260 break;
257 261 case 2:
258   - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
259   - gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2;
  262 + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
  263 + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
260 264 break;
261 265 case 3:
262   - gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK;
263   - gpio->par_dma |= GPIO_PAR_DMA_DACK0_PCS3;
  266 + clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
  267 + setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
264 268 break;
265 269 case 5:
266   - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
267   - gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5;
  270 + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
  271 + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
268 272 break;
269 273 }
270 274  
271 275  
272 276  
273 277  
274 278  
275 279  
276 280  
... ... @@ -273,26 +277,27 @@
273 277  
274 278 void cfspi_release_bus(uint bus, uint cs)
275 279 {
276   - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
277   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  280 + dspi_t *dspi = (dspi_t *) MMAP_DSPI;
  281 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
278 282  
279   - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */
  283 + /* Clear FIFO */
  284 + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
280 285  
281 286 switch (cs) {
282 287 case 0:
283   - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
  288 + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
284 289 break;
285 290 case 1:
286   - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1;
  291 + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
287 292 break;
288 293 case 2:
289   - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2;
  294 + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
290 295 break;
291 296 case 3:
292   - gpio->par_dma &= GPIO_PAR_DMA_DACK0_UNMASK;
  297 + clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
293 298 break;
294 299 case 5:
295   - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5;
  300 + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
296 301 break;
297 302 }
298 303 }
arch/m68k/cpu/mcf5445x/interrupts.c
Diff comments   View file @ 198cafb
... ... @@ -3,7 +3,7 @@
3 3 * (C) Copyright 2000-2004
4 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 5 *
6   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 8 *
9 9 * See file CREDITS for list of people who contributed to this
10 10  
11 11  
... ... @@ -28,14 +28,15 @@
28 28 /* CPU specific interrupt routine */
29 29 #include <common.h>
30 30 #include <asm/immap.h>
  31 +#include <asm/io.h>
31 32  
32 33 int interrupt_init(void)
33 34 {
34   - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
  35 + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
35 36  
36 37 /* Make sure all interrupts are disabled */
37   - intp->imrh0 |= 0xFFFFFFFF;
38   - intp->imrl0 |= 0xFFFFFFFF;
  38 + setbits_be32(&intp->imrh0, 0xffffffff);
  39 + setbits_be32(&intp->imrl0, 0xffffffff);
39 40  
40 41 enable_interrupts();
41 42 return 0;
42 43  
... ... @@ -44,10 +45,10 @@
44 45 #if defined(CONFIG_MCFTMR)
45 46 void dtimer_intr_setup(void)
46 47 {
47   - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
  48 + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
48 49  
49   - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
50   - intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
  50 + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
  51 + clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
51 52 }
52 53 #endif
arch/m68k/cpu/mcf5445x/pci.c
Diff comments   View file @ 198cafb
1 1 /*
2   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
3 3 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
4 4 *
5 5 * See file CREDITS for list of people who contributed to this
6 6  
7 7  
8 8  
9 9  
10 10  
11 11  
12 12  
13 13  
14 14  
15 15  
16 16  
17 17  
18 18  
19 19  
20 20  
21 21  
22 22  
... ... @@ -60,78 +60,82 @@
60 60  
61 61 void pci_mcf5445x_init(struct pci_controller *hose)
62 62 {
63   - volatile pci_t *pci = (volatile pci_t *)MMAP_PCI;
64   - volatile pciarb_t *pciarb = (volatile pciarb_t *)MMAP_PCIARB;
65   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  63 + pci_t *pci = (pci_t *)MMAP_PCI;
  64 + pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
  65 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
66 66 u32 barEn = 0;
67 67  
68   - pciarb->acr = 0x001F001F;
  68 + out_be32(&pciarb->acr, 0x001f001f);
69 69  
70 70 /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
71 71 PCIREQ2, PCIGNT2 */
72   - gpio->par_pci =
73   - GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 | GPIO_PAR_PCI_GNT1 |
74   - GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
75   - GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;
  72 + out_be16(&gpio->par_pci,
  73 + GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
  74 + GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
  75 + GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
  76 + GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);
76 77  
77 78 /* Assert reset bit */
78   - pci->gscr |= PCI_GSCR_PR;
  79 + setbits_be32(&pci->gscr, PCI_GSCR_PR);
79 80  
80   - pci->tcr1 |= PCI_TCR1_P;
  81 + setbits_be32(&pci->tcr1, PCI_TCR1_P);
81 82  
82 83 /* Initiator windows */
83   - pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
84   - pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
85   - pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
  84 + out_be32(&pci->iw0btar,
  85 + CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
  86 + out_be32(&pci->iw1btar,
  87 + CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
  88 + out_be32(&pci->iw2btar,
  89 + CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
86 90  
87   - pci->iwcr =
88   - PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
89   - PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
  91 + out_be32(&pci->iwcr,
  92 + PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
  93 + PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
90 94  
91   - pci->icr = 0;
  95 + out_be32(&pci->icr, 0);
92 96  
93 97 /* Enable bus master and mem access */
94   - pci->scr = PCI_SCR_B | PCI_SCR_M;
  98 + out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
95 99  
96 100 /* Cache line size and master latency */
97   - pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
98   - pci->cr2 = 0;
  101 + out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
  102 + out_be32(&pci->cr2, 0);
99 103  
100 104 #ifdef CONFIG_SYS_PCI_BAR0
101   - pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
102   - pci->tbatr0 = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
  105 + out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
  106 + out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
103 107 barEn |= PCI_TCR2_B0E;
104 108 #endif
105 109 #ifdef CONFIG_SYS_PCI_BAR1
106   - pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
107   - pci->tbatr1 = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
  110 + out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
  111 + out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
108 112 barEn |= PCI_TCR2_B1E;
109 113 #endif
110 114 #ifdef CONFIG_SYS_PCI_BAR2
111   - pci->bar2 = PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2);
112   - pci->tbatr2 = CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN;
  115 + out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
  116 + out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
113 117 barEn |= PCI_TCR2_B2E;
114 118 #endif
115 119 #ifdef CONFIG_SYS_PCI_BAR3
116   - pci->bar3 = PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3);
117   - pci->tbatr3 = CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN;
  120 + out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
  121 + out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
118 122 barEn |= PCI_TCR2_B3E;
119 123 #endif
120 124 #ifdef CONFIG_SYS_PCI_BAR4
121   - pci->bar4 = PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4);
122   - pci->tbatr4 = CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN;
  125 + out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
  126 + out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
123 127 barEn |= PCI_TCR2_B4E;
124 128 #endif
125 129 #ifdef CONFIG_SYS_PCI_BAR5
126   - pci->bar5 = PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5);
127   - pci->tbatr5 = CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN;
  130 + out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
  131 + out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
128 132 barEn |= PCI_TCR2_B5E;
129 133 #endif
130 134  
131   - pci->tcr2 = barEn;
  135 + out_be32(&pci->tcr2, barEn);
132 136  
133 137 /* Deassert reset bit */
134   - pci->gscr &= ~PCI_GSCR_PR;
  138 + clrbits_be32(&pci->gscr, PCI_GSCR_PR);
135 139 udelay(1000);
136 140  
137 141 /* Enable PCI bus master support */
arch/m68k/cpu/mcf5445x/speed.c
Diff comments   View file @ 198cafb
1 1 /*
2 2 *
3   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  3 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
4 4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 5 *
6 6 * See file CREDITS for list of people who contributed to this
... ... @@ -26,6 +26,7 @@
26 26 #include <asm/processor.h>
27 27  
28 28 #include <asm/immap.h>
  29 +#include <asm/io.h>
29 30  
30 31 DECLARE_GLOBAL_DATA_PTR;
31 32  
... ... @@ -44,7 +45,7 @@
44 45  
45 46 void clock_enter_limp(int lpdiv)
46 47 {
47   - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
  48 + ccm_t *ccm = (ccm_t *)MMAP_CCM;
48 49 int i, j;
49 50  
50 51 /* Check bounds of divider */
51 52  
... ... @@ -57,10 +58,10 @@
57 58 for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
58 59  
59 60 /* Apply the divider to the system clock */
60   - ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
  61 + clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
61 62  
62 63 /* Enable Limp Mode */
63   - ccm->misccr |= CCM_MISCCR_LIMP;
  64 + setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
64 65 }
65 66  
66 67 /*
67 68  
68 69  
... ... @@ -69,14 +70,15 @@
69 70 */
70 71 void clock_exit_limp(void)
71 72 {
72   - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
73   - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
  73 + ccm_t *ccm = (ccm_t *)MMAP_CCM;
  74 + pll_t *pll = (pll_t *)MMAP_PLL;
74 75  
75 76 /* Exit Limp mode */
76   - ccm->misccr &= ~CCM_MISCCR_LIMP;
  77 + clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
77 78  
78 79 /* Wait for the PLL to lock */
79   - while (!(pll->psr & PLL_PSR_LOCK)) ;
  80 + while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
  81 + ;
80 82 }
81 83  
82 84 /*
... ... @@ -85,8 +87,8 @@
85 87 int get_clocks(void)
86 88 {
87 89  
88   - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
89   - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
  90 + ccm_t *ccm = (ccm_t *)MMAP_CCM;
  91 + pll_t *pll = (pll_t *)MMAP_PLL;
90 92 int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
91 93 int pllmult_pci[] = { 12, 6, 16, 8 };
92 94 int vco = 0, bPci, temp, fbtemp, pcrvalue;
93 95  
... ... @@ -94,13 +96,13 @@
94 96 u16 fbpll_mask;
95 97  
96 98 #ifdef CONFIG_M54455EVB
97   - volatile u8 *cpld = (volatile u8 *)(CONFIG_SYS_CS2_BASE + 3);
  99 + u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
98 100 #endif
99 101 u8 bootmode;
100 102  
101 103 /* To determine PCI is present or not */
102   - if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
103   - ((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
  104 + if (((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
  105 + ((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
104 106 pPllmult = &pllmult_pci[0];
105 107 fbpll_mask = 3; /* 11b */
106 108 bPci = 1;
... ... @@ -114,7 +116,7 @@
114 116 }
115 117  
116 118 #ifdef CONFIG_M54455EVB
117   - bootmode = (*cpld & 0x03);
  119 + bootmode = (in_8(cpld) & 0x03);
118 120  
119 121 if (bootmode != 3) {
120 122 /* Temporary read from CCR- fixed fb issue, must be the same clock
121 123  
... ... @@ -122,11 +124,11 @@
122 124 fbtemp = pPllmult[ccm->ccr & fbpll_mask];
123 125  
124 126 /* Break down into small pieces, code still in flex bus */
125   - pcrvalue = pll->pcr & 0xFFFFF0FF;
  127 + pcrvalue = in_be32(&pll->pcr) & 0xFFFFF0FF;
126 128 temp = fbtemp - 1;
127 129 pcrvalue |= PLL_PCR_OUTDIV3(temp);
128 130  
129   - pll->pcr = pcrvalue;
  131 + out_be32(&pll->pcr, pcrvalue);
130 132 }
131 133 #endif
132 134 #ifdef CONFIG_M54451EVB
... ... @@ -137,9 +139,10 @@
137 139 bootmode = 2;
138 140  
139 141 /* default value is 16 mul, set to 20 mul */
140   - pcrvalue = (pll->pcr & 0x00FFFFFF) | 0x14000000;
141   - pll->pcr = pcrvalue;
142   - while ((pll->psr & PLL_PSR_LOCK) != PLL_PSR_LOCK);
  142 + pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF) | 0x14000000;
  143 + out_be32(&pll->pcr, pcrvalue);
  144 + while ((in_be32(&pll->psr) & PLL_PSR_LOCK) != PLL_PSR_LOCK)
  145 + ;
143 146 #endif
144 147 #endif
145 148  
146 149  
... ... @@ -149,10 +152,10 @@
149 152  
150 153 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
151 154 /* invaild range, re-set in PCR */
152   - int temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
  155 + int temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
153 156 int i, j, bus;
154 157  
155   - j = (pll->pcr & 0xFF000000) >> 24;
  158 + j = (in_be32(&pll->pcr) & 0xFF000000) >> 24;
156 159 for (i = j; i < 0xFF; i++) {
157 160 vco = i * CONFIG_SYS_INPUT_CLKSRC;
158 161 if (vco >= CLOCK_PLL_FVCO_MIN) {
159 162  
160 163  
161 164  
162 165  
163 166  
164 167  
165 168  
166 169  
167 170  
... ... @@ -163,47 +166,47 @@
163 166 break;
164 167 }
165 168 }
166   - pcrvalue = pll->pcr & 0x00FF00FF;
  169 + pcrvalue = in_be32(&pll->pcr) & 0x00FF00FF;
167 170 fbtemp = ((i - 1) << 8) | ((i - 1) << 12);
168 171 pcrvalue |= ((i << 24) | fbtemp);
169 172  
170   - pll->pcr = pcrvalue;
  173 + out_be32(&pll->pcr, pcrvalue);
171 174 }
172 175 gd->vco_clk = vco; /* Vco clock */
173 176 } else if (bootmode == 2) {
174 177 /* Normal mode */
175   - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
  178 + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
176 179 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
177 180 /* Default value */
178   - pcrvalue = (pll->pcr & 0x00FFFFFF);
179   - pcrvalue |= pPllmult[ccm->ccr & fbpll_mask] << 24;
180   - pll->pcr = pcrvalue;
181   - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
  181 + pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
  182 + pcrvalue |= pPllmult[in_be16(&ccm->ccr) & fbpll_mask] << 24;
  183 + out_be32(&pll->pcr, pcrvalue);
  184 + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
182 185 }
183 186 gd->vco_clk = vco; /* Vco clock */
184 187 } else if (bootmode == 3) {
185 188 /* serial mode */
186   - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
  189 + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
187 190 gd->vco_clk = vco; /* Vco clock */
188 191 }
189 192  
190   - if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
  193 + if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
191 194 /* Limp mode */
192 195 } else {
193 196 gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
194 197  
195   - temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
  198 + temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
196 199 gd->cpu_clk = vco / temp; /* cpu clock */
197 200  
198   - temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
  201 + temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
199 202 gd->bus_clk = vco / temp; /* bus clock */
200 203  
201   - temp = ((pll->pcr & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
  204 + temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV3_MASK) >> 8) + 1;
202 205 gd->flb_clk = vco / temp; /* FlexBus clock */
203 206  
204 207 #ifdef CONFIG_PCI
205 208 if (bPci) {
206   - temp = ((pll->pcr & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
  209 + temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV4_MASK) >> 12) + 1;
207 210 gd->pci_clk = vco / temp; /* PCI clock */
208 211 }
209 212 #endif
board/freescale/m54451evb/m54451evb.c
Diff comments   View file @ 198cafb
... ... @@ -2,7 +2,7 @@
2 2 * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5   - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
  5 + * Copyright (C) 2004-2008, 2012 Freescale Semiconductor, Inc.
6 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 7 *
8 8 * See file CREDITS for list of people who contributed to this
... ... @@ -27,6 +27,7 @@
27 27 #include <common.h>
28 28 #include <spi.h>
29 29 #include <asm/immap.h>
  30 +#include <asm/io.h>
30 31  
31 32 DECLARE_GLOBAL_DATA_PTR;
32 33  
33 34  
... ... @@ -51,14 +52,14 @@
51 52 */
52 53 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
53 54 #else
54   - volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
55   - volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
  55 + sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
  56 + gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
56 57 u32 i;
57 58  
58 59 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
59 60  
60   - if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) &&
61   - (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2))
  61 + if ((in_be32(&sdram->sdcfg1) == CONFIG_SYS_SDRAM_CFG1) &&
  62 + (in_be32(&sdram->sdcfg2) == CONFIG_SYS_SDRAM_CFG2))
62 63 return dramsize;
63 64  
64 65 for (i = 0x13; i < 0x20; i++) {
65 66  
66 67  
67 68  
68 69  
69 70  
70 71  
71 72  
72 73  
... ... @@ -67,32 +68,33 @@
67 68 }
68 69 i--;
69 70  
70   - gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
  71 + out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
71 72  
72   - sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
  73 + out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
73 74  
74   - sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
75   - sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
  75 + out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
  76 + out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
76 77  
77 78 udelay(200);
78 79  
79 80 /* Issue PALL */
80   - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
  81 + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
81 82 __asm__("nop");
82 83  
83 84 /* Perform two refresh cycles */
84   - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
  85 + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
85 86 __asm__("nop");
86   - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
  87 + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
87 88 __asm__("nop");
88 89  
89 90 /* Issue LEMR */
90   - sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
  91 + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
91 92 __asm__("nop");
92   - sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
  93 + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
93 94 __asm__("nop");
94 95  
95   - sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000;
  96 + out_be32(&sdram->sdcr,
  97 + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000);
96 98  
97 99 udelay(100);
98 100 #endif
board/freescale/m54455evb/m54455evb.c
Diff comments   View file @ 198cafb
... ... @@ -2,7 +2,7 @@
2 2 * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  5 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 7 *
8 8 * See file CREDITS for list of people who contributed to this
... ... @@ -27,6 +27,7 @@
27 27 #include <common.h>
28 28 #include <pci.h>
29 29 #include <asm/immap.h>
  30 +#include <asm/io.h>
30 31  
31 32 DECLARE_GLOBAL_DATA_PTR;
32 33  
... ... @@ -47,8 +48,8 @@
47 48 */
48 49 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
49 50 #else
50   - volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
51   - volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
  51 + sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
  52 + gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
52 53 u32 i;
53 54  
54 55 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
55 56  
56 57  
57 58  
58 59  
59 60  
60 61  
61 62  
62 63  
... ... @@ -59,33 +60,34 @@
59 60 }
60 61 i--;
61 62  
62   - gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
  63 + out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
63 64  
64   - sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
65   - sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i);
  65 + out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
  66 + out_be32(&sdram->sdcs1, CONFIG_SYS_SDRAM_BASE1 | i);
66 67  
67   - sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
68   - sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
  68 + out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
  69 + out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
69 70  
70 71 /* Issue PALL */
71   - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
  72 + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
72 73  
73 74 /* Issue LEMR */
74   - sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408;
75   - sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300;
  75 + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD | 0x408);
  76 + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x300);
76 77  
77 78 udelay(500);
78 79  
79 80 /* Issue PALL */
80   - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
  81 + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
81 82  
82 83 /* Perform two refresh cycles */
83   - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
84   - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
  84 + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
  85 + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
85 86  
86   - sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200;
  87 + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE | 0x200);
87 88  
88   - sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
  89 + out_be32(&sdram->sdcr,
  90 + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
89 91  
90 92 udelay(100);
91 93 #endif
92 94  
93 95  
94 96  
... ... @@ -105,26 +107,29 @@
105 107  
106 108 int ide_preinit(void)
107 109 {
108   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  110 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  111 + u32 tmp;
109 112  
110   - gpio->par_fec |= (gpio->par_fec & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
111   - gpio->par_feci2c |=
112   - (gpio->par_feci2c & 0xF0FF) | (GPIO_PAR_FECI2C_MDC1_ATA_DIOR |
113   - GPIO_PAR_FECI2C_MDIO1_ATA_DIOW);
114   - gpio->par_ata |=
115   - (GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
116   - GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0
117   - | GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
118   - GPIO_PAR_ATA_IORDY_IORDY);
119   - gpio->par_pci |=
120   - (GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
  113 + tmp = (in_8(&gpio->par_fec) & GPIO_PAR_FEC_FEC1_UNMASK) | 0x10;
  114 + setbits_8(&gpio->par_fec, tmp);
  115 + tmp = ((in_be16(&gpio->par_feci2c) & 0xf0ff) |
  116 + (GPIO_PAR_FECI2C_MDC1_ATA_DIOR | GPIO_PAR_FECI2C_MDIO1_ATA_DIOW));
  117 + setbits_be16(&gpio->par_feci2c, tmp);
121 118  
  119 + setbits_be16(&gpio->par_ata,
  120 + GPIO_PAR_ATA_BUFEN | GPIO_PAR_ATA_CS1 | GPIO_PAR_ATA_CS0 |
  121 + GPIO_PAR_ATA_DA2 | GPIO_PAR_ATA_DA1 | GPIO_PAR_ATA_DA0 |
  122 + GPIO_PAR_ATA_RESET_RESET | GPIO_PAR_ATA_DMARQ_DMARQ |
  123 + GPIO_PAR_ATA_IORDY_IORDY);
  124 + setbits_be16(&gpio->par_pci,
  125 + GPIO_PAR_PCI_GNT3_ATA_DMACK | GPIO_PAR_PCI_REQ3_ATA_INTRQ);
  126 +
122 127 return (0);
123 128 }
124 129  
125 130 void ide_set_reset(int idereset)
126 131 {
127   - volatile atac_t *ata = (atac_t *) MMAP_ATA;
  132 + atac_t *ata = (atac_t *) MMAP_ATA;
128 133 long period;
129 134 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
130 135 int piotms[5][9] = {
131 136  
132 137  
133 138  
... ... @@ -136,24 +141,27 @@
136 141 }; /* PIO 4 */
137 142  
138 143 if (idereset) {
139   - ata->cr = 0; /* control reset */
  144 + /* control reset */
  145 + out_8(&ata->cr, 0);
140 146 udelay(10000);
141 147 } else {
142 148 #define CALC_TIMING(t) (t + period - 1) / period
143 149 period = 1000000000 / gd->bus_clk; /* period in ns */
144 150  
145 151 /*ata->ton = CALC_TIMING (180); */
146   - ata->t1 = CALC_TIMING(piotms[2][0]);
147   - ata->t2w = CALC_TIMING(piotms[2][1]);
148   - ata->t2r = CALC_TIMING(piotms[2][1]);
149   - ata->ta = CALC_TIMING(piotms[2][8]);
150   - ata->trd = CALC_TIMING(piotms[2][7]);
151   - ata->t4 = CALC_TIMING(piotms[2][3]);
152   - ata->t9 = CALC_TIMING(piotms[2][6]);
  152 + out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
  153 + out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
  154 + out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
  155 + out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
  156 + out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
  157 + out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
  158 + out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
153 159  
154   - ata->cr = 0x40; /* IORDY enable */
  160 + /* IORDY enable */
  161 + out_8(&ata->cr, 0x40);
155 162 udelay(200000);
156   - ata->cr |= 0x01; /* IORDY enable */
  163 + /* IORDY enable */
  164 + setbits_8(&ata->cr, 0x01);
157 165 }
158 166 }
159 167 #endif