Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit a4110eecf2944b2f8b47f38273cc3730ddd394a3

Authored by Alison Wang
Committed by Jason
1 parent c6d8863015
Exists in master and in 57 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ColdFire: Clean up checkpatch warnings for MCF547x and MCF548x 

Signed-off-by: Alison Wang <b18965@freescale.com>

Showing 7 changed files with 158 additions and 144 deletions Side-by-side Diff

arch/m68k/cpu/mcf547x_8x/cpu.c
Diff comments   View file @ a4110ee
... ... @@ -3,7 +3,7 @@
3 3 * (C) Copyright 2000-2003
4 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 5 *
6   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 8 *
9 9 * See file CREDITS for list of people who contributed to this
10 10  
11 11  
12 12  
... ... @@ -31,19 +31,20 @@
31 31 #include <netdev.h>
32 32  
33 33 #include <asm/immap.h>
  34 +#include <asm/io.h>
34 35  
35 36 DECLARE_GLOBAL_DATA_PTR;
36 37  
37 38 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
38 39 {
39   - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
  40 + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
40 41  
41   - gptmr->pre = 10;
42   - gptmr->cnt = 1;
  42 + out_be16(&gptmr->pre, 10);
  43 + out_be16(&gptmr->cnt, 1);
43 44  
44 45 /* enable watchdog, set timeout to 0 and wait */
45   - gptmr->mode = GPT_TMS_SGPIO;
46   - gptmr->ctrl = GPT_CTRL_WDEN | GPT_CTRL_CE;
  46 + out_8(&gptmr->mode, GPT_TMS_SGPIO);
  47 + out_8(&gptmr->ctrl, GPT_CTRL_WDEN | GPT_CTRL_CE);
47 48  
48 49 /* we don't return! */
49 50 return 1;
50 51  
... ... @@ -51,12 +52,12 @@
51 52  
52 53 int checkcpu(void)
53 54 {
54   - volatile siu_t *siu = (siu_t *) MMAP_SIU;
  55 + siu_t *siu = (siu_t *) MMAP_SIU;
55 56 u16 id = 0;
56 57  
57 58 puts("CPU: ");
58 59  
59   - switch ((siu->jtagid & 0x000FF000) >> 12) {
  60 + switch ((in_be32(&siu->jtagid) & 0x000FF000) >> 12) {
60 61 case 0x0C:
61 62 id = 5485;
62 63 break;
63 64  
64 65  
65 66  
... ... @@ -111,18 +112,18 @@
111 112 /* Called by macro WATCHDOG_RESET */
112 113 void hw_watchdog_reset(void)
113 114 {
114   - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
  115 + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
115 116  
116   - gptmr->ocpw = 0xa5;
  117 + out_8(&gptmr->ocpw, 0xa5);
117 118 }
118 119  
119 120 int watchdog_disable(void)
120 121 {
121   - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
  122 + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
122 123  
123 124 /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */
124   - gptmr->mode = 0;
125   - gptmr->ctrl = 0;
  125 + out_8(&gptmr->mode, 0);
  126 + out_8(&gptmr->ctrl, 0);
126 127  
127 128 puts("WATCHDOG:disabled\n");
128 129  
129 130  
130 131  
... ... @@ -131,14 +132,13 @@
131 132  
132 133 int watchdog_init(void)
133 134 {
  135 + gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
134 136  
135   - volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
  137 + out_be16(&gptmr->pre, CONFIG_WATCHDOG_TIMEOUT);
  138 + out_be16(&gptmr->cnt, CONFIG_SYS_TIMER_PRESCALER * 1000);
136 139  
137   - gptmr->pre = CONFIG_WATCHDOG_TIMEOUT;
138   - gptmr->cnt = CONFIG_SYS_TIMER_PRESCALER * 1000;
139   -
140   - gptmr->mode = GPT_TMS_SGPIO;
141   - gptmr->ctrl = GPT_CTRL_CE | GPT_CTRL_WDEN;
  140 + out_8(&gptmr->mode, GPT_TMS_SGPIO);
  141 + out_8(&gptmr->ctrl, GPT_CTRL_CE | GPT_CTRL_WDEN);
142 142 puts("WATCHDOG:enabled\n");
143 143  
144 144 return (0);
arch/m68k/cpu/mcf547x_8x/cpu_init.c
Diff comments   View file @ a4110ee
... ... @@ -3,7 +3,7 @@
3 3 * (C) Copyright 2000-2003
4 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 5 *
6   - * (C) Copyright 2007 Freescale Semiconductor, Inc.
  6 + * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
7 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 8 *
9 9 * See file CREDITS for list of people who contributed to this
... ... @@ -28,6 +28,7 @@
28 28 #include <common.h>
29 29 #include <MCD_dma.h>
30 30 #include <asm/immap.h>
  31 +#include <asm/io.h>
31 32  
32 33 #if defined(CONFIG_CMD_NET)
33 34 #include <config.h>
34 35  
35 36  
36 37  
37 38  
38 39  
39 40  
40 41  
41 42  
42 43  
43 44  
... ... @@ -44,58 +45,59 @@
44 45 */
45 46 void cpu_init_f(void)
46 47 {
47   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
48   - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
49   - volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB;
  48 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  49 + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  50 + xlbarb_t *xlbarb = (xlbarb_t *) MMAP_XARB;
50 51  
51   - xlbarb->adrto = 0x2000;
52   - xlbarb->datto = 0x2500;
53   - xlbarb->busto = 0x3000;
  52 + out_be32(&xlbarb->adrto, 0x2000);
  53 + out_be32(&xlbarb->datto, 0x2500);
  54 + out_be32(&xlbarb->busto, 0x3000);
54 55  
55   - xlbarb->cfg = XARB_CFG_AT | XARB_CFG_DT;
  56 + out_be32(&xlbarb->cfg, XARB_CFG_AT | XARB_CFG_DT);
56 57  
57 58 /* Master Priority Enable */
58   - xlbarb->prien = 0xff;
59   - xlbarb->pri = 0;
  59 + out_be32(&xlbarb->prien, 0xff);
  60 + out_be32(&xlbarb->pri, 0);
60 61  
61 62 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
62   - fbcs->csar0 = CONFIG_SYS_CS0_BASE;
63   - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
64   - fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
  63 + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  64 + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  65 + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
65 66 #endif
66 67  
67 68 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
68   - fbcs->csar1 = CONFIG_SYS_CS1_BASE;
69   - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
70   - fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
  69 + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  70 + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  71 + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
71 72 #endif
72 73  
73 74 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
74   - fbcs->csar2 = CONFIG_SYS_CS2_BASE;
75   - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
76   - fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
  75 + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  76 + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  77 + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
77 78 #endif
78 79  
79 80 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
80   - fbcs->csar3 = CONFIG_SYS_CS3_BASE;
81   - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
82   - fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
  81 + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  82 + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  83 + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
83 84 #endif
84 85  
85 86 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
86   - fbcs->csar4 = CONFIG_SYS_CS4_BASE;
87   - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
88   - fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
  87 + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  88 + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  89 + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
89 90 #endif
90 91  
91 92 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
92   - fbcs->csar5 = CONFIG_SYS_CS5_BASE;
93   - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
94   - fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
  93 + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  94 + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  95 + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
95 96 #endif
96 97  
97 98 #ifdef CONFIG_FSL_I2C
98   - gpio->par_feci2cirq = GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA;
  99 + out_be16(&gpio->par_feci2cirq,
  100 + GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA);
99 101 #endif
100 102  
101 103 icache_enable();
102 104  
103 105  
104 106  
105 107  
106 108  
107 109  
108 110  
109 111  
110 112  
111 113  
... ... @@ -115,44 +117,44 @@
115 117  
116 118 void uart_port_conf(int port)
117 119 {
118   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
119   - volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
  120 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  121 + u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
120 122  
121 123 /* Setup Ports: */
122 124 switch (port) {
123 125 case 0:
124   - gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
  126 + out_8(&gpio->par_psc0, GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
125 127 break;
126 128 case 1:
127   - gpio->par_psc1 = (GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
  129 + out_8(&gpio->par_psc1, GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1);
128 130 break;
129 131 case 2:
130   - gpio->par_psc2 = (GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
  132 + out_8(&gpio->par_psc2, GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2);
131 133 break;
132 134 case 3:
133   - gpio->par_psc3 = (GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
  135 + out_8(&gpio->par_psc3, GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3);
134 136 break;
135 137 }
136 138  
137   - *pscsicr &= 0xF8;
  139 + clrbits_8(pscsicr, 0x07);
138 140 }
139 141  
140 142 #if defined(CONFIG_CMD_NET)
141 143 int fecpin_setclear(struct eth_device *dev, int setclear)
142 144 {
143   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  145 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
144 146 struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
145 147  
146 148 if (setclear) {
147 149 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
148   - gpio->par_feci2cirq |= 0xF000;
  150 + setbits_be16(&gpio->par_feci2cirq, 0xf000);
149 151 else
150   - gpio->par_feci2cirq |= 0x0FC0;
  152 + setbits_be16(&gpio->par_feci2cirq, 0x0fc0);
151 153 } else {
152 154 if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
153   - gpio->par_feci2cirq &= 0x0FFF;
  155 + clrbits_be16(&gpio->par_feci2cirq, 0xf000);
154 156 else
155   - gpio->par_feci2cirq &= 0xF03F;
  157 + clrbits_be16(&gpio->par_feci2cirq, 0x0fc0);
156 158 }
157 159 return 0;
158 160 }
arch/m68k/cpu/mcf547x_8x/interrupts.c
Diff comments   View file @ a4110ee
1 1 /*
2 2 *
3   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  3 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
4 4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 5 *
6 6 * See file CREDITS for list of people who contributed to this
7 7  
8 8  
... ... @@ -25,14 +25,15 @@
25 25 /* CPU specific interrupt routine */
26 26 #include <common.h>
27 27 #include <asm/immap.h>
  28 +#include <asm/io.h>
28 29  
29 30 int interrupt_init(void)
30 31 {
31   - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
  32 + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
32 33  
33 34 /* Make sure all interrupts are disabled */
34   - intp->imrh0 |= 0xFFFFFFFF;
35   - intp->imrl0 |= 0xFFFFFFFF;
  35 + setbits_be32(&intp->imrh0, 0xffffffff);
  36 + setbits_be32(&intp->imrl0, 0xffffffff);
36 37  
37 38 enable_interrupts();
38 39  
39 40  
... ... @@ -42,10 +43,10 @@
42 43 #if defined(CONFIG_SLTTMR)
43 44 void dtimer_intr_setup(void)
44 45 {
45   - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
  46 + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
46 47  
47   - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
48   - intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
  48 + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
  49 + clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
49 50 }
50 51 #endif
arch/m68k/cpu/mcf547x_8x/pci.c
Diff comments   View file @ a4110ee
1 1 /*
2   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
3 3 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
4 4 *
5 5 * See file CREDITS for list of people who contributed to this
6 6  
7 7  
8 8  
9 9  
10 10  
11 11  
12 12  
13 13  
14 14  
15 15  
16 16  
... ... @@ -88,53 +88,56 @@
88 88  
89 89 void pci_mcf547x_8x_init(struct pci_controller *hose)
90 90 {
91   - volatile pci_t *pci = (volatile pci_t *) MMAP_PCI;
92   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  91 + pci_t *pci = (pci_t *) MMAP_PCI;
  92 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
93 93  
94 94 /* Port configuration */
95   - gpio->par_pcibg =
96   - GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
97   - GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
98   - GPIO_PAR_PCIBG_PCIBG4(3);
99   - gpio->par_pcibr =
100   - GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
101   - GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
102   - GPIO_PAR_PCIBR_PCIBR4(3);
  95 + out_be16(&gpio->par_pcibg,
  96 + GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) |
  97 + GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) |
  98 + GPIO_PAR_PCIBG_PCIBG4(3));
  99 + out_be16(&gpio->par_pcibr,
  100 + GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) |
  101 + GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) |
  102 + GPIO_PAR_PCIBR_PCIBR4(3));
103 103  
104 104 /* Assert reset bit */
105   - pci->gscr |= PCI_GSCR_PR;
  105 + setbits_be32(&pci->gscr, PCI_GSCR_PR);
106 106  
107   - pci->tcr1 = PCI_TCR1_P;
  107 + out_be32(&pci->tcr1, PCI_TCR1_P);
108 108  
109 109 /* Initiator windows */
110   - pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
111   - pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
112   - pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
  110 + out_be32(&pci->iw0btar,
  111 + CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
  112 + out_be32(&pci->iw1btar,
  113 + CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
  114 + out_be32(&pci->iw2btar,
  115 + CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
113 116  
114   - pci->iwcr =
115   - PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
116   - PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
  117 + out_be32(&pci->iwcr,
  118 + PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
  119 + PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
117 120  
118   - pci->icr = 0;
  121 + out_be32(&pci->icr, 0);
119 122  
120 123 /* Enable bus master and mem access */
121   - pci->scr = PCI_SCR_B | PCI_SCR_M;
  124 + out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
122 125  
123 126 /* Cache line size and master latency */
124   - pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
125   - pci->cr2 = 0;
  127 + out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xf8));
  128 + out_be32(&pci->cr2, 0);
126 129  
127 130 #ifdef CONFIG_SYS_PCI_BAR0
128   - pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
129   - pci->tbatr0a = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
  131 + out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
  132 + out_be32(&pci->tbatr0a, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
130 133 #endif
131 134 #ifdef CONFIG_SYS_PCI_BAR1
132   - pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
133   - pci->tbatr1a = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
  135 + out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
  136 + out_be32(&pci->tbatr1a, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
134 137 #endif
135 138  
136 139 /* Deassert reset bit */
137   - pci->gscr &= ~PCI_GSCR_PR;
  140 + clrbits_be32(&pci->gscr, PCI_GSCR_PR);
138 141 udelay(1000);
139 142  
140 143 /* Enable PCI bus master support */
arch/m68k/cpu/mcf547x_8x/slicetimer.c
Diff comments   View file @ a4110ee
1 1 /*
2   - * (C) Copyright 2007 Freescale Semiconductor, Inc.
  2 + * (C) Copyright 2007, 2012 Freescale Semiconductor, Inc.
3 3 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
4 4 *
5 5 * See file CREDITS for list of people who contributed to this
... ... @@ -25,6 +25,7 @@
25 25  
26 26 #include <asm/timer.h>
27 27 #include <asm/immap.h>
  28 +#include <asm/io.h>
28 29  
29 30 DECLARE_GLOBAL_DATA_PTR;
30 31  
31 32  
32 33  
33 34  
34 35  
35 36  
36 37  
... ... @@ -42,31 +43,32 @@
42 43  
43 44 void __udelay(unsigned long usec)
44 45 {
45   - volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
  46 + slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
46 47 u32 now, freq;
47 48  
48 49 /* 1 us period */
49 50 freq = CONFIG_SYS_TIMER_PRESCALER;
50 51  
51   - timerp->cr = 0; /* Disable */
52   - timerp->tcnt = usec * freq;
53   - timerp->cr = SLT_CR_TEN;
  52 + /* Disable */
  53 + out_be32(&timerp->cr, 0);
  54 + out_be32(&timerp->tcnt, usec * freq);
  55 + out_be32(&timerp->cr, SLT_CR_TEN);
54 56  
55   - now = timerp->cnt;
  57 + now = in_be32(&timerp->cnt);
56 58 while (now != 0)
57   - now = timerp->cnt;
  59 + now = in_be32(&timerp->cnt);
58 60  
59   - timerp->sr |= SLT_SR_ST;
60   - timerp->cr = 0;
  61 + setbits_be32(&timerp->sr, SLT_SR_ST);
  62 + out_be32(&timerp->cr, 0);
61 63 }
62 64  
63 65 void dtimer_interrupt(void *not_used)
64 66 {
65   - volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
  67 + slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
66 68  
67 69 /* check for timer interrupt asserted */
68 70 if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
69   - timerp->sr |= SLT_SR_ST;
  71 + setbits_be32(&timerp->sr, SLT_SR_ST);
70 72 timestamp++;
71 73 return;
72 74 }
73 75  
74 76  
75 77  
... ... @@ -74,25 +76,27 @@
74 76  
75 77 int timer_init(void)
76 78 {
77   - volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
  79 + slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
78 80  
79 81 timestamp = 0;
80 82  
81   - timerp->cr = 0; /* disable timer */
82   - timerp->tcnt = 0;
83   - timerp->sr = SLT_SR_BE | SLT_SR_ST; /* clear status */
  83 + /* disable timer */
  84 + out_be32(&timerp->cr, 0);
  85 + out_be32(&timerp->tcnt, 0);
  86 + /* clear status */
  87 + out_be32(&timerp->sr, SLT_SR_BE | SLT_SR_ST);
84 88  
85 89 /* initialize and enable timer interrupt */
86 90 irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
87 91  
88 92 /* Interrupt every ms */
89   - timerp->tcnt = 1000 * CONFIG_SYS_TIMER_PRESCALER;
  93 + out_be32(&timerp->tcnt, 1000 * CONFIG_SYS_TIMER_PRESCALER);
90 94  
91 95 dtimer_intr_setup();
92 96  
93 97 /* set a period of 1us, set timer mode to restart and
94 98 enable timer and interrupt */
95   - timerp->cr = SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN;
  99 + out_be32(&timerp->cr, SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN);
96 100 return 0;
97 101 }
98 102  
board/freescale/m547xevb/m547xevb.c
Diff comments   View file @ a4110ee
... ... @@ -2,7 +2,7 @@
2 2 * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  5 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 7 *
8 8 * See file CREDITS for list of people who contributed to this
... ... @@ -28,6 +28,7 @@
28 28 #include <common.h>
29 29 #include <pci.h>
30 30 #include <asm/immap.h>
  31 +#include <asm/io.h>
31 32  
32 33 DECLARE_GLOBAL_DATA_PTR;
33 34  
34 35  
... ... @@ -40,14 +41,14 @@
40 41  
41 42 phys_size_t initdram(int board_type)
42 43 {
43   - volatile siu_t *siu = (siu_t *) (MMAP_SIU);
44   - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
  44 + siu_t *siu = (siu_t *) (MMAP_SIU);
  45 + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
45 46 u32 dramsize, i;
46 47 #ifdef CONFIG_SYS_DRAMSZ1
47 48 u32 temp;
48 49 #endif
49 50  
50   - siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
  51 + out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
51 52  
52 53 dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
53 54 for (i = 0x13; i < 0x20; i++) {
... ... @@ -55,7 +56,7 @@
55 56 break;
56 57 }
57 58 i--;
58   - siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
  59 + out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
59 60  
60 61 #ifdef CONFIG_SYS_DRAMSZ1
61 62 temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
62 63  
63 64  
64 65  
65 66  
66 67  
67 68  
68 69  
... ... @@ -65,31 +66,32 @@
65 66 }
66 67 i--;
67 68 dramsize += temp;
68   - siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
  69 + out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
69 70 #endif
70 71  
71   - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
72   - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
  72 + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
  73 + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
73 74  
74 75 /* Issue PALL */
75   - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
  76 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
76 77  
77 78 /* Issue LEMR */
78   - sdram->mode = CONFIG_SYS_SDRAM_EMOD;
79   - sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
  79 + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
  80 + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
80 81  
81 82 udelay(500);
82 83  
83 84 /* Issue PALL */
84   - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
  85 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
85 86  
86 87 /* Perform two refresh cycles */
87   - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
88   - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
  88 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
  89 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
89 90  
90   - sdram->mode = CONFIG_SYS_SDRAM_MODE;
  91 + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
91 92  
92   - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
  93 + out_be32(&sdram->ctrl,
  94 + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
93 95  
94 96 udelay(100);
95 97  
board/freescale/m548xevb/m548xevb.c
Diff comments   View file @ a4110ee
... ... @@ -2,7 +2,7 @@
2 2 * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  5 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 7 *
8 8 * See file CREDITS for list of people who contributed to this
... ... @@ -28,6 +28,7 @@
28 28 #include <common.h>
29 29 #include <pci.h>
30 30 #include <asm/immap.h>
  31 +#include <asm/io.h>
31 32  
32 33 DECLARE_GLOBAL_DATA_PTR;
33 34  
34 35  
... ... @@ -40,14 +41,14 @@
40 41  
41 42 phys_size_t initdram(int board_type)
42 43 {
43   - volatile siu_t *siu = (siu_t *) (MMAP_SIU);
44   - volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
  44 + siu_t *siu = (siu_t *) (MMAP_SIU);
  45 + sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
45 46 u32 dramsize, i;
46 47 #ifdef CONFIG_SYS_DRAMSZ1
47 48 u32 temp;
48 49 #endif
49 50  
50   - siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
  51 + out_be32(&siu->drv, CONFIG_SYS_SDRAM_DRVSTRENGTH);
51 52  
52 53 dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
53 54 for (i = 0x13; i < 0x20; i++) {
... ... @@ -55,7 +56,7 @@
55 56 break;
56 57 }
57 58 i--;
58   - siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
  59 + out_be32(&siu->cs0cfg, CONFIG_SYS_SDRAM_BASE | i);
59 60  
60 61 #ifdef CONFIG_SYS_DRAMSZ1
61 62 temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
62 63  
63 64  
64 65  
65 66  
66 67  
67 68  
68 69  
... ... @@ -65,31 +66,32 @@
65 66 }
66 67 i--;
67 68 dramsize += temp;
68   - siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
  69 + out_be32(&siu->cs1cfg, (CONFIG_SYS_SDRAM_BASE + temp) | i);
69 70 #endif
70 71  
71   - sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
72   - sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
  72 + out_be32(&sdram->cfg1, CONFIG_SYS_SDRAM_CFG1);
  73 + out_be32(&sdram->cfg2, CONFIG_SYS_SDRAM_CFG2);
73 74  
74 75 /* Issue PALL */
75   - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
  76 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
76 77  
77 78 /* Issue LEMR */
78   - sdram->mode = CONFIG_SYS_SDRAM_EMOD;
79   - sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
  79 + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_EMOD);
  80 + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE | 0x04000000);
80 81  
81 82 udelay(500);
82 83  
83 84 /* Issue PALL */
84   - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
  85 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 2);
85 86  
86 87 /* Perform two refresh cycles */
87   - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
88   - sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
  88 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
  89 + out_be32(&sdram->ctrl, CONFIG_SYS_SDRAM_CTRL | 4);
89 90  
90   - sdram->mode = CONFIG_SYS_SDRAM_MODE;
  91 + out_be32(&sdram->mode, CONFIG_SYS_SDRAM_MODE);
91 92  
92   - sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
  93 + out_be32(&sdram->ctrl,
  94 + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00);
93 95  
94 96 udelay(100);
95 97