Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 19ac1a8346d55134618a224ea45d99a650671801

Authored by Nishanth Menon
Committed by Lokesh Vutla
1 parent cb7e5a72e2
Exists in v2015.07-smarct4x and in 3 other branches ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc

ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0 

DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
provided IODELAY values for standard RGMII phys do not work.

Silicon Revision(SR) 2.0 provides an alternative bit configuration
that allows us to do a "gross adjustment" to launch the data off a
different internal clock edge. Manual IO Delay overrides are still
necessary to fine tune the clock-to-data delays. This is a necessary
workaround for the quirky ethernet Phy we have on the platform.

NOTE: SMA registers are spare "kitchen sink" registers that does
contain bits for other workaround as necessary as well. Hence the
control for the same is introduced in a generic SoC specific, board
generic location.

Signed-off-by: Nishanth Menon <nm@ti.com>

Showing 5 changed files with 19 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/armv7/omap5/prcm-regs.c
Diff comments   View file @ 19ac1a8
... ... @@ -11,6 +11,7 @@
11 11 */
12 12  
13 13 #include <asm/omap_common.h>
  14 +#include <asm/io.h>
14 15  
15 16 struct prcm_regs const omap5_es1_prcm = {
16 17 /* cm1.ckgen */
... ... @@ -379,6 +380,7 @@
379 380 .control_phy_power_usb = 0x4A002370,
380 381 .control_phy_power_sata = 0x4A002374,
381 382 .ctrl_core_sma_sw_0 = 0x4A0023FC,
  383 + .ctrl_core_sma_sw_1 = 0x4A002534,
382 384 .control_core_mac_id_0_lo = 0x4A002514,
383 385 .control_core_mac_id_0_hi = 0x4A002518,
384 386 .control_core_mac_id_1_lo = 0x4A00251C,
... ... @@ -996,4 +998,11 @@
996 998 .cm_l3main1_tptc1_clkctrl = 0x4a008778,
997 999 .cm_l3main1_tptc2_clkctrl = 0x4a008780,
998 1000 };
  1001 +
  1002 +void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits)
  1003 +{
  1004 + u32 reg = spare_type ? (*ctrl)->ctrl_core_sma_sw_1 :
  1005 + (*ctrl)->ctrl_core_sma_sw_0;
  1006 + clrsetbits_le32(reg, clear_bits, set_bits);
  1007 +}
arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
Diff comments   View file @ 19ac1a8
... ... @@ -49,6 +49,10 @@
49 49 #define ISOLATE_IO 1
50 50 #define DEISOLATE_IO 0
51 51  
  52 +/* CTRL_CORE_SMA_SW_1 */
  53 +#define RGMII2_ID_MODE_N_MASK (1 << 26)
  54 +#define RGMII1_ID_MODE_N_MASK (1 << 25)
  55 +
52 56 /* PRM_IO_PMCTRL */
53 57 #define PMCTRL_ISOCLK_OVERRIDE_SHIFT 0
54 58 #define PMCTRL_ISOCLK_OVERRIDE_MASK (1 << 0)
arch/arm/include/asm/arch-omap5/omap.h
Diff comments   View file @ 19ac1a8
... ... @@ -241,6 +241,8 @@
241 241 u32 ctrl_ddr_ctrl_ext_0;
242 242 };
243 243  
  244 +void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits);
  245 +
244 246 #endif /* __ASSEMBLY__ */
245 247 #endif
arch/arm/include/asm/omap_common.h
Diff comments   View file @ 19ac1a8
... ... @@ -468,6 +468,7 @@
468 468 u32 control_padconf_wkup_base;
469 469 u32 iodelay_config_base;
470 470 u32 ctrl_core_sma_sw_0;
  471 + u32 ctrl_core_sma_sw_1;
471 472 };
472 473  
473 474 struct dpll_params {
board/ti/dra7xx/evm.c
Diff comments   View file @ 19ac1a8
... ... @@ -109,6 +109,9 @@
109 109 npads = ARRAY_SIZE(dra74x_core_padconf_array);
110 110 iodelay = dra742_es2_0_iodelay_cfg_array;
111 111 niodelays = ARRAY_SIZE(dra742_es2_0_iodelay_cfg_array);
  112 + /* Setup port1 and port2 for rgmii with 'no-id' mode */
  113 + clrset_spare_register(1, 0, RGMII2_ID_MODE_N_MASK |
  114 + RGMII1_ID_MODE_N_MASK);
112 115 break;
113 116 }
114 117 __recalibrate_iodelay(pads, npads, iodelay, niodelays);