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Commit 1b8607e1f7143548c6062c28371449ec69588c00

Authored by Anatolij Gustschin
Committed by Wolfgang Denk
1 parent 4124382de0
Exists in master and in 57 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Extend ATI Radeon driver to support more video modes 

Adds ATI Radeon 9200 support for 1280x1024, 1024x768,
800x600, 640x480 at 24, 16 and 8 bpp.

Signed-off-by: Anatolij Gustschin <agust@denx.de>

Showing 2 changed files with 308 additions and 15 deletions Inline Diff

drivers/video/ati_radeon_fb.c
Diff comments   View file @ 1b8607e
1 /* 1 /*
2 * ATI Radeon Video card Framebuffer driver. 2 * ATI Radeon Video card Framebuffer driver.
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor, Inc. 4 * Copyright 2007 Freescale Semiconductor, Inc.
5 * Zhang Wei <wei.zhang@freescale.com> 5 * Zhang Wei <wei.zhang@freescale.com>
6 * Jason Jin <jason.jin@freescale.com> 6 * Jason Jin <jason.jin@freescale.com>
7 * 7 *
8 * See file CREDITS for list of people who contributed to this 8 * See file CREDITS for list of people who contributed to this
9 * project. 9 * project.
10 * 10 *
11 * This program is free software; you can redistribute it and/or 11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as 12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of 13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version. 14 * the License, or (at your option) any later version.
15 * 15 *
16 * This program is distributed in the hope that it will be useful, 16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details. 19 * GNU General Public License for more details.
20 * 20 *
21 * You should have received a copy of the GNU General Public License 21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software 22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA 24 * MA 02111-1307 USA
25 * 25 *
26 * Some codes of this file is partly ported from Linux kernel 26 * Some codes of this file is partly ported from Linux kernel
27 * ATI video framebuffer driver. 27 * ATI video framebuffer driver.
28 * 28 *
29 * Now the driver is tested on below ATI chips: 29 * Now the driver is tested on below ATI chips:
30 * 9200 30 * 9200
31 * X300 31 * X300
32 * X700 32 * X700
33 * 33 *
34 */ 34 */
35 35
36 #include <common.h> 36 #include <common.h>
37 37
38 #ifdef CONFIG_ATI_RADEON_FB 38 #ifdef CONFIG_ATI_RADEON_FB
39 39
40 #include <command.h> 40 #include <command.h>
41 #include <pci.h> 41 #include <pci.h>
42 #include <asm/processor.h> 42 #include <asm/processor.h>
43 #include <asm/errno.h> 43 #include <asm/errno.h>
44 #include <asm/io.h> 44 #include <asm/io.h>
45 #include <malloc.h> 45 #include <malloc.h>
46 #include <video_fb.h> 46 #include <video_fb.h>
47 #include "videomodes.h"
47 48
48 #include <radeon.h> 49 #include <radeon.h>
49 #include "ati_ids.h" 50 #include "ati_ids.h"
50 #include "ati_radeon_fb.h" 51 #include "ati_radeon_fb.h"
51 52
52 #undef DEBUG 53 #undef DEBUG
53 54
54 #ifdef DEBUG 55 #ifdef DEBUG
55 #define DPRINT(x...) printf(x) 56 #define DPRINT(x...) printf(x)
56 #else 57 #else
57 #define DPRINT(x...) do{}while(0) 58 #define DPRINT(x...) do{}while(0)
58 #endif 59 #endif
59 60
60 #ifndef min_t 61 #ifndef min_t
61 #define min_t(type,x,y) \ 62 #define min_t(type,x,y) \
62 ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) 63 ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
63 #endif 64 #endif
64 65
65 #define MAX_MAPPED_VRAM (2048*2048*4) 66 #define MAX_MAPPED_VRAM (2048*2048*4)
66 #define MIN_MAPPED_VRAM (1024*768*1) 67 #define MIN_MAPPED_VRAM (1024*768*1)
67 68
69 #define RADEON_BUFFER_ALIGN 0x00000fff
70 #define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \
71 & ~RADEON_BUFFER_ALIGN) - 1)
72 #define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \
73 ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16))
74
75 #define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \
76 (((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16))
77 #define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \
78 (((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16))
79 #define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \
80 ((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16))
81 #define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \
82 ((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16))
83
68 /*#define PCI_VENDOR_ID_ATI*/ 84 /*#define PCI_VENDOR_ID_ATI*/
69 #define PCI_CHIP_RV280_5960 0x5960 85 #define PCI_CHIP_RV280_5960 0x5960
70 #define PCI_CHIP_RV280_5961 0x5961 86 #define PCI_CHIP_RV280_5961 0x5961
71 #define PCI_CHIP_RV280_5962 0x5962 87 #define PCI_CHIP_RV280_5962 0x5962
72 #define PCI_CHIP_RV280_5964 0x5964 88 #define PCI_CHIP_RV280_5964 0x5964
73 #define PCI_CHIP_RV370_5B60 0x5B60 89 #define PCI_CHIP_RV370_5B60 0x5B60
74 #define PCI_CHIP_RV380_5657 0x5657 90 #define PCI_CHIP_RV380_5657 0x5657
75 #define PCI_CHIP_R420_554d 0x554d 91 #define PCI_CHIP_R420_554d 0x554d
76 92
77 static struct pci_device_id ati_radeon_pci_ids[] = { 93 static struct pci_device_id ati_radeon_pci_ids[] = {
78 {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960}, 94 {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960},
79 {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961}, 95 {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961},
80 {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962}, 96 {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962},
81 {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964}, 97 {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964},
82 {PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60}, 98 {PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60},
83 {PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657}, 99 {PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657},
84 {PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d}, 100 {PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d},
85 {0, 0} 101 {0, 0}
86 }; 102 };
87 103
88 static u16 ati_radeon_id_family_table[][2] = { 104 static u16 ati_radeon_id_family_table[][2] = {
89 {PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280}, 105 {PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280},
90 {PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280}, 106 {PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280},
91 {PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280}, 107 {PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280},
92 {PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280}, 108 {PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280},
93 {PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380}, 109 {PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380},
94 {PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380}, 110 {PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380},
95 {PCI_CHIP_R420_554d, CHIP_FAMILY_R420}, 111 {PCI_CHIP_R420_554d, CHIP_FAMILY_R420},
96 {0, 0} 112 {0, 0}
97 }; 113 };
98 114
99 u16 get_radeon_id_family(u16 device) 115 u16 get_radeon_id_family(u16 device)
100 { 116 {
101 int i; 117 int i;
102 for (i=0; ati_radeon_id_family_table[0][i]; i+=2) 118 for (i=0; ati_radeon_id_family_table[0][i]; i+=2)
103 if (ati_radeon_id_family_table[0][i] == device) 119 if (ati_radeon_id_family_table[0][i] == device)
104 return ati_radeon_id_family_table[0][i + 1]; 120 return ati_radeon_id_family_table[0][i + 1];
105 return 0; 121 return 0;
106 } 122 }
107 123
108 struct radeonfb_info *rinfo; 124 struct radeonfb_info *rinfo;
109 125
110 static void radeon_identify_vram(struct radeonfb_info *rinfo) 126 static void radeon_identify_vram(struct radeonfb_info *rinfo)
111 { 127 {
112 u32 tmp; 128 u32 tmp;
113 129
114 /* framebuffer size */ 130 /* framebuffer size */
115 if ((rinfo->family == CHIP_FAMILY_RS100) || 131 if ((rinfo->family == CHIP_FAMILY_RS100) ||
116 (rinfo->family == CHIP_FAMILY_RS200) || 132 (rinfo->family == CHIP_FAMILY_RS200) ||
117 (rinfo->family == CHIP_FAMILY_RS300)) { 133 (rinfo->family == CHIP_FAMILY_RS300)) {
118 u32 tom = INREG(NB_TOM); 134 u32 tom = INREG(NB_TOM);
119 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); 135 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
120 136
121 radeon_fifo_wait(6); 137 radeon_fifo_wait(6);
122 OUTREG(MC_FB_LOCATION, tom); 138 OUTREG(MC_FB_LOCATION, tom);
123 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 139 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
124 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); 140 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
125 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); 141 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
126 142
127 /* This is supposed to fix the crtc2 noise problem. */ 143 /* This is supposed to fix the crtc2 noise problem. */
128 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); 144 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
129 145
130 if ((rinfo->family == CHIP_FAMILY_RS100) || 146 if ((rinfo->family == CHIP_FAMILY_RS100) ||
131 (rinfo->family == CHIP_FAMILY_RS200)) { 147 (rinfo->family == CHIP_FAMILY_RS200)) {
132 /* This is to workaround the asic bug for RMX, some versions 148 /* This is to workaround the asic bug for RMX, some versions
133 of BIOS dosen't have this register initialized correctly. 149 of BIOS dosen't have this register initialized correctly.
134 */ 150 */
135 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, 151 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
136 ~CRTC_H_CUTOFF_ACTIVE_EN); 152 ~CRTC_H_CUTOFF_ACTIVE_EN);
137 } 153 }
138 } else { 154 } else {
139 tmp = INREG(CONFIG_MEMSIZE); 155 tmp = INREG(CONFIG_MEMSIZE);
140 } 156 }
141 157
142 /* mem size is bits [28:0], mask off the rest */ 158 /* mem size is bits [28:0], mask off the rest */
143 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; 159 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
144 160
145 /* 161 /*
146 * Hack to get around some busted production M6's 162 * Hack to get around some busted production M6's
147 * reporting no ram 163 * reporting no ram
148 */ 164 */
149 if (rinfo->video_ram == 0) { 165 if (rinfo->video_ram == 0) {
150 switch (rinfo->pdev.device) { 166 switch (rinfo->pdev.device) {
151 case PCI_CHIP_RADEON_LY: 167 case PCI_CHIP_RADEON_LY:
152 case PCI_CHIP_RADEON_LZ: 168 case PCI_CHIP_RADEON_LZ:
153 rinfo->video_ram = 8192 * 1024; 169 rinfo->video_ram = 8192 * 1024;
154 break; 170 break;
155 default: 171 default:
156 break; 172 break;
157 } 173 }
158 } 174 }
159 175
160 /* 176 /*
161 * Now try to identify VRAM type 177 * Now try to identify VRAM type
162 */ 178 */
163 if ((rinfo->family >= CHIP_FAMILY_R300) || 179 if ((rinfo->family >= CHIP_FAMILY_R300) ||
164 (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) 180 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
165 rinfo->vram_ddr = 1; 181 rinfo->vram_ddr = 1;
166 else 182 else
167 rinfo->vram_ddr = 0; 183 rinfo->vram_ddr = 0;
168 184
169 tmp = INREG(MEM_CNTL); 185 tmp = INREG(MEM_CNTL);
170 if (IS_R300_VARIANT(rinfo)) { 186 if (IS_R300_VARIANT(rinfo)) {
171 tmp &= R300_MEM_NUM_CHANNELS_MASK; 187 tmp &= R300_MEM_NUM_CHANNELS_MASK;
172 switch (tmp) { 188 switch (tmp) {
173 case 0: rinfo->vram_width = 64; break; 189 case 0: rinfo->vram_width = 64; break;
174 case 1: rinfo->vram_width = 128; break; 190 case 1: rinfo->vram_width = 128; break;
175 case 2: rinfo->vram_width = 256; break; 191 case 2: rinfo->vram_width = 256; break;
176 default: rinfo->vram_width = 128; break; 192 default: rinfo->vram_width = 128; break;
177 } 193 }
178 } else if ((rinfo->family == CHIP_FAMILY_RV100) || 194 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
179 (rinfo->family == CHIP_FAMILY_RS100) || 195 (rinfo->family == CHIP_FAMILY_RS100) ||
180 (rinfo->family == CHIP_FAMILY_RS200)){ 196 (rinfo->family == CHIP_FAMILY_RS200)){
181 if (tmp & RV100_MEM_HALF_MODE) 197 if (tmp & RV100_MEM_HALF_MODE)
182 rinfo->vram_width = 32; 198 rinfo->vram_width = 32;
183 else 199 else
184 rinfo->vram_width = 64; 200 rinfo->vram_width = 64;
185 } else { 201 } else {
186 if (tmp & MEM_NUM_CHANNELS_MASK) 202 if (tmp & MEM_NUM_CHANNELS_MASK)
187 rinfo->vram_width = 128; 203 rinfo->vram_width = 128;
188 else 204 else
189 rinfo->vram_width = 64; 205 rinfo->vram_width = 64;
190 } 206 }
191 207
192 /* This may not be correct, as some cards can have half of channel disabled 208 /* This may not be correct, as some cards can have half of channel disabled
193 * ToDo: identify these cases 209 * ToDo: identify these cases
194 */ 210 */
195 211
196 DPRINT("radeonfb: Found %ldk of %s %d bits wide videoram\n", 212 DPRINT("radeonfb: Found %ldk of %s %d bits wide videoram\n",
197 rinfo->video_ram / 1024, 213 rinfo->video_ram / 1024,
198 rinfo->vram_ddr ? "DDR" : "SDRAM", 214 rinfo->vram_ddr ? "DDR" : "SDRAM",
199 rinfo->vram_width); 215 rinfo->vram_width);
200 216
201 } 217 }
202 218
203 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) 219 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
204 { 220 {
205 int i; 221 int i;
206 222
207 radeon_fifo_wait(20); 223 radeon_fifo_wait(20);
208 224
209 #if 0 225 #if 0
210 /* Workaround from XFree */ 226 /* Workaround from XFree */
211 if (rinfo->is_mobility) { 227 if (rinfo->is_mobility) {
212 /* A temporal workaround for the occational blanking on certain laptop 228 /* A temporal workaround for the occational blanking on certain laptop
213 * panels. This appears to related to the PLL divider registers 229 * panels. This appears to related to the PLL divider registers
214 * (fail to lock?). It occurs even when all dividers are the same 230 * (fail to lock?). It occurs even when all dividers are the same
215 * with their old settings. In this case we really don't need to 231 * with their old settings. In this case we really don't need to
216 * fiddle with PLL registers. By doing this we can avoid the blanking 232 * fiddle with PLL registers. By doing this we can avoid the blanking
217 * problem with some panels. 233 * problem with some panels.
218 */ 234 */
219 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && 235 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
220 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & 236 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
221 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { 237 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
222 /* We still have to force a switch to selected PPLL div thanks to 238 /* We still have to force a switch to selected PPLL div thanks to
223 * an XFree86 driver bug which will switch it away in some cases 239 * an XFree86 driver bug which will switch it away in some cases
224 * even when using UseFDev */ 240 * even when using UseFDev */
225 OUTREGP(CLOCK_CNTL_INDEX, 241 OUTREGP(CLOCK_CNTL_INDEX,
226 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, 242 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
227 ~PPLL_DIV_SEL_MASK); 243 ~PPLL_DIV_SEL_MASK);
228 radeon_pll_errata_after_index(rinfo); 244 radeon_pll_errata_after_index(rinfo);
229 radeon_pll_errata_after_data(rinfo); 245 radeon_pll_errata_after_data(rinfo);
230 return; 246 return;
231 } 247 }
232 } 248 }
233 #endif 249 #endif
234 if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return; 250 if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return;
235 251
236 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ 252 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
237 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); 253 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
238 254
239 /* Reset PPLL & enable atomic update */ 255 /* Reset PPLL & enable atomic update */
240 OUTPLLP(PPLL_CNTL, 256 OUTPLLP(PPLL_CNTL,
241 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, 257 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
242 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); 258 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
243 259
244 /* Switch to selected PPLL divider */ 260 /* Switch to selected PPLL divider */
245 OUTREGP(CLOCK_CNTL_INDEX, 261 OUTREGP(CLOCK_CNTL_INDEX,
246 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, 262 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
247 ~PPLL_DIV_SEL_MASK); 263 ~PPLL_DIV_SEL_MASK);
248 264
249 /* Set PPLL ref. div */ 265 /* Set PPLL ref. div */
250 if (rinfo->family == CHIP_FAMILY_R300 || 266 if (rinfo->family == CHIP_FAMILY_R300 ||
251 rinfo->family == CHIP_FAMILY_RS300 || 267 rinfo->family == CHIP_FAMILY_RS300 ||
252 rinfo->family == CHIP_FAMILY_R350 || 268 rinfo->family == CHIP_FAMILY_R350 ||
253 rinfo->family == CHIP_FAMILY_RV350) { 269 rinfo->family == CHIP_FAMILY_RV350) {
254 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { 270 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
255 /* When restoring console mode, use saved PPLL_REF_DIV 271 /* When restoring console mode, use saved PPLL_REF_DIV
256 * setting. 272 * setting.
257 */ 273 */
258 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); 274 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
259 } else { 275 } else {
260 /* R300 uses ref_div_acc field as real ref divider */ 276 /* R300 uses ref_div_acc field as real ref divider */
261 OUTPLLP(PPLL_REF_DIV, 277 OUTPLLP(PPLL_REF_DIV,
262 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), 278 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
263 ~R300_PPLL_REF_DIV_ACC_MASK); 279 ~R300_PPLL_REF_DIV_ACC_MASK);
264 } 280 }
265 } else 281 } else
266 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); 282 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
267 283
268 /* Set PPLL divider 3 & post divider*/ 284 /* Set PPLL divider 3 & post divider*/
269 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); 285 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
270 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); 286 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
271 287
272 /* Write update */ 288 /* Write update */
273 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) 289 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
274 ; 290 ;
275 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); 291 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
276 292
277 /* Wait read update complete */ 293 /* Wait read update complete */
278 /* FIXME: Certain revisions of R300 can't recover here. Not sure of 294 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
279 the cause yet, but this workaround will mask the problem for now. 295 the cause yet, but this workaround will mask the problem for now.
280 Other chips usually will pass at the very first test, so the 296 Other chips usually will pass at the very first test, so the
281 workaround shouldn't have any effect on them. */ 297 workaround shouldn't have any effect on them. */
282 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) 298 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
283 ; 299 ;
284 300
285 OUTPLL(HTOTAL_CNTL, 0); 301 OUTPLL(HTOTAL_CNTL, 0);
286 302
287 /* Clear reset & atomic update */ 303 /* Clear reset & atomic update */
288 OUTPLLP(PPLL_CNTL, 0, 304 OUTPLLP(PPLL_CNTL, 0,
289 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); 305 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
290 306
291 /* We may want some locking ... oh well */ 307 /* We may want some locking ... oh well */
292 udelay(5000); 308 udelay(5000);
293 309
294 /* Switch back VCLK source to PPLL */ 310 /* Switch back VCLK source to PPLL */
295 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); 311 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
296 } 312 }
297 313
298 typedef struct { 314 typedef struct {
299 u16 reg; 315 u16 reg;
300 u32 val; 316 u32 val;
301 } reg_val; 317 } reg_val;
302 318
303 #if 0 /* unused ? -> scheduled for removal */ 319 #if 0 /* unused ? -> scheduled for removal */
304 /* these common regs are cleared before mode setting so they do not 320 /* these common regs are cleared before mode setting so they do not
305 * interfere with anything 321 * interfere with anything
306 */ 322 */
307 static reg_val common_regs[] = { 323 static reg_val common_regs[] = {
308 { OVR_CLR, 0 }, 324 { OVR_CLR, 0 },
309 { OVR_WID_LEFT_RIGHT, 0 }, 325 { OVR_WID_LEFT_RIGHT, 0 },
310 { OVR_WID_TOP_BOTTOM, 0 }, 326 { OVR_WID_TOP_BOTTOM, 0 },
311 { OV0_SCALE_CNTL, 0 }, 327 { OV0_SCALE_CNTL, 0 },
312 { SUBPIC_CNTL, 0 }, 328 { SUBPIC_CNTL, 0 },
313 { VIPH_CONTROL, 0 }, 329 { VIPH_CONTROL, 0 },
314 { I2C_CNTL_1, 0 }, 330 { I2C_CNTL_1, 0 },
315 { GEN_INT_CNTL, 0 }, 331 { GEN_INT_CNTL, 0 },
316 { CAP0_TRIG_CNTL, 0 }, 332 { CAP0_TRIG_CNTL, 0 },
317 { CAP1_TRIG_CNTL, 0 }, 333 { CAP1_TRIG_CNTL, 0 },
318 }; 334 };
319 #endif /* 0 */ 335 #endif /* 0 */
320 336
321 void radeon_setmode(void) 337 void radeon_setmode(void)
322 { 338 {
323 struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); 339 struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
324 340
325 mode->crtc_gen_cntl = 0x03000200; 341 mode->crtc_gen_cntl = 0x03000200;
326 mode->crtc_ext_cntl = 0x00008048; 342 mode->crtc_ext_cntl = 0x00008048;
327 mode->dac_cntl = 0xff002100; 343 mode->dac_cntl = 0xff002100;
328 mode->crtc_h_total_disp = 0x4f0063; 344 mode->crtc_h_total_disp = 0x4f0063;
329 mode->crtc_h_sync_strt_wid = 0x8c02a2; 345 mode->crtc_h_sync_strt_wid = 0x8c02a2;
330 mode->crtc_v_total_disp = 0x01df020c; 346 mode->crtc_v_total_disp = 0x01df020c;
331 mode->crtc_v_sync_strt_wid = 0x8201ea; 347 mode->crtc_v_sync_strt_wid = 0x8201ea;
332 mode->crtc_pitch = 0x00500050; 348 mode->crtc_pitch = 0x00500050;
333 349
334 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); 350 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
335 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, 351 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
336 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); 352 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
337 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); 353 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
338 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); 354 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
339 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); 355 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
340 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); 356 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
341 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); 357 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
342 OUTREG(CRTC_OFFSET, 0); 358 OUTREG(CRTC_OFFSET, 0);
343 OUTREG(CRTC_OFFSET_CNTL, 0); 359 OUTREG(CRTC_OFFSET_CNTL, 0);
344 OUTREG(CRTC_PITCH, mode->crtc_pitch); 360 OUTREG(CRTC_PITCH, mode->crtc_pitch);
345 361
346 mode->clk_cntl_index = 0x300; 362 mode->clk_cntl_index = 0x300;
347 mode->ppll_ref_div = 0xc; 363 mode->ppll_ref_div = 0xc;
348 mode->ppll_div_3 = 0x00030059; 364 mode->ppll_div_3 = 0x00030059;
349 365
350 radeon_write_pll_regs(rinfo, mode); 366 radeon_write_pll_regs(rinfo, mode);
351 } 367 }
352 368
369 static void set_pal(void)
370 {
371 int idx, val = 0;
372
373 for (idx = 0; idx < 256; idx++) {
374 OUTREG8(PALETTE_INDEX, idx);
375 OUTREG(PALETTE_DATA, val);
376 val += 0x00010101;
377 }
378 }
379
380 void radeon_setmode_9200(int vesa_idx, int bpp)
381 {
382 struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
383
384 mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN;
385 mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON;
386 mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN;
387 mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN;
388
389 switch (bpp) {
390 case 24:
391 mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */
392 #if defined(__BIG_ENDIAN)
393 mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
394 mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
395 #endif
396 break;
397 case 16:
398 mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */
399 #if defined(__BIG_ENDIAN)
400 mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
401 mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
402 #endif
403 break;
404 default:
405 mode->crtc_gen_cntl |= 0x2 << 8; /* palette */
406 mode->surface_cntl = 0x00000000;
407 break;
408 }
409
410 switch (vesa_idx) {
411 case RES_MODE_1280x1024:
412 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280);
413 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024);
414 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3);
415 #if defined(CONFIG_RADEON_VREFRESH_75HZ)
416 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18);
417 mode->ppll_div_3 = 0x00010078;
418 #else /* default @ 60 Hz */
419 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14);
420 mode->ppll_div_3 = 0x00010060;
421 #endif
422 /*
423 * for this mode pitch expands to the same value for 32, 16 and 8 bpp,
424 * so we set it here once only.
425 */
426 mode->crtc_pitch = RADEON_CRT_PITCH(1280,32);
427 switch (bpp) {
428 case 24:
429 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16);
430 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32);
431 break;
432 case 16:
433 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16);
434 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16);
435 break;
436 default: /* 8 bpp */
437 mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16);
438 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8);
439 break;
440 }
441 break;
442 case RES_MODE_1024x768:
443 #if defined(CONFIG_RADEON_VREFRESH_75HZ)
444 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024);
445 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12);
446 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768);
447 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3);
448 mode->ppll_div_3 = 0x0002008c;
449 #else /* @ 60 Hz */
450 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024);
451 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL;
452 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768);
453 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL;
454 mode->ppll_div_3 = 0x00020074;
455 #endif
456 /* also same pitch value for 32, 16 and 8 bpp */
457 mode->crtc_pitch = RADEON_CRT_PITCH(1024,32);
458 switch (bpp) {
459 case 24:
460 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16);
461 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32);
462 break;
463 case 16:
464 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16);
465 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16);
466 break;
467 default: /* 8 bpp */
468 mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
469 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8);
470 break;
471 }
472 break;
473 case RES_MODE_800x600:
474 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800);
475 #if defined(CONFIG_RADEON_VREFRESH_75HZ)
476 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10);
477 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600);
478 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3);
479 mode->ppll_div_3 = 0x000300b0;
480 #else /* @ 60 Hz */
481 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16);
482 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600);
483 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4);
484 mode->ppll_div_3 = 0x0003008e;
485 #endif
486 switch (bpp) {
487 case 24:
488 mode->crtc_pitch = RADEON_CRT_PITCH(832,32);
489 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16);
490 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32);
491 break;
492 case 16:
493 mode->crtc_pitch = RADEON_CRT_PITCH(896,16);
494 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16);
495 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16);
496 break;
497 default: /* 8 bpp */
498 mode->crtc_pitch = RADEON_CRT_PITCH(1024,8);
499 mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
500 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8);
501 break;
502 }
503 break;
504 default: /* RES_MODE_640x480 */
505 #if defined(CONFIG_RADEON_VREFRESH_75HZ)
506 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640);
507 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL;
508 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480);
509 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL;
510 mode->ppll_div_3 = 0x00030070;
511 #else /* @ 60 Hz */
512 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640);
513 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL;
514 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480);
515 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL;
516 mode->ppll_div_3 = 0x00030059;
517 #endif
518 /* also same pitch value for 32, 16 and 8 bpp */
519 mode->crtc_pitch = RADEON_CRT_PITCH(640,32);
520 switch (bpp) {
521 case 24:
522 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16);
523 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32);
524 break;
525 case 16:
526 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16);
527 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16);
528 break;
529 default: /* 8 bpp */
530 mode->crtc_offset_cntl = 0x00000000;
531 break;
532 }
533 break;
534 }
535
536 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
537 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
538 (CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
539 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
540 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
541 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
542 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
543 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
544 OUTREG(CRTC_OFFSET, 0);
545 OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl);
546 OUTREG(CRTC_PITCH, mode->crtc_pitch);
547 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
548
549 mode->clk_cntl_index = 0x300;
550 mode->ppll_ref_div = 0xc;
551
552 radeon_write_pll_regs(rinfo, mode);
553
554 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
555 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
556 OUTREG(SURFACE0_INFO, mode->surf_info[0]);
557 OUTREG(SURFACE0_LOWER_BOUND, 0);
558 OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]);
559 OUTREG(SURFACE_CNTL, mode->surface_cntl);
560
561 if (bpp > 8)
562 set_pal();
563
564 free(mode);
565 }
566
353 #include "../bios_emulator/include/biosemu.h" 567 #include "../bios_emulator/include/biosemu.h"
354 extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp); 568 extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp);
355 569
356 int radeon_probe(struct radeonfb_info *rinfo) 570 int radeon_probe(struct radeonfb_info *rinfo)
357 { 571 {
358 pci_dev_t pdev; 572 pci_dev_t pdev;
359 u16 did; 573 u16 did;
360 574
361 pdev = pci_find_devices(ati_radeon_pci_ids, 0); 575 pdev = pci_find_devices(ati_radeon_pci_ids, 0);
362 576
363 if (pdev != -1) { 577 if (pdev != -1) {
364 pci_read_config_word(pdev, PCI_DEVICE_ID, &did); 578 pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
365 printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n", 579 printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n",
366 PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff, 580 PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff,
367 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); 581 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
368 582
369 strcpy(rinfo->name, "ATI Radeon"); 583 strcpy(rinfo->name, "ATI Radeon");
370 rinfo->pdev.vendor = PCI_VENDOR_ID_ATI; 584 rinfo->pdev.vendor = PCI_VENDOR_ID_ATI;
371 rinfo->pdev.device = did; 585 rinfo->pdev.device = did;
372 rinfo->family = get_radeon_id_family(rinfo->pdev.device); 586 rinfo->family = get_radeon_id_family(rinfo->pdev.device);
373 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, 587 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0,
374 &rinfo->fb_base_phys); 588 &rinfo->fb_base_phys);
375 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2, 589 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2,
376 &rinfo->mmio_base_phys); 590 &rinfo->mmio_base_phys);
377 rinfo->fb_base_phys &= 0xfffff000; 591 rinfo->fb_base_phys &= 0xfffff000;
378 rinfo->mmio_base_phys &= ~0x04; 592 rinfo->mmio_base_phys &= ~0x04;
379 593
380 rinfo->mmio_base = (void *)rinfo->mmio_base_phys; 594 rinfo->mmio_base = (void *)rinfo->mmio_base_phys;
381 DPRINT("rinfo->mmio_base = 0x%x\n",rinfo->mmio_base); 595 DPRINT("rinfo->mmio_base = 0x%x\n",rinfo->mmio_base);
382 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; 596 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
383 DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base); 597 DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base);
384 /* PostBIOS with x86 emulater */ 598 /* PostBIOS with x86 emulater */
385 BootVideoCardBIOS(pdev, NULL, 0); 599 BootVideoCardBIOS(pdev, NULL, 0);
386 600
387 /* 601 /*
388 * Check for errata 602 * Check for errata
389 * (These will be added in the future for the chipfamily 603 * (These will be added in the future for the chipfamily
390 * R300, RV200, RS200, RV100, RS100.) 604 * R300, RV200, RS200, RV100, RS100.)
391 */ 605 */
392 606
393 /* Get VRAM size and type */ 607 /* Get VRAM size and type */
394 radeon_identify_vram(rinfo); 608 radeon_identify_vram(rinfo);
395 609
396 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, 610 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM,
397 rinfo->video_ram); 611 rinfo->video_ram);
398 rinfo->fb_base = (void *)rinfo->fb_base_phys; 612 rinfo->fb_base = (void *)rinfo->fb_base_phys;
399 613
400 DPRINT("Radeon: framebuffer base phy address 0x%08x," \ 614 DPRINT("Radeon: framebuffer base phy address 0x%08x," \
401 "MMIO base phy address 0x%08x," \ 615 "MMIO base phy address 0x%08x," \
402 "framebuffer local base 0x%08x.\n ", 616 "framebuffer local base 0x%08x.\n ",
403 rinfo->fb_base_phys, rinfo->mmio_base_phys, 617 rinfo->fb_base_phys, rinfo->mmio_base_phys,
404 rinfo->fb_local_base); 618 rinfo->fb_local_base);
405 619
406 return 0; 620 return 0;
407 } 621 }
408 return -1; 622 return -1;
409 } 623 }
410 624
411 /* 625 /*
412 * The Graphic Device 626 * The Graphic Device
413 */ 627 */
414 GraphicDevice ctfb; 628 GraphicDevice ctfb;
415 629
416 #define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */ 630 #define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */
417 #define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */ 631 #define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */
418 #define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */ 632 #define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */
419 #define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */ 633 #define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */
420 634
421 void *video_hw_init(void) 635 void *video_hw_init(void)
422 { 636 {
423 GraphicDevice *pGD = (GraphicDevice *) & ctfb; 637 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
424 int i;
425 u32 *vm; 638 u32 *vm;
639 char *penv;
640 unsigned long t1, hsynch, vsynch;
641 int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
642 struct ctfb_res_modes *res_mode;
643 struct ctfb_res_modes var_mode;
426 644
427 rinfo = malloc(sizeof(struct radeonfb_info)); 645 rinfo = malloc(sizeof(struct radeonfb_info));
428 646
647 printf("Video: ");
429 if(radeon_probe(rinfo)) { 648 if(radeon_probe(rinfo)) {
430 printf("No radeon video card found!\n"); 649 printf("No radeon video card found!\n");
431 return NULL; 650 return NULL;
432 } 651 }
433 652
653 tmp = 0;
654
655 videomode = CFG_DEFAULT_VIDEO_MODE;
656 /* get video mode via environment */
657 if ((penv = getenv ("videomode")) != NULL) {
658 /* deceide if it is a string */
659 if (penv[0] <= '9') {
660 videomode = (int) simple_strtoul (penv, NULL, 16);
661 tmp = 1;
662 }
663 } else {
664 tmp = 1;
665 }
666 if (tmp) {
667 /* parameter are vesa modes */
668 /* search params */
669 for (i = 0; i < VESA_MODES_COUNT; i++) {
670 if (vesa_modes[i].vesanr == videomode)
671 break;
672 }
673 if (i == VESA_MODES_COUNT) {
674 printf ("no VESA Mode found, switching to mode 0x%x ", CFG_DEFAULT_VIDEO_MODE);
675 i = 0;
676 }
677 res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex];
678 bits_per_pixel = vesa_modes[i].bits_per_pixel;
679 vesa_idx = vesa_modes[i].resindex;
680 } else {
681 res_mode = (struct ctfb_res_modes *) &var_mode;
682 bits_per_pixel = video_get_params (res_mode, penv);
683 }
684
685 /* calculate hsynch and vsynch freq (info only) */
686 t1 = (res_mode->left_margin + res_mode->xres +
687 res_mode->right_margin + res_mode->hsync_len) / 8;
688 t1 *= 8;
689 t1 *= res_mode->pixclock;
690 t1 /= 1000;
691 hsynch = 1000000000L / t1;
692 t1 *= (res_mode->upper_margin + res_mode->yres +
693 res_mode->lower_margin + res_mode->vsync_len);
694 t1 /= 1000;
695 vsynch = 1000000000L / t1;
696
434 /* fill in Graphic device struct */ 697 /* fill in Graphic device struct */
435 sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", 640, 698 sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
436 480, 16, (1000 / 1000), 699 res_mode->yres, bits_per_pixel, (hsynch / 1000),
437 (2000 / 1000)); 700 (vsynch / 1000));
438 printf ("%s\n", pGD->modeIdent); 701 printf ("%s\n", pGD->modeIdent);
702 pGD->winSizeX = res_mode->xres;
703 pGD->winSizeY = res_mode->yres;
704 pGD->plnSizeX = res_mode->xres;
705 pGD->plnSizeY = res_mode->yres;
439 706
440 pGD->winSizeX = 640; 707 switch (bits_per_pixel) {
441 pGD->winSizeY = 480; 708 case 24:
442 pGD->plnSizeX = 640; 709 pGD->gdfBytesPP = 4;
443 pGD->plnSizeY = 480; 710 pGD->gdfIndex = GDF_32BIT_X888RGB;
711 if (res_mode->xres == 800) {
712 pGD->winSizeX = 832;
713 pGD->plnSizeX = 832;
714 }
715 break;
716 case 16:
717 pGD->gdfBytesPP = 2;
718 pGD->gdfIndex = GDF_16BIT_565RGB;
719 if (res_mode->xres == 800) {
720 pGD->winSizeX = 896;
721 pGD->plnSizeX = 896;
722 }
723 break;
724 default:
725 if (res_mode->xres == 800) {
726 pGD->winSizeX = 1024;
727 pGD->plnSizeX = 1024;
728 }
729 pGD->gdfBytesPP = 1;
730 pGD->gdfIndex = GDF__8BIT_INDEX;
731 break;
732 }
444 733
445 pGD->gdfBytesPP = 1;
446 pGD->gdfIndex = GDF__8BIT_INDEX;
447
448 pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS; 734 pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS;
449 pGD->pciBase = rinfo->fb_base_phys; 735 pGD->pciBase = rinfo->fb_base_phys;
450 pGD->frameAdrs = rinfo->fb_base_phys; 736 pGD->frameAdrs = rinfo->fb_base_phys;
451 pGD->memSize = 64 * 1024 * 1024; 737 pGD->memSize = 64 * 1024 * 1024;
452 738
453 /* Cursor Start Address */ 739 /* Cursor Start Address */
454 pGD->dprBase = 740 pGD->dprBase =
455 (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + rinfo->fb_base_phys; 741 (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + rinfo->fb_base_phys;
456 if ((pGD->dprBase & 0x0fff) != 0) { 742 if ((pGD->dprBase & 0x0fff) != 0) {
457 /* allign it */ 743 /* allign it */
458 pGD->dprBase &= 0xfffff000; 744 pGD->dprBase &= 0xfffff000;
459 pGD->dprBase += 0x00001000; 745 pGD->dprBase += 0x00001000;
460 } 746 }
461 DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase, 747 DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
462 PATTERN_ADR); 748 PATTERN_ADR);
463 pGD->vprBase = rinfo->fb_base_phys; /* Dummy */ 749 pGD->vprBase = rinfo->fb_base_phys; /* Dummy */
464 pGD->cprBase = rinfo->fb_base_phys; /* Dummy */ 750 pGD->cprBase = rinfo->fb_base_phys; /* Dummy */
465 /* set up Hardware */ 751 /* set up Hardware */
466 752
467 /* Clear video memory */ 753 /* Clear video memory (only visible screen area) */
468 i = pGD->memSize / 4; 754 i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4;
469 vm = (unsigned int *) pGD->pciBase; 755 vm = (unsigned int *) pGD->pciBase;
470 while (i--) 756 while (i--)
471 *vm++ = 0; 757 *vm++ = 0;
472 /*SetDrawingEngine (bits_per_pixel);*/ 758 /*SetDrawingEngine (bits_per_pixel);*/
473 759
474 radeon_setmode(); 760 if (rinfo->family == CHIP_FAMILY_RV280)
761 radeon_setmode_9200(vesa_idx, bits_per_pixel);
762 else
763 radeon_setmode();
475 764
476 return ((void *) pGD); 765 return ((void *) pGD);
477 } 766 }
478 767
479 void video_set_lut (unsigned int index, /* color number */ 768 void video_set_lut (unsigned int index, /* color number */
480 unsigned char r, /* red */ 769 unsigned char r, /* red */
481 unsigned char g, /* green */ 770 unsigned char g, /* green */
482 unsigned char b /* blue */ 771 unsigned char b /* blue */
483 ) 772 )
484 { 773 {
485 OUTREG(PALETTE_INDEX, index); 774 OUTREG(PALETTE_INDEX, index);
1 #ifndef _RADEON_H 1 #ifndef _RADEON_H
2 #define _RADEON_H 2 #define _RADEON_H
3 3
4 4
5 #define RADEON_REGSIZE 0x4000 5 #define RADEON_REGSIZE 0x4000
6 6
7 7
8 #define MM_INDEX 0x0000 8 #define MM_INDEX 0x0000
9 #define MM_DATA 0x0004 9 #define MM_DATA 0x0004
10 #define BUS_CNTL 0x0030 10 #define BUS_CNTL 0x0030
11 #define HI_STAT 0x004C 11 #define HI_STAT 0x004C
12 #define BUS_CNTL1 0x0034 12 #define BUS_CNTL1 0x0034
13 #define I2C_CNTL_1 0x0094 13 #define I2C_CNTL_1 0x0094
14 #define CONFIG_CNTL 0x00E0 14 #define CONFIG_CNTL 0x00E0
15 #define CONFIG_MEMSIZE 0x00F8 15 #define CONFIG_MEMSIZE 0x00F8
16 #define CONFIG_APER_0_BASE 0x0100 16 #define CONFIG_APER_0_BASE 0x0100
17 #define CONFIG_APER_1_BASE 0x0104 17 #define CONFIG_APER_1_BASE 0x0104
18 #define CONFIG_APER_SIZE 0x0108 18 #define CONFIG_APER_SIZE 0x0108
19 #define CONFIG_REG_1_BASE 0x010C 19 #define CONFIG_REG_1_BASE 0x010C
20 #define CONFIG_REG_APER_SIZE 0x0110 20 #define CONFIG_REG_APER_SIZE 0x0110
21 #define PAD_AGPINPUT_DELAY 0x0164 21 #define PAD_AGPINPUT_DELAY 0x0164
22 #define PAD_CTLR_STRENGTH 0x0168 22 #define PAD_CTLR_STRENGTH 0x0168
23 #define PAD_CTLR_UPDATE 0x016C 23 #define PAD_CTLR_UPDATE 0x016C
24 #define PAD_CTLR_MISC 0x0aa0 24 #define PAD_CTLR_MISC 0x0aa0
25 #define AGP_CNTL 0x0174 25 #define AGP_CNTL 0x0174
26 #define BM_STATUS 0x0160 26 #define BM_STATUS 0x0160
27 #define CAP0_TRIG_CNTL 0x0950 27 #define CAP0_TRIG_CNTL 0x0950
28 #define CAP1_TRIG_CNTL 0x09c0 28 #define CAP1_TRIG_CNTL 0x09c0
29 #define VIPH_CONTROL 0x0C40 29 #define VIPH_CONTROL 0x0C40
30 #define VENDOR_ID 0x0F00 30 #define VENDOR_ID 0x0F00
31 #define DEVICE_ID 0x0F02 31 #define DEVICE_ID 0x0F02
32 #define COMMAND 0x0F04 32 #define COMMAND 0x0F04
33 #define STATUS 0x0F06 33 #define STATUS 0x0F06
34 #define REVISION_ID 0x0F08 34 #define REVISION_ID 0x0F08
35 #define REGPROG_INF 0x0F09 35 #define REGPROG_INF 0x0F09
36 #define SUB_CLASS 0x0F0A 36 #define SUB_CLASS 0x0F0A
37 #define BASE_CODE 0x0F0B 37 #define BASE_CODE 0x0F0B
38 #define CACHE_LINE 0x0F0C 38 #define CACHE_LINE 0x0F0C
39 #define LATENCY 0x0F0D 39 #define LATENCY 0x0F0D
40 #define HEADER 0x0F0E 40 #define HEADER 0x0F0E
41 #define BIST 0x0F0F 41 #define BIST 0x0F0F
42 #define REG_MEM_BASE 0x0F10 42 #define REG_MEM_BASE 0x0F10
43 #define REG_IO_BASE 0x0F14 43 #define REG_IO_BASE 0x0F14
44 #define REG_REG_BASE 0x0F18 44 #define REG_REG_BASE 0x0F18
45 #define ADAPTER_ID 0x0F2C 45 #define ADAPTER_ID 0x0F2C
46 #define BIOS_ROM 0x0F30 46 #define BIOS_ROM 0x0F30
47 #define CAPABILITIES_PTR 0x0F34 47 #define CAPABILITIES_PTR 0x0F34
48 #define INTERRUPT_LINE 0x0F3C 48 #define INTERRUPT_LINE 0x0F3C
49 #define INTERRUPT_PIN 0x0F3D 49 #define INTERRUPT_PIN 0x0F3D
50 #define MIN_GRANT 0x0F3E 50 #define MIN_GRANT 0x0F3E
51 #define MAX_LATENCY 0x0F3F 51 #define MAX_LATENCY 0x0F3F
52 #define ADAPTER_ID_W 0x0F4C 52 #define ADAPTER_ID_W 0x0F4C
53 #define PMI_CAP_ID 0x0F50 53 #define PMI_CAP_ID 0x0F50
54 #define PMI_NXT_CAP_PTR 0x0F51 54 #define PMI_NXT_CAP_PTR 0x0F51
55 #define PMI_PMC_REG 0x0F52 55 #define PMI_PMC_REG 0x0F52
56 #define PM_STATUS 0x0F54 56 #define PM_STATUS 0x0F54
57 #define PMI_DATA 0x0F57 57 #define PMI_DATA 0x0F57
58 #define AGP_CAP_ID 0x0F58 58 #define AGP_CAP_ID 0x0F58
59 #define AGP_STATUS 0x0F5C 59 #define AGP_STATUS 0x0F5C
60 #define AGP_COMMAND 0x0F60 60 #define AGP_COMMAND 0x0F60
61 #define AIC_CTRL 0x01D0 61 #define AIC_CTRL 0x01D0
62 #define AIC_STAT 0x01D4 62 #define AIC_STAT 0x01D4
63 #define AIC_PT_BASE 0x01D8 63 #define AIC_PT_BASE 0x01D8
64 #define AIC_LO_ADDR 0x01DC 64 #define AIC_LO_ADDR 0x01DC
65 #define AIC_HI_ADDR 0x01E0 65 #define AIC_HI_ADDR 0x01E0
66 #define AIC_TLB_ADDR 0x01E4 66 #define AIC_TLB_ADDR 0x01E4
67 #define AIC_TLB_DATA 0x01E8 67 #define AIC_TLB_DATA 0x01E8
68 #define DAC_CNTL 0x0058 68 #define DAC_CNTL 0x0058
69 #define DAC_CNTL2 0x007c 69 #define DAC_CNTL2 0x007c
70 #define CRTC_GEN_CNTL 0x0050 70 #define CRTC_GEN_CNTL 0x0050
71 #define MEM_CNTL 0x0140 71 #define MEM_CNTL 0x0140
72 #define MC_CNTL 0x0140 72 #define MC_CNTL 0x0140
73 #define EXT_MEM_CNTL 0x0144 73 #define EXT_MEM_CNTL 0x0144
74 #define MC_TIMING_CNTL 0x0144 74 #define MC_TIMING_CNTL 0x0144
75 #define MC_AGP_LOCATION 0x014C 75 #define MC_AGP_LOCATION 0x014C
76 #define MEM_IO_CNTL_A0 0x0178 76 #define MEM_IO_CNTL_A0 0x0178
77 #define MEM_REFRESH_CNTL 0x0178 77 #define MEM_REFRESH_CNTL 0x0178
78 #define MEM_INIT_LATENCY_TIMER 0x0154 78 #define MEM_INIT_LATENCY_TIMER 0x0154
79 #define MC_INIT_GFX_LAT_TIMER 0x0154 79 #define MC_INIT_GFX_LAT_TIMER 0x0154
80 #define MEM_SDRAM_MODE_REG 0x0158 80 #define MEM_SDRAM_MODE_REG 0x0158
81 #define AGP_BASE 0x0170 81 #define AGP_BASE 0x0170
82 #define MEM_IO_CNTL_A1 0x017C 82 #define MEM_IO_CNTL_A1 0x017C
83 #define MC_READ_CNTL_AB 0x017C 83 #define MC_READ_CNTL_AB 0x017C
84 #define MEM_IO_CNTL_B0 0x0180 84 #define MEM_IO_CNTL_B0 0x0180
85 #define MC_INIT_MISC_LAT_TIMER 0x0180 85 #define MC_INIT_MISC_LAT_TIMER 0x0180
86 #define MEM_IO_CNTL_B1 0x0184 86 #define MEM_IO_CNTL_B1 0x0184
87 #define MC_IOPAD_CNTL 0x0184 87 #define MC_IOPAD_CNTL 0x0184
88 #define MC_DEBUG 0x0188 88 #define MC_DEBUG 0x0188
89 #define MC_STATUS 0x0150 89 #define MC_STATUS 0x0150
90 #define MEM_IO_OE_CNTL 0x018C 90 #define MEM_IO_OE_CNTL 0x018C
91 #define MC_CHIP_IO_OE_CNTL_AB 0x018C 91 #define MC_CHIP_IO_OE_CNTL_AB 0x018C
92 #define MC_FB_LOCATION 0x0148 92 #define MC_FB_LOCATION 0x0148
93 /* #define MC_FB_LOCATION 0x0188 */ 93 /* #define MC_FB_LOCATION 0x0188 */
94 #define HOST_PATH_CNTL 0x0130 94 #define HOST_PATH_CNTL 0x0130
95 #define MEM_VGA_WP_SEL 0x0038 95 #define MEM_VGA_WP_SEL 0x0038
96 #define MEM_VGA_RP_SEL 0x003C 96 #define MEM_VGA_RP_SEL 0x003C
97 #define HDP_DEBUG 0x0138 97 #define HDP_DEBUG 0x0138
98 #define SW_SEMAPHORE 0x013C 98 #define SW_SEMAPHORE 0x013C
99 #define CRTC2_GEN_CNTL 0x03f8 99 #define CRTC2_GEN_CNTL 0x03f8
100 #define CRTC2_DISPLAY_BASE_ADDR 0x033c 100 #define CRTC2_DISPLAY_BASE_ADDR 0x033c
101 #define SURFACE_CNTL 0x0B00 101 #define SURFACE_CNTL 0x0B00
102 #define SURFACE0_LOWER_BOUND 0x0B04 102 #define SURFACE0_LOWER_BOUND 0x0B04
103 #define SURFACE1_LOWER_BOUND 0x0B14 103 #define SURFACE1_LOWER_BOUND 0x0B14
104 #define SURFACE2_LOWER_BOUND 0x0B24 104 #define SURFACE2_LOWER_BOUND 0x0B24
105 #define SURFACE3_LOWER_BOUND 0x0B34 105 #define SURFACE3_LOWER_BOUND 0x0B34
106 #define SURFACE4_LOWER_BOUND 0x0B44 106 #define SURFACE4_LOWER_BOUND 0x0B44
107 #define SURFACE5_LOWER_BOUND 0x0B54 107 #define SURFACE5_LOWER_BOUND 0x0B54
108 #define SURFACE6_LOWER_BOUND 0x0B64 108 #define SURFACE6_LOWER_BOUND 0x0B64
109 #define SURFACE7_LOWER_BOUND 0x0B74 109 #define SURFACE7_LOWER_BOUND 0x0B74
110 #define SURFACE0_UPPER_BOUND 0x0B08 110 #define SURFACE0_UPPER_BOUND 0x0B08
111 #define SURFACE1_UPPER_BOUND 0x0B18 111 #define SURFACE1_UPPER_BOUND 0x0B18
112 #define SURFACE2_UPPER_BOUND 0x0B28 112 #define SURFACE2_UPPER_BOUND 0x0B28
113 #define SURFACE3_UPPER_BOUND 0x0B38 113 #define SURFACE3_UPPER_BOUND 0x0B38
114 #define SURFACE4_UPPER_BOUND 0x0B48 114 #define SURFACE4_UPPER_BOUND 0x0B48
115 #define SURFACE5_UPPER_BOUND 0x0B58 115 #define SURFACE5_UPPER_BOUND 0x0B58
116 #define SURFACE6_UPPER_BOUND 0x0B68 116 #define SURFACE6_UPPER_BOUND 0x0B68
117 #define SURFACE7_UPPER_BOUND 0x0B78 117 #define SURFACE7_UPPER_BOUND 0x0B78
118 #define SURFACE0_INFO 0x0B0C 118 #define SURFACE0_INFO 0x0B0C
119 #define SURFACE1_INFO 0x0B1C 119 #define SURFACE1_INFO 0x0B1C
120 #define SURFACE2_INFO 0x0B2C 120 #define SURFACE2_INFO 0x0B2C
121 #define SURFACE3_INFO 0x0B3C 121 #define SURFACE3_INFO 0x0B3C
122 #define SURFACE4_INFO 0x0B4C 122 #define SURFACE4_INFO 0x0B4C
123 #define SURFACE5_INFO 0x0B5C 123 #define SURFACE5_INFO 0x0B5C
124 #define SURFACE6_INFO 0x0B6C 124 #define SURFACE6_INFO 0x0B6C
125 #define SURFACE7_INFO 0x0B7C 125 #define SURFACE7_INFO 0x0B7C
126 #define SURFACE_ACCESS_FLAGS 0x0BF8 126 #define SURFACE_ACCESS_FLAGS 0x0BF8
127 #define SURFACE_ACCESS_CLR 0x0BFC 127 #define SURFACE_ACCESS_CLR 0x0BFC
128 #define GEN_INT_CNTL 0x0040 128 #define GEN_INT_CNTL 0x0040
129 #define GEN_INT_STATUS 0x0044 129 #define GEN_INT_STATUS 0x0044
130 #define CRTC_EXT_CNTL 0x0054 130 #define CRTC_EXT_CNTL 0x0054
131 #define RB3D_CNTL 0x1C3C 131 #define RB3D_CNTL 0x1C3C
132 #define WAIT_UNTIL 0x1720 132 #define WAIT_UNTIL 0x1720
133 #define ISYNC_CNTL 0x1724 133 #define ISYNC_CNTL 0x1724
134 #define RBBM_GUICNTL 0x172C 134 #define RBBM_GUICNTL 0x172C
135 #define RBBM_STATUS 0x0E40 135 #define RBBM_STATUS 0x0E40
136 #define RBBM_STATUS_alt_1 0x1740 136 #define RBBM_STATUS_alt_1 0x1740
137 #define RBBM_CNTL 0x00EC 137 #define RBBM_CNTL 0x00EC
138 #define RBBM_CNTL_alt_1 0x0E44 138 #define RBBM_CNTL_alt_1 0x0E44
139 #define RBBM_SOFT_RESET 0x00F0 139 #define RBBM_SOFT_RESET 0x00F0
140 #define RBBM_SOFT_RESET_alt_1 0x0E48 140 #define RBBM_SOFT_RESET_alt_1 0x0E48
141 #define NQWAIT_UNTIL 0x0E50 141 #define NQWAIT_UNTIL 0x0E50
142 #define RBBM_DEBUG 0x0E6C 142 #define RBBM_DEBUG 0x0E6C
143 #define RBBM_CMDFIFO_ADDR 0x0E70 143 #define RBBM_CMDFIFO_ADDR 0x0E70
144 #define RBBM_CMDFIFO_DATAL 0x0E74 144 #define RBBM_CMDFIFO_DATAL 0x0E74
145 #define RBBM_CMDFIFO_DATAH 0x0E78 145 #define RBBM_CMDFIFO_DATAH 0x0E78
146 #define RBBM_CMDFIFO_STAT 0x0E7C 146 #define RBBM_CMDFIFO_STAT 0x0E7C
147 #define CRTC_STATUS 0x005C 147 #define CRTC_STATUS 0x005C
148 #define GPIO_VGA_DDC 0x0060 148 #define GPIO_VGA_DDC 0x0060
149 #define GPIO_DVI_DDC 0x0064 149 #define GPIO_DVI_DDC 0x0064
150 #define GPIO_MONID 0x0068 150 #define GPIO_MONID 0x0068
151 #define GPIO_CRT2_DDC 0x006c 151 #define GPIO_CRT2_DDC 0x006c
152 #define PALETTE_INDEX 0x00B0 152 #define PALETTE_INDEX 0x00B0
153 #define PALETTE_DATA 0x00B4 153 #define PALETTE_DATA 0x00B4
154 #define PALETTE_30_DATA 0x00B8 154 #define PALETTE_30_DATA 0x00B8
155 #define CRTC_H_TOTAL_DISP 0x0200 155 #define CRTC_H_TOTAL_DISP 0x0200
156 #define CRTC_H_SYNC_STRT_WID 0x0204 156 #define CRTC_H_SYNC_STRT_WID 0x0204
157 #define CRTC_H_SYNC_POL (1 << 23)
157 #define CRTC_V_TOTAL_DISP 0x0208 158 #define CRTC_V_TOTAL_DISP 0x0208
158 #define CRTC_V_SYNC_STRT_WID 0x020C 159 #define CRTC_V_SYNC_STRT_WID 0x020C
160 #define CRTC_V_SYNC_POL (1 << 23)
159 #define CRTC_VLINE_CRNT_VLINE 0x0210 161 #define CRTC_VLINE_CRNT_VLINE 0x0210
160 #define CRTC_CRNT_FRAME 0x0214 162 #define CRTC_CRNT_FRAME 0x0214
161 #define CRTC_GUI_TRIG_VLINE 0x0218 163 #define CRTC_GUI_TRIG_VLINE 0x0218
162 #define CRTC_DEBUG 0x021C 164 #define CRTC_DEBUG 0x021C
163 #define CRTC_OFFSET_RIGHT 0x0220 165 #define CRTC_OFFSET_RIGHT 0x0220
164 #define CRTC_OFFSET 0x0224 166 #define CRTC_OFFSET 0x0224
165 #define CRTC_OFFSET_CNTL 0x0228 167 #define CRTC_OFFSET_CNTL 0x0228
166 #define CRTC_PITCH 0x022C 168 #define CRTC_PITCH 0x022C
167 #define OVR_CLR 0x0230 169 #define OVR_CLR 0x0230
168 #define OVR_WID_LEFT_RIGHT 0x0234 170 #define OVR_WID_LEFT_RIGHT 0x0234
169 #define OVR_WID_TOP_BOTTOM 0x0238 171 #define OVR_WID_TOP_BOTTOM 0x0238
170 #define DISPLAY_BASE_ADDR 0x023C 172 #define DISPLAY_BASE_ADDR 0x023C
171 #define SNAPSHOT_VH_COUNTS 0x0240 173 #define SNAPSHOT_VH_COUNTS 0x0240
172 #define SNAPSHOT_F_COUNT 0x0244 174 #define SNAPSHOT_F_COUNT 0x0244
173 #define N_VIF_COUNT 0x0248 175 #define N_VIF_COUNT 0x0248
174 #define SNAPSHOT_VIF_COUNT 0x024C 176 #define SNAPSHOT_VIF_COUNT 0x024C
175 #define FP_CRTC_H_TOTAL_DISP 0x0250 177 #define FP_CRTC_H_TOTAL_DISP 0x0250
176 #define FP_CRTC_V_TOTAL_DISP 0x0254 178 #define FP_CRTC_V_TOTAL_DISP 0x0254
177 #define CRT_CRTC_H_SYNC_STRT_WID 0x0258 179 #define CRT_CRTC_H_SYNC_STRT_WID 0x0258
178 #define CRT_CRTC_V_SYNC_STRT_WID 0x025C 180 #define CRT_CRTC_V_SYNC_STRT_WID 0x025C
179 #define CUR_OFFSET 0x0260 181 #define CUR_OFFSET 0x0260
180 #define CUR_HORZ_VERT_POSN 0x0264 182 #define CUR_HORZ_VERT_POSN 0x0264
181 #define CUR_HORZ_VERT_OFF 0x0268 183 #define CUR_HORZ_VERT_OFF 0x0268
182 #define CUR_CLR0 0x026C 184 #define CUR_CLR0 0x026C
183 #define CUR_CLR1 0x0270 185 #define CUR_CLR1 0x0270
184 #define FP_HORZ_VERT_ACTIVE 0x0278 186 #define FP_HORZ_VERT_ACTIVE 0x0278
185 #define CRTC_MORE_CNTL 0x027C 187 #define CRTC_MORE_CNTL 0x027C
186 #define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) 188 #define CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
187 #define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) 189 #define CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
188 #define DAC_EXT_CNTL 0x0280 190 #define DAC_EXT_CNTL 0x0280
189 #define FP_GEN_CNTL 0x0284 191 #define FP_GEN_CNTL 0x0284
190 #define FP_HORZ_STRETCH 0x028C 192 #define FP_HORZ_STRETCH 0x028C
191 #define FP_VERT_STRETCH 0x0290 193 #define FP_VERT_STRETCH 0x0290
192 #define FP_H_SYNC_STRT_WID 0x02C4 194 #define FP_H_SYNC_STRT_WID 0x02C4
193 #define FP_V_SYNC_STRT_WID 0x02C8 195 #define FP_V_SYNC_STRT_WID 0x02C8
194 #define AUX_WINDOW_HORZ_CNTL 0x02D8 196 #define AUX_WINDOW_HORZ_CNTL 0x02D8
195 #define AUX_WINDOW_VERT_CNTL 0x02DC 197 #define AUX_WINDOW_VERT_CNTL 0x02DC
196 /* #define DDA_CONFIG 0x02e0 */ 198 /* #define DDA_CONFIG 0x02e0 */
197 /* #define DDA_ON_OFF 0x02e4 */ 199 /* #define DDA_ON_OFF 0x02e4 */
198 #define DVI_I2C_CNTL_1 0x02e4 200 #define DVI_I2C_CNTL_1 0x02e4
199 #define GRPH_BUFFER_CNTL 0x02F0 201 #define GRPH_BUFFER_CNTL 0x02F0
200 #define GRPH2_BUFFER_CNTL 0x03F0 202 #define GRPH2_BUFFER_CNTL 0x03F0
201 #define VGA_BUFFER_CNTL 0x02F4 203 #define VGA_BUFFER_CNTL 0x02F4
202 #define OV0_Y_X_START 0x0400 204 #define OV0_Y_X_START 0x0400
203 #define OV0_Y_X_END 0x0404 205 #define OV0_Y_X_END 0x0404
204 #define OV0_PIPELINE_CNTL 0x0408 206 #define OV0_PIPELINE_CNTL 0x0408
205 #define OV0_REG_LOAD_CNTL 0x0410 207 #define OV0_REG_LOAD_CNTL 0x0410
206 #define OV0_SCALE_CNTL 0x0420 208 #define OV0_SCALE_CNTL 0x0420
207 #define OV0_V_INC 0x0424 209 #define OV0_V_INC 0x0424
208 #define OV0_P1_V_ACCUM_INIT 0x0428 210 #define OV0_P1_V_ACCUM_INIT 0x0428
209 #define OV0_P23_V_ACCUM_INIT 0x042C 211 #define OV0_P23_V_ACCUM_INIT 0x042C
210 #define OV0_P1_BLANK_LINES_AT_TOP 0x0430 212 #define OV0_P1_BLANK_LINES_AT_TOP 0x0430
211 #define OV0_P23_BLANK_LINES_AT_TOP 0x0434 213 #define OV0_P23_BLANK_LINES_AT_TOP 0x0434
212 #define OV0_BASE_ADDR 0x043C 214 #define OV0_BASE_ADDR 0x043C
213 #define OV0_VID_BUF0_BASE_ADRS 0x0440 215 #define OV0_VID_BUF0_BASE_ADRS 0x0440
214 #define OV0_VID_BUF1_BASE_ADRS 0x0444 216 #define OV0_VID_BUF1_BASE_ADRS 0x0444
215 #define OV0_VID_BUF2_BASE_ADRS 0x0448 217 #define OV0_VID_BUF2_BASE_ADRS 0x0448
216 #define OV0_VID_BUF3_BASE_ADRS 0x044C 218 #define OV0_VID_BUF3_BASE_ADRS 0x044C
217 #define OV0_VID_BUF4_BASE_ADRS 0x0450 219 #define OV0_VID_BUF4_BASE_ADRS 0x0450
218 #define OV0_VID_BUF5_BASE_ADRS 0x0454 220 #define OV0_VID_BUF5_BASE_ADRS 0x0454
219 #define OV0_VID_BUF_PITCH0_VALUE 0x0460 221 #define OV0_VID_BUF_PITCH0_VALUE 0x0460
220 #define OV0_VID_BUF_PITCH1_VALUE 0x0464 222 #define OV0_VID_BUF_PITCH1_VALUE 0x0464
221 #define OV0_AUTO_FLIP_CNTRL 0x0470 223 #define OV0_AUTO_FLIP_CNTRL 0x0470
222 #define OV0_DEINTERLACE_PATTERN 0x0474 224 #define OV0_DEINTERLACE_PATTERN 0x0474
223 #define OV0_SUBMIT_HISTORY 0x0478 225 #define OV0_SUBMIT_HISTORY 0x0478
224 #define OV0_H_INC 0x0480 226 #define OV0_H_INC 0x0480
225 #define OV0_STEP_BY 0x0484 227 #define OV0_STEP_BY 0x0484
226 #define OV0_P1_H_ACCUM_INIT 0x0488 228 #define OV0_P1_H_ACCUM_INIT 0x0488
227 #define OV0_P23_H_ACCUM_INIT 0x048C 229 #define OV0_P23_H_ACCUM_INIT 0x048C
228 #define OV0_P1_X_START_END 0x0494 230 #define OV0_P1_X_START_END 0x0494
229 #define OV0_P2_X_START_END 0x0498 231 #define OV0_P2_X_START_END 0x0498
230 #define OV0_P3_X_START_END 0x049C 232 #define OV0_P3_X_START_END 0x049C
231 #define OV0_FILTER_CNTL 0x04A0 233 #define OV0_FILTER_CNTL 0x04A0
232 #define OV0_FOUR_TAP_COEF_0 0x04B0 234 #define OV0_FOUR_TAP_COEF_0 0x04B0
233 #define OV0_FOUR_TAP_COEF_1 0x04B4 235 #define OV0_FOUR_TAP_COEF_1 0x04B4
234 #define OV0_FOUR_TAP_COEF_2 0x04B8 236 #define OV0_FOUR_TAP_COEF_2 0x04B8
235 #define OV0_FOUR_TAP_COEF_3 0x04BC 237 #define OV0_FOUR_TAP_COEF_3 0x04BC
236 #define OV0_FOUR_TAP_COEF_4 0x04C0 238 #define OV0_FOUR_TAP_COEF_4 0x04C0
237 #define OV0_FLAG_CNTRL 0x04DC 239 #define OV0_FLAG_CNTRL 0x04DC
238 #define OV0_SLICE_CNTL 0x04E0 240 #define OV0_SLICE_CNTL 0x04E0
239 #define OV0_VID_KEY_CLR_LOW 0x04E4 241 #define OV0_VID_KEY_CLR_LOW 0x04E4
240 #define OV0_VID_KEY_CLR_HIGH 0x04E8 242 #define OV0_VID_KEY_CLR_HIGH 0x04E8
241 #define OV0_GRPH_KEY_CLR_LOW 0x04EC 243 #define OV0_GRPH_KEY_CLR_LOW 0x04EC
242 #define OV0_GRPH_KEY_CLR_HIGH 0x04F0 244 #define OV0_GRPH_KEY_CLR_HIGH 0x04F0
243 #define OV0_KEY_CNTL 0x04F4 245 #define OV0_KEY_CNTL 0x04F4
244 #define OV0_TEST 0x04F8 246 #define OV0_TEST 0x04F8
245 #define SUBPIC_CNTL 0x0540 247 #define SUBPIC_CNTL 0x0540
246 #define SUBPIC_DEFCOLCON 0x0544 248 #define SUBPIC_DEFCOLCON 0x0544
247 #define SUBPIC_Y_X_START 0x054C 249 #define SUBPIC_Y_X_START 0x054C
248 #define SUBPIC_Y_X_END 0x0550 250 #define SUBPIC_Y_X_END 0x0550
249 #define SUBPIC_V_INC 0x0554 251 #define SUBPIC_V_INC 0x0554
250 #define SUBPIC_H_INC 0x0558 252 #define SUBPIC_H_INC 0x0558
251 #define SUBPIC_BUF0_OFFSET 0x055C 253 #define SUBPIC_BUF0_OFFSET 0x055C
252 #define SUBPIC_BUF1_OFFSET 0x0560 254 #define SUBPIC_BUF1_OFFSET 0x0560
253 #define SUBPIC_LC0_OFFSET 0x0564 255 #define SUBPIC_LC0_OFFSET 0x0564
254 #define SUBPIC_LC1_OFFSET 0x0568 256 #define SUBPIC_LC1_OFFSET 0x0568
255 #define SUBPIC_PITCH 0x056C 257 #define SUBPIC_PITCH 0x056C
256 #define SUBPIC_BTN_HLI_COLCON 0x0570 258 #define SUBPIC_BTN_HLI_COLCON 0x0570
257 #define SUBPIC_BTN_HLI_Y_X_START 0x0574 259 #define SUBPIC_BTN_HLI_Y_X_START 0x0574
258 #define SUBPIC_BTN_HLI_Y_X_END 0x0578 260 #define SUBPIC_BTN_HLI_Y_X_END 0x0578
259 #define SUBPIC_PALETTE_INDEX 0x057C 261 #define SUBPIC_PALETTE_INDEX 0x057C
260 #define SUBPIC_PALETTE_DATA 0x0580 262 #define SUBPIC_PALETTE_DATA 0x0580
261 #define SUBPIC_H_ACCUM_INIT 0x0584 263 #define SUBPIC_H_ACCUM_INIT 0x0584
262 #define SUBPIC_V_ACCUM_INIT 0x0588 264 #define SUBPIC_V_ACCUM_INIT 0x0588
263 #define DISP_MISC_CNTL 0x0D00 265 #define DISP_MISC_CNTL 0x0D00
264 #define DAC_MACRO_CNTL 0x0D04 266 #define DAC_MACRO_CNTL 0x0D04
265 #define DISP_PWR_MAN 0x0D08 267 #define DISP_PWR_MAN 0x0D08
266 #define DISP_TEST_DEBUG_CNTL 0x0D10 268 #define DISP_TEST_DEBUG_CNTL 0x0D10
267 #define DISP_HW_DEBUG 0x0D14 269 #define DISP_HW_DEBUG 0x0D14
268 #define DAC_CRC_SIG1 0x0D18 270 #define DAC_CRC_SIG1 0x0D18
269 #define DAC_CRC_SIG2 0x0D1C 271 #define DAC_CRC_SIG2 0x0D1C
270 #define OV0_LIN_TRANS_A 0x0D20 272 #define OV0_LIN_TRANS_A 0x0D20
271 #define OV0_LIN_TRANS_B 0x0D24 273 #define OV0_LIN_TRANS_B 0x0D24
272 #define OV0_LIN_TRANS_C 0x0D28 274 #define OV0_LIN_TRANS_C 0x0D28
273 #define OV0_LIN_TRANS_D 0x0D2C 275 #define OV0_LIN_TRANS_D 0x0D2C
274 #define OV0_LIN_TRANS_E 0x0D30 276 #define OV0_LIN_TRANS_E 0x0D30
275 #define OV0_LIN_TRANS_F 0x0D34 277 #define OV0_LIN_TRANS_F 0x0D34
276 #define OV0_GAMMA_0_F 0x0D40 278 #define OV0_GAMMA_0_F 0x0D40
277 #define OV0_GAMMA_10_1F 0x0D44 279 #define OV0_GAMMA_10_1F 0x0D44
278 #define OV0_GAMMA_20_3F 0x0D48 280 #define OV0_GAMMA_20_3F 0x0D48
279 #define OV0_GAMMA_40_7F 0x0D4C 281 #define OV0_GAMMA_40_7F 0x0D4C
280 #define OV0_GAMMA_380_3BF 0x0D50 282 #define OV0_GAMMA_380_3BF 0x0D50
281 #define OV0_GAMMA_3C0_3FF 0x0D54 283 #define OV0_GAMMA_3C0_3FF 0x0D54
282 #define DISP_MERGE_CNTL 0x0D60 284 #define DISP_MERGE_CNTL 0x0D60
283 #define DISP_OUTPUT_CNTL 0x0D64 285 #define DISP_OUTPUT_CNTL 0x0D64
284 #define DISP_LIN_TRANS_GRPH_A 0x0D80 286 #define DISP_LIN_TRANS_GRPH_A 0x0D80
285 #define DISP_LIN_TRANS_GRPH_B 0x0D84 287 #define DISP_LIN_TRANS_GRPH_B 0x0D84
286 #define DISP_LIN_TRANS_GRPH_C 0x0D88 288 #define DISP_LIN_TRANS_GRPH_C 0x0D88
287 #define DISP_LIN_TRANS_GRPH_D 0x0D8C 289 #define DISP_LIN_TRANS_GRPH_D 0x0D8C
288 #define DISP_LIN_TRANS_GRPH_E 0x0D90 290 #define DISP_LIN_TRANS_GRPH_E 0x0D90
289 #define DISP_LIN_TRANS_GRPH_F 0x0D94 291 #define DISP_LIN_TRANS_GRPH_F 0x0D94
290 #define DISP_LIN_TRANS_VID_A 0x0D98 292 #define DISP_LIN_TRANS_VID_A 0x0D98
291 #define DISP_LIN_TRANS_VID_B 0x0D9C 293 #define DISP_LIN_TRANS_VID_B 0x0D9C
292 #define DISP_LIN_TRANS_VID_C 0x0DA0 294 #define DISP_LIN_TRANS_VID_C 0x0DA0
293 #define DISP_LIN_TRANS_VID_D 0x0DA4 295 #define DISP_LIN_TRANS_VID_D 0x0DA4
294 #define DISP_LIN_TRANS_VID_E 0x0DA8 296 #define DISP_LIN_TRANS_VID_E 0x0DA8
295 #define DISP_LIN_TRANS_VID_F 0x0DAC 297 #define DISP_LIN_TRANS_VID_F 0x0DAC
296 #define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 298 #define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0
297 #define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 299 #define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4
298 #define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 300 #define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8
299 #define RMX_HORZ_PHASE 0x0DBC 301 #define RMX_HORZ_PHASE 0x0DBC
300 #define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 302 #define DAC_EMBEDDED_SYNC_CNTL 0x0DC0
301 #define DAC_BROAD_PULSE 0x0DC4 303 #define DAC_BROAD_PULSE 0x0DC4
302 #define DAC_SKEW_CLKS 0x0DC8 304 #define DAC_SKEW_CLKS 0x0DC8
303 #define DAC_INCR 0x0DCC 305 #define DAC_INCR 0x0DCC
304 #define DAC_NEG_SYNC_LEVEL 0x0DD0 306 #define DAC_NEG_SYNC_LEVEL 0x0DD0
305 #define DAC_POS_SYNC_LEVEL 0x0DD4 307 #define DAC_POS_SYNC_LEVEL 0x0DD4
306 #define DAC_BLANK_LEVEL 0x0DD8 308 #define DAC_BLANK_LEVEL 0x0DD8
307 #define CLOCK_CNTL_INDEX 0x0008 309 #define CLOCK_CNTL_INDEX 0x0008
308 #define CLOCK_CNTL_DATA 0x000C 310 #define CLOCK_CNTL_DATA 0x000C
309 #define CP_RB_CNTL 0x0704 311 #define CP_RB_CNTL 0x0704
310 #define CP_RB_BASE 0x0700 312 #define CP_RB_BASE 0x0700
311 #define CP_RB_RPTR_ADDR 0x070C 313 #define CP_RB_RPTR_ADDR 0x070C
312 #define CP_RB_RPTR 0x0710 314 #define CP_RB_RPTR 0x0710
313 #define CP_RB_WPTR 0x0714 315 #define CP_RB_WPTR 0x0714
314 #define CP_RB_WPTR_DELAY 0x0718 316 #define CP_RB_WPTR_DELAY 0x0718
315 #define CP_IB_BASE 0x0738 317 #define CP_IB_BASE 0x0738
316 #define CP_IB_BUFSZ 0x073C 318 #define CP_IB_BUFSZ 0x073C
317 #define SCRATCH_REG0 0x15E0 319 #define SCRATCH_REG0 0x15E0
318 #define GUI_SCRATCH_REG0 0x15E0 320 #define GUI_SCRATCH_REG0 0x15E0
319 #define SCRATCH_REG1 0x15E4 321 #define SCRATCH_REG1 0x15E4
320 #define GUI_SCRATCH_REG1 0x15E4 322 #define GUI_SCRATCH_REG1 0x15E4
321 #define SCRATCH_REG2 0x15E8 323 #define SCRATCH_REG2 0x15E8
322 #define GUI_SCRATCH_REG2 0x15E8 324 #define GUI_SCRATCH_REG2 0x15E8
323 #define SCRATCH_REG3 0x15EC 325 #define SCRATCH_REG3 0x15EC
324 #define GUI_SCRATCH_REG3 0x15EC 326 #define GUI_SCRATCH_REG3 0x15EC
325 #define SCRATCH_REG4 0x15F0 327 #define SCRATCH_REG4 0x15F0
326 #define GUI_SCRATCH_REG4 0x15F0 328 #define GUI_SCRATCH_REG4 0x15F0
327 #define SCRATCH_REG5 0x15F4 329 #define SCRATCH_REG5 0x15F4
328 #define GUI_SCRATCH_REG5 0x15F4 330 #define GUI_SCRATCH_REG5 0x15F4
329 #define SCRATCH_UMSK 0x0770 331 #define SCRATCH_UMSK 0x0770
330 #define SCRATCH_ADDR 0x0774 332 #define SCRATCH_ADDR 0x0774
331 #define DP_BRUSH_FRGD_CLR 0x147C 333 #define DP_BRUSH_FRGD_CLR 0x147C
332 #define DP_BRUSH_BKGD_CLR 0x1478 334 #define DP_BRUSH_BKGD_CLR 0x1478
333 #define DST_LINE_START 0x1600 335 #define DST_LINE_START 0x1600
334 #define DST_LINE_END 0x1604 336 #define DST_LINE_END 0x1604
335 #define SRC_OFFSET 0x15AC 337 #define SRC_OFFSET 0x15AC
336 #define SRC_PITCH 0x15B0 338 #define SRC_PITCH 0x15B0
337 #define SRC_TILE 0x1704 339 #define SRC_TILE 0x1704
338 #define SRC_PITCH_OFFSET 0x1428 340 #define SRC_PITCH_OFFSET 0x1428
339 #define SRC_X 0x1414 341 #define SRC_X 0x1414
340 #define SRC_Y 0x1418 342 #define SRC_Y 0x1418
341 #define SRC_X_Y 0x1590 343 #define SRC_X_Y 0x1590
342 #define SRC_Y_X 0x1434 344 #define SRC_Y_X 0x1434
343 #define DST_Y_X 0x1438 345 #define DST_Y_X 0x1438
344 #define DST_WIDTH_HEIGHT 0x1598 346 #define DST_WIDTH_HEIGHT 0x1598
345 #define DST_HEIGHT_WIDTH 0x143c 347 #define DST_HEIGHT_WIDTH 0x143c
346 #define DST_OFFSET 0x1404 348 #define DST_OFFSET 0x1404
347 #define SRC_CLUT_ADDRESS 0x1780 349 #define SRC_CLUT_ADDRESS 0x1780
348 #define SRC_CLUT_DATA 0x1784 350 #define SRC_CLUT_DATA 0x1784
349 #define SRC_CLUT_DATA_RD 0x1788 351 #define SRC_CLUT_DATA_RD 0x1788
350 #define HOST_DATA0 0x17C0 352 #define HOST_DATA0 0x17C0
351 #define HOST_DATA1 0x17C4 353 #define HOST_DATA1 0x17C4
352 #define HOST_DATA2 0x17C8 354 #define HOST_DATA2 0x17C8
353 #define HOST_DATA3 0x17CC 355 #define HOST_DATA3 0x17CC
354 #define HOST_DATA4 0x17D0 356 #define HOST_DATA4 0x17D0
355 #define HOST_DATA5 0x17D4 357 #define HOST_DATA5 0x17D4
356 #define HOST_DATA6 0x17D8 358 #define HOST_DATA6 0x17D8
357 #define HOST_DATA7 0x17DC 359 #define HOST_DATA7 0x17DC
358 #define HOST_DATA_LAST 0x17E0 360 #define HOST_DATA_LAST 0x17E0
359 #define DP_SRC_ENDIAN 0x15D4 361 #define DP_SRC_ENDIAN 0x15D4
360 #define DP_SRC_FRGD_CLR 0x15D8 362 #define DP_SRC_FRGD_CLR 0x15D8
361 #define DP_SRC_BKGD_CLR 0x15DC 363 #define DP_SRC_BKGD_CLR 0x15DC
362 #define SC_LEFT 0x1640 364 #define SC_LEFT 0x1640
363 #define SC_RIGHT 0x1644 365 #define SC_RIGHT 0x1644
364 #define SC_TOP 0x1648 366 #define SC_TOP 0x1648
365 #define SC_BOTTOM 0x164C 367 #define SC_BOTTOM 0x164C
366 #define SRC_SC_RIGHT 0x1654 368 #define SRC_SC_RIGHT 0x1654
367 #define SRC_SC_BOTTOM 0x165C 369 #define SRC_SC_BOTTOM 0x165C
368 #define DP_CNTL 0x16C0 370 #define DP_CNTL 0x16C0
369 #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 371 #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0
370 #define DP_DATATYPE 0x16C4 372 #define DP_DATATYPE 0x16C4
371 #define DP_MIX 0x16C8 373 #define DP_MIX 0x16C8
372 #define DP_WRITE_MSK 0x16CC 374 #define DP_WRITE_MSK 0x16CC
373 #define DP_XOP 0x17F8 375 #define DP_XOP 0x17F8
374 #define CLR_CMP_CLR_SRC 0x15C4 376 #define CLR_CMP_CLR_SRC 0x15C4
375 #define CLR_CMP_CLR_DST 0x15C8 377 #define CLR_CMP_CLR_DST 0x15C8
376 #define CLR_CMP_CNTL 0x15C0 378 #define CLR_CMP_CNTL 0x15C0
377 #define CLR_CMP_MSK 0x15CC 379 #define CLR_CMP_MSK 0x15CC
378 #define DSTCACHE_MODE 0x1710 380 #define DSTCACHE_MODE 0x1710
379 #define DSTCACHE_CTLSTAT 0x1714 381 #define DSTCACHE_CTLSTAT 0x1714
380 #define DEFAULT_PITCH_OFFSET 0x16E0 382 #define DEFAULT_PITCH_OFFSET 0x16E0
381 #define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 383 #define DEFAULT_SC_BOTTOM_RIGHT 0x16E8
382 #define DEFAULT_SC_TOP_LEFT 0x16EC 384 #define DEFAULT_SC_TOP_LEFT 0x16EC
383 #define SRC_PITCH_OFFSET 0x1428 385 #define SRC_PITCH_OFFSET 0x1428
384 #define DST_PITCH_OFFSET 0x142C 386 #define DST_PITCH_OFFSET 0x142C
385 #define DP_GUI_MASTER_CNTL 0x146C 387 #define DP_GUI_MASTER_CNTL 0x146C
386 #define SC_TOP_LEFT 0x16EC 388 #define SC_TOP_LEFT 0x16EC
387 #define SC_BOTTOM_RIGHT 0x16F0 389 #define SC_BOTTOM_RIGHT 0x16F0
388 #define SRC_SC_BOTTOM_RIGHT 0x16F4 390 #define SRC_SC_BOTTOM_RIGHT 0x16F4
389 #define RB2D_DSTCACHE_MODE 0x3428 391 #define RB2D_DSTCACHE_MODE 0x3428
390 #define RB2D_DSTCACHE_CTLSTAT 0x342C 392 #define RB2D_DSTCACHE_CTLSTAT 0x342C
391 #define LVDS_GEN_CNTL 0x02d0 393 #define LVDS_GEN_CNTL 0x02d0
392 #define LVDS_PLL_CNTL 0x02d4 394 #define LVDS_PLL_CNTL 0x02d4
393 #define FP2_GEN_CNTL 0x0288 395 #define FP2_GEN_CNTL 0x0288
394 #define TMDS_CNTL 0x0294 396 #define TMDS_CNTL 0x0294
395 #define TMDS_CRC 0x02a0 397 #define TMDS_CRC 0x02a0
396 #define TMDS_TRANSMITTER_CNTL 0x02a4 398 #define TMDS_TRANSMITTER_CNTL 0x02a4
397 #define MPP_TB_CONFIG 0x01c0 399 #define MPP_TB_CONFIG 0x01c0
398 #define PAMAC0_DLY_CNTL 0x0a94 400 #define PAMAC0_DLY_CNTL 0x0a94
399 #define PAMAC1_DLY_CNTL 0x0a98 401 #define PAMAC1_DLY_CNTL 0x0a98
400 #define PAMAC2_DLY_CNTL 0x0a9c 402 #define PAMAC2_DLY_CNTL 0x0a9c
401 #define FW_CNTL 0x0118 403 #define FW_CNTL 0x0118
402 #define FCP_CNTL 0x0910 404 #define FCP_CNTL 0x0910
403 #define VGA_DDA_ON_OFF 0x02ec 405 #define VGA_DDA_ON_OFF 0x02ec
404 #define TV_MASTER_CNTL 0x0800 406 #define TV_MASTER_CNTL 0x0800
405 407
406 /* #define BASE_CODE 0x0f0b */ 408 /* #define BASE_CODE 0x0f0b */
407 #define BIOS_0_SCRATCH 0x0010 409 #define BIOS_0_SCRATCH 0x0010
408 #define BIOS_1_SCRATCH 0x0014 410 #define BIOS_1_SCRATCH 0x0014
409 #define BIOS_2_SCRATCH 0x0018 411 #define BIOS_2_SCRATCH 0x0018
410 #define BIOS_3_SCRATCH 0x001c 412 #define BIOS_3_SCRATCH 0x001c
411 #define BIOS_4_SCRATCH 0x0020 413 #define BIOS_4_SCRATCH 0x0020
412 #define BIOS_5_SCRATCH 0x0024 414 #define BIOS_5_SCRATCH 0x0024
413 #define BIOS_6_SCRATCH 0x0028 415 #define BIOS_6_SCRATCH 0x0028
414 #define BIOS_7_SCRATCH 0x002c 416 #define BIOS_7_SCRATCH 0x002c
415 417
416 #define HDP_SOFT_RESET (1 << 26) 418 #define HDP_SOFT_RESET (1 << 26)
417 419
418 #define TV_DAC_CNTL 0x088c 420 #define TV_DAC_CNTL 0x088c
419 #define GPIOPAD_MASK 0x0198 421 #define GPIOPAD_MASK 0x0198
420 #define GPIOPAD_A 0x019c 422 #define GPIOPAD_A 0x019c
421 #define GPIOPAD_EN 0x01a0 423 #define GPIOPAD_EN 0x01a0
422 #define GPIOPAD_Y 0x01a4 424 #define GPIOPAD_Y 0x01a4
423 #define ZV_LCDPAD_MASK 0x01a8 425 #define ZV_LCDPAD_MASK 0x01a8
424 #define ZV_LCDPAD_A 0x01ac 426 #define ZV_LCDPAD_A 0x01ac
425 #define ZV_LCDPAD_EN 0x01b0 427 #define ZV_LCDPAD_EN 0x01b0
426 #define ZV_LCDPAD_Y 0x01b4 428 #define ZV_LCDPAD_Y 0x01b4
427 429
428 /* PLL Registers */ 430 /* PLL Registers */
429 #define CLK_PIN_CNTL 0x0001 431 #define CLK_PIN_CNTL 0x0001
430 #define PPLL_CNTL 0x0002 432 #define PPLL_CNTL 0x0002
431 #define PPLL_REF_DIV 0x0003 433 #define PPLL_REF_DIV 0x0003
432 #define PPLL_DIV_0 0x0004 434 #define PPLL_DIV_0 0x0004
433 #define PPLL_DIV_1 0x0005 435 #define PPLL_DIV_1 0x0005
434 #define PPLL_DIV_2 0x0006 436 #define PPLL_DIV_2 0x0006
435 #define PPLL_DIV_3 0x0007 437 #define PPLL_DIV_3 0x0007
436 #define VCLK_ECP_CNTL 0x0008 438 #define VCLK_ECP_CNTL 0x0008
437 #define HTOTAL_CNTL 0x0009 439 #define HTOTAL_CNTL 0x0009
438 #define M_SPLL_REF_FB_DIV 0x000a 440 #define M_SPLL_REF_FB_DIV 0x000a
439 #define AGP_PLL_CNTL 0x000b 441 #define AGP_PLL_CNTL 0x000b
440 #define SPLL_CNTL 0x000c 442 #define SPLL_CNTL 0x000c
441 #define SCLK_CNTL 0x000d 443 #define SCLK_CNTL 0x000d
442 #define MPLL_CNTL 0x000e 444 #define MPLL_CNTL 0x000e
443 #define MDLL_CKO 0x000f 445 #define MDLL_CKO 0x000f
444 #define MDLL_RDCKA 0x0010 446 #define MDLL_RDCKA 0x0010
445 #define MCLK_CNTL 0x0012 447 #define MCLK_CNTL 0x0012
446 #define AGP_PLL_CNTL 0x000b 448 #define AGP_PLL_CNTL 0x000b
447 #define PLL_TEST_CNTL 0x0013 449 #define PLL_TEST_CNTL 0x0013
448 #define CLK_PWRMGT_CNTL 0x0014 450 #define CLK_PWRMGT_CNTL 0x0014
449 #define PLL_PWRMGT_CNTL 0x0015 451 #define PLL_PWRMGT_CNTL 0x0015
450 #define MCLK_MISC 0x001f 452 #define MCLK_MISC 0x001f
451 #define P2PLL_CNTL 0x002a 453 #define P2PLL_CNTL 0x002a
452 #define P2PLL_REF_DIV 0x002b 454 #define P2PLL_REF_DIV 0x002b
453 #define PIXCLKS_CNTL 0x002d 455 #define PIXCLKS_CNTL 0x002d
454 #define SCLK_MORE_CNTL 0x0035 456 #define SCLK_MORE_CNTL 0x0035
455 457
456 /* MCLK_CNTL bit constants */ 458 /* MCLK_CNTL bit constants */
457 #define FORCEON_MCLKA (1 << 16) 459 #define FORCEON_MCLKA (1 << 16)
458 #define FORCEON_MCLKB (1 << 17) 460 #define FORCEON_MCLKB (1 << 17)
459 #define FORCEON_YCLKA (1 << 18) 461 #define FORCEON_YCLKA (1 << 18)
460 #define FORCEON_YCLKB (1 << 19) 462 #define FORCEON_YCLKB (1 << 19)
461 #define FORCEON_MC (1 << 20) 463 #define FORCEON_MC (1 << 20)
462 #define FORCEON_AIC (1 << 21) 464 #define FORCEON_AIC (1 << 21)
463 465
464 /* SCLK_CNTL bit constants */ 466 /* SCLK_CNTL bit constants */
465 #define DYN_STOP_LAT_MASK 0x00007ff8 467 #define DYN_STOP_LAT_MASK 0x00007ff8
466 #define CP_MAX_DYN_STOP_LAT 0x0008 468 #define CP_MAX_DYN_STOP_LAT 0x0008
467 #define SCLK_FORCEON_MASK 0xffff8000 469 #define SCLK_FORCEON_MASK 0xffff8000
468 470
469 /* SCLK_MORE_CNTL bit constants */ 471 /* SCLK_MORE_CNTL bit constants */
470 #define SCLK_MORE_FORCEON 0x0700 472 #define SCLK_MORE_FORCEON 0x0700
471 473
472 /* BUS_CNTL bit constants */ 474 /* BUS_CNTL bit constants */
473 #define BUS_DBL_RESYNC 0x00000001 475 #define BUS_DBL_RESYNC 0x00000001
474 #define BUS_MSTR_RESET 0x00000002 476 #define BUS_MSTR_RESET 0x00000002
475 #define BUS_FLUSH_BUF 0x00000004 477 #define BUS_FLUSH_BUF 0x00000004
476 #define BUS_STOP_REQ_DIS 0x00000008 478 #define BUS_STOP_REQ_DIS 0x00000008
477 #define BUS_ROTATION_DIS 0x00000010 479 #define BUS_ROTATION_DIS 0x00000010
478 #define BUS_MASTER_DIS 0x00000040 480 #define BUS_MASTER_DIS 0x00000040
479 #define BUS_ROM_WRT_EN 0x00000080 481 #define BUS_ROM_WRT_EN 0x00000080
480 #define BUS_DIS_ROM 0x00001000 482 #define BUS_DIS_ROM 0x00001000
481 #define BUS_PCI_READ_RETRY_EN 0x00002000 483 #define BUS_PCI_READ_RETRY_EN 0x00002000
482 #define BUS_AGP_AD_STEPPING_EN 0x00004000 484 #define BUS_AGP_AD_STEPPING_EN 0x00004000
483 #define BUS_PCI_WRT_RETRY_EN 0x00008000 485 #define BUS_PCI_WRT_RETRY_EN 0x00008000
484 #define BUS_MSTR_RD_MULT 0x00100000 486 #define BUS_MSTR_RD_MULT 0x00100000
485 #define BUS_MSTR_RD_LINE 0x00200000 487 #define BUS_MSTR_RD_LINE 0x00200000
486 #define BUS_SUSPEND 0x00400000 488 #define BUS_SUSPEND 0x00400000
487 #define LAT_16X 0x00800000 489 #define LAT_16X 0x00800000
488 #define BUS_RD_DISCARD_EN 0x01000000 490 #define BUS_RD_DISCARD_EN 0x01000000
489 #define BUS_RD_ABORT_EN 0x02000000 491 #define BUS_RD_ABORT_EN 0x02000000
490 #define BUS_MSTR_WS 0x04000000 492 #define BUS_MSTR_WS 0x04000000
491 #define BUS_PARKING_DIS 0x08000000 493 #define BUS_PARKING_DIS 0x08000000
492 #define BUS_MSTR_DISCONNECT_EN 0x10000000 494 #define BUS_MSTR_DISCONNECT_EN 0x10000000
493 #define BUS_WRT_BURST 0x20000000 495 #define BUS_WRT_BURST 0x20000000
494 #define BUS_READ_BURST 0x40000000 496 #define BUS_READ_BURST 0x40000000
495 #define BUS_RDY_READ_DLY 0x80000000 497 #define BUS_RDY_READ_DLY 0x80000000
496 498
497 /* PIXCLKS_CNTL */ 499 /* PIXCLKS_CNTL */
498 #define PIX2CLK_SRC_SEL_MASK 0x03 500 #define PIX2CLK_SRC_SEL_MASK 0x03
499 #define PIX2CLK_SRC_SEL_CPUCLK 0x00 501 #define PIX2CLK_SRC_SEL_CPUCLK 0x00
500 #define PIX2CLK_SRC_SEL_PSCANCLK 0x01 502 #define PIX2CLK_SRC_SEL_PSCANCLK 0x01
501 #define PIX2CLK_SRC_SEL_BYTECLK 0x02 503 #define PIX2CLK_SRC_SEL_BYTECLK 0x02
502 #define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 504 #define PIX2CLK_SRC_SEL_P2PLLCLK 0x03
503 #define PIX2CLK_ALWAYS_ONb (1<<6) 505 #define PIX2CLK_ALWAYS_ONb (1<<6)
504 #define PIX2CLK_DAC_ALWAYS_ONb (1<<7) 506 #define PIX2CLK_DAC_ALWAYS_ONb (1<<7)
505 #define PIXCLK_TV_SRC_SEL (1 << 8) 507 #define PIXCLK_TV_SRC_SEL (1 << 8)
506 #define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) 508 #define PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
507 #define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) 509 #define PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
508 510
509 511
510 /* CLOCK_CNTL_INDEX bit constants */ 512 /* CLOCK_CNTL_INDEX bit constants */
511 #define PLL_WR_EN 0x00000080 513 #define PLL_WR_EN 0x00000080
512 514
513 /* CONFIG_CNTL bit constants */ 515 /* CONFIG_CNTL bit constants */
514 #define CFG_VGA_RAM_EN 0x00000100 516 #define CFG_VGA_RAM_EN 0x00000100
515 #define CFG_ATI_REV_ID_MASK (0xf << 16) 517 #define CFG_ATI_REV_ID_MASK (0xf << 16)
516 #define CFG_ATI_REV_A11 (0 << 16) 518 #define CFG_ATI_REV_A11 (0 << 16)
517 #define CFG_ATI_REV_A12 (1 << 16) 519 #define CFG_ATI_REV_A12 (1 << 16)
518 #define CFG_ATI_REV_A13 (2 << 16) 520 #define CFG_ATI_REV_A13 (2 << 16)
519 521
520 /* CRTC_EXT_CNTL bit constants */ 522 /* CRTC_EXT_CNTL bit constants */
521 #define VGA_ATI_LINEAR 0x00000008 523 #define VGA_ATI_LINEAR 0x00000008
522 #define VGA_128KAP_PAGING 0x00000010 524 #define VGA_128KAP_PAGING 0x00000010
523 #define XCRT_CNT_EN (1 << 6) 525 #define XCRT_CNT_EN (1 << 6)
524 #define CRTC_HSYNC_DIS (1 << 8) 526 #define CRTC_HSYNC_DIS (1 << 8)
525 #define CRTC_VSYNC_DIS (1 << 9) 527 #define CRTC_VSYNC_DIS (1 << 9)
526 #define CRTC_DISPLAY_DIS (1 << 10) 528 #define CRTC_DISPLAY_DIS (1 << 10)
527 #define CRTC_CRT_ON (1 << 15) 529 #define CRTC_CRT_ON (1 << 15)
528 530
529 531
530 /* DSTCACHE_CTLSTAT bit constants */ 532 /* DSTCACHE_CTLSTAT bit constants */
531 #define RB2D_DC_FLUSH (3 << 0) 533 #define RB2D_DC_FLUSH (3 << 0)
532 #define RB2D_DC_FLUSH_ALL 0xf 534 #define RB2D_DC_FLUSH_ALL 0xf
533 #define RB2D_DC_BUSY (1 << 31) 535 #define RB2D_DC_BUSY (1 << 31)
534 536
535 537
536 /* CRTC_GEN_CNTL bit constants */ 538 /* CRTC_GEN_CNTL bit constants */
537 #define CRTC_DBL_SCAN_EN 0x00000001 539 #define CRTC_DBL_SCAN_EN 0x00000001
538 #define CRTC_CUR_EN 0x00010000 540 #define CRTC_CUR_EN 0x00010000
539 #define CRTC_INTERLACE_EN (1 << 1) 541 #define CRTC_INTERLACE_EN (1 << 1)
540 #define CRTC_BYPASS_LUT_EN (1 << 14) 542 #define CRTC_BYPASS_LUT_EN (1 << 14)
541 #define CRTC_EXT_DISP_EN (1 << 24) 543 #define CRTC_EXT_DISP_EN (1 << 24)
542 #define CRTC_EN (1 << 25) 544 #define CRTC_EN (1 << 25)
543 #define CRTC_DISP_REQ_EN_B (1 << 26) 545 #define CRTC_DISP_REQ_EN_B (1 << 26)
544 546
545 /* CRTC_STATUS bit constants */ 547 /* CRTC_STATUS bit constants */
546 #define CRTC_VBLANK 0x00000001 548 #define CRTC_VBLANK 0x00000001
547 549
548 /* CRTC2_GEN_CNTL bit constants */ 550 /* CRTC2_GEN_CNTL bit constants */
549 #define CRT2_ON (1 << 7) 551 #define CRT2_ON (1 << 7)
550 #define CRTC2_DISPLAY_DIS (1 << 23) 552 #define CRTC2_DISPLAY_DIS (1 << 23)
551 #define CRTC2_EN (1 << 25) 553 #define CRTC2_EN (1 << 25)
552 #define CRTC2_DISP_REQ_EN_B (1 << 26) 554 #define CRTC2_DISP_REQ_EN_B (1 << 26)
553 555
554 /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ 556 /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */
555 #define CUR_LOCK 0x80000000 557 #define CUR_LOCK 0x80000000
556 558
557 /* GPIO bit constants */ 559 /* GPIO bit constants */
558 #define GPIO_A_0 (1 << 0) 560 #define GPIO_A_0 (1 << 0)
559 #define GPIO_A_1 (1 << 1) 561 #define GPIO_A_1 (1 << 1)
560 #define GPIO_Y_0 (1 << 8) 562 #define GPIO_Y_0 (1 << 8)
561 #define GPIO_Y_1 (1 << 9) 563 #define GPIO_Y_1 (1 << 9)
562 #define GPIO_EN_0 (1 << 16) 564 #define GPIO_EN_0 (1 << 16)
563 #define GPIO_EN_1 (1 << 17) 565 #define GPIO_EN_1 (1 << 17)
564 #define GPIO_MASK_0 (1 << 24) 566 #define GPIO_MASK_0 (1 << 24)
565 #define GPIO_MASK_1 (1 << 25) 567 #define GPIO_MASK_1 (1 << 25)
566 #define VGA_DDC_DATA_OUTPUT GPIO_A_0 568 #define VGA_DDC_DATA_OUTPUT GPIO_A_0
567 #define VGA_DDC_CLK_OUTPUT GPIO_A_1 569 #define VGA_DDC_CLK_OUTPUT GPIO_A_1
568 #define VGA_DDC_DATA_INPUT GPIO_Y_0 570 #define VGA_DDC_DATA_INPUT GPIO_Y_0
569 #define VGA_DDC_CLK_INPUT GPIO_Y_1 571 #define VGA_DDC_CLK_INPUT GPIO_Y_1
570 #define VGA_DDC_DATA_OUT_EN GPIO_EN_0 572 #define VGA_DDC_DATA_OUT_EN GPIO_EN_0
571 #define VGA_DDC_CLK_OUT_EN GPIO_EN_1 573 #define VGA_DDC_CLK_OUT_EN GPIO_EN_1
572 574
573 575
574 /* FP bit constants */ 576 /* FP bit constants */
575 #define FP_CRTC_H_TOTAL_MASK 000003ff 577 #define FP_CRTC_H_TOTAL_MASK 000003ff
576 #define FP_CRTC_H_DISP_MASK 0x01ff0000 578 #define FP_CRTC_H_DISP_MASK 0x01ff0000
577 #define FP_CRTC_V_TOTAL_MASK 0x00000fff 579 #define FP_CRTC_V_TOTAL_MASK 0x00000fff
578 #define FP_CRTC_V_DISP_MASK 0x0fff0000 580 #define FP_CRTC_V_DISP_MASK 0x0fff0000
579 #define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 581 #define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
580 #define FP_H_SYNC_WID_MASK 0x003f0000 582 #define FP_H_SYNC_WID_MASK 0x003f0000
581 #define FP_V_SYNC_STRT_MASK 0x00000fff 583 #define FP_V_SYNC_STRT_MASK 0x00000fff
582 #define FP_V_SYNC_WID_MASK 0x001f0000 584 #define FP_V_SYNC_WID_MASK 0x001f0000
583 #define FP_CRTC_H_TOTAL_SHIFT 0x00000000 585 #define FP_CRTC_H_TOTAL_SHIFT 0x00000000
584 #define FP_CRTC_H_DISP_SHIFT 0x00000010 586 #define FP_CRTC_H_DISP_SHIFT 0x00000010
585 #define FP_CRTC_V_TOTAL_SHIFT 0x00000000 587 #define FP_CRTC_V_TOTAL_SHIFT 0x00000000
586 #define FP_CRTC_V_DISP_SHIFT 0x00000010 588 #define FP_CRTC_V_DISP_SHIFT 0x00000010
587 #define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 589 #define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
588 #define FP_H_SYNC_WID_SHIFT 0x00000010 590 #define FP_H_SYNC_WID_SHIFT 0x00000010
589 #define FP_V_SYNC_STRT_SHIFT 0x00000000 591 #define FP_V_SYNC_STRT_SHIFT 0x00000000
590 #define FP_V_SYNC_WID_SHIFT 0x00000010 592 #define FP_V_SYNC_WID_SHIFT 0x00000010
591 593
592 /* FP_GEN_CNTL bit constants */ 594 /* FP_GEN_CNTL bit constants */
593 #define FP_FPON (1 << 0) 595 #define FP_FPON (1 << 0)
594 #define FP_TMDS_EN (1 << 2) 596 #define FP_TMDS_EN (1 << 2)
595 #define FP_PANEL_FORMAT (1 << 3) 597 #define FP_PANEL_FORMAT (1 << 3)
596 #define FP_EN_TMDS (1 << 7) 598 #define FP_EN_TMDS (1 << 7)
597 #define FP_DETECT_SENSE (1 << 8) 599 #define FP_DETECT_SENSE (1 << 8)
598 #define R200_FP_SOURCE_SEL_MASK (3 << 10) 600 #define R200_FP_SOURCE_SEL_MASK (3 << 10)
599 #define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) 601 #define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
600 #define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) 602 #define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
601 #define R200_FP_SOURCE_SEL_RMX (2 << 10) 603 #define R200_FP_SOURCE_SEL_RMX (2 << 10)
602 #define R200_FP_SOURCE_SEL_TRANS (3 << 10) 604 #define R200_FP_SOURCE_SEL_TRANS (3 << 10)
603 #define FP_SEL_CRTC1 (0 << 13) 605 #define FP_SEL_CRTC1 (0 << 13)
604 #define FP_SEL_CRTC2 (1 << 13) 606 #define FP_SEL_CRTC2 (1 << 13)
605 #define FP_USE_VGA_HSYNC (1 << 14) 607 #define FP_USE_VGA_HSYNC (1 << 14)
606 #define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) 608 #define FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
607 #define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) 609 #define FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
608 #define FP_CRTC_DONT_SHADOW_HEND (1 << 17) 610 #define FP_CRTC_DONT_SHADOW_HEND (1 << 17)
609 #define FP_CRTC_USE_SHADOW_VEND (1 << 18) 611 #define FP_CRTC_USE_SHADOW_VEND (1 << 18)
610 #define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) 612 #define FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
611 #define FP_DFP_SYNC_SEL (1 << 21) 613 #define FP_DFP_SYNC_SEL (1 << 21)
612 #define FP_CRTC_LOCK_8DOT (1 << 22) 614 #define FP_CRTC_LOCK_8DOT (1 << 22)
613 #define FP_CRT_SYNC_SEL (1 << 23) 615 #define FP_CRT_SYNC_SEL (1 << 23)
614 #define FP_USE_SHADOW_EN (1 << 24) 616 #define FP_USE_SHADOW_EN (1 << 24)
615 #define FP_CRT_SYNC_ALT (1 << 26) 617 #define FP_CRT_SYNC_ALT (1 << 26)
616 618
617 /* FP2_GEN_CNTL bit constants */ 619 /* FP2_GEN_CNTL bit constants */
618 #define FP2_BLANK_EN (1 << 1) 620 #define FP2_BLANK_EN (1 << 1)
619 #define FP2_ON (1 << 2) 621 #define FP2_ON (1 << 2)
620 #define FP2_PANEL_FORMAT (1 << 3) 622 #define FP2_PANEL_FORMAT (1 << 3)
621 #define FP2_SOURCE_SEL_MASK (3 << 10) 623 #define FP2_SOURCE_SEL_MASK (3 << 10)
622 #define FP2_SOURCE_SEL_CRTC2 (1 << 10) 624 #define FP2_SOURCE_SEL_CRTC2 (1 << 10)
623 #define FP2_SRC_SEL_MASK (3 << 13) 625 #define FP2_SRC_SEL_MASK (3 << 13)
624 #define FP2_SRC_SEL_CRTC2 (1 << 13) 626 #define FP2_SRC_SEL_CRTC2 (1 << 13)
625 #define FP2_FP_POL (1 << 16) 627 #define FP2_FP_POL (1 << 16)
626 #define FP2_LP_POL (1 << 17) 628 #define FP2_LP_POL (1 << 17)
627 #define FP2_SCK_POL (1 << 18) 629 #define FP2_SCK_POL (1 << 18)
628 #define FP2_LCD_CNTL_MASK (7 << 19) 630 #define FP2_LCD_CNTL_MASK (7 << 19)
629 #define FP2_PAD_FLOP_EN (1 << 22) 631 #define FP2_PAD_FLOP_EN (1 << 22)
630 #define FP2_CRC_EN (1 << 23) 632 #define FP2_CRC_EN (1 << 23)
631 #define FP2_CRC_READ_EN (1 << 24) 633 #define FP2_CRC_READ_EN (1 << 24)
632 #define FP2_DV0_EN (1 << 25) 634 #define FP2_DV0_EN (1 << 25)
633 #define FP2_DV0_RATE_SEL_SDR (1 << 26) 635 #define FP2_DV0_RATE_SEL_SDR (1 << 26)
634 636
635 637
636 /* LVDS_GEN_CNTL bit constants */ 638 /* LVDS_GEN_CNTL bit constants */
637 #define LVDS_ON (1 << 0) 639 #define LVDS_ON (1 << 0)
638 #define LVDS_DISPLAY_DIS (1 << 1) 640 #define LVDS_DISPLAY_DIS (1 << 1)
639 #define LVDS_PANEL_TYPE (1 << 2) 641 #define LVDS_PANEL_TYPE (1 << 2)
640 #define LVDS_PANEL_FORMAT (1 << 3) 642 #define LVDS_PANEL_FORMAT (1 << 3)
641 #define LVDS_EN (1 << 7) 643 #define LVDS_EN (1 << 7)
642 #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 644 #define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00
643 #define LVDS_BL_MOD_LEVEL_SHIFT 8 645 #define LVDS_BL_MOD_LEVEL_SHIFT 8
644 #define LVDS_BL_MOD_EN (1 << 16) 646 #define LVDS_BL_MOD_EN (1 << 16)
645 #define LVDS_DIGON (1 << 18) 647 #define LVDS_DIGON (1 << 18)
646 #define LVDS_BLON (1 << 19) 648 #define LVDS_BLON (1 << 19)
647 #define LVDS_SEL_CRTC2 (1 << 23) 649 #define LVDS_SEL_CRTC2 (1 << 23)
648 #define LVDS_STATE_MASK \ 650 #define LVDS_STATE_MASK \
649 (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON) 651 (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON)
650 652
651 /* LVDS_PLL_CNTL bit constatns */ 653 /* LVDS_PLL_CNTL bit constatns */
652 #define HSYNC_DELAY_SHIFT 0x1c 654 #define HSYNC_DELAY_SHIFT 0x1c
653 #define HSYNC_DELAY_MASK (0xf << 0x1c) 655 #define HSYNC_DELAY_MASK (0xf << 0x1c)
654 656
655 /* TMDS_TRANSMITTER_CNTL bit constants */ 657 /* TMDS_TRANSMITTER_CNTL bit constants */
656 #define TMDS_PLL_EN (1 << 0) 658 #define TMDS_PLL_EN (1 << 0)
657 #define TMDS_PLLRST (1 << 1) 659 #define TMDS_PLLRST (1 << 1)
658 #define TMDS_RAN_PAT_RST (1 << 7) 660 #define TMDS_RAN_PAT_RST (1 << 7)
659 #define TMDS_ICHCSEL (1 << 28) 661 #define TMDS_ICHCSEL (1 << 28)
660 662
661 /* FP_HORZ_STRETCH bit constants */ 663 /* FP_HORZ_STRETCH bit constants */
662 #define HORZ_STRETCH_RATIO_MASK 0xffff 664 #define HORZ_STRETCH_RATIO_MASK 0xffff
663 #define HORZ_STRETCH_RATIO_MAX 4096 665 #define HORZ_STRETCH_RATIO_MAX 4096
664 #define HORZ_PANEL_SIZE (0x1ff << 16) 666 #define HORZ_PANEL_SIZE (0x1ff << 16)
665 #define HORZ_PANEL_SHIFT 16 667 #define HORZ_PANEL_SHIFT 16
666 #define HORZ_STRETCH_PIXREP (0 << 25) 668 #define HORZ_STRETCH_PIXREP (0 << 25)
667 #define HORZ_STRETCH_BLEND (1 << 26) 669 #define HORZ_STRETCH_BLEND (1 << 26)
668 #define HORZ_STRETCH_ENABLE (1 << 25) 670 #define HORZ_STRETCH_ENABLE (1 << 25)
669 #define HORZ_AUTO_RATIO (1 << 27) 671 #define HORZ_AUTO_RATIO (1 << 27)
670 #define HORZ_FP_LOOP_STRETCH (0x7 << 28) 672 #define HORZ_FP_LOOP_STRETCH (0x7 << 28)
671 #define HORZ_AUTO_RATIO_INC (1 << 31) 673 #define HORZ_AUTO_RATIO_INC (1 << 31)
672 674
673 675
674 /* FP_VERT_STRETCH bit constants */ 676 /* FP_VERT_STRETCH bit constants */
675 #define VERT_STRETCH_RATIO_MASK 0xfff 677 #define VERT_STRETCH_RATIO_MASK 0xfff
676 #define VERT_STRETCH_RATIO_MAX 4096 678 #define VERT_STRETCH_RATIO_MAX 4096
677 #define VERT_PANEL_SIZE (0xfff << 12) 679 #define VERT_PANEL_SIZE (0xfff << 12)
678 #define VERT_PANEL_SHIFT 12 680 #define VERT_PANEL_SHIFT 12
679 #define VERT_STRETCH_LINREP (0 << 26) 681 #define VERT_STRETCH_LINREP (0 << 26)
680 #define VERT_STRETCH_BLEND (1 << 26) 682 #define VERT_STRETCH_BLEND (1 << 26)
681 #define VERT_STRETCH_ENABLE (1 << 25) 683 #define VERT_STRETCH_ENABLE (1 << 25)
682 #define VERT_AUTO_RATIO_EN (1 << 27) 684 #define VERT_AUTO_RATIO_EN (1 << 27)
683 #define VERT_FP_LOOP_STRETCH (0x7 << 28) 685 #define VERT_FP_LOOP_STRETCH (0x7 << 28)
684 #define VERT_STRETCH_RESERVED 0xf1000000 686 #define VERT_STRETCH_RESERVED 0xf1000000
685 687
686 /* DAC_CNTL bit constants */ 688 /* DAC_CNTL bit constants */
687 #define DAC_8BIT_EN 0x00000100 689 #define DAC_8BIT_EN 0x00000100
688 #define DAC_4BPP_PIX_ORDER 0x00000200 690 #define DAC_4BPP_PIX_ORDER 0x00000200
689 #define DAC_CRC_EN 0x00080000 691 #define DAC_CRC_EN 0x00080000
690 #define DAC_MASK_ALL (0xff << 24) 692 #define DAC_MASK_ALL (0xff << 24)
691 #define DAC_PDWN (1 << 15) 693 #define DAC_PDWN (1 << 15)
692 #define DAC_EXPAND_MODE (1 << 14) 694 #define DAC_EXPAND_MODE (1 << 14)
693 #define DAC_VGA_ADR_EN (1 << 13) 695 #define DAC_VGA_ADR_EN (1 << 13)
694 #define DAC_RANGE_CNTL (3 << 0) 696 #define DAC_RANGE_CNTL (3 << 0)
695 #define DAC_RANGE_CNTL_MASK 0x03 697 #define DAC_RANGE_CNTL_MASK 0x03
696 #define DAC_BLANKING (1 << 2) 698 #define DAC_BLANKING (1 << 2)
697 #define DAC_CMP_EN (1 << 3) 699 #define DAC_CMP_EN (1 << 3)
698 #define DAC_CMP_OUTPUT (1 << 7) 700 #define DAC_CMP_OUTPUT (1 << 7)
699 701
700 /* DAC_CNTL2 bit constants */ 702 /* DAC_CNTL2 bit constants */
701 #define DAC2_EXPAND_MODE (1 << 14) 703 #define DAC2_EXPAND_MODE (1 << 14)
702 #define DAC2_CMP_EN (1 << 7) 704 #define DAC2_CMP_EN (1 << 7)
703 #define DAC2_PALETTE_ACCESS_CNTL (1 << 5) 705 #define DAC2_PALETTE_ACCESS_CNTL (1 << 5)
704 706
705 /* DAC_EXT_CNTL bit constants */ 707 /* DAC_EXT_CNTL bit constants */
706 #define DAC_FORCE_BLANK_OFF_EN (1 << 4) 708 #define DAC_FORCE_BLANK_OFF_EN (1 << 4)
707 #define DAC_FORCE_DATA_EN (1 << 5) 709 #define DAC_FORCE_DATA_EN (1 << 5)
708 #define DAC_FORCE_DATA_SEL_MASK (3 << 6) 710 #define DAC_FORCE_DATA_SEL_MASK (3 << 6)
709 #define DAC_FORCE_DATA_MASK 0x0003ff00 711 #define DAC_FORCE_DATA_MASK 0x0003ff00
710 #define DAC_FORCE_DATA_SHIFT 8 712 #define DAC_FORCE_DATA_SHIFT 8
711 713
712 /* GEN_RESET_CNTL bit constants */ 714 /* GEN_RESET_CNTL bit constants */
713 #define SOFT_RESET_GUI 0x00000001 715 #define SOFT_RESET_GUI 0x00000001
714 #define SOFT_RESET_VCLK 0x00000100 716 #define SOFT_RESET_VCLK 0x00000100
715 #define SOFT_RESET_PCLK 0x00000200 717 #define SOFT_RESET_PCLK 0x00000200
716 #define SOFT_RESET_ECP 0x00000400 718 #define SOFT_RESET_ECP 0x00000400
717 #define SOFT_RESET_DISPENG_XCLK 0x00000800 719 #define SOFT_RESET_DISPENG_XCLK 0x00000800
718 720
719 /* MEM_CNTL bit constants */ 721 /* MEM_CNTL bit constants */
720 #define MEM_CTLR_STATUS_IDLE 0x00000000 722 #define MEM_CTLR_STATUS_IDLE 0x00000000
721 #define MEM_CTLR_STATUS_BUSY 0x00100000 723 #define MEM_CTLR_STATUS_BUSY 0x00100000
722 #define MEM_SEQNCR_STATUS_IDLE 0x00000000 724 #define MEM_SEQNCR_STATUS_IDLE 0x00000000
723 #define MEM_SEQNCR_STATUS_BUSY 0x00200000 725 #define MEM_SEQNCR_STATUS_BUSY 0x00200000
724 #define MEM_ARBITER_STATUS_IDLE 0x00000000 726 #define MEM_ARBITER_STATUS_IDLE 0x00000000
725 #define MEM_ARBITER_STATUS_BUSY 0x00400000 727 #define MEM_ARBITER_STATUS_BUSY 0x00400000
726 #define MEM_REQ_UNLOCK 0x00000000 728 #define MEM_REQ_UNLOCK 0x00000000
727 #define MEM_REQ_LOCK 0x00800000 729 #define MEM_REQ_LOCK 0x00800000
728 #define MEM_NUM_CHANNELS_MASK 0x00000001 730 #define MEM_NUM_CHANNELS_MASK 0x00000001
729 #define MEM_USE_B_CH_ONLY 0x00000002 731 #define MEM_USE_B_CH_ONLY 0x00000002
730 #define RV100_MEM_HALF_MODE 0x00000008 732 #define RV100_MEM_HALF_MODE 0x00000008
731 #define R300_MEM_NUM_CHANNELS_MASK 0x00000003 733 #define R300_MEM_NUM_CHANNELS_MASK 0x00000003
732 #define R300_MEM_USE_CD_CH_ONLY 0x00000004 734 #define R300_MEM_USE_CD_CH_ONLY 0x00000004
733 735
734 736
735 /* RBBM_SOFT_RESET bit constants */ 737 /* RBBM_SOFT_RESET bit constants */
736 #define SOFT_RESET_CP (1 << 0) 738 #define SOFT_RESET_CP (1 << 0)
737 #define SOFT_RESET_HI (1 << 1) 739 #define SOFT_RESET_HI (1 << 1)
738 #define SOFT_RESET_SE (1 << 2) 740 #define SOFT_RESET_SE (1 << 2)
739 #define SOFT_RESET_RE (1 << 3) 741 #define SOFT_RESET_RE (1 << 3)
740 #define SOFT_RESET_PP (1 << 4) 742 #define SOFT_RESET_PP (1 << 4)
741 #define SOFT_RESET_E2 (1 << 5) 743 #define SOFT_RESET_E2 (1 << 5)
742 #define SOFT_RESET_RB (1 << 6) 744 #define SOFT_RESET_RB (1 << 6)
743 #define SOFT_RESET_HDP (1 << 7) 745 #define SOFT_RESET_HDP (1 << 7)
744 746
745 /* SURFACE_CNTL bit consants */ 747 /* SURFACE_CNTL bit consants */
746 #define SURF_TRANSLATION_DIS (1 << 8) 748 #define SURF_TRANSLATION_DIS (1 << 8)
747 #define NONSURF_AP0_SWP_16BPP (1 << 20) 749 #define NONSURF_AP0_SWP_16BPP (1 << 20)
748 #define NONSURF_AP0_SWP_32BPP (1 << 21) 750 #define NONSURF_AP0_SWP_32BPP (1 << 21)
749 #define NONSURF_AP1_SWP_16BPP (1 << 22) 751 #define NONSURF_AP1_SWP_16BPP (1 << 22)
750 #define NONSURF_AP1_SWP_32BPP (1 << 23) 752 #define NONSURF_AP1_SWP_32BPP (1 << 23)
753
754 #define R200_SURF_TILE_COLOR_MACRO (1 << 16)
751 755
752 /* DEFAULT_SC_BOTTOM_RIGHT bit constants */ 756 /* DEFAULT_SC_BOTTOM_RIGHT bit constants */
753 #define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) 757 #define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
754 #define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) 758 #define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
755 759
756 /* MM_INDEX bit constants */ 760 /* MM_INDEX bit constants */
757 #define MM_APER 0x80000000 761 #define MM_APER 0x80000000
758 762
759 /* CLR_CMP_CNTL bit constants */ 763 /* CLR_CMP_CNTL bit constants */
760 #define COMPARE_SRC_FALSE 0x00000000 764 #define COMPARE_SRC_FALSE 0x00000000
761 #define COMPARE_SRC_TRUE 0x00000001 765 #define COMPARE_SRC_TRUE 0x00000001
762 #define COMPARE_SRC_NOT_EQUAL 0x00000004 766 #define COMPARE_SRC_NOT_EQUAL 0x00000004
763 #define COMPARE_SRC_EQUAL 0x00000005 767 #define COMPARE_SRC_EQUAL 0x00000005
764 #define COMPARE_SRC_EQUAL_FLIP 0x00000007 768 #define COMPARE_SRC_EQUAL_FLIP 0x00000007
765 #define COMPARE_DST_FALSE 0x00000000 769 #define COMPARE_DST_FALSE 0x00000000
766 #define COMPARE_DST_TRUE 0x00000100 770 #define COMPARE_DST_TRUE 0x00000100
767 #define COMPARE_DST_NOT_EQUAL 0x00000400 771 #define COMPARE_DST_NOT_EQUAL 0x00000400
768 #define COMPARE_DST_EQUAL 0x00000500 772 #define COMPARE_DST_EQUAL 0x00000500
769 #define COMPARE_DESTINATION 0x00000000 773 #define COMPARE_DESTINATION 0x00000000
770 #define COMPARE_SOURCE 0x01000000 774 #define COMPARE_SOURCE 0x01000000
771 #define COMPARE_SRC_AND_DST 0x02000000 775 #define COMPARE_SRC_AND_DST 0x02000000
772 776
773 777
774 /* DP_CNTL bit constants */ 778 /* DP_CNTL bit constants */
775 #define DST_X_RIGHT_TO_LEFT 0x00000000 779 #define DST_X_RIGHT_TO_LEFT 0x00000000
776 #define DST_X_LEFT_TO_RIGHT 0x00000001 780 #define DST_X_LEFT_TO_RIGHT 0x00000001
777 #define DST_Y_BOTTOM_TO_TOP 0x00000000 781 #define DST_Y_BOTTOM_TO_TOP 0x00000000
778 #define DST_Y_TOP_TO_BOTTOM 0x00000002 782 #define DST_Y_TOP_TO_BOTTOM 0x00000002
779 #define DST_X_MAJOR 0x00000000 783 #define DST_X_MAJOR 0x00000000
780 #define DST_Y_MAJOR 0x00000004 784 #define DST_Y_MAJOR 0x00000004
781 #define DST_X_TILE 0x00000008 785 #define DST_X_TILE 0x00000008
782 #define DST_Y_TILE 0x00000010 786 #define DST_Y_TILE 0x00000010
783 #define DST_LAST_PEL 0x00000020 787 #define DST_LAST_PEL 0x00000020
784 #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 788 #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000
785 #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 789 #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040
786 #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 790 #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000
787 #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 791 #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080
788 #define DST_BRES_SIGN 0x00000100 792 #define DST_BRES_SIGN 0x00000100
789 #define DST_HOST_BIG_ENDIAN_EN 0x00000200 793 #define DST_HOST_BIG_ENDIAN_EN 0x00000200
790 #define DST_POLYLINE_NONLAST 0x00008000 794 #define DST_POLYLINE_NONLAST 0x00008000
791 #define DST_RASTER_STALL 0x00010000 795 #define DST_RASTER_STALL 0x00010000
792 #define DST_POLY_EDGE 0x00040000 796 #define DST_POLY_EDGE 0x00040000
793 797
794 798
795 /* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ 799 /* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */
796 #define DST_X_MAJOR_S 0x00000000 800 #define DST_X_MAJOR_S 0x00000000
797 #define DST_Y_MAJOR_S 0x00000001 801 #define DST_Y_MAJOR_S 0x00000001
798 #define DST_Y_BOTTOM_TO_TOP_S 0x00000000 802 #define DST_Y_BOTTOM_TO_TOP_S 0x00000000
799 #define DST_Y_TOP_TO_BOTTOM_S 0x00008000 803 #define DST_Y_TOP_TO_BOTTOM_S 0x00008000
800 #define DST_X_RIGHT_TO_LEFT_S 0x00000000 804 #define DST_X_RIGHT_TO_LEFT_S 0x00000000
801 #define DST_X_LEFT_TO_RIGHT_S 0x80000000 805 #define DST_X_LEFT_TO_RIGHT_S 0x80000000
802 806
803 807
804 /* DP_DATATYPE bit constants */ 808 /* DP_DATATYPE bit constants */
805 #define DST_8BPP 0x00000002 809 #define DST_8BPP 0x00000002
806 #define DST_15BPP 0x00000003 810 #define DST_15BPP 0x00000003
807 #define DST_16BPP 0x00000004 811 #define DST_16BPP 0x00000004
808 #define DST_24BPP 0x00000005 812 #define DST_24BPP 0x00000005
809 #define DST_32BPP 0x00000006 813 #define DST_32BPP 0x00000006
810 #define DST_8BPP_RGB332 0x00000007 814 #define DST_8BPP_RGB332 0x00000007
811 #define DST_8BPP_Y8 0x00000008 815 #define DST_8BPP_Y8 0x00000008
812 #define DST_8BPP_RGB8 0x00000009 816 #define DST_8BPP_RGB8 0x00000009
813 #define DST_16BPP_VYUY422 0x0000000b 817 #define DST_16BPP_VYUY422 0x0000000b
814 #define DST_16BPP_YVYU422 0x0000000c 818 #define DST_16BPP_YVYU422 0x0000000c
815 #define DST_32BPP_AYUV444 0x0000000e 819 #define DST_32BPP_AYUV444 0x0000000e
816 #define DST_16BPP_ARGB4444 0x0000000f 820 #define DST_16BPP_ARGB4444 0x0000000f
817 #define BRUSH_SOLIDCOLOR 0x00000d00 821 #define BRUSH_SOLIDCOLOR 0x00000d00
818 #define SRC_MONO 0x00000000 822 #define SRC_MONO 0x00000000
819 #define SRC_MONO_LBKGD 0x00010000 823 #define SRC_MONO_LBKGD 0x00010000
820 #define SRC_DSTCOLOR 0x00030000 824 #define SRC_DSTCOLOR 0x00030000
821 #define BYTE_ORDER_MSB_TO_LSB 0x00000000 825 #define BYTE_ORDER_MSB_TO_LSB 0x00000000
822 #define BYTE_ORDER_LSB_TO_MSB 0x40000000 826 #define BYTE_ORDER_LSB_TO_MSB 0x40000000
823 #define DP_CONVERSION_TEMP 0x80000000 827 #define DP_CONVERSION_TEMP 0x80000000
824 #define HOST_BIG_ENDIAN_EN (1 << 29) 828 #define HOST_BIG_ENDIAN_EN (1 << 29)
825 829
826 830
827 /* DP_GUI_MASTER_CNTL bit constants */ 831 /* DP_GUI_MASTER_CNTL bit constants */
828 #define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 832 #define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000
829 #define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 833 #define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001
830 #define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 834 #define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000
831 #define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 835 #define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002
832 #define GMC_SRC_CLIP_DEFAULT 0x00000000 836 #define GMC_SRC_CLIP_DEFAULT 0x00000000
833 #define GMC_SRC_CLIP_LEAVE 0x00000004 837 #define GMC_SRC_CLIP_LEAVE 0x00000004
834 #define GMC_DST_CLIP_DEFAULT 0x00000000 838 #define GMC_DST_CLIP_DEFAULT 0x00000000
835 #define GMC_DST_CLIP_LEAVE 0x00000008 839 #define GMC_DST_CLIP_LEAVE 0x00000008
836 #define GMC_BRUSH_8x8MONO 0x00000000 840 #define GMC_BRUSH_8x8MONO 0x00000000
837 #define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 841 #define GMC_BRUSH_8x8MONO_LBKGD 0x00000010
838 #define GMC_BRUSH_8x1MONO 0x00000020 842 #define GMC_BRUSH_8x1MONO 0x00000020
839 #define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 843 #define GMC_BRUSH_8x1MONO_LBKGD 0x00000030
840 #define GMC_BRUSH_1x8MONO 0x00000040 844 #define GMC_BRUSH_1x8MONO 0x00000040
841 #define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 845 #define GMC_BRUSH_1x8MONO_LBKGD 0x00000050
842 #define GMC_BRUSH_32x1MONO 0x00000060 846 #define GMC_BRUSH_32x1MONO 0x00000060
843 #define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 847 #define GMC_BRUSH_32x1MONO_LBKGD 0x00000070
844 #define GMC_BRUSH_32x32MONO 0x00000080 848 #define GMC_BRUSH_32x32MONO 0x00000080
845 #define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 849 #define GMC_BRUSH_32x32MONO_LBKGD 0x00000090
846 #define GMC_BRUSH_8x8COLOR 0x000000a0 850 #define GMC_BRUSH_8x8COLOR 0x000000a0
847 #define GMC_BRUSH_8x1COLOR 0x000000b0 851 #define GMC_BRUSH_8x1COLOR 0x000000b0
848 #define GMC_BRUSH_1x8COLOR 0x000000c0 852 #define GMC_BRUSH_1x8COLOR 0x000000c0
849 #define GMC_BRUSH_SOLID_COLOR 0x000000d0 853 #define GMC_BRUSH_SOLID_COLOR 0x000000d0
850 #define GMC_DST_8BPP 0x00000200 854 #define GMC_DST_8BPP 0x00000200
851 #define GMC_DST_15BPP 0x00000300 855 #define GMC_DST_15BPP 0x00000300
852 #define GMC_DST_16BPP 0x00000400 856 #define GMC_DST_16BPP 0x00000400
853 #define GMC_DST_24BPP 0x00000500 857 #define GMC_DST_24BPP 0x00000500
854 #define GMC_DST_32BPP 0x00000600 858 #define GMC_DST_32BPP 0x00000600
855 #define GMC_DST_8BPP_RGB332 0x00000700 859 #define GMC_DST_8BPP_RGB332 0x00000700
856 #define GMC_DST_8BPP_Y8 0x00000800 860 #define GMC_DST_8BPP_Y8 0x00000800
857 #define GMC_DST_8BPP_RGB8 0x00000900 861 #define GMC_DST_8BPP_RGB8 0x00000900
858 #define GMC_DST_16BPP_VYUY422 0x00000b00 862 #define GMC_DST_16BPP_VYUY422 0x00000b00
859 #define GMC_DST_16BPP_YVYU422 0x00000c00 863 #define GMC_DST_16BPP_YVYU422 0x00000c00
860 #define GMC_DST_32BPP_AYUV444 0x00000e00 864 #define GMC_DST_32BPP_AYUV444 0x00000e00
861 #define GMC_DST_16BPP_ARGB4444 0x00000f00 865 #define GMC_DST_16BPP_ARGB4444 0x00000f00
862 #define GMC_SRC_MONO 0x00000000 866 #define GMC_SRC_MONO 0x00000000
863 #define GMC_SRC_MONO_LBKGD 0x00001000 867 #define GMC_SRC_MONO_LBKGD 0x00001000
864 #define GMC_SRC_DSTCOLOR 0x00003000 868 #define GMC_SRC_DSTCOLOR 0x00003000
865 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 869 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000
866 #define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 870 #define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000
867 #define GMC_DP_CONVERSION_TEMP_9300 0x00008000 871 #define GMC_DP_CONVERSION_TEMP_9300 0x00008000
868 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 872 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000
869 #define GMC_DP_SRC_RECT 0x02000000 873 #define GMC_DP_SRC_RECT 0x02000000
870 #define GMC_DP_SRC_HOST 0x03000000 874 #define GMC_DP_SRC_HOST 0x03000000
871 #define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 875 #define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000
872 #define GMC_3D_FCN_EN_CLR 0x00000000 876 #define GMC_3D_FCN_EN_CLR 0x00000000
873 #define GMC_3D_FCN_EN_SET 0x08000000 877 #define GMC_3D_FCN_EN_SET 0x08000000
874 #define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 878 #define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000
875 #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 879 #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000
876 #define GMC_AUX_CLIP_LEAVE 0x00000000 880 #define GMC_AUX_CLIP_LEAVE 0x00000000
877 #define GMC_AUX_CLIP_CLEAR 0x20000000 881 #define GMC_AUX_CLIP_CLEAR 0x20000000
878 #define GMC_WRITE_MASK_LEAVE 0x00000000 882 #define GMC_WRITE_MASK_LEAVE 0x00000000
879 #define GMC_WRITE_MASK_SET 0x40000000 883 #define GMC_WRITE_MASK_SET 0x40000000
880 #define GMC_CLR_CMP_CNTL_DIS (1 << 28) 884 #define GMC_CLR_CMP_CNTL_DIS (1 << 28)
881 #define GMC_SRC_DATATYPE_COLOR (3 << 12) 885 #define GMC_SRC_DATATYPE_COLOR (3 << 12)
882 #define ROP3_S 0x00cc0000 886 #define ROP3_S 0x00cc0000
883 #define ROP3_SRCCOPY 0x00cc0000 887 #define ROP3_SRCCOPY 0x00cc0000
884 #define ROP3_P 0x00f00000 888 #define ROP3_P 0x00f00000
885 #define ROP3_PATCOPY 0x00f00000 889 #define ROP3_PATCOPY 0x00f00000
886 #define DP_SRC_SOURCE_MASK (7 << 24) 890 #define DP_SRC_SOURCE_MASK (7 << 24)
887 #define GMC_BRUSH_NONE (15 << 4) 891 #define GMC_BRUSH_NONE (15 << 4)
888 #define DP_SRC_SOURCE_MEMORY (2 << 24) 892 #define DP_SRC_SOURCE_MEMORY (2 << 24)
889 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 893 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0
890 894
891 /* DP_MIX bit constants */ 895 /* DP_MIX bit constants */
892 #define DP_SRC_RECT 0x00000200 896 #define DP_SRC_RECT 0x00000200
893 #define DP_SRC_HOST 0x00000300 897 #define DP_SRC_HOST 0x00000300
894 #define DP_SRC_HOST_BYTEALIGN 0x00000400 898 #define DP_SRC_HOST_BYTEALIGN 0x00000400
895 899
896 /* MPLL_CNTL bit constants */ 900 /* MPLL_CNTL bit constants */
897 #define MPLL_RESET 0x00000001 901 #define MPLL_RESET 0x00000001
898 902
899 /* MDLL_CKO bit constants */ 903 /* MDLL_CKO bit constants */
900 #define MCKOA_SLEEP 0x00000001 904 #define MCKOA_SLEEP 0x00000001
901 #define MCKOA_RESET 0x00000002 905 #define MCKOA_RESET 0x00000002
902 #define MCKOA_REF_SKEW_MASK 0x00000700 906 #define MCKOA_REF_SKEW_MASK 0x00000700
903 #define MCKOA_FB_SKEW_MASK 0x00007000 907 #define MCKOA_FB_SKEW_MASK 0x00007000
904 908
905 /* MDLL_RDCKA bit constants */ 909 /* MDLL_RDCKA bit constants */
906 #define MRDCKA0_SLEEP 0x00000001 910 #define MRDCKA0_SLEEP 0x00000001
907 #define MRDCKA0_RESET 0x00000002 911 #define MRDCKA0_RESET 0x00000002
908 #define MRDCKA1_SLEEP 0x00010000 912 #define MRDCKA1_SLEEP 0x00010000
909 #define MRDCKA1_RESET 0x00020000 913 #define MRDCKA1_RESET 0x00020000
910 914
911 /* VCLK_ECP_CNTL constants */ 915 /* VCLK_ECP_CNTL constants */
912 #define VCLK_SRC_SEL_MASK 0x03 916 #define VCLK_SRC_SEL_MASK 0x03
913 #define VCLK_SRC_SEL_CPUCLK 0x00 917 #define VCLK_SRC_SEL_CPUCLK 0x00
914 #define VCLK_SRC_SEL_PSCANCLK 0x01 918 #define VCLK_SRC_SEL_PSCANCLK 0x01
915 #define VCLK_SRC_SEL_BYTECLK 0x02 919 #define VCLK_SRC_SEL_BYTECLK 0x02
916 #define VCLK_SRC_SEL_PPLLCLK 0x03 920 #define VCLK_SRC_SEL_PPLLCLK 0x03
917 #define PIXCLK_ALWAYS_ONb 0x00000040 921 #define PIXCLK_ALWAYS_ONb 0x00000040
918 #define PIXCLK_DAC_ALWAYS_ONb 0x00000080 922 #define PIXCLK_DAC_ALWAYS_ONb 0x00000080
919 923
920 /* BUS_CNTL1 constants */ 924 /* BUS_CNTL1 constants */
921 #define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 925 #define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000
922 #define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 926 #define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26
923 #define BUS_CNTL1_AGPCLK_VALID 0x80000000 927 #define BUS_CNTL1_AGPCLK_VALID 0x80000000
924 928
925 /* PLL_PWRMGT_CNTL constants */ 929 /* PLL_PWRMGT_CNTL constants */
926 #define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 930 #define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002
927 #define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 931 #define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004
928 #define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 932 #define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008
929 #define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 933 #define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010
930 #define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 934 #define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000
931 #define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 935 #define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000
932 #define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 936 #define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000
933 937
934 /* TV_DAC_CNTL constants */ 938 /* TV_DAC_CNTL constants */
935 #define TV_DAC_CNTL_BGSLEEP 0x00000040 939 #define TV_DAC_CNTL_BGSLEEP 0x00000040
936 #define TV_DAC_CNTL_DETECT 0x00000010 940 #define TV_DAC_CNTL_DETECT 0x00000010
937 #define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 941 #define TV_DAC_CNTL_BGADJ_MASK 0x000f0000
938 #define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 942 #define TV_DAC_CNTL_DACADJ_MASK 0x00f00000
939 #define TV_DAC_CNTL_BGADJ__SHIFT 16 943 #define TV_DAC_CNTL_BGADJ__SHIFT 16
940 #define TV_DAC_CNTL_DACADJ__SHIFT 20 944 #define TV_DAC_CNTL_DACADJ__SHIFT 20
941 #define TV_DAC_CNTL_RDACPD 0x01000000 945 #define TV_DAC_CNTL_RDACPD 0x01000000
942 #define TV_DAC_CNTL_GDACPD 0x02000000 946 #define TV_DAC_CNTL_GDACPD 0x02000000
943 #define TV_DAC_CNTL_BDACPD 0x04000000 947 #define TV_DAC_CNTL_BDACPD 0x04000000
944 948
945 /* DISP_MISC_CNTL constants */ 949 /* DISP_MISC_CNTL constants */
946 #define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) 950 #define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0)
947 #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) 951 #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1)
948 #define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) 952 #define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2)
949 #define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) 953 #define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4)
950 #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) 954 #define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5)
951 #define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) 955 #define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6)
952 #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) 956 #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12)
953 #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) 957 #define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15)
954 #define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) 958 #define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16)
955 #define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) 959 #define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17)
956 #define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) 960 #define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18)
957 #define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) 961 #define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19)
958 962
959 /* DISP_PWR_MAN constants */ 963 /* DISP_PWR_MAN constants */
960 #define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) 964 #define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)
961 #define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) 965 #define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4)
962 #define DISP_PWR_MAN_DISP_D3_RST (1 << 16) 966 #define DISP_PWR_MAN_DISP_D3_RST (1 << 16)
963 #define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) 967 #define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17)
964 #define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) 968 #define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18)
965 #define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) 969 #define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19)
966 #define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) 970 #define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20)
967 #define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) 971 #define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21)
968 #define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) 972 #define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22)
969 #define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) 973 #define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23)
970 #define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) 974 #define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24)
971 #define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) 975 #define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25)
972 #define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) 976 #define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26)
973 977
974 /* masks */ 978 /* masks */
975 979
976 #define CONFIG_MEMSIZE_MASK 0x1f000000 980 #define CONFIG_MEMSIZE_MASK 0x1f000000
977 #define MEM_CFG_TYPE 0x40000000 981 #define MEM_CFG_TYPE 0x40000000
978 #define DST_OFFSET_MASK 0x003fffff 982 #define DST_OFFSET_MASK 0x003fffff
979 #define DST_PITCH_MASK 0x3fc00000 983 #define DST_PITCH_MASK 0x3fc00000
980 #define DEFAULT_TILE_MASK 0xc0000000 984 #define DEFAULT_TILE_MASK 0xc0000000
981 #define PPLL_DIV_SEL_MASK 0x00000300 985 #define PPLL_DIV_SEL_MASK 0x00000300
982 #define PPLL_RESET 0x00000001 986 #define PPLL_RESET 0x00000001
983 #define PPLL_SLEEP 0x00000002 987 #define PPLL_SLEEP 0x00000002
984 #define PPLL_ATOMIC_UPDATE_EN 0x00010000 988 #define PPLL_ATOMIC_UPDATE_EN 0x00010000
985 #define PPLL_REF_DIV_MASK 0x000003ff 989 #define PPLL_REF_DIV_MASK 0x000003ff
986 #define PPLL_FB3_DIV_MASK 0x000007ff 990 #define PPLL_FB3_DIV_MASK 0x000007ff
987 #define PPLL_POST3_DIV_MASK 0x00070000 991 #define PPLL_POST3_DIV_MASK 0x00070000
988 #define PPLL_ATOMIC_UPDATE_R 0x00008000 992 #define PPLL_ATOMIC_UPDATE_R 0x00008000
989 #define PPLL_ATOMIC_UPDATE_W 0x00008000 993 #define PPLL_ATOMIC_UPDATE_W 0x00008000
990 #define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 994 #define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000
991 #define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) 995 #define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
992 #define R300_PPLL_REF_DIV_ACC_SHIFT 18 996 #define R300_PPLL_REF_DIV_ACC_SHIFT 18
993 997
994 #define GUI_ACTIVE 0x80000000 998 #define GUI_ACTIVE 0x80000000
995 999
996 1000
997 #define MC_IND_INDEX 0x01F8 1001 #define MC_IND_INDEX 0x01F8
998 #define MC_IND_DATA 0x01FC 1002 #define MC_IND_DATA 0x01FC
999 1003
1000 /* PAD_CTLR_STRENGTH */ 1004 /* PAD_CTLR_STRENGTH */
1001 #define PAD_MANUAL_OVERRIDE 0x80000000 1005 #define PAD_MANUAL_OVERRIDE 0x80000000
1002 1006
1003 /* pllCLK_PIN_CNTL */ 1007 /* pllCLK_PIN_CNTL */
1004 #define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L 1008 #define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L
1005 #define CLK_PIN_CNTL__OSC_EN 0x00000001L 1009 #define CLK_PIN_CNTL__OSC_EN 0x00000001L
1006 #define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L 1010 #define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L
1007 #define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L 1011 #define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L
1008 #define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L 1012 #define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L
1009 #define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L 1013 #define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L
1010 #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L 1014 #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L
1011 #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L 1015 #define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L
1012 #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L 1016 #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L
1013 #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L 1017 #define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L
1014 #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L 1018 #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L
1015 #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L 1019 #define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L
1016 #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L 1020 #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L
1017 #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L 1021 #define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L
1018 #define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L 1022 #define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L
1019 #define CLK_PIN_CNTL__CG_SPARE 0x00004000L 1023 #define CLK_PIN_CNTL__CG_SPARE 0x00004000L
1020 #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L 1024 #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L
1021 #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L 1025 #define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L
1022 #define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L 1026 #define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L
1023 #define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L 1027 #define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L
1024 #define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L 1028 #define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L
1025 #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L 1029 #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L
1026 #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L 1030 #define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L
1027 #define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L 1031 #define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L
1028 1032
1029 /* pllCLK_PWRMGT_CNTL */ 1033 /* pllCLK_PWRMGT_CNTL */
1030 #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 1034 #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000
1031 #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 1035 #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001
1032 #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 1036 #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002
1033 #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 1037 #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003
1034 #define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004 1038 #define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004
1035 #define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005 1039 #define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005
1036 #define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006 1040 #define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006
1037 #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007 1041 #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007
1038 #define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008 1042 #define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008
1039 #define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009 1043 #define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009
1040 #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a 1044 #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a
1041 #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c 1045 #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c
1042 #define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d 1046 #define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d
1043 #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f 1047 #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f
1044 #define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010 1048 #define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010
1045 #define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011 1049 #define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011
1046 #define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012 1050 #define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012
1047 #define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013 1051 #define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013
1048 #define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014 1052 #define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014
1049 #define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015 1053 #define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015
1050 #define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018 1054 #define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018
1051 #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e 1055 #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e
1052 #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f 1056 #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f
1053 1057
1054 /* pllP2PLL_CNTL */ 1058 /* pllP2PLL_CNTL */
1055 #define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L 1059 #define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L
1056 #define P2PLL_CNTL__P2PLL_RESET 0x00000001L 1060 #define P2PLL_CNTL__P2PLL_RESET 0x00000001L
1057 #define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L 1061 #define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L
1058 #define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L 1062 #define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L
1059 #define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L 1063 #define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L
1060 #define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L 1064 #define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L
1061 #define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L 1065 #define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L
1062 #define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L 1066 #define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L
1063 #define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L 1067 #define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L
1064 #define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L 1068 #define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L
1065 #define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L 1069 #define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L
1066 #define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L 1070 #define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L
1067 #define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L 1071 #define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L
1068 #define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L 1072 #define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L
1069 #define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L 1073 #define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L
1070 #define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L 1074 #define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L
1071 #define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L 1075 #define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L
1072 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L 1076 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L
1073 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L 1077 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L
1074 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L 1078 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L
1075 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L 1079 #define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L
1076 #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L 1080 #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L
1077 #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L 1081 #define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L
1078 1082
1079 /* pllPIXCLKS_CNTL */ 1083 /* pllPIXCLKS_CNTL */
1080 #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 1084 #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000
1081 #define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 1085 #define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004
1082 #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 1086 #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005
1083 #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 1087 #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006
1084 #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 1088 #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007
1085 #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 1089 #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008
1086 #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b 1090 #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b
1087 #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c 1091 #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c
1088 #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d 1092 #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d
1089 #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e 1093 #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e
1090 #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f 1094 #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f
1091 1095
1092 1096
1093 /* pllPIXCLKS_CNTL */ 1097 /* pllPIXCLKS_CNTL */
1094 #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L 1098 #define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L
1095 #define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L 1099 #define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L
1096 #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L 1100 #define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L
1097 #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L 1101 #define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L
1098 #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L 1102 #define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L
1099 #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L 1103 #define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L
1100 #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L 1104 #define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L
1101 #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L 1105 #define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L
1102 #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L 1106 #define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L
1103 #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L 1107 #define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L
1104 #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L 1108 #define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L
1105 #define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) 1109 #define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
1106 #define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) 1110 #define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10)
1107 #define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) 1111 #define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
1108 #define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) 1112 #define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
1109 #define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) 1113 #define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
1110 #define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) 1114 #define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18)
1111 #define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) 1115 #define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
1112 #define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) 1116 #define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
1113 1117
1114 1118
1115 /* pllP2PLL_DIV_0 */ 1119 /* pllP2PLL_DIV_0 */
1116 #define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL 1120 #define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL
1117 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L 1121 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L
1118 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L 1122 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L
1119 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L 1123 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L
1120 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L 1124 #define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L
1121 #define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L 1125 #define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L
1122 1126
1123 /* pllSCLK_CNTL */ 1127 /* pllSCLK_CNTL */
1124 #define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L 1128 #define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L
1125 #define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L 1129 #define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L
1126 #define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L 1130 #define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L
1127 #define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L 1131 #define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L
1128 #define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L 1132 #define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L
1129 #define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L 1133 #define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L
1130 #define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L 1134 #define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L
1131 #define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L 1135 #define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L
1132 #define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L 1136 #define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L
1133 #define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L 1137 #define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L
1134 #define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L 1138 #define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L
1135 #define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L 1139 #define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L
1136 #define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L 1140 #define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L
1137 #define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8 1141 #define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8
1138 #define SCLK_CNTL__FORCE_DISP2 0x00008000L 1142 #define SCLK_CNTL__FORCE_DISP2 0x00008000L
1139 #define SCLK_CNTL__FORCE_CP 0x00010000L 1143 #define SCLK_CNTL__FORCE_CP 0x00010000L
1140 #define SCLK_CNTL__FORCE_HDP 0x00020000L 1144 #define SCLK_CNTL__FORCE_HDP 0x00020000L
1141 #define SCLK_CNTL__FORCE_DISP1 0x00040000L 1145 #define SCLK_CNTL__FORCE_DISP1 0x00040000L
1142 #define SCLK_CNTL__FORCE_TOP 0x00080000L 1146 #define SCLK_CNTL__FORCE_TOP 0x00080000L
1143 #define SCLK_CNTL__FORCE_E2 0x00100000L 1147 #define SCLK_CNTL__FORCE_E2 0x00100000L
1144 #define SCLK_CNTL__FORCE_SE 0x00200000L 1148 #define SCLK_CNTL__FORCE_SE 0x00200000L
1145 #define SCLK_CNTL__FORCE_IDCT 0x00400000L 1149 #define SCLK_CNTL__FORCE_IDCT 0x00400000L
1146 #define SCLK_CNTL__FORCE_VIP 0x00800000L 1150 #define SCLK_CNTL__FORCE_VIP 0x00800000L
1147 #define SCLK_CNTL__FORCE_RE 0x01000000L 1151 #define SCLK_CNTL__FORCE_RE 0x01000000L
1148 #define SCLK_CNTL__FORCE_PB 0x02000000L 1152 #define SCLK_CNTL__FORCE_PB 0x02000000L
1149 #define SCLK_CNTL__FORCE_TAM 0x04000000L 1153 #define SCLK_CNTL__FORCE_TAM 0x04000000L
1150 #define SCLK_CNTL__FORCE_TDM 0x08000000L 1154 #define SCLK_CNTL__FORCE_TDM 0x08000000L
1151 #define SCLK_CNTL__FORCE_RB 0x10000000L 1155 #define SCLK_CNTL__FORCE_RB 0x10000000L
1152 #define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L 1156 #define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L
1153 #define SCLK_CNTL__FORCE_SUBPIC 0x40000000L 1157 #define SCLK_CNTL__FORCE_SUBPIC 0x40000000L
1154 #define SCLK_CNTL__FORCE_OV0 0x80000000L 1158 #define SCLK_CNTL__FORCE_OV0 0x80000000L
1155 #define SCLK_CNTL__R300_FORCE_VAP (1<<21) 1159 #define SCLK_CNTL__R300_FORCE_VAP (1<<21)
1156 #define SCLK_CNTL__R300_FORCE_SR (1<<25) 1160 #define SCLK_CNTL__R300_FORCE_SR (1<<25)
1157 #define SCLK_CNTL__R300_FORCE_PX (1<<26) 1161 #define SCLK_CNTL__R300_FORCE_PX (1<<26)
1158 #define SCLK_CNTL__R300_FORCE_TX (1<<27) 1162 #define SCLK_CNTL__R300_FORCE_TX (1<<27)
1159 #define SCLK_CNTL__R300_FORCE_US (1<<28) 1163 #define SCLK_CNTL__R300_FORCE_US (1<<28)
1160 #define SCLK_CNTL__R300_FORCE_SU (1<<30) 1164 #define SCLK_CNTL__R300_FORCE_SU (1<<30)
1161 #define SCLK_CNTL__FORCEON_MASK 0xffff8000L 1165 #define SCLK_CNTL__FORCEON_MASK 0xffff8000L
1162 1166
1163 /* pllSCLK_CNTL2 */ 1167 /* pllSCLK_CNTL2 */
1164 #define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) 1168 #define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10)
1165 #define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) 1169 #define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11)
1166 #define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) 1170 #define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12)
1167 #define SCLK_CNTL2__R300_FORCE_TCL (1<<13) 1171 #define SCLK_CNTL2__R300_FORCE_TCL (1<<13)
1168 #define SCLK_CNTL2__R300_FORCE_CBA (1<<14) 1172 #define SCLK_CNTL2__R300_FORCE_CBA (1<<14)
1169 #define SCLK_CNTL2__R300_FORCE_GA (1<<15) 1173 #define SCLK_CNTL2__R300_FORCE_GA (1<<15)
1170 1174
1171 /* SCLK_MORE_CNTL */ 1175 /* SCLK_MORE_CNTL */
1172 #define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L 1176 #define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L
1173 #define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L 1177 #define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L
1174 #define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L 1178 #define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L
1175 #define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L 1179 #define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L
1176 #define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L 1180 #define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L
1177 #define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L 1181 #define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L
1178 #define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L 1182 #define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L
1179 #define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L 1183 #define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L
1180 #define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L 1184 #define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L
1181 #define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L 1185 #define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L
1182 #define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L 1186 #define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L
1183 #define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L 1187 #define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L
1184 #define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L 1188 #define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L
1185 #define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L 1189 #define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L
1186 #define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L 1190 #define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L
1187 #define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L 1191 #define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L
1188 #define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L 1192 #define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L
1189 #define SCLK_MORE_CNTL__FORCEON 0x00000700L 1193 #define SCLK_MORE_CNTL__FORCEON 0x00000700L
1190 1194
1191 /* MCLK_CNTL */ 1195 /* MCLK_CNTL */
1192 #define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L 1196 #define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L
1193 #define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L 1197 #define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L
1194 #define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L 1198 #define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L
1195 #define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L 1199 #define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L
1196 #define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L 1200 #define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L
1197 #define MCLK_CNTL__FORCE_MCLKA 0x00010000L 1201 #define MCLK_CNTL__FORCE_MCLKA 0x00010000L
1198 #define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L 1202 #define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L
1199 #define MCLK_CNTL__FORCE_MCLKB 0x00020000L 1203 #define MCLK_CNTL__FORCE_MCLKB 0x00020000L
1200 #define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L 1204 #define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L
1201 #define MCLK_CNTL__FORCE_YCLKA 0x00040000L 1205 #define MCLK_CNTL__FORCE_YCLKA 0x00040000L
1202 #define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L 1206 #define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L
1203 #define MCLK_CNTL__FORCE_YCLKB 0x00080000L 1207 #define MCLK_CNTL__FORCE_YCLKB 0x00080000L
1204 #define MCLK_CNTL__FORCE_MC_MASK 0x00100000L 1208 #define MCLK_CNTL__FORCE_MC_MASK 0x00100000L
1205 #define MCLK_CNTL__FORCE_MC 0x00100000L 1209 #define MCLK_CNTL__FORCE_MC 0x00100000L
1206 #define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L 1210 #define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L
1207 #define MCLK_CNTL__FORCE_AIC 0x00200000L 1211 #define MCLK_CNTL__FORCE_AIC 0x00200000L
1208 #define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L 1212 #define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L
1209 #define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L 1213 #define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L
1210 #define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L 1214 #define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L
1211 #define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L 1215 #define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L
1212 #define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) 1216 #define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21)
1213 #define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) 1217 #define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21)
1214 1218
1215 /* MCLK_MISC */ 1219 /* MCLK_MISC */
1216 #define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L 1220 #define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L
1217 #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L 1221 #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L
1218 #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L 1222 #define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L
1219 #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L 1223 #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L
1220 #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L 1224 #define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L
1221 #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L 1225 #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L
1222 #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L 1226 #define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L
1223 #define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L 1227 #define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L
1224 #define MCLK_MISC__DLL_READY_LAT 0x00000100L 1228 #define MCLK_MISC__DLL_READY_LAT 0x00000100L
1225 #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L 1229 #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L
1226 #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L 1230 #define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L
1227 #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L 1231 #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L
1228 #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L 1232 #define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L
1229 #define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L 1233 #define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L
1230 #define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L 1234 #define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L
1231 #define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L 1235 #define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L
1232 #define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L 1236 #define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L
1233 #define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L 1237 #define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L
1234 #define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L 1238 #define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L
1235 #define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L 1239 #define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L
1236 #define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L 1240 #define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L
1237 #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L 1241 #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L
1238 #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L 1242 #define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L
1239 #define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L 1243 #define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L
1240 #define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L 1244 #define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L
1241 #define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L 1245 #define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L
1242 #define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L 1246 #define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L
1243 #define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L 1247 #define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L
1244 1248
1245 /* VCLK_ECP_CNTL */ 1249 /* VCLK_ECP_CNTL */
1246 #define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L 1250 #define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L
1247 #define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L 1251 #define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L
1248 #define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L 1252 #define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L
1249 #define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L 1253 #define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L
1250 #define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L 1254 #define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L
1251 #define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L 1255 #define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L
1252 #define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L 1256 #define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L
1253 #define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L 1257 #define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L
1254 #define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) 1258 #define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
1255 1259
1256 /* PLL_PWRMGT_CNTL */ 1260 /* PLL_PWRMGT_CNTL */
1257 #define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L 1261 #define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L
1258 #define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L 1262 #define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L
1259 #define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L 1263 #define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L
1260 #define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L 1264 #define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L
1261 #define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L 1265 #define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L
1262 #define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L 1266 #define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L
1263 #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L 1267 #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L
1264 #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L 1268 #define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L
1265 #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L 1269 #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L
1266 #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L 1270 #define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L
1267 #define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L 1271 #define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L
1268 #define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L 1272 #define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L
1269 #define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L 1273 #define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L
1270 #define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L 1274 #define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L
1271 #define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L 1275 #define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L
1272 #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L 1276 #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L
1273 #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L 1277 #define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L
1274 #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L 1278 #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L
1275 #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L 1279 #define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L
1276 #define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L 1280 #define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L
1277 #define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L 1281 #define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L
1278 #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L 1282 #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L
1279 #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L 1283 #define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L
1280 #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L 1284 #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L
1281 #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L 1285 #define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L
1282 #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L 1286 #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L
1283 #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L 1287 #define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L
1284 #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L 1288 #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L
1285 #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L 1289 #define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L
1286 #define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L 1290 #define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L
1287 #define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L 1291 #define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L
1288 #define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L 1292 #define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L
1289 1293
1290 /* CLK_PWRMGT_CNTL */ 1294 /* CLK_PWRMGT_CNTL */
1291 #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L 1295 #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L
1292 #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L 1296 #define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L
1293 #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L 1297 #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L
1294 #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L 1298 #define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L
1295 #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L 1299 #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L
1296 #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L 1300 #define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L
1297 #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L 1301 #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L
1298 #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L 1302 #define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L
1299 #define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L 1303 #define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L
1300 #define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L 1304 #define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L
1301 #define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L 1305 #define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L
1302 #define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L 1306 #define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L
1303 #define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L 1307 #define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L
1304 #define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L 1308 #define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L
1305 #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L 1309 #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L
1306 #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L 1310 #define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L
1307 #define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L 1311 #define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L
1308 #define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L 1312 #define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L
1309 #define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L 1313 #define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L
1310 #define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L 1314 #define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L
1311 #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L 1315 #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L
1312 #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L 1316 #define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L
1313 #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L 1317 #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L
1314 #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L 1318 #define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L
1315 #define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L 1319 #define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L
1316 #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L 1320 #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L
1317 #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L 1321 #define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L
1318 #define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L 1322 #define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L
1319 #define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L 1323 #define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L
1320 #define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L 1324 #define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L
1321 #define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L 1325 #define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L
1322 #define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L 1326 #define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L
1323 #define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L 1327 #define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L
1324 #define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L 1328 #define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L
1325 #define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L 1329 #define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L
1326 #define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L 1330 #define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L
1327 #define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L 1331 #define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L
1328 #define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L 1332 #define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L
1329 #define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L 1333 #define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L
1330 #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L 1334 #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L
1331 #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L 1335 #define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L
1332 #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L 1336 #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L
1333 #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L 1337 #define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L
1334 1338
1335 /* BUS_CNTL1 */ 1339 /* BUS_CNTL1 */
1336 #define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L 1340 #define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L
1337 #define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L 1341 #define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L
1338 #define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L 1342 #define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L
1339 #define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L 1343 #define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L
1340 #define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L 1344 #define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L
1341 #define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L 1345 #define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L
1342 #define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L 1346 #define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L
1343 #define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L 1347 #define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L
1344 #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L 1348 #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L
1345 #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L 1349 #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L
1346 #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L 1350 #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L
1347 #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L 1351 #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L
1348 #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L 1352 #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L
1349 #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L 1353 #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L
1350 #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L 1354 #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L
1351 #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L 1355 #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L
1352 #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L 1356 #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L
1353 #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L 1357 #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L
1354 #define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L 1358 #define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L
1355 #define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L 1359 #define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L
1356 #define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L 1360 #define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L
1357 #define BUS_CNTL1__AGPCLK_VALID 0x80000000L 1361 #define BUS_CNTL1__AGPCLK_VALID 0x80000000L
1358 1362
1359 /* BUS_CNTL1 */ 1363 /* BUS_CNTL1 */
1360 #define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 1364 #define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000
1361 #define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 1365 #define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001
1362 #define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 1366 #define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002
1363 #define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 1367 #define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003
1364 #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 1368 #define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005
1365 #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 1369 #define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008
1366 #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 1370 #define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009
1367 #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a 1371 #define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a
1368 #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b 1372 #define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b
1369 #define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a 1373 #define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a
1370 #define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c 1374 #define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c
1371 #define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f 1375 #define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f
1372 1376
1373 /* CRTC_OFFSET_CNTL */ 1377 /* CRTC_OFFSET_CNTL */
1374 #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL 1378 #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL
1375 #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L 1379 #define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L
1376 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L 1380 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L
1377 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L 1381 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L
1378 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L 1382 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L
1379 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L 1383 #define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L
1380 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L 1384 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L
1381 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L 1385 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L
1382 #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L 1386 #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L
1383 #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L 1387 #define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L
1384 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L 1388 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L
1385 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L 1389 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L
1386 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L 1390 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L
1387 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L 1391 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L
1388 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L 1392 #define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L
1389 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L 1393 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L
1390 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L 1394 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L
1391 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L 1395 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L
1392 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L 1396 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L
1393 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L 1397 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L
1394 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L 1398 #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L
1395 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L 1399 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L
1396 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L 1400 #define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L
1397 1401
1398 /* CRTC_GEN_CNTL */ 1402 /* CRTC_GEN_CNTL */
1399 #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L 1403 #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L
1400 #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L 1404 #define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L
1401 #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L 1405 #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L
1402 #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L 1406 #define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L
1403 #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L 1407 #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L
1404 #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L 1408 #define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L
1405 #define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L 1409 #define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L
1406 #define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L 1410 #define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L
1407 #define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L 1411 #define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L
1408 #define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L 1412 #define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L
1409 #define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L 1413 #define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L
1410 #define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L 1414 #define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L
1411 #define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L 1415 #define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L
1412 #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L 1416 #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L
1413 #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L 1417 #define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L
1414 #define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L 1418 #define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L
1415 #define CRTC_GEN_CNTL__CRTC_EN 0x02000000L 1419 #define CRTC_GEN_CNTL__CRTC_EN 0x02000000L
1416 #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L 1420 #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L
1417 #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L 1421 #define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L
1418 1422
1419 /* CRTC2_GEN_CNTL */ 1423 /* CRTC2_GEN_CNTL */
1420 #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L 1424 #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L
1421 #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L 1425 #define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L
1422 #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L 1426 #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L
1423 #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L 1427 #define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L
1424 #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L 1428 #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L
1425 #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L 1429 #define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L
1426 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L 1430 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L
1427 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L 1431 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L
1428 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L 1432 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L
1429 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L 1433 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L
1430 #define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L 1434 #define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L
1431 #define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L 1435 #define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L
1432 #define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L 1436 #define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L
1433 #define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L 1437 #define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L
1434 #define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L 1438 #define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L
1435 #define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L 1439 #define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L
1436 #define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L 1440 #define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L
1437 #define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L 1441 #define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L
1438 #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L 1442 #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L
1439 #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L 1443 #define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L
1440 #define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L 1444 #define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L
1441 #define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L 1445 #define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L
1442 #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L 1446 #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L
1443 #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L 1447 #define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L
1444 #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L 1448 #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L
1445 #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L 1449 #define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L
1446 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L 1450 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L
1447 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L 1451 #define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L
1448 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L 1452 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L
1449 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L 1453 #define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L
1450 1454
1451 /* AGP_CNTL */ 1455 /* AGP_CNTL */
1452 #define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL 1456 #define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL
1453 #define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L 1457 #define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L
1454 #define AGP_CNTL__HOLD_RD_FIFO 0x00000100L 1458 #define AGP_CNTL__HOLD_RD_FIFO 0x00000100L
1455 #define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L 1459 #define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L
1456 #define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L 1460 #define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L
1457 #define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L 1461 #define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L
1458 #define AGP_CNTL__EN_2X_STBB 0x00000400L 1462 #define AGP_CNTL__EN_2X_STBB 0x00000400L
1459 #define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L 1463 #define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L
1460 #define AGP_CNTL__FORCE_FULL_SBA 0x00000800L 1464 #define AGP_CNTL__FORCE_FULL_SBA 0x00000800L
1461 #define AGP_CNTL__SBA_DIS_MASK 0x00001000L 1465 #define AGP_CNTL__SBA_DIS_MASK 0x00001000L
1462 #define AGP_CNTL__SBA_DIS 0x00001000L 1466 #define AGP_CNTL__SBA_DIS 0x00001000L
1463 #define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L 1467 #define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L
1464 #define AGP_CNTL__AGP_REV_ID 0x00002000L 1468 #define AGP_CNTL__AGP_REV_ID 0x00002000L
1465 #define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L 1469 #define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L
1466 #define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L 1470 #define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L
1467 #define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L 1471 #define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L
1468 #define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L 1472 #define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L
1469 #define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L 1473 #define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L
1470 #define AGP_CNTL__FORCE_INT_VREF 0x00010000L 1474 #define AGP_CNTL__FORCE_INT_VREF 0x00010000L
1471 #define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L 1475 #define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L
1472 #define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L 1476 #define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L
1473 #define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L 1477 #define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L
1474 #define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L 1478 #define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L
1475 #define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L 1479 #define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L
1476 #define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L 1480 #define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L
1477 #define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L 1481 #define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L
1478 #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L 1482 #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L
1479 #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L 1483 #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L
1480 #define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L 1484 #define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L
1481 #define AGP_CNTL__EN_RBFCALM 0x00800000L 1485 #define AGP_CNTL__EN_RBFCALM 0x00800000L
1482 #define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L 1486 #define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L
1483 #define AGP_CNTL__FORCE_EXT_VREF 0x01000000L 1487 #define AGP_CNTL__FORCE_EXT_VREF 0x01000000L
1484 #define AGP_CNTL__DIS_RBF_MASK 0x02000000L 1488 #define AGP_CNTL__DIS_RBF_MASK 0x02000000L
1485 #define AGP_CNTL__DIS_RBF 0x02000000L 1489 #define AGP_CNTL__DIS_RBF 0x02000000L
1486 #define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L 1490 #define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L
1487 #define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L 1491 #define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L
1488 #define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L 1492 #define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L
1489 #define AGP_CNTL__AGP_MISC_MASK 0xc0000000L 1493 #define AGP_CNTL__AGP_MISC_MASK 0xc0000000L
1490 1494
1491 /* AGP_CNTL */ 1495 /* AGP_CNTL */
1492 #define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 1496 #define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000
1493 #define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 1497 #define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008
1494 #define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 1498 #define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009
1495 #define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a 1499 #define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a
1496 #define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b 1500 #define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b
1497 #define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c 1501 #define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c
1498 #define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d 1502 #define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d
1499 #define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e 1503 #define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e
1500 #define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f 1504 #define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f
1501 #define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 1505 #define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010
1502 #define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 1506 #define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011
1503 #define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 1507 #define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013
1504 #define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 1508 #define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014
1505 #define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 1509 #define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015
1506 #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 1510 #define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016
1507 #define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 1511 #define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017
1508 #define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 1512 #define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018
1509 #define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 1513 #define AGP_CNTL__DIS_RBF__SHIFT 0x00000019
1510 #define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a 1514 #define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a
1511 #define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b 1515 #define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b
1512 #define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e 1516 #define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e
1513 1517
1514 /* DISP_MISC_CNTL */ 1518 /* DISP_MISC_CNTL */
1515 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L 1519 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L
1516 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L 1520 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L
1517 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L 1521 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L
1518 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L 1522 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L
1519 #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L 1523 #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L
1520 #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L 1524 #define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L
1521 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L 1525 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L
1522 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L 1526 #define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L
1523 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L 1527 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L
1524 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L 1528 #define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L
1525 #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L 1529 #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L
1526 #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L 1530 #define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L
1527 #define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L 1531 #define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L
1528 #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L 1532 #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L
1529 #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L 1533 #define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L
1530 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L 1534 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L
1531 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L 1535 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L
1532 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L 1536 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L
1533 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L 1537 #define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L
1534 #define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L 1538 #define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L
1535 #define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L 1539 #define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L
1536 #define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L 1540 #define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L
1537 #define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L 1541 #define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L
1538 #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L 1542 #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L
1539 #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L 1543 #define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L
1540 #define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L 1544 #define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L
1541 #define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L 1545 #define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L
1542 #define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L 1546 #define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L
1543 #define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L 1547 #define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L
1544 #define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L 1548 #define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L
1545 1549
1546 /* DISP_PWR_MAN */ 1550 /* DISP_PWR_MAN */
1547 #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L 1551 #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L
1548 #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L 1552 #define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L
1549 #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L 1553 #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L
1550 #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L 1554 #define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L
1551 #define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L 1555 #define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L
1552 #define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L 1556 #define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L
1553 #define DISP_PWR_MAN__DISP_D3_RST 0x00010000L 1557 #define DISP_PWR_MAN__DISP_D3_RST 0x00010000L
1554 #define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L 1558 #define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L
1555 #define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L 1559 #define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L
1556 #define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L 1560 #define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L
1557 #define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L 1561 #define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L
1558 #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L 1562 #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L
1559 #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L 1563 #define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L
1560 #define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L 1564 #define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L
1561 #define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L 1565 #define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L
1562 #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L 1566 #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L
1563 #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L 1567 #define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L
1564 #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L 1568 #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L
1565 #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L 1569 #define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L
1566 #define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L 1570 #define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L
1567 #define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L 1571 #define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L
1568 #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L 1572 #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L
1569 #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L 1573 #define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L
1570 #define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L 1574 #define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L
1571 #define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L 1575 #define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L
1572 #define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L 1576 #define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L
1573 #define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L 1577 #define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L
1574 1578
1575 /* MC_IND_INDEX */ 1579 /* MC_IND_INDEX */
1576 #define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL 1580 #define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL
1577 #define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L 1581 #define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L
1578 #define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L 1582 #define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L
1579 1583
1580 /* MC_IND_DATA */ 1584 /* MC_IND_DATA */
1581 #define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL 1585 #define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL
1582 1586
1583 /* MC_CHP_IO_CNTL_A1 */ 1587 /* MC_CHP_IO_CNTL_A1 */
1584 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 1588 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000
1585 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 1589 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001
1586 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 1590 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002
1587 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 1591 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003
1588 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 1592 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004
1589 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 1593 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005
1590 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 1594 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006
1591 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 1595 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007
1592 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 1596 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008
1593 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 1597 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009
1594 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a 1598 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a
1595 #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c 1599 #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c
1596 #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e 1600 #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e
1597 #define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 1601 #define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010
1598 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 1602 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012
1599 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 1603 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014
1600 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 1604 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016
1601 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 1605 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017
1602 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 1606 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018
1603 #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a 1607 #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a
1604 #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c 1608 #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c
1605 #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e 1609 #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e
1606 #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f 1610 #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f
1607 1611
1608 /* MC_CHP_IO_CNTL_B1 */ 1612 /* MC_CHP_IO_CNTL_B1 */
1609 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 1613 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000
1610 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 1614 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001
1611 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 1615 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002
1612 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 1616 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003
1613 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 1617 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004
1614 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 1618 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005
1615 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 1619 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006
1616 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 1620 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007
1617 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 1621 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008
1618 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 1622 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009
1619 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a 1623 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a
1620 #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c 1624 #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c
1621 #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e 1625 #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e
1622 #define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 1626 #define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010
1623 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 1627 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012
1624 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 1628 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014
1625 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 1629 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016
1626 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 1630 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017
1627 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 1631 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018
1628 #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a 1632 #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a
1629 #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c 1633 #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c
1630 #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e 1634 #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e
1631 #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f 1635 #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f
1632 1636
1633 /* MC_CHP_IO_CNTL_A1 */ 1637 /* MC_CHP_IO_CNTL_A1 */
1634 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L 1638 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L
1635 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L 1639 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L
1636 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L 1640 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L
1637 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L 1641 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L
1638 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L 1642 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L
1639 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L 1643 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L
1640 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L 1644 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L
1641 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L 1645 #define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L
1642 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L 1646 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L
1643 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L 1647 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L
1644 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L 1648 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L
1645 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L 1649 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L
1646 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L 1650 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L
1647 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L 1651 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L
1648 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L 1652 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L
1649 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L 1653 #define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L
1650 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L 1654 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L
1651 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L 1655 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L
1652 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L 1656 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L
1653 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L 1657 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L
1654 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L 1658 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L
1655 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L 1659 #define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L
1656 #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L 1660 #define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L
1657 #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L 1661 #define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L
1658 #define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L 1662 #define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L
1659 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L 1663 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L
1660 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L 1664 #define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L
1661 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L 1665 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L
1662 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L 1666 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L
1663 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L 1667 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L
1664 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L 1668 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L
1665 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L 1669 #define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L
1666 #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L 1670 #define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L
1667 #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L 1671 #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L
1668 #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L 1672 #define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L
1669 #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L 1673 #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L
1670 #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L 1674 #define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L
1671 #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L 1675 #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L
1672 #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L 1676 #define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L
1673 1677
1674 /* MC_CHP_IO_CNTL_B1 */ 1678 /* MC_CHP_IO_CNTL_B1 */
1675 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L 1679 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L
1676 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L 1680 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L
1677 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L 1681 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L
1678 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L 1682 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L
1679 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L 1683 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L
1680 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L 1684 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L
1681 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L 1685 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L
1682 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L 1686 #define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L
1683 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L 1687 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L
1684 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L 1688 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L
1685 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L 1689 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L
1686 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L 1690 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L
1687 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L 1691 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L
1688 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L 1692 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L
1689 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L 1693 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L
1690 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L 1694 #define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L
1691 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L 1695 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L
1692 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L 1696 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L
1693 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L 1697 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L
1694 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L 1698 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L
1695 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L 1699 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L
1696 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L 1700 #define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L
1697 #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L 1701 #define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L
1698 #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L 1702 #define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L
1699 #define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L 1703 #define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L
1700 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L 1704 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L
1701 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L 1705 #define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L
1702 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L 1706 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L
1703 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L 1707 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L
1704 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L 1708 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L
1705 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L 1709 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L
1706 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L 1710 #define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L
1707 #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L 1711 #define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L
1708 #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L 1712 #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L
1709 #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L 1713 #define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L
1710 #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L 1714 #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L
1711 #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L 1715 #define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L
1712 #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L 1716 #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L
1713 #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L 1717 #define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L
1714 1718
1715 /* MEM_SDRAM_MODE_REG */ 1719 /* MEM_SDRAM_MODE_REG */
1716 #define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL 1720 #define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL
1717 #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L 1721 #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L
1718 #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L 1722 #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L
1719 #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L 1723 #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L
1720 #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L 1724 #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L
1721 #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L 1725 #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L
1722 #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L 1726 #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L
1723 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L 1727 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L
1724 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L 1728 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L
1725 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L 1729 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L
1726 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L 1730 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L
1727 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L 1731 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L
1728 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L 1732 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L
1729 #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L 1733 #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L
1730 #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L 1734 #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L
1731 #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L 1735 #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L
1732 #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L 1736 #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L
1733 #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L 1737 #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L
1734 #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L 1738 #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L
1735 #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L 1739 #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L
1736 #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L 1740 #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L
1737 1741
1738 /* MEM_SDRAM_MODE_REG */ 1742 /* MEM_SDRAM_MODE_REG */
1739 #define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 1743 #define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000
1740 #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 1744 #define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010
1741 #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 1745 #define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014
1742 #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 1746 #define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017
1743 #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 1747 #define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018
1744 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 1748 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019
1745 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a 1749 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a
1746 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b 1750 #define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b
1747 #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c 1751 #define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c
1748 #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d 1752 #define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d
1749 #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e 1753 #define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e
1750 #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f 1754 #define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f
1751 1755
1752 /* MEM_REFRESH_CNTL */ 1756 /* MEM_REFRESH_CNTL */
1753 #define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL 1757 #define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL
1754 #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L 1758 #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L
1755 #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L 1759 #define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L
1756 #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L 1760 #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L
1757 #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L 1761 #define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L
1758 #define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L 1762 #define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L
1759 #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L 1763 #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L
1760 #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L 1764 #define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L
1761 #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L 1765 #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L
1762 #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L 1766 #define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L
1763 #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L 1767 #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L
1764 #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L 1768 #define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L
1765 #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L 1769 #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L
1766 #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L 1770 #define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L
1767 #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L 1771 #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L
1768 #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L 1772 #define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L
1769 #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L 1773 #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L
1770 #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L 1774 #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L
1771 #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L 1775 #define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L
1772 #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L 1776 #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L
1773 #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L 1777 #define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L
1774 #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L 1778 #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L
1775 #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L 1779 #define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L
1776 #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L 1780 #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L
1777 #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L 1781 #define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L
1778 #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L 1782 #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L
1779 #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L 1783 #define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L
1780 #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L 1784 #define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L
1781 1785
1782 /* MC_STATUS */ 1786 /* MC_STATUS */
1783 #define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L 1787 #define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L
1784 #define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L 1788 #define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L
1785 #define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L 1789 #define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L
1786 #define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L 1790 #define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L
1787 #define MC_STATUS__MC_IDLE_MASK 0x00000004L 1791 #define MC_STATUS__MC_IDLE_MASK 0x00000004L
1788 #define MC_STATUS__MC_IDLE 0x00000004L 1792 #define MC_STATUS__MC_IDLE 0x00000004L
1789 #define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L 1793 #define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L
1790 #define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L 1794 #define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L
1791 #define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L 1795 #define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L
1792 #define MC_STATUS__TEST_OUT_R_BACK 0x00000800L 1796 #define MC_STATUS__TEST_OUT_R_BACK 0x00000800L
1793 #define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L 1797 #define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L
1794 #define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L 1798 #define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L
1795 #define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L 1799 #define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L
1796 #define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L 1800 #define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L
1797 #define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L 1801 #define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L
1798 #define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L 1802 #define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L
1799 1803
1800 /* MDLL_CKO */ 1804 /* MDLL_CKO */
1801 #define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L 1805 #define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L
1802 #define MDLL_CKO__MCKOA_SLEEP 0x00000001L 1806 #define MDLL_CKO__MCKOA_SLEEP 0x00000001L
1803 #define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L 1807 #define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L
1804 #define MDLL_CKO__MCKOA_RESET 0x00000002L 1808 #define MDLL_CKO__MCKOA_RESET 0x00000002L
1805 #define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL 1809 #define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL
1806 #define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L 1810 #define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L
1807 #define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L 1811 #define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L
1808 #define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L 1812 #define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L
1809 #define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L 1813 #define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L
1810 #define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L 1814 #define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L
1811 #define MDLL_CKO__MCKOA_BP_SEL 0x00008000L 1815 #define MDLL_CKO__MCKOA_BP_SEL 0x00008000L
1812 #define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L 1816 #define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L
1813 #define MDLL_CKO__MCKOB_SLEEP 0x00010000L 1817 #define MDLL_CKO__MCKOB_SLEEP 0x00010000L
1814 #define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L 1818 #define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L
1815 #define MDLL_CKO__MCKOB_RESET 0x00020000L 1819 #define MDLL_CKO__MCKOB_RESET 0x00020000L
1816 #define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L 1820 #define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L
1817 #define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L 1821 #define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L
1818 #define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L 1822 #define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L
1819 #define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L 1823 #define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L
1820 #define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L 1824 #define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L
1821 #define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L 1825 #define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L
1822 #define MDLL_CKO__MCKOB_BP_SEL 0x80000000L 1826 #define MDLL_CKO__MCKOB_BP_SEL 0x80000000L
1823 1827
1824 /* MDLL_RDCKA */ 1828 /* MDLL_RDCKA */
1825 #define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L 1829 #define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L
1826 #define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L 1830 #define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L
1827 #define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L 1831 #define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L
1828 #define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L 1832 #define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L
1829 #define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL 1833 #define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL
1830 #define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L 1834 #define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L
1831 #define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L 1835 #define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L
1832 #define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L 1836 #define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L
1833 #define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L 1837 #define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L
1834 #define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L 1838 #define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L
1835 #define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L 1839 #define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L
1836 #define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L 1840 #define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L
1837 #define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L 1841 #define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L
1838 #define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L 1842 #define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L
1839 #define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L 1843 #define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L
1840 #define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L 1844 #define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L
1841 #define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L 1845 #define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L
1842 #define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L 1846 #define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L
1843 #define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L 1847 #define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L
1844 #define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L 1848 #define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L
1845 #define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L 1849 #define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L
1846 #define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L 1850 #define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L
1847 #define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L 1851 #define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L
1848 #define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L 1852 #define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L
1849 #define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L 1853 #define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L
1850 #define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L 1854 #define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L
1851 1855
1852 /* MDLL_RDCKB */ 1856 /* MDLL_RDCKB */
1853 #define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L 1857 #define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L
1854 #define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L 1858 #define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L
1855 #define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L 1859 #define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L
1856 #define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L 1860 #define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L
1857 #define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL 1861 #define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL
1858 #define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L 1862 #define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L
1859 #define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L 1863 #define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L
1860 #define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L 1864 #define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L
1861 #define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L 1865 #define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L
1862 #define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L 1866 #define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L
1863 #define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L 1867 #define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L
1864 #define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L 1868 #define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L
1865 #define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L 1869 #define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L
1866 #define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L 1870 #define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L
1867 #define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L 1871 #define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L
1868 #define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L 1872 #define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L
1869 #define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L 1873 #define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L
1870 #define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L 1874 #define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L
1871 #define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L 1875 #define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L
1872 #define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L 1876 #define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L
1873 #define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L 1877 #define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L
1874 #define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L 1878 #define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L
1875 #define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L 1879 #define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L
1876 #define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L 1880 #define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L
1877 #define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L 1881 #define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L
1878 #define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L 1882 #define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L
1879 1883
1880 #define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L 1884 #define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L
1881 #define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L 1885 #define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L
1882 #define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L 1886 #define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L
1883 #define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L 1887 #define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L
1884 #define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L 1888 #define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L
1885 #define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L 1889 #define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L
1886 #define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L 1890 #define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L
1887 #define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L 1891 #define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L
1888 1892
1889 #define pllCLK_PIN_CNTL 0x0001 1893 #define pllCLK_PIN_CNTL 0x0001
1890 #define pllPPLL_CNTL 0x0002 1894 #define pllPPLL_CNTL 0x0002
1891 #define pllPPLL_REF_DIV 0x0003 1895 #define pllPPLL_REF_DIV 0x0003
1892 #define pllPPLL_DIV_0 0x0004 1896 #define pllPPLL_DIV_0 0x0004
1893 #define pllPPLL_DIV_1 0x0005 1897 #define pllPPLL_DIV_1 0x0005
1894 #define pllPPLL_DIV_2 0x0006 1898 #define pllPPLL_DIV_2 0x0006
1895 #define pllPPLL_DIV_3 0x0007 1899 #define pllPPLL_DIV_3 0x0007
1896 #define pllVCLK_ECP_CNTL 0x0008 1900 #define pllVCLK_ECP_CNTL 0x0008
1897 #define pllHTOTAL_CNTL 0x0009 1901 #define pllHTOTAL_CNTL 0x0009
1898 #define pllM_SPLL_REF_FB_DIV 0x000A 1902 #define pllM_SPLL_REF_FB_DIV 0x000A
1899 #define pllAGP_PLL_CNTL 0x000B 1903 #define pllAGP_PLL_CNTL 0x000B
1900 #define pllSPLL_CNTL 0x000C 1904 #define pllSPLL_CNTL 0x000C
1901 #define pllSCLK_CNTL 0x000D 1905 #define pllSCLK_CNTL 0x000D
1902 #define pllMPLL_CNTL 0x000E 1906 #define pllMPLL_CNTL 0x000E
1903 #define pllMDLL_CKO 0x000F 1907 #define pllMDLL_CKO 0x000F
1904 #define pllMDLL_RDCKA 0x0010 1908 #define pllMDLL_RDCKA 0x0010
1905 #define pllMDLL_RDCKB 0x0011 1909 #define pllMDLL_RDCKB 0x0011
1906 #define pllMCLK_CNTL 0x0012 1910 #define pllMCLK_CNTL 0x0012
1907 #define pllPLL_TEST_CNTL 0x0013 1911 #define pllPLL_TEST_CNTL 0x0013
1908 #define pllCLK_PWRMGT_CNTL 0x0014 1912 #define pllCLK_PWRMGT_CNTL 0x0014
1909 #define pllPLL_PWRMGT_CNTL 0x0015 1913 #define pllPLL_PWRMGT_CNTL 0x0015
1910 #define pllCG_TEST_MACRO_RW_WRITE 0x0016 1914 #define pllCG_TEST_MACRO_RW_WRITE 0x0016
1911 #define pllCG_TEST_MACRO_RW_READ 0x0017 1915 #define pllCG_TEST_MACRO_RW_READ 0x0017
1912 #define pllCG_TEST_MACRO_RW_DATA 0x0018 1916 #define pllCG_TEST_MACRO_RW_DATA 0x0018
1913 #define pllCG_TEST_MACRO_RW_CNTL 0x0019 1917 #define pllCG_TEST_MACRO_RW_CNTL 0x0019
1914 #define pllDISP_TEST_MACRO_RW_WRITE 0x001A 1918 #define pllDISP_TEST_MACRO_RW_WRITE 0x001A
1915 #define pllDISP_TEST_MACRO_RW_READ 0x001B 1919 #define pllDISP_TEST_MACRO_RW_READ 0x001B
1916 #define pllDISP_TEST_MACRO_RW_DATA 0x001C 1920 #define pllDISP_TEST_MACRO_RW_DATA 0x001C
1917 #define pllDISP_TEST_MACRO_RW_CNTL 0x001D 1921 #define pllDISP_TEST_MACRO_RW_CNTL 0x001D
1918 #define pllSCLK_CNTL2 0x001E 1922 #define pllSCLK_CNTL2 0x001E
1919 #define pllMCLK_MISC 0x001F 1923 #define pllMCLK_MISC 0x001F
1920 #define pllTV_PLL_FINE_CNTL 0x0020 1924 #define pllTV_PLL_FINE_CNTL 0x0020
1921 #define pllTV_PLL_CNTL 0x0021 1925 #define pllTV_PLL_CNTL 0x0021
1922 #define pllTV_PLL_CNTL1 0x0022 1926 #define pllTV_PLL_CNTL1 0x0022
1923 #define pllTV_DTO_INCREMENTS 0x0023 1927 #define pllTV_DTO_INCREMENTS 0x0023
1924 #define pllSPLL_AUX_CNTL 0x0024 1928 #define pllSPLL_AUX_CNTL 0x0024
1925 #define pllMPLL_AUX_CNTL 0x0025 1929 #define pllMPLL_AUX_CNTL 0x0025
1926 #define pllP2PLL_CNTL 0x002A 1930 #define pllP2PLL_CNTL 0x002A
1927 #define pllP2PLL_REF_DIV 0x002B 1931 #define pllP2PLL_REF_DIV 0x002B
1928 #define pllP2PLL_DIV_0 0x002C 1932 #define pllP2PLL_DIV_0 0x002C
1929 #define pllPIXCLKS_CNTL 0x002D 1933 #define pllPIXCLKS_CNTL 0x002D
1930 #define pllHTOTAL2_CNTL 0x002E 1934 #define pllHTOTAL2_CNTL 0x002E
1931 #define pllSSPLL_CNTL 0x0030 1935 #define pllSSPLL_CNTL 0x0030
1932 #define pllSSPLL_REF_DIV 0x0031 1936 #define pllSSPLL_REF_DIV 0x0031
1933 #define pllSSPLL_DIV_0 0x0032 1937 #define pllSSPLL_DIV_0 0x0032
1934 #define pllSS_INT_CNTL 0x0033 1938 #define pllSS_INT_CNTL 0x0033
1935 #define pllSS_TST_CNTL 0x0034 1939 #define pllSS_TST_CNTL 0x0034
1936 #define pllSCLK_MORE_CNTL 0x0035 1940 #define pllSCLK_MORE_CNTL 0x0035
1937 1941
1938 #define ixMC_PERF_CNTL 0x0000 1942 #define ixMC_PERF_CNTL 0x0000
1939 #define ixMC_PERF_SEL 0x0001 1943 #define ixMC_PERF_SEL 0x0001
1940 #define ixMC_PERF_REGION_0 0x0002 1944 #define ixMC_PERF_REGION_0 0x0002
1941 #define ixMC_PERF_REGION_1 0x0003 1945 #define ixMC_PERF_REGION_1 0x0003
1942 #define ixMC_PERF_COUNT_0 0x0004 1946 #define ixMC_PERF_COUNT_0 0x0004
1943 #define ixMC_PERF_COUNT_1 0x0005 1947 #define ixMC_PERF_COUNT_1 0x0005
1944 #define ixMC_PERF_COUNT_2 0x0006 1948 #define ixMC_PERF_COUNT_2 0x0006
1945 #define ixMC_PERF_COUNT_3 0x0007 1949 #define ixMC_PERF_COUNT_3 0x0007
1946 #define ixMC_PERF_COUNT_MEMCH_A 0x0008 1950 #define ixMC_PERF_COUNT_MEMCH_A 0x0008
1947 #define ixMC_PERF_COUNT_MEMCH_B 0x0009 1951 #define ixMC_PERF_COUNT_MEMCH_B 0x0009
1948 #define ixMC_IMP_CNTL 0x000A 1952 #define ixMC_IMP_CNTL 0x000A
1949 #define ixMC_CHP_IO_CNTL_A0 0x000B 1953 #define ixMC_CHP_IO_CNTL_A0 0x000B
1950 #define ixMC_CHP_IO_CNTL_A1 0x000C 1954 #define ixMC_CHP_IO_CNTL_A1 0x000C
1951 #define ixMC_CHP_IO_CNTL_B0 0x000D 1955 #define ixMC_CHP_IO_CNTL_B0 0x000D
1952 #define ixMC_CHP_IO_CNTL_B1 0x000E 1956 #define ixMC_CHP_IO_CNTL_B1 0x000E
1953 #define ixMC_IMP_CNTL_0 0x000F 1957 #define ixMC_IMP_CNTL_0 0x000F
1954 #define ixTC_MISMATCH_1 0x0010 1958 #define ixTC_MISMATCH_1 0x0010
1955 #define ixTC_MISMATCH_2 0x0011 1959 #define ixTC_MISMATCH_2 0x0011
1956 #define ixMC_BIST_CTRL 0x0012 1960 #define ixMC_BIST_CTRL 0x0012
1957 #define ixREG_COLLAR_WRITE 0x0013 1961 #define ixREG_COLLAR_WRITE 0x0013
1958 #define ixREG_COLLAR_READ 0x0014 1962 #define ixREG_COLLAR_READ 0x0014
1959 #define ixR300_MC_IMP_CNTL 0x0018 1963 #define ixR300_MC_IMP_CNTL 0x0018
1960 #define ixR300_MC_CHP_IO_CNTL_A0 0x0019 1964 #define ixR300_MC_CHP_IO_CNTL_A0 0x0019
1961 #define ixR300_MC_CHP_IO_CNTL_A1 0x001a 1965 #define ixR300_MC_CHP_IO_CNTL_A1 0x001a
1962 #define ixR300_MC_CHP_IO_CNTL_B0 0x001b 1966 #define ixR300_MC_CHP_IO_CNTL_B0 0x001b
1963 #define ixR300_MC_CHP_IO_CNTL_B1 0x001c 1967 #define ixR300_MC_CHP_IO_CNTL_B1 0x001c
1964 #define ixR300_MC_CHP_IO_CNTL_C0 0x001d 1968 #define ixR300_MC_CHP_IO_CNTL_C0 0x001d
1965 #define ixR300_MC_CHP_IO_CNTL_C1 0x001e 1969 #define ixR300_MC_CHP_IO_CNTL_C1 0x001e
1966 #define ixR300_MC_CHP_IO_CNTL_D0 0x001f 1970 #define ixR300_MC_CHP_IO_CNTL_D0 0x001f
1967 #define ixR300_MC_CHP_IO_CNTL_D1 0x0020 1971 #define ixR300_MC_CHP_IO_CNTL_D1 0x0020
1968 #define ixR300_MC_IMP_CNTL_0 0x0021 1972 #define ixR300_MC_IMP_CNTL_0 0x0021
1969 #define ixR300_MC_ELPIDA_CNTL 0x0022 1973 #define ixR300_MC_ELPIDA_CNTL 0x0022
1970 #define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023 1974 #define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023
1971 #define ixR300_MC_READ_CNTL_CD 0x0024 1975 #define ixR300_MC_READ_CNTL_CD 0x0024
1972 #define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025 1976 #define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025
1973 #define ixR300_MC_DEBUG_CNTL 0x0026 1977 #define ixR300_MC_DEBUG_CNTL 0x0026
1974 #define ixR300_MC_BIST_CNTL_0 0x0028 1978 #define ixR300_MC_BIST_CNTL_0 0x0028
1975 #define ixR300_MC_BIST_CNTL_1 0x0029 1979 #define ixR300_MC_BIST_CNTL_1 0x0029
1976 #define ixR300_MC_BIST_CNTL_2 0x002a 1980 #define ixR300_MC_BIST_CNTL_2 0x002a
1977 #define ixR300_MC_BIST_CNTL_3 0x002b 1981 #define ixR300_MC_BIST_CNTL_3 0x002b
1978 #define ixR300_MC_BIST_CNTL_4 0x002c 1982 #define ixR300_MC_BIST_CNTL_4 0x002c
1979 #define ixR300_MC_BIST_CNTL_5 0x002d 1983 #define ixR300_MC_BIST_CNTL_5 0x002d
1980 #define ixR300_MC_IMP_STATUS 0x002e 1984 #define ixR300_MC_IMP_STATUS 0x002e
1981 #define ixR300_MC_DLL_CNTL 0x002f 1985 #define ixR300_MC_DLL_CNTL 0x002f
1982 #define NB_TOM 0x15C 1986 #define NB_TOM 0x15C
1983 1987
1984 #endif /* _RADEON_H */ 1988 #endif /* _RADEON_H */
1985 1989