Extend ATI Radeon driver to support more video modes

Adds ATI Radeon 9200 support for 1280x1024, 1024x768, 800x600, 640x480 at 24, 16 and 8 bpp. Signed-off-by: Anatolij Gustschin <agust@denx.de>

Extend ATI Radeon driver to support more video modes
Adds ATI Radeon 9200 support for 1280x1024, 1024x768, 800x600, 640x480 at 24, 16 and 8 bpp. Signed-off-by: Anatolij Gustschin <agust@denx.de>
Anatolij Gustschin · Wolfgang Denk
1 parent 4124382de0
Showing 2 changed files with 308 additions and 15 deletions Side-by-side Diff
drivers/video/ati_radeon_fb.c
include/radeon.h
@@ -44,6 +44,7 @@
 #include <asm/io.h>
 #include <malloc.h>
 #include <video_fb.h>
+#include "videomodes.h"
  
 #include <radeon.h>
 #include "ati_ids.h"
@@ -65,6 +66,21 @@
 #define MAX_MAPPED_VRAM	(2048*2048*4)
 #define MIN_MAPPED_VRAM	(1024*768*1)
  
+#define RADEON_BUFFER_ALIGN		0x00000fff
+#define SURF_UPPER_BOUND(x,y,bpp)	(((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \
+					  & ~RADEON_BUFFER_ALIGN) - 1)
+#define RADEON_CRT_PITCH(width, bpp)	((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \
+					 ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16))
+
+#define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \
+		(((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16))
+#define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \
+		(((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16))
+#define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \
+		((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16))
+#define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \
+		((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16))
+
 /*#define PCI_VENDOR_ID_ATI*/
 #define PCI_CHIP_RV280_5960		0x5960
 #define PCI_CHIP_RV280_5961		0x5961
@@ -350,6 +366,204 @@
 	radeon_write_pll_regs(rinfo, mode);
 }
  
+static void set_pal(void)
+{
+	int idx, val = 0;
+
+	for (idx = 0; idx < 256; idx++) {
+		OUTREG8(PALETTE_INDEX, idx);
+		OUTREG(PALETTE_DATA, val);
+		val += 0x00010101;
+	}
+}
+
+void radeon_setmode_9200(int vesa_idx, int bpp)
+{
+	struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
+
+	mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN;
+	mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON;
+	mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN;
+	mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN;
+
+	switch (bpp) {
+	case 24:
+		mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */
+#if defined(__BIG_ENDIAN)
+		mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
+		mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP;
+#endif
+		break;
+	case 16:
+		mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */
+#if defined(__BIG_ENDIAN)
+		mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
+		mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP;
+#endif
+		break;
+	default:
+		mode->crtc_gen_cntl |= 0x2 << 8; /* palette */
+		mode->surface_cntl = 0x00000000;
+		break;
+	}
+
+	switch (vesa_idx) {
+	case RES_MODE_1280x1024:
+		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280);
+		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024);
+		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3);
+#if defined(CONFIG_RADEON_VREFRESH_75HZ)
+		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18);
+		mode->ppll_div_3 = 0x00010078;
+#else /* default @ 60 Hz */
+		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14);
+		mode->ppll_div_3 = 0x00010060;
+#endif
+		/*
+		 * for this mode pitch expands to the same value for 32, 16 and 8 bpp,
+		 * so we set it here once only.
+		 */
+		mode->crtc_pitch = RADEON_CRT_PITCH(1280,32);
+		switch (bpp) {
+		case 24:
+			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16);
+			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32);
+			break;
+		case 16:
+			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16);
+			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16);
+			break;
+		default: /* 8 bpp */
+			mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16);
+			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8);
+			break;
+		}
+		break;
+	case RES_MODE_1024x768:
+#if defined(CONFIG_RADEON_VREFRESH_75HZ)
+		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024);
+		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12);
+		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768);
+		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3);
+		mode->ppll_div_3 = 0x0002008c;
+#else /* @ 60 Hz */
+		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024);
+		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL;
+		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768);
+		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL;
+		mode->ppll_div_3 = 0x00020074;
+#endif
+		/* also same pitch value for 32, 16 and 8 bpp */
+		mode->crtc_pitch = RADEON_CRT_PITCH(1024,32);
+		switch (bpp) {
+		case 24:
+			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16);
+			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32);
+			break;
+		case 16:
+			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16);
+			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16);
+			break;
+		default: /* 8 bpp */
+			mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
+			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8);
+			break;
+		}
+		break;
+	case RES_MODE_800x600:
+		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800);
+#if defined(CONFIG_RADEON_VREFRESH_75HZ)
+		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10);
+		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600);
+		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3);
+		mode->ppll_div_3 = 0x000300b0;
+#else /* @ 60 Hz */
+		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16);
+		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600);
+		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4);
+		mode->ppll_div_3 = 0x0003008e;
+#endif
+		switch (bpp) {
+		case 24:
+			mode->crtc_pitch = RADEON_CRT_PITCH(832,32);
+			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16);
+			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32);
+			break;
+		case 16:
+			mode->crtc_pitch = RADEON_CRT_PITCH(896,16);
+			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16);
+			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16);
+			break;
+		default: /* 8 bpp */
+			mode->crtc_pitch = RADEON_CRT_PITCH(1024,8);
+			mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16);
+			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8);
+			break;
+		}
+		break;
+	default: /* RES_MODE_640x480 */
+#if defined(CONFIG_RADEON_VREFRESH_75HZ)
+		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640);
+		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL;
+		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480);
+		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL;
+		mode->ppll_div_3 = 0x00030070;
+#else /* @ 60 Hz */
+		mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640);
+		mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL;
+		mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480);
+		mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL;
+		mode->ppll_div_3 = 0x00030059;
+#endif
+		/* also same pitch value for 32, 16 and 8 bpp */
+		mode->crtc_pitch = RADEON_CRT_PITCH(640,32);
+		switch (bpp) {
+		case 24:
+			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16);
+			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32);
+			break;
+		case 16:
+			mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16);
+			mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16);
+			break;
+		default: /* 8 bpp */
+			mode->crtc_offset_cntl = 0x00000000;
+			break;
+		}
+		break;
+	}
+
+	OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
+	OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
+		(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
+	OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
+	OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
+	OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
+	OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
+	OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
+	OUTREG(CRTC_OFFSET, 0);
+	OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl);
+	OUTREG(CRTC_PITCH, mode->crtc_pitch);
+	OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
+
+	mode->clk_cntl_index = 0x300;
+	mode->ppll_ref_div = 0xc;
+
+	radeon_write_pll_regs(rinfo, mode);
+
+	OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
+		~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
+	OUTREG(SURFACE0_INFO, mode->surf_info[0]);
+	OUTREG(SURFACE0_LOWER_BOUND, 0);
+	OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]);
+	OUTREG(SURFACE_CNTL, mode->surface_cntl);
+
+	if (bpp > 8)
+		set_pal();
+
+	free(mode);
+}
+
 #include "../bios_emulator/include/biosemu.h"
 extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp);
  
  
  
  
  
  
  
  
@@ -421,30 +635,102 @@
 void *video_hw_init(void)
 {
 	GraphicDevice *pGD = (GraphicDevice *) & ctfb;
-	int i;
 	u32 *vm;
+	char *penv;
+	unsigned long t1, hsynch, vsynch;
+	int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
+	struct ctfb_res_modes *res_mode;
+	struct ctfb_res_modes var_mode;
  
 	rinfo = malloc(sizeof(struct radeonfb_info));
  
+	printf("Video: ");
 	if(radeon_probe(rinfo)) {
 		printf("No radeon video card found!\n");
 		return NULL;
 	}
  
+	tmp = 0;
+
+	videomode = CFG_DEFAULT_VIDEO_MODE;
+	/* get video mode via environment */
+	if ((penv = getenv ("videomode")) != NULL) {
+		/* deceide if it is a string */
+		if (penv[0] <= '9') {
+			videomode = (int) simple_strtoul (penv, NULL, 16);
+			tmp = 1;
+		}
+	} else {
+		tmp = 1;
+	}
+	if (tmp) {
+		/* parameter are vesa modes */
+		/* search params */
+		for (i = 0; i < VESA_MODES_COUNT; i++) {
+			if (vesa_modes[i].vesanr == videomode)
+				break;
+		}
+		if (i == VESA_MODES_COUNT) {
+			printf ("no VESA Mode found, switching to mode 0x%x ", CFG_DEFAULT_VIDEO_MODE);
+			i = 0;
+		}
+		res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex];
+		bits_per_pixel = vesa_modes[i].bits_per_pixel;
+		vesa_idx = vesa_modes[i].resindex;
+	} else {
+		res_mode = (struct ctfb_res_modes *) &var_mode;
+		bits_per_pixel = video_get_params (res_mode, penv);
+	}
+
+	/* calculate hsynch and vsynch freq (info only) */
+	t1 = (res_mode->left_margin + res_mode->xres +
+	      res_mode->right_margin + res_mode->hsync_len) / 8;
+	t1 *= 8;
+	t1 *= res_mode->pixclock;
+	t1 /= 1000;
+	hsynch = 1000000000L / t1;
+	t1 *= (res_mode->upper_margin + res_mode->yres +
+	       res_mode->lower_margin + res_mode->vsync_len);
+	t1 /= 1000;
+	vsynch = 1000000000L / t1;
+
 	/* fill in Graphic device struct */
-	sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", 640,
-		 480, 16, (1000 / 1000),
-		 (2000 / 1000));
+	sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
+		 res_mode->yres, bits_per_pixel, (hsynch / 1000),
+		 (vsynch / 1000));
 	printf ("%s\n", pGD->modeIdent);
+	pGD->winSizeX = res_mode->xres;
+	pGD->winSizeY = res_mode->yres;
+	pGD->plnSizeX = res_mode->xres;
+	pGD->plnSizeY = res_mode->yres;
  
-	pGD->winSizeX = 640;
-	pGD->winSizeY = 480;
-	pGD->plnSizeX = 640;
-	pGD->plnSizeY = 480;
+	switch (bits_per_pixel) {
+	case 24:
+		pGD->gdfBytesPP = 4;
+		pGD->gdfIndex = GDF_32BIT_X888RGB;
+		if (res_mode->xres == 800) {
+			pGD->winSizeX = 832;
+			pGD->plnSizeX = 832;
+		}
+		break;
+	case 16:
+		pGD->gdfBytesPP = 2;
+		pGD->gdfIndex = GDF_16BIT_565RGB;
+		if (res_mode->xres == 800) {
+			pGD->winSizeX = 896;
+			pGD->plnSizeX = 896;
+		}
+		break;
+	default:
+		if (res_mode->xres == 800) {
+			pGD->winSizeX = 1024;
+			pGD->plnSizeX = 1024;
+		}
+		pGD->gdfBytesPP = 1;
+		pGD->gdfIndex = GDF__8BIT_INDEX;
+		break;
+	}
  
-	pGD->gdfBytesPP = 1;
-	pGD->gdfIndex = GDF__8BIT_INDEX;
-
 	pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS;
 	pGD->pciBase = rinfo->fb_base_phys;
 	pGD->frameAdrs = rinfo->fb_base_phys;
  
@@ -464,14 +750,17 @@
 	pGD->cprBase = rinfo->fb_base_phys;	/* Dummy */
 	/* set up Hardware */
  
-	/* Clear video memory */
-	i = pGD->memSize / 4;
+	/* Clear video memory (only visible screen area) */
+	i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4;
 	vm = (unsigned int *) pGD->pciBase;
 	while (i--)
 		*vm++ = 0;
 	/*SetDrawingEngine (bits_per_pixel);*/
  
-	radeon_setmode();
+	if (rinfo->family == CHIP_FAMILY_RV280)
+		radeon_setmode_9200(vesa_idx, bits_per_pixel);
+	else
+		radeon_setmode();
  
 	return ((void *) pGD);
 }
@@ -154,8 +154,10 @@
 #define PALETTE_30_DATA			0x00B8
 #define CRTC_H_TOTAL_DISP		0x0200
 #define CRTC_H_SYNC_STRT_WID		0x0204
+#define CRTC_H_SYNC_POL			(1 << 23)
 #define CRTC_V_TOTAL_DISP		0x0208
 #define CRTC_V_SYNC_STRT_WID		0x020C
+#define CRTC_V_SYNC_POL			(1 << 23)
 #define CRTC_VLINE_CRNT_VLINE		0x0210
 #define CRTC_CRNT_FRAME			0x0214
 #define CRTC_GUI_TRIG_VLINE		0x0218
@@ -748,6 +750,8 @@
 #define NONSURF_AP0_SWP_32BPP		(1 << 21)
 #define NONSURF_AP1_SWP_16BPP		(1 << 22)
 #define NONSURF_AP1_SWP_32BPP		(1 << 23)
+
+#define R200_SURF_TILE_COLOR_MACRO	(1 << 16)
  
 /* DEFAULT_SC_BOTTOM_RIGHT bit constants */
 #define DEFAULT_SC_RIGHT_MAX		(0x1fff << 0)
...	...	@@ -44,6 +44,7 @@
44	44	#include <asm/io.h>
45	45	#include <malloc.h>
46	46	#include <video_fb.h>
	47	+#include "videomodes.h"
47	48
48	49	#include <radeon.h>
49	50	#include "ati_ids.h"
...	...	@@ -65,6 +66,21 @@
65	66	#define MAX_MAPPED_VRAM (204820484)
66	67	#define MIN_MAPPED_VRAM (10247681)
67	68
	69	+#define RADEON_BUFFER_ALIGN 0x00000fff
	70	+#define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \
	71	+ & ~RADEON_BUFFER_ALIGN) - 1)
	72	+#define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) \| \
	73	+ ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16))
	74	+
	75	+#define CRTC_H_TOTAL_DISP_VAL(htotal, hdisp) \
	76	+ (((((htotal) / 8) - 1) & 0x3ff) \| (((((hdisp) / 8) - 1) & 0x1ff) << 16))
	77	+#define CRTC_HSYNC_STRT_WID_VAL(hsync_srtr, hsync_wid) \
	78	+ (((hsync_srtr) & 0x1fff) \| (((hsync_wid) & 0x3f) << 16))
	79	+#define CRTC_V_TOTAL_DISP_VAL(vtotal, vdisp) \
	80	+ ((((vtotal) - 1) & 0xffff) \| (((vdisp) - 1) << 16))
	81	+#define CRTC_VSYNC_STRT_WID_VAL(vsync_srtr, vsync_wid) \
	82	+ ((((vsync_srtr) - 1) & 0xfff) \| (((vsync_wid) & 0x1f) << 16))
	83	+
68	84	/#define PCI_VENDOR_ID_ATI/
69	85	#define PCI_CHIP_RV280_5960 0x5960
70	86	#define PCI_CHIP_RV280_5961 0x5961
...	...	@@ -350,6 +366,204 @@
350	366	radeon_write_pll_regs(rinfo, mode);
351	367	}
352	368
	369	+static void set_pal(void)
	370	+{
	371	+ int idx, val = 0;
	372	+
	373	+ for (idx = 0; idx < 256; idx++) {
	374	+ OUTREG8(PALETTE_INDEX, idx);
	375	+ OUTREG(PALETTE_DATA, val);
	376	+ val += 0x00010101;
	377	+ }
	378	+}
	379	+
	380	+void radeon_setmode_9200(int vesa_idx, int bpp)
	381	+{
	382	+ struct radeon_regs *mode = malloc(sizeof(struct radeon_regs));
	383	+
	384	+ mode->crtc_gen_cntl = CRTC_EN \| CRTC_EXT_DISP_EN;
	385	+ mode->crtc_ext_cntl = VGA_ATI_LINEAR \| XCRT_CNT_EN \| CRTC_CRT_ON;
	386	+ mode->dac_cntl = DAC_MASK_ALL \| DAC_VGA_ADR_EN \| DAC_8BIT_EN;
	387	+ mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN;
	388	+
	389	+ switch (bpp) {
	390	+ case 24:
	391	+ mode->crtc_gen_cntl \|= 0x6 << 8; /* x888 */
	392	+#if defined(__BIG_ENDIAN)
	393	+ mode->surface_cntl = NONSURF_AP0_SWP_32BPP \| NONSURF_AP1_SWP_32BPP;
	394	+ mode->surf_info[0] = NONSURF_AP0_SWP_32BPP \| NONSURF_AP1_SWP_32BPP;
	395	+#endif
	396	+ break;
	397	+ case 16:
	398	+ mode->crtc_gen_cntl \|= 0x4 << 8; /* 565 */
	399	+#if defined(__BIG_ENDIAN)
	400	+ mode->surface_cntl = NONSURF_AP0_SWP_16BPP \| NONSURF_AP1_SWP_16BPP;
	401	+ mode->surf_info[0] = NONSURF_AP0_SWP_16BPP \| NONSURF_AP1_SWP_16BPP;
	402	+#endif
	403	+ break;
	404	+ default:
	405	+ mode->crtc_gen_cntl \|= 0x2 << 8; /* palette */
	406	+ mode->surface_cntl = 0x00000000;
	407	+ break;
	408	+ }
	409	+
	410	+ switch (vesa_idx) {
	411	+ case RES_MODE_1280x1024:
	412	+ mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280);
	413	+ mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024);
	414	+ mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3);
	415	+#if defined(CONFIG_RADEON_VREFRESH_75HZ)
	416	+ mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18);
	417	+ mode->ppll_div_3 = 0x00010078;
	418	+#else /* default @ 60 Hz */
	419	+ mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14);
	420	+ mode->ppll_div_3 = 0x00010060;
	421	+#endif
	422	+ /*
	423	+ * for this mode pitch expands to the same value for 32, 16 and 8 bpp,
	424	+ * so we set it here once only.
	425	+ */
	426	+ mode->crtc_pitch = RADEON_CRT_PITCH(1280,32);
	427	+ switch (bpp) {
	428	+ case 24:
	429	+ mode->surf_info[0] \|= R200_SURF_TILE_COLOR_MACRO \| (1280 * 4 / 16);
	430	+ mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32);
	431	+ break;
	432	+ case 16:
	433	+ mode->surf_info[0] \|= R200_SURF_TILE_COLOR_MACRO \| (1280 * 2 / 16);
	434	+ mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16);
	435	+ break;
	436	+ default: /* 8 bpp */
	437	+ mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO \| (1280 * 1 / 16);
	438	+ mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8);
	439	+ break;
	440	+ }
	441	+ break;
	442	+ case RES_MODE_1024x768:
	443	+#if defined(CONFIG_RADEON_VREFRESH_75HZ)
	444	+ mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024);
	445	+ mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12);
	446	+ mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768);
	447	+ mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3);
	448	+ mode->ppll_div_3 = 0x0002008c;
	449	+#else /* @ 60 Hz */
	450	+ mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024);
	451	+ mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) \| CRTC_H_SYNC_POL;
	452	+ mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768);
	453	+ mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) \| CRTC_V_SYNC_POL;
	454	+ mode->ppll_div_3 = 0x00020074;
	455	+#endif
	456	+ /* also same pitch value for 32, 16 and 8 bpp */
	457	+ mode->crtc_pitch = RADEON_CRT_PITCH(1024,32);
	458	+ switch (bpp) {
	459	+ case 24:
	460	+ mode->surf_info[0] \|= R200_SURF_TILE_COLOR_MACRO \| (1024 * 4 / 16);
	461	+ mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32);
	462	+ break;
	463	+ case 16:
	464	+ mode->surf_info[0] \|= R200_SURF_TILE_COLOR_MACRO \| (1024 * 2 / 16);
	465	+ mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16);
	466	+ break;
	467	+ default: /* 8 bpp */
	468	+ mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO \| (1024 * 1 / 16);
	469	+ mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8);
	470	+ break;
	471	+ }
	472	+ break;
	473	+ case RES_MODE_800x600:
	474	+ mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800);
	475	+#if defined(CONFIG_RADEON_VREFRESH_75HZ)
	476	+ mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10);
	477	+ mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600);
	478	+ mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3);
	479	+ mode->ppll_div_3 = 0x000300b0;
	480	+#else /* @ 60 Hz */
	481	+ mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16);
	482	+ mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600);
	483	+ mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4);
	484	+ mode->ppll_div_3 = 0x0003008e;
	485	+#endif
	486	+ switch (bpp) {
	487	+ case 24:
	488	+ mode->crtc_pitch = RADEON_CRT_PITCH(832,32);
	489	+ mode->surf_info[0] \|= R200_SURF_TILE_COLOR_MACRO \| (832 * 4 / 16);
	490	+ mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32);
	491	+ break;
	492	+ case 16:
	493	+ mode->crtc_pitch = RADEON_CRT_PITCH(896,16);
	494	+ mode->surf_info[0] \|= R200_SURF_TILE_COLOR_MACRO \| (896 * 2 / 16);
	495	+ mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16);
	496	+ break;
	497	+ default: /* 8 bpp */
	498	+ mode->crtc_pitch = RADEON_CRT_PITCH(1024,8);
	499	+ mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO \| (1024 * 1 / 16);
	500	+ mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8);
	501	+ break;
	502	+ }
	503	+ break;
	504	+ default: /* RES_MODE_640x480 */
	505	+#if defined(CONFIG_RADEON_VREFRESH_75HZ)
	506	+ mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640);
	507	+ mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) \| CRTC_H_SYNC_POL;
	508	+ mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480);
	509	+ mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) \| CRTC_V_SYNC_POL;
	510	+ mode->ppll_div_3 = 0x00030070;
	511	+#else /* @ 60 Hz */
	512	+ mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640);
	513	+ mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) \| CRTC_H_SYNC_POL;
	514	+ mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480);
	515	+ mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) \| CRTC_V_SYNC_POL;
	516	+ mode->ppll_div_3 = 0x00030059;
	517	+#endif
	518	+ /* also same pitch value for 32, 16 and 8 bpp */
	519	+ mode->crtc_pitch = RADEON_CRT_PITCH(640,32);
	520	+ switch (bpp) {
	521	+ case 24:
	522	+ mode->surf_info[0] \|= R200_SURF_TILE_COLOR_MACRO \| (640 * 4 / 16);
	523	+ mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32);
	524	+ break;
	525	+ case 16:
	526	+ mode->surf_info[0] \|= R200_SURF_TILE_COLOR_MACRO \| (640 * 2 / 16);
	527	+ mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16);
	528	+ break;
	529	+ default: /* 8 bpp */
	530	+ mode->crtc_offset_cntl = 0x00000000;
	531	+ break;
	532	+ }
	533	+ break;
	534	+ }
	535	+
	536	+ OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl \| CRTC_DISP_REQ_EN_B);
	537	+ OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
	538	+ (CRTC_HSYNC_DIS \| CRTC_VSYNC_DIS \| CRTC_DISPLAY_DIS));
	539	+ OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL \| DAC_BLANKING);
	540	+ OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
	541	+ OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
	542	+ OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
	543	+ OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
	544	+ OUTREG(CRTC_OFFSET, 0);
	545	+ OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl);
	546	+ OUTREG(CRTC_PITCH, mode->crtc_pitch);
	547	+ OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
	548	+
	549	+ mode->clk_cntl_index = 0x300;
	550	+ mode->ppll_ref_div = 0xc;
	551	+
	552	+ radeon_write_pll_regs(rinfo, mode);
	553	+
	554	+ OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
	555	+ ~(CRTC_HSYNC_DIS \| CRTC_VSYNC_DIS \| CRTC_DISPLAY_DIS));
	556	+ OUTREG(SURFACE0_INFO, mode->surf_info[0]);
	557	+ OUTREG(SURFACE0_LOWER_BOUND, 0);
	558	+ OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]);
	559	+ OUTREG(SURFACE_CNTL, mode->surface_cntl);
	560	+
	561	+ if (bpp > 8)
	562	+ set_pal();
	563	+
	564	+ free(mode);
	565	+}
	566	+
353	567	#include "../bios_emulator/include/biosemu.h"
354	568	extern int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo ** pVGAInfo, int cleanUp);
355	569
356	570
357	571
358	572
359	573
360	574
361	575
362	576
...	...	@@ -421,30 +635,102 @@
421	635	void *video_hw_init(void)
422	636	{
423	637	GraphicDevice pGD = (GraphicDevice ) & ctfb;
424		- int i;
425	638	u32 *vm;
	639	+ char *penv;
	640	+ unsigned long t1, hsynch, vsynch;
	641	+ int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
	642	+ struct ctfb_res_modes *res_mode;
	643	+ struct ctfb_res_modes var_mode;
426	644
427	645	rinfo = malloc(sizeof(struct radeonfb_info));
428	646
	647	+ printf("Video: ");
429	648	if(radeon_probe(rinfo)) {
430	649	printf("No radeon video card found!\n");
431	650	return NULL;
432	651	}
433	652
	653	+ tmp = 0;
	654	+
	655	+ videomode = CFG_DEFAULT_VIDEO_MODE;
	656	+ /* get video mode via environment */
	657	+ if ((penv = getenv ("videomode")) != NULL) {
	658	+ /* deceide if it is a string */
	659	+ if (penv[0] <= '9') {
	660	+ videomode = (int) simple_strtoul (penv, NULL, 16);
	661	+ tmp = 1;
	662	+ }
	663	+ } else {
	664	+ tmp = 1;
	665	+ }
	666	+ if (tmp) {
	667	+ /* parameter are vesa modes */
	668	+ /* search params */
	669	+ for (i = 0; i < VESA_MODES_COUNT; i++) {
	670	+ if (vesa_modes[i].vesanr == videomode)
	671	+ break;
	672	+ }
	673	+ if (i == VESA_MODES_COUNT) {
	674	+ printf ("no VESA Mode found, switching to mode 0x%x ", CFG_DEFAULT_VIDEO_MODE);
	675	+ i = 0;
	676	+ }
	677	+ res_mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex];
	678	+ bits_per_pixel = vesa_modes[i].bits_per_pixel;
	679	+ vesa_idx = vesa_modes[i].resindex;
	680	+ } else {
	681	+ res_mode = (struct ctfb_res_modes *) &var_mode;
	682	+ bits_per_pixel = video_get_params (res_mode, penv);
	683	+ }
	684	+
	685	+ /* calculate hsynch and vsynch freq (info only) */
	686	+ t1 = (res_mode->left_margin + res_mode->xres +
	687	+ res_mode->right_margin + res_mode->hsync_len) / 8;
	688	+ t1 *= 8;
	689	+ t1 *= res_mode->pixclock;
	690	+ t1 /= 1000;
	691	+ hsynch = 1000000000L / t1;
	692	+ t1 *= (res_mode->upper_margin + res_mode->yres +
	693	+ res_mode->lower_margin + res_mode->vsync_len);
	694	+ t1 /= 1000;
	695	+ vsynch = 1000000000L / t1;
	696	+
434	697	/* fill in Graphic device struct */
435		- sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", 640,
436		- 480, 16, (1000 / 1000),
437		- (2000 / 1000));
	698	+ sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
	699	+ res_mode->yres, bits_per_pixel, (hsynch / 1000),
	700	+ (vsynch / 1000));
438	701	printf ("%s\n", pGD->modeIdent);
	702	+ pGD->winSizeX = res_mode->xres;
	703	+ pGD->winSizeY = res_mode->yres;
	704	+ pGD->plnSizeX = res_mode->xres;
	705	+ pGD->plnSizeY = res_mode->yres;
439	706
440		- pGD->winSizeX = 640;
441		- pGD->winSizeY = 480;
442		- pGD->plnSizeX = 640;
443		- pGD->plnSizeY = 480;
	707	+ switch (bits_per_pixel) {
	708	+ case 24:
	709	+ pGD->gdfBytesPP = 4;
	710	+ pGD->gdfIndex = GDF_32BIT_X888RGB;
	711	+ if (res_mode->xres == 800) {
	712	+ pGD->winSizeX = 832;
	713	+ pGD->plnSizeX = 832;
	714	+ }
	715	+ break;
	716	+ case 16:
	717	+ pGD->gdfBytesPP = 2;
	718	+ pGD->gdfIndex = GDF_16BIT_565RGB;
	719	+ if (res_mode->xres == 800) {
	720	+ pGD->winSizeX = 896;
	721	+ pGD->plnSizeX = 896;
	722	+ }
	723	+ break;
	724	+ default:
	725	+ if (res_mode->xres == 800) {
	726	+ pGD->winSizeX = 1024;
	727	+ pGD->plnSizeX = 1024;
	728	+ }
	729	+ pGD->gdfBytesPP = 1;
	730	+ pGD->gdfIndex = GDF__8BIT_INDEX;
	731	+ break;
	732	+ }
444	733
445		- pGD->gdfBytesPP = 1;
446		- pGD->gdfIndex = GDF__8BIT_INDEX;
447		-
448	734	pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS;
449	735	pGD->pciBase = rinfo->fb_base_phys;
450	736	pGD->frameAdrs = rinfo->fb_base_phys;
451	737
...	...	@@ -464,14 +750,17 @@
464	750	pGD->cprBase = rinfo->fb_base_phys; /* Dummy */
465	751	/* set up Hardware */
466	752
467		- /* Clear video memory */
468		- i = pGD->memSize / 4;
	753	+ /* Clear video memory (only visible screen area) */
	754	+ i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4;
469	755	vm = (unsigned int *) pGD->pciBase;
470	756	while (i--)
471	757	*vm++ = 0;
472	758	/SetDrawingEngine (bits_per_pixel);/
473	759
474		- radeon_setmode();
	760	+ if (rinfo->family == CHIP_FAMILY_RV280)
	761	+ radeon_setmode_9200(vesa_idx, bits_per_pixel);
	762	+ else
	763	+ radeon_setmode();
475	764
476	765	return ((void *) pGD);
477	766	}
...	...	@@ -154,8 +154,10 @@
154	154	#define PALETTE_30_DATA 0x00B8
155	155	#define CRTC_H_TOTAL_DISP 0x0200
156	156	#define CRTC_H_SYNC_STRT_WID 0x0204
	157	+#define CRTC_H_SYNC_POL (1 << 23)
157	158	#define CRTC_V_TOTAL_DISP 0x0208
158	159	#define CRTC_V_SYNC_STRT_WID 0x020C
	160	+#define CRTC_V_SYNC_POL (1 << 23)
159	161	#define CRTC_VLINE_CRNT_VLINE 0x0210
160	162	#define CRTC_CRNT_FRAME 0x0214
161	163	#define CRTC_GUI_TRIG_VLINE 0x0218
...	...	@@ -748,6 +750,8 @@
748	750	#define NONSURF_AP0_SWP_32BPP (1 << 21)
749	751	#define NONSURF_AP1_SWP_16BPP (1 << 22)
750	752	#define NONSURF_AP1_SWP_32BPP (1 << 23)
	753	+
	754	+#define R200_SURF_TILE_COLOR_MACRO (1 << 16)
751	755
752	756	/* DEFAULT_SC_BOTTOM_RIGHT bit constants */
753	757	#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0)