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Commit 1ecab0f30f9051821fdb5ec1c689b7c531b4feda

Authored by Piotr Wilczek
Committed by Minkyu Kang
1 parent fe60164792
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

board:trats2: Enable device tree on Trats2 

This patch enables to run Trats2 board on device tree.

Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Showing 4 changed files with 483 additions and 391 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ 1ecab0f
1 1 dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \
2 2 exynos4210-universal_c210.dtb \
3   - exynos4210-trats.dtb
  3 + exynos4210-trats.dtb \
  4 + exynos4412-trats2.dtb
4 5  
5 6 dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
6 7 exynos5250-snow.dtb \
arch/arm/dts/exynos4412-trats2.dts
Diff comments   View file @ 1ecab0f
  1 +/*
  2 + * Samsung's Exynos4412 based Trats2 board device tree source
  3 + *
  4 + * Copyright (c) 2014 Samsung Electronics Co., Ltd.
  5 + * http://www.samsung.com
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +/dts-v1/;
  11 +/include/ "exynos4.dtsi"
  12 +
  13 +/ {
  14 + model = "Samsung Trats2 based on Exynos4412";
  15 + compatible = "samsung,trats2", "samsung,exynos4412";
  16 +
  17 + config {
  18 + samsung,dsim-device-name = "s6e8ax0";
  19 + };
  20 +
  21 + aliases {
  22 + i2c0 = "/i2c@13860000";
  23 + i2c1 = "/i2c@13870000";
  24 + i2c2 = "/i2c@13880000";
  25 + i2c3 = "/i2c@13890000";
  26 + i2c4 = "/i2c@138a0000";
  27 + i2c5 = "/i2c@138b0000";
  28 + i2c6 = "/i2c@138c0000";
  29 + i2c7 = "/i2c@138d0000";
  30 + serial0 = "/serial@13800000";
  31 + console = "/serial@13820000";
  32 + mmc0 = "sdhci@12510000";
  33 + mmc2 = "sdhci@12530000";
  34 + };
  35 +
  36 + i2c@138d0000 {
  37 + samsung,i2c-sda-delay = <100>;
  38 + samsung,i2c-slave-addr = <0x10>;
  39 + samsung,i2c-max-bus-freq = <100000>;
  40 + status = "okay";
  41 +
  42 + max77686_pmic@09 {
  43 + compatible = "maxim,max77686_pmic";
  44 + interrupts = <7 0>;
  45 + reg = <0x09 0 0>;
  46 + #clock-cells = <1>;
  47 +
  48 + voltage-regulators {
  49 + ldo1_reg: ldo1 {
  50 + regulator-compatible = "LDO1";
  51 + regulator-name = "VALIVE_1.0V_AP";
  52 + regulator-min-microvolt = <1000000>;
  53 + regulator-max-microvolt = <1000000>;
  54 + regulator-always-on;
  55 + regulator-mem-on;
  56 + };
  57 +
  58 + ldo2_reg: ldo2 {
  59 + regulator-compatible = "LDO2";
  60 + regulator-name = "VM1M2_1.2V_AP";
  61 + regulator-min-microvolt = <1200000>;
  62 + regulator-max-microvolt = <1200000>;
  63 + regulator-always-on;
  64 + regulator-mem-on;
  65 + };
  66 +
  67 + ldo3_reg: ldo3 {
  68 + regulator-compatible = "LDO3";
  69 + regulator-name = "VCC_1.8V_AP";
  70 + regulator-min-microvolt = <1800000>;
  71 + regulator-max-microvolt = <1800000>;
  72 + regulator-always-on;
  73 + regulator-mem-on;
  74 + };
  75 +
  76 + ldo4_reg: ldo4 {
  77 + regulator-compatible = "LDO4";
  78 + regulator-name = "VCC_2.8V_AP";
  79 + regulator-min-microvolt = <2800000>;
  80 + regulator-max-microvolt = <2800000>;
  81 + regulator-always-on;
  82 + regulator-mem-on;
  83 + };
  84 +
  85 + ldo5_reg: ldo5 {
  86 + regulator-compatible = "LDO5";
  87 + regulator-name = "VCC_1.8V_IO";
  88 + regulator-min-microvolt = <1800000>;
  89 + regulator-max-microvolt = <1800000>;
  90 + regulator-always-on;
  91 + regulator-mem-on;
  92 + };
  93 +
  94 + ldo6_reg: ldo6 {
  95 + regulator-compatible = "LDO6";
  96 + regulator-name = "VMPLL_1.0V_AP";
  97 + regulator-min-microvolt = <1000000>;
  98 + regulator-max-microvolt = <1000000>;
  99 + regulator-always-on;
  100 + regulator-mem-on;
  101 + };
  102 +
  103 + ldo7_reg: ldo7 {
  104 + regulator-compatible = "LDO7";
  105 + regulator-name = "VPLL_1.0V_AP";
  106 + regulator-min-microvolt = <1000000>;
  107 + regulator-max-microvolt = <1000000>;
  108 + regulator-always-on;
  109 + regulator-mem-on;
  110 + };
  111 +
  112 + ldo8_reg: ldo8 {
  113 + regulator-compatible = "LDO8";
  114 + regulator-name = "VMIPI_1.0V";
  115 + regulator-min-microvolt = <1000000>;
  116 + regulator-max-microvolt = <1000000>;
  117 + regulator-mem-off;
  118 + };
  119 +
  120 + ldo9_reg: ldo9 {
  121 + regulator-compatible = "LDO9";
  122 + regulator-name = "CAM_ISP_MIPI_1.2V";
  123 + regulator-min-microvolt = <1200000>;
  124 + regulator-max-microvolt = <1200000>;
  125 + regulator-mem-idle;
  126 + };
  127 +
  128 + ldo10_reg: ldo10 {
  129 + regulator-compatible = "LDO10";
  130 + regulator-name = "VMIPI_1.8V";
  131 + regulator-min-microvolt = <1800000>;
  132 + regulator-max-microvolt = <1800000>;
  133 + regulator-mem-off;
  134 + };
  135 +
  136 + ldo11_reg: ldo11 {
  137 + regulator-compatible = "LDO11";
  138 + regulator-name = "VABB1_1.95V";
  139 + regulator-min-microvolt = <1950000>;
  140 + regulator-max-microvolt = <1950000>;
  141 + regulator-always-on;
  142 + regulator-mem-off;
  143 + };
  144 +
  145 + ldo12_reg: ldo12 {
  146 + regulator-compatible = "LDO12";
  147 + regulator-name = "VUOTG_3.0V";
  148 + regulator-min-microvolt = <3000000>;
  149 + regulator-max-microvolt = <3000000>;
  150 + regulator-mem-off;
  151 + };
  152 +
  153 + ldo13_reg: ldo13 {
  154 + regulator-compatible = "LDO13";
  155 + regulator-name = "NFC_AVDD_1.8V";
  156 + regulator-min-microvolt = <1800000>;
  157 + regulator-max-microvolt = <1800000>;
  158 + regulator-mem-idle;
  159 + };
  160 +
  161 + ldo14_reg: ldo14 {
  162 + regulator-compatible = "LDO14";
  163 + regulator-name = "VABB2_1.95V";
  164 + regulator-min-microvolt = <1950000>;
  165 + regulator-max-microvolt = <1950000>;
  166 + regulator-always-on;
  167 + regulator-mem-off;
  168 + };
  169 +
  170 + ldo15_reg: ldo15 {
  171 + regulator-compatible = "LDO15";
  172 + regulator-name = "VHSIC_1.0V";
  173 + regulator-min-microvolt = <1000000>;
  174 + regulator-max-microvolt = <1000000>;
  175 + regulator-mem-off;
  176 + };
  177 +
  178 + ldo16_reg: ldo16 {
  179 + regulator-compatible = "LDO16";
  180 + regulator-name = "VHSIC_1.8V";
  181 + regulator-min-microvolt = <1800000>;
  182 + regulator-max-microvolt = <1800000>;
  183 + regulator-mem-off;
  184 + };
  185 +
  186 + ldo17_reg: ldo17 {
  187 + regulator-compatible = "LDO17";
  188 + regulator-name = "CAM_SENSOR_CORE_1.2V";
  189 + regulator-min-microvolt = <1200000>;
  190 + regulator-max-microvolt = <1200000>;
  191 + regulator-mem-idle;
  192 + };
  193 +
  194 + ldo18_reg: ldo18 {
  195 + regulator-compatible = "LDO18";
  196 + regulator-name = "CAM_ISP_SEN_IO_1.8V";
  197 + regulator-min-microvolt = <1800000>;
  198 + regulator-max-microvolt = <1800000>;
  199 + regulator-mem-idle;
  200 + };
  201 +
  202 + ldo19_reg: ldo19 {
  203 + regulator-compatible = "LDO19";
  204 + regulator-name = "VT_CAM_1.8V";
  205 + regulator-min-microvolt = <1800000>;
  206 + regulator-max-microvolt = <1800000>;
  207 + regulator-mem-idle;
  208 + };
  209 +
  210 + ldo20_reg: ldo20 {
  211 + regulator-compatible = "LDO20";
  212 + regulator-name = "VDDQ_PRE_1.8V";
  213 + regulator-min-microvolt = <1800000>;
  214 + regulator-max-microvolt = <1800000>;
  215 + regulator-mem-idle;
  216 + };
  217 +
  218 + ldo21_reg: ldo21 {
  219 + regulator-compatible = "LDO21";
  220 + regulator-name = "VTF_2.8V";
  221 + regulator-min-microvolt = <2800000>;
  222 + regulator-max-microvolt = <2800000>;
  223 + regulator-mem-idle;
  224 + };
  225 +
  226 + ldo22_reg: ldo22 {
  227 + regulator-compatible = "LDO22";
  228 + regulator-name = "VMEM_VDD_2.8V";
  229 + regulator-min-microvolt = <2800000>;
  230 + regulator-max-microvolt = <2800000>;
  231 + regulator-always-on;
  232 + regulator-mem-off;
  233 + };
  234 +
  235 + ldo23_reg: ldo23 {
  236 + regulator-compatible = "LDO23";
  237 + regulator-name = "TSP_AVDD_3.3V";
  238 + regulator-min-microvolt = <3300000>;
  239 + regulator-max-microvolt = <3300000>;
  240 + regulator-mem-idle;
  241 + };
  242 +
  243 + ldo24_reg: ldo24 {
  244 + regulator-compatible = "LDO24";
  245 + regulator-name = "TSP_VDD_1.8V";
  246 + regulator-min-microvolt = <1800000>;
  247 + regulator-max-microvolt = <1800000>;
  248 + regulator-mem-idle;
  249 + };
  250 +
  251 + ldo25_reg: ldo25 {
  252 + regulator-compatible = "LDO25";
  253 + regulator-name = "LCD_VCC_3.3V";
  254 + regulator-min-microvolt = <2800000>;
  255 + regulator-max-microvolt = <2800000>;
  256 + regulator-mem-idle;
  257 + };
  258 +
  259 + ldo26_reg: ldo26 {
  260 + regulator-compatible = "LDO26";
  261 + regulator-name = "MOTOR_VCC_3.0V";
  262 + regulator-min-microvolt = <3000000>;
  263 + regulator-max-microvolt = <3000000>;
  264 + regulator-mem-idle;
  265 + };
  266 +
  267 + buck1_reg: buck1 {
  268 + regulator-compatible = "BUCK1";
  269 + regulator-name = "vdd_mif";
  270 + regulator-min-microvolt = <850000>;
  271 + regulator-max-microvolt = <1100000>;
  272 + regulator-always-on;
  273 + regulator-boot-on;
  274 + regulator-mem-off;
  275 + };
  276 +
  277 + buck2_reg: buck2 {
  278 + regulator-compatible = "BUCK2";
  279 + regulator-name = "vdd_arm";
  280 + regulator-min-microvolt = <850000>;
  281 + regulator-max-microvolt = <1500000>;
  282 + regulator-always-on;
  283 + regulator-boot-on;
  284 + regulator-mem-off;
  285 + };
  286 +
  287 + buck3_reg: buck3 {
  288 + regulator-compatible = "BUCK3";
  289 + regulator-name = "vdd_int";
  290 + regulator-min-microvolt = <850000>;
  291 + regulator-max-microvolt = <1150000>;
  292 + regulator-always-on;
  293 + regulator-boot-on;
  294 + regulator-mem-off;
  295 + };
  296 +
  297 + buck4_reg: buck4 {
  298 + regulator-compatible = "BUCK4";
  299 + regulator-name = "vdd_g3d";
  300 + regulator-min-microvolt = <850000>;
  301 + regulator-max-microvolt = <1150000>;
  302 + regulator-boot-on;
  303 + regulator-mem-off;
  304 + };
  305 +
  306 + buck5_reg: buck5 {
  307 + regulator-compatible = "BUCK5";
  308 + regulator-name = "VMEM_1.2V_AP";
  309 + regulator-min-microvolt = <1200000>;
  310 + regulator-max-microvolt = <1200000>;
  311 + regulator-always-on;
  312 + };
  313 +
  314 + buck6_reg: buck6 {
  315 + regulator-compatible = "BUCK6";
  316 + regulator-name = "VCC_SUB_1.35V";
  317 + regulator-min-microvolt = <1350000>;
  318 + regulator-max-microvolt = <1350000>;
  319 + regulator-always-on;
  320 + };
  321 +
  322 + buck7_reg: buck7 {
  323 + regulator-compatible = "BUCK7";
  324 + regulator-name = "VCC_SUB_2.0V";
  325 + regulator-min-microvolt = <2000000>;
  326 + regulator-max-microvolt = <2000000>;
  327 + regulator-always-on;
  328 + };
  329 +
  330 + buck8_reg: buck8 {
  331 + regulator-compatible = "BUCK8";
  332 + regulator-name = "VMEM_VDDF_3.0V";
  333 + regulator-min-microvolt = <2850000>;
  334 + regulator-max-microvolt = <2850000>;
  335 + regulator-always-on;
  336 + regulator-mem-off;
  337 + };
  338 +
  339 + buck9_reg: buck9 {
  340 + regulator-compatible = "BUCK9";
  341 + regulator-name = "CAM_ISP_CORE_1.2V";
  342 + regulator-min-microvolt = <1000000>;
  343 + regulator-max-microvolt = <1200000>;
  344 + regulator-mem-off;
  345 + };
  346 + };
  347 + };
  348 + };
  349 +
  350 + fimd@11c00000 {
  351 + compatible = "samsung,exynos-fimd";
  352 + reg = <0x11c00000 0xa4>;
  353 +
  354 + samsung,vl-freq = <60>;
  355 + samsung,vl-col = <720>;
  356 + samsung,vl-row = <1280>;
  357 + samsung,vl-width = <720>;
  358 + samsung,vl-height = <1280>;
  359 +
  360 + samsung,vl-clkp = <0>;
  361 + samsung,vl-oep = <0>;
  362 + samsung,vl-hsp = <1>;
  363 + samsung,vl-vsp = <1>;
  364 + samsung,vl-dp = <1>;
  365 + samsung,vl-bpix = <4>;
  366 +
  367 + samsung,vl-hspw = <5>;
  368 + samsung,vl-hbpd = <10>;
  369 + samsung,vl-hfpd = <10>;
  370 + samsung,vl-vspw = <2>;
  371 + samsung,vl-vbpd = <1>;
  372 + samsung,vl-vfpd = <13>;
  373 + samsung,vl-cmd-allow-len = <0xf>;
  374 +
  375 + samsung,winid = <0>;
  376 + samsung,power-on-delay = <30>;
  377 + samsung,interface-mode = <1>;
  378 + samsung,mipi-enabled = <1>;
  379 + samsung,dp-enabled;
  380 + samsung,dual-lcd-enabled;
  381 +
  382 + samsung,logo-on = <1>;
  383 + samsung,resolution = <0>;
  384 + samsung,rgb-mode = <0>;
  385 + };
  386 +
  387 + mipidsi@11c80000 {
  388 + compatible = "samsung,exynos-mipi-dsi";
  389 + reg = <0x11c80000 0x5c>;
  390 +
  391 + samsung,dsim-config-e-interface = <1>;
  392 + samsung,dsim-config-e-virtual-ch = <0>;
  393 + samsung,dsim-config-e-pixel-format = <7>;
  394 + samsung,dsim-config-e-burst-mode = <1>;
  395 + samsung,dsim-config-e-no-data-lane = <3>;
  396 + samsung,dsim-config-e-byte-clk = <0>;
  397 + samsung,dsim-config-hfp = <1>;
  398 +
  399 + samsung,dsim-config-p = <3>;
  400 + samsung,dsim-config-m = <120>;
  401 + samsung,dsim-config-s = <1>;
  402 +
  403 + samsung,dsim-config-pll-stable-time = <500>;
  404 + samsung,dsim-config-esc-clk = <20000000>;
  405 + samsung,dsim-config-stop-holding-cnt = <0x7ff>;
  406 + samsung,dsim-config-bta-timeout = <0xff>;
  407 + samsung,dsim-config-rx-timeout = <0xffff>;
  408 +
  409 + samsung,dsim-device-id = <0xffffffff>;
  410 + samsung,dsim-device-bus-id = <0>;
  411 +
  412 + samsung,dsim-device-reverse-panel = <1>;
  413 + };
  414 +
  415 + sdhci@12510000 {
  416 + samsung,bus-width = <8>;
  417 + samsung,timing = <1 3 3>;
  418 + pwr-gpios = <&gpio 0x2004002 0>;
  419 + };
  420 +
  421 + sdhci@12520000 {
  422 + status = "disabled";
  423 + };
  424 +
  425 + sdhci@12530000 {
  426 + samsung,bus-width = <4>;
  427 + samsung,timing = <1 2 3>;
  428 + cd-gpios = <&gpio 0x20C6004 0>;
  429 + };
  430 +
  431 + sdhci@12540000 {
  432 + status = "disabled";
  433 + };
  434 +};
board/samsung/trats2/trats2.c
Diff comments   View file @ 1ecab0f
... ... @@ -8,15 +8,9 @@
8 8  
9 9 #include <common.h>
10 10 #include <lcd.h>
11   -#include <asm/io.h>
12   -#include <asm/arch/gpio.h>
13   -#include <asm/arch/mmc.h>
14   -#include <asm/arch/power.h>
15   -#include <asm/arch/clk.h>
16   -#include <asm/arch/clock.h>
17   -#include <asm/arch/mipi_dsim.h>
18 11 #include <asm/arch/pinmux.h>
19 12 #include <asm/arch/power.h>
  13 +#include <asm/arch/mipi_dsim.h>
20 14 #include <power/pmic.h>
21 15 #include <power/max77686_pmic.h>
22 16 #include <power/battery.h>
... ... @@ -28,7 +22,6 @@
28 22 #include <usb.h>
29 23 #include <usb/s3c_udc.h>
30 24 #include <usb_mass_storage.h>
31   -#include <samsung/misc.h>
32 25  
33 26 DECLARE_GLOBAL_DATA_PTR;
34 27  
... ... @@ -69,16 +62,6 @@
69 62 board_rev = modelrev << 8;
70 63 }
71 64  
72   -#ifdef CONFIG_DISPLAY_BOARDINFO
73   -int checkboard(void)
74   -{
75   - puts("Board:\tTRATS2\n");
76   - printf("HW Revision:\t0x%04x\n", board_rev);
77   -
78   - return 0;
79   -}
80   -#endif
81   -
82 65 u32 get_board_rev(void)
83 66 {
84 67 return board_rev;
85 68  
86 69  
87 70  
88 71  
89 72  
90 73  
... ... @@ -156,33 +139,24 @@
156 139 }
157 140 #endif
158 141  
159   -int board_early_init_f(void)
  142 +int exynos_early_init_f(void)
160 143 {
161   - check_hw_revision();
162 144 board_external_gpio_init();
163 145  
164   - gd->flags |= GD_FLG_DISABLE_CONSOLE;
165   -
166 146 return 0;
167 147 }
168 148  
169 149 static int pmic_init_max77686(void);
170 150  
171   -int board_init(void)
  151 +int exynos_init(void)
172 152 {
173   - struct exynos4_power *pwr =
174   - (struct exynos4_power *)samsung_get_base_power();
  153 + check_hw_revision();
  154 + printf("HW Revision:\t0x%04x\n", board_rev);
175 155  
176   - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
177   -
178   - /* workaround: clear INFORM4..5 */
179   - writel(0, (unsigned int)&pwr->inform4);
180   - writel(0, (unsigned int)&pwr->inform5);
181   -
182 156 return 0;
183 157 }
184 158  
185   -int power_init_board(void)
  159 +int exynos_power_init(void)
186 160 {
187 161 int chrg;
188 162 struct power_battery *pb;
... ... @@ -248,90 +222,6 @@
248 222 return 0;
249 223 }
250 224  
251   -int dram_init(void)
252   -{
253   - u32 size_mb;
254   -
255   - size_mb = (get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) +
256   - get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) +
257   - get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) +
258   - get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE)) >> 20;
259   -
260   - gd->ram_size = size_mb << 20;
261   -
262   - return 0;
263   -}
264   -
265   -void dram_init_banksize(void)
266   -{
267   - gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
268   - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
269   - gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
270   - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
271   - gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
272   - gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
273   - gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
274   - gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
275   -}
276   -
277   -int board_mmc_init(bd_t *bis)
278   -{
279   - int err0, err2 = 0;
280   -
281   - gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
282   -
283   - /* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
284   - s5p_gpio_direction_output(&gpio2->k0, 2, 1);
285   - s5p_gpio_set_pull(&gpio2->k0, 2, GPIO_PULL_NONE);
286   -
287   - /*
288   - * eMMC GPIO:
289   - * SDR 8-bit@48MHz at MMC0
290   - * GPK0[0] SD_0_CLK(2)
291   - * GPK0[1] SD_0_CMD(2)
292   - * GPK0[2] SD_0_CDn -> Not used
293   - * GPK0[3:6] SD_0_DATA[0:3](2)
294   - * GPK1[3:6] SD_0_DATA[0:3](3)
295   - *
296   - * DDR 4-bit@26MHz at MMC4
297   - * GPK0[0] SD_4_CLK(3)
298   - * GPK0[1] SD_4_CMD(3)
299   - * GPK0[2] SD_4_CDn -> Not used
300   - * GPK0[3:6] SD_4_DATA[0:3](3)
301   - * GPK1[3:6] SD_4_DATA[4:7](4)
302   - */
303   -
304   - err0 = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
305   -
306   - /*
307   - * MMC device init
308   - * mmc0 : eMMC (8-bit buswidth)
309   - * mmc2 : SD card (4-bit buswidth)
310   - */
311   - if (err0)
312   - debug("SDMMC0 not configured\n");
313   - else
314   - err0 = s5p_mmc_init(0, 8);
315   -
316   - /* T-flash detect */
317   - s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
318   - s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
319   -
320   - /*
321   - * Check the T-flash detect pin
322   - * GPX3[4] T-flash detect pin
323   - */
324   - if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
325   - err2 = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
326   - if (err2)
327   - debug("SDMMC2 not configured\n");
328   - else
329   - err2 = s5p_mmc_init(2, 4);
330   - }
331   -
332   - return err0 & err2;
333   -}
334   -
335 225 #ifdef CONFIG_USB_GADGET
336 226 static int s5pc210_phy_control(int on)
337 227 {
... ... @@ -479,46 +369,7 @@
479 369 */
480 370  
481 371 #ifdef CONFIG_LCD
482   -static struct mipi_dsim_config dsim_config = {
483   - .e_interface = DSIM_VIDEO,
484   - .e_virtual_ch = DSIM_VIRTUAL_CH_0,
485   - .e_pixel_format = DSIM_24BPP_888,
486   - .e_burst_mode = DSIM_BURST_SYNC_EVENT,
487   - .e_no_data_lane = DSIM_DATA_LANE_4,
488   - .e_byte_clk = DSIM_PLL_OUT_DIV8,
489   - .hfp = 1,
490   -
491   - .p = 3,
492   - .m = 120,
493   - .s = 1,
494   -
495   - /* D-PHY PLL stable time spec :min = 200usec ~ max 400usec */
496   - .pll_stable_time = 500,
497   -
498   - /* escape clk : 10MHz */
499   - .esc_clk = 20 * 1000000,
500   -
501   - /* stop state holding counter after bta change count 0 ~ 0xfff */
502   - .stop_holding_cnt = 0x7ff,
503   - /* bta timeout 0 ~ 0xff */
504   - .bta_timeout = 0xff,
505   - /* lp rx timeout 0 ~ 0xffff */
506   - .rx_timeout = 0xffff,
507   -};
508   -
509   -static struct exynos_platform_mipi_dsim dsim_platform_data = {
510   - .lcd_panel_info = NULL,
511   - .dsim_config = &dsim_config,
512   -};
513   -
514   -static struct mipi_dsim_lcd_device mipi_lcd_device = {
515   - .name = "s6e8ax0",
516   - .id = -1,
517   - .bus_id = 0,
518   - .platform_data = (void *)&dsim_platform_data,
519   -};
520   -
521   -static int mipi_power(void)
  372 +int mipi_power(void)
522 373 {
523 374 struct pmic *p = pmic_get("MAX77686_PMIC");
524 375  
525 376  
526 377  
527 378  
528 379  
529 380  
... ... @@ -556,78 +407,14 @@
556 407 s5p_gpio_set_value(&gpio1->f2, 1, 1);
557 408 }
558 409  
559   -vidinfo_t panel_info = {
560   - .vl_freq = 60,
561   - .vl_col = 720,
562   - .vl_row = 1280,
563   - .vl_width = 720,
564   - .vl_height = 1280,
565   - .vl_clkp = CONFIG_SYS_HIGH,
566   - .vl_hsp = CONFIG_SYS_LOW,
567   - .vl_vsp = CONFIG_SYS_LOW,
568   - .vl_dp = CONFIG_SYS_LOW,
569   - .vl_bpix = 4, /* Bits per pixel, 2^4 = 16 */
570   -
571   - /* s6e8ax0 Panel infomation */
572   - .vl_hspw = 5,
573   - .vl_hbpd = 10,
574   - .vl_hfpd = 10,
575   -
576   - .vl_vspw = 2,
577   - .vl_vbpd = 1,
578   - .vl_vfpd = 13,
579   - .vl_cmd_allow_len = 0xf,
580   - .mipi_enabled = 1,
581   -
582   - .dual_lcd_enabled = 0,
583   -
584   - .init_delay = 0,
585   - .power_on_delay = 25,
586   - .reset_delay = 0,
587   - .interface_mode = FIMD_RGB_INTERFACE,
588   -};
589   -
590   -void init_panel_info(vidinfo_t *vid)
  410 +void exynos_lcd_misc_init(vidinfo_t *vid)
591 411 {
592   - vid->logo_on = 1;
593   - vid->resolution = HD_RESOLUTION;
594   - vid->rgb_mode = MODE_RGB_P;
595   -
596   - vid->power_on_delay = 30;
597   -
598   - mipi_lcd_device.reverse_panel = 1;
599   -
600 412 #ifdef CONFIG_TIZEN
601 413 get_tizen_logo_info(vid);
602 414 #endif
603   -
604   - strcpy(dsim_platform_data.lcd_panel_name, mipi_lcd_device.name);
605   - dsim_platform_data.mipi_power = mipi_power;
606   - dsim_platform_data.phy_enable = set_mipi_phy_ctrl;
607   - dsim_platform_data.lcd_panel_info = (void *)vid;
608   - exynos_mipi_dsi_register_lcd_device(&mipi_lcd_device);
609   -
  415 +#ifdef CONFIG_S6E8AX0
610 416 s6e8ax0_init();
611   -
612   - exynos_set_dsim_platform_data(&dsim_platform_data);
613   -}
614   -#endif /* LCD */
615   -
616   -#ifdef CONFIG_MISC_INIT_R
617   -int misc_init_r(void)
618   -{
619   -#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
620   - set_board_info();
621 417 #endif
622   -#ifdef CONFIG_LCD_MENU
623   - keys_init();
624   - check_boot_mode();
625   -#endif
626   -#ifdef CONFIG_CMD_BMP
627   - if (panel_info.logo_on)
628   - draw_logo();
629   -#endif
630   - return 0;
631 418 }
632   -#endif
  419 +#endif /* LCD */
include/configs/trats2.h
Diff comments   View file @ 1ecab0f
... ... @@ -8,149 +8,65 @@
8 8 * SPDX-License-Identifier: GPL-2.0+
9 9 */
10 10  
11   -#ifndef __CONFIG_H
12   -#define __CONFIG_H
  11 +#ifndef __CONFIG_TRATS2_H
  12 +#define __CONFIG_TRATS2_H
13 13  
14   -/*
15   - * High Level Configuration Options
16   - * (easy to change)
17   - */
18   -#define CONFIG_SAMSUNG /* in a SAMSUNG core */
19   -#define CONFIG_S5P /* which is in a S5P Family */
20   -#define CONFIG_EXYNOS4 /* which is in a EXYNOS4XXX */
21   -#define CONFIG_TIZEN /* TIZEN lib */
  14 +#include <configs/exynos4-dt.h>
22 15  
23   -#include <asm/arch/cpu.h> /* get chip and board defs */
  16 +#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
24 17  
25   -#define CONFIG_ARCH_CPU_INIT
26   -#define CONFIG_DISPLAY_CPUINFO
27   -#define CONFIG_DISPLAY_BOARDINFO
  18 +#undef CONFIG_DEFAULT_DEVICE_TREE
  19 +#define CONFIG_DEFAULT_DEVICE_TREE exynos4412-trats2
28 20  
29   -#define CONFIG_SKIP_LOWLEVEL_INIT
  21 +#define CONFIG_TIZEN /* TIZEN lib */
30 22  
31   -#define CONFIG_SYS_CACHELINE_SIZE 32
32   -
33 23 #define CONFIG_SYS_L2CACHE_OFF
34 24 #ifndef CONFIG_SYS_L2CACHE_OFF
35 25 #define CONFIG_SYS_L2_PL310
36 26 #define CONFIG_SYS_PL310_BASE 0x10502000
37 27 #endif
38 28  
39   -#define CONFIG_NR_DRAM_BANKS 4
40   -#define PHYS_SDRAM_1 0x40000000 /* LDDDR2 DMC 0 */
41   -#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 */
42   -#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
43   -#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 */
44   -#define PHYS_SDRAM_3 0x60000000 /* LPDDR2 DMC 1 */
45   -#define PHYS_SDRAM_3_SIZE (256 << 20) /* 256 MB in CS 0 */
46   -#define PHYS_SDRAM_4 0x70000000 /* LPDDR2 DMC 1 */
47   -#define PHYS_SDRAM_4_SIZE (256 << 20) /* 256 MB in CS 0 */
48   -#define PHYS_SDRAM_END 0x80000000
  29 +/* TRATS2 has 4 banks of DRAM */
  30 +#define CONFIG_NR_DRAM_BANKS 4
  31 +#define CONFIG_SYS_SDRAM_BASE 0x40000000
  32 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
  33 +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
  34 +/* memtest works on */
  35 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
  36 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
  37 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
49 38  
50   -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
51   -
52   -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
53 39 #define CONFIG_SYS_TEXT_BASE 0x78100000
54 40  
55   -#define CONFIG_SYS_CLK_FREQ 24000000
56   -
57   -#define CONFIG_SETUP_MEMORY_TAGS
58   -#define CONFIG_CMDLINE_TAG
59   -#define CONFIG_REVISION_TAG
60   -
61   -/* MACH_TYPE_TRATS2 */
62   -#define MACH_TYPE_TRATS2 3765
63   -#define CONFIG_MACH_TYPE MACH_TYPE_TRATS2
64   -
65   -#define CONFIG_DISPLAY_CPUINFO
66   -
67 41 #include <linux/sizes.h>
68 42 /* Size of malloc() pool */
69 43 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
70 44  
71 45 /* select serial console configuration */
72 46 #define CONFIG_SERIAL2
73   -
74   -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
75   -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
76   -
77   -#define CONFIG_CMDLINE_EDITING
78   -
79 47 #define CONFIG_BAUDRATE 115200
80 48  
81   -/* It should define before config_cmd_default.h */
82   -#define CONFIG_SYS_NO_FLASH
  49 +/* Console configuration */
  50 +#define CONFIG_SYS_CONSOLE_INFO_QUIET
  51 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
83 52  
84   -/***********************************************************
85   - * Command definition
86   - ***********************************************************/
87   -#include <config_cmd_default.h>
  53 +#define CONFIG_BOOTARGS "Please use defined boot"
  54 +#define CONFIG_BOOTCOMMAND "run mmcboot"
  55 +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
88 56  
89   -#undef CONFIG_CMD_ECHO
90   -#undef CONFIG_CMD_FPGA
91   -#undef CONFIG_CMD_FLASH
92   -#undef CONFIG_CMD_IMLS
93   -#undef CONFIG_CMD_NAND
94   -#undef CONFIG_CMD_MISC
95   -#undef CONFIG_CMD_NFS
96   -#undef CONFIG_CMD_SOURCE
97   -#undef CONFIG_CMD_XIMG
98   -#define CONFIG_CMD_CACHE
99   -#define CONFIG_CMD_I2C
100   -#define CONFIG_CMD_MMC
101   -#define CONFIG_CMD_DFU
102   -#define CONFIG_CMD_GPT
103   -#define CONFIG_CMD_PMIC
  57 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
  58 + - GENERATED_GBL_DATA_SIZE)
104 59  
105   -#define CONFIG_BOOTDELAY 3
106   -#define CONFIG_ZERO_BOOTDELAY_CHECK
  60 +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
107 61  
108   -#define CONFIG_CMD_FAT
109   -#define CONFIG_FAT_WRITE
  62 +#define CONFIG_SYS_MONITOR_BASE 0x00000000
110 63  
111   -/* EXT4 */
112   -#define CONFIG_CMD_EXT4
113   -#define CONFIG_CMD_EXT4_WRITE
  64 +#define CONFIG_ENV_IS_IN_MMC
  65 +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
  66 +#define CONFIG_ENV_SIZE 4096
  67 +#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
114 68  
115   -/* USB Composite download gadget - g_dnl */
116   -#define CONFIG_USBDOWNLOAD_GADGET
117   -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
118   -#define DFU_DEFAULT_POLL_TIMEOUT 300
119   -#define CONFIG_DFU_FUNCTION
120   -#define CONFIG_DFU_MMC
121   -
122   -/* TIZEN THOR downloader support */
123   -#define CONFIG_CMD_THOR_DOWNLOAD
124   -#define CONFIG_THOR_FUNCTION
125   -
126   -/* USB Samsung's IDs */
127   -#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
128   -#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
129   -#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
130   -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
131   -#define CONFIG_G_DNL_MANUFACTURER "Samsung"
132   -
133   -/* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */
134   -#undef CONFIG_CMD_NET
135   -
136   -/* MMC */
137   -#define CONFIG_GENERIC_MMC
138   -#define CONFIG_MMC
139   -#define CONFIG_S5P_SDHCI
140   -#define CONFIG_SDHCI
141   -#define CONFIG_MMC_SDMA
142   -#define CONFIG_MMC_DEFAULT_DEV 0
143   -
144   -/* PWM */
145   -#define CONFIG_PWM
146   -
147   -#define CONFIG_BOOTARGS "Please use defined boot"
148   -#define CONFIG_BOOTCOMMAND "run mmcboot"
149   -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
150   -
151 69 #define CONFIG_ENV_OVERWRITE
152   -#define CONFIG_SYS_CONSOLE_INFO_QUIET
153   -#define CONFIG_SYS_CONSOLE_IS_IN_ENV
154 70  
155 71 #define CONFIG_ENV_VARS_UBOOT_CONFIG
156 72 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
157 73  
... ... @@ -246,49 +162,11 @@
246 162 "setenv spl_addr_tmp;\0" \
247 163 "fdtaddr=40800000\0" \
248 164  
249   -/*
250   - * Miscellaneous configurable options
251   - */
252   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
253   -#define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
254   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
255   -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
256   -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
257   -
258   -/* Boot Argument Buffer Size */
259   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
260   -
261   -/* memtest works on */
262   -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
263   -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
264   -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
265   -
266   -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
267   - - GENERATED_GBL_DATA_SIZE)
268   -
269   -/* valid baudrates */
270   -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
271   -
272   -#define CONFIG_SYS_MONITOR_BASE 0x00000000
273   -
274   -/*-----------------------------------------------------------------------
275   - * FLASH and environment organization
276   - */
277   -
278   -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
279   -
280   -#define CONFIG_ENV_IS_IN_MMC
281   -#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
282   -#define CONFIG_ENV_SIZE 4096
283   -#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
284   -#define CONFIG_EFI_PARTITION
285   -#define CONFIG_PARTITION_UUIDS
286   -
287   -#define CONFIG_BOARD_EARLY_INIT_F
288   -
289 165 /* I2C */
290 166 #include <asm/arch/gpio.h>
291 167  
  168 +#define CONFIG_CMD_I2C
  169 +
292 170 #define CONFIG_SYS_I2C
293 171 #define CONFIG_SYS_I2C_S3C24X0
294 172 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
... ... @@ -318,11 +196,6 @@
318 196 #define CONFIG_POWER_MUIC_MAX77693
319 197 #define CONFIG_POWER_FG_MAX77693
320 198 #define CONFIG_POWER_BATTERY_TRATS2
321   -#define CONFIG_USB_GADGET
322   -#define CONFIG_USB_GADGET_S3C_UDC_OTG
323   -#define CONFIG_USB_GADGET_DUALSPEED
324   -#define CONFIG_USB_GADGET_VBUS_DRAW 2
325   -#define CONFIG_USB_CABLE_CHECK
326 199  
327 200 /* Common misc for Samsung */
328 201 #define CONFIG_MISC_COMMON
... ... @@ -362,11 +235,8 @@
362 235 #define CONFIG_VIDEO_BMP_GZIP
363 236 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
364 237  
365   -#define CONFIG_CMD_USB_MASS_STORAGE
366   -#define CONFIG_USB_GADGET_MASS_STORAGE
367   -
368   -/* Pass open firmware flat tree */
369   -#define CONFIG_OF_LIBFDT 1
  238 +#define LCD_XRES 720
  239 +#define LCD_YRES 1280
370 240  
371 241 #endif /* __CONFIG_H */