ARM: remove broken "sbc2410x" board

Signed-off-by: Wolfgang Denk <wd@denx.de>

ARM: remove broken "sbc2410x" board
Signed-off-by: Wolfgang Denk <wd@denx.de>
Wolfgang Denk · Albert ARIBAUD
1 parent 6ea2405489
Showing 9 changed files with 1 additions and 1085 deletions Side-by-side Diff
MAKEALL
board/sbc2410x/Makefile
board/sbc2410x/config.mk
board/sbc2410x/flash.c
board/sbc2410x/lowlevel_init.S
board/sbc2410x/sbc2410x.c
boards.cfg
doc/README.scrapyard
include/configs/sbc2410x.h
@@ -338,7 +338,6 @@
 	openrd_ultimate		\
 	portl2			\
 	rd6281a			\
-	sbc2410x		\
 	scb9328			\
 	sheevaplug		\
 	smdk2400		\
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	:= sbc2410x.o flash.o
-SOBJS	:= lowlevel_init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
-#
-# see http://www.samsung.com/ for more information on SAMSUNG
-#
-
-#
-# SMDK2410 has 1 bank of 64 MB DRAM
-#
-# 3000'0000 to 3400'0000
-#
-# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
-# optionally with a ramdisk at 3080'0000
-#
-# we load ourself to 33F8'0000
-#
-# download area is 3300'0000
-
-CONFIG_SYS_TEXT_BASE = 0x33F80000
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-ulong myflush (void);
-
-#define FLASH_BANK_SIZE	PHYS_FLASH_SIZE
-#define MAIN_SECT_SIZE  0x10000	/* 64 KB */
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-#define CMD_READ_ARRAY		0x000000F0
-#define CMD_UNLOCK1		0x000000AA
-#define CMD_UNLOCK2		0x00000055
-#define CMD_ERASE_SETUP		0x00000080
-#define CMD_ERASE_CONFIRM	0x00000030
-#define CMD_PROGRAM		0x000000A0
-#define CMD_UNLOCK_BYPASS	0x00000020
-
-#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1)))
-#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1)))
-
-#define BIT_ERASE_DONE		0x00000080
-#define BIT_RDY_MASK		0x00000080
-#define BIT_PROGRAM_ERROR	0x00000020
-#define BIT_TIMEOUT		0x80000000	/* our flag */
-
-#define READY 1
-#define ERR   2
-#define TMO   4
-
-/*-----------------------------------------------------------------------
- */
-
-ulong flash_init (void)
-{
-	int i, j;
-	ulong size = 0;
-
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		ulong flashbase = 0;
-
-		flash_info[i].flash_id =
-#if defined(CONFIG_AMD_LV400)
-			(AMD_MANUFACT & FLASH_VENDMASK) |
-			(AMD_ID_LV400B & FLASH_TYPEMASK);
-#elif defined(CONFIG_AMD_LV800)
-			(AMD_MANUFACT & FLASH_VENDMASK) |
-			(AMD_ID_LV800B & FLASH_TYPEMASK);
-#else
-#error "Unknown flash configured"
-#endif
-			flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
-		if (i == 0)
-			flashbase = PHYS_FLASH_1;
-		else
-			panic ("configured too many flash banks!\n");
-		for (j = 0; j < flash_info[i].sector_count; j++) {
-			if (j <= 3) {
-				/* 1st one is 16 KB */
-				if (j == 0) {
-					flash_info[i].start[j] =
-						flashbase + 0;
-				}
-
-				/* 2nd and 3rd are both 8 KB */
-				if ((j == 1) || (j == 2)) {
-					flash_info[i].start[j] =
-						flashbase + 0x4000 + (j -
-								      1) *
-						0x2000;
-				}
-
-				/* 4th 32 KB */
-				if (j == 3) {
-					flash_info[i].start[j] =
-						flashbase + 0x8000;
-				}
-			} else {
-				flash_info[i].start[j] =
-					flashbase + (j - 3) * MAIN_SECT_SIZE;
-			}
-		}
-		size += flash_info[i].size;
-	}
-
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_FLASH_BASE,
-		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
-		       &flash_info[0]);
-
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR,
-		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case (AMD_MANUFACT & FLASH_VENDMASK):
-		printf ("AMD: ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case (AMD_ID_LV400B & FLASH_TYPEMASK):
-		printf ("1x Amd29LV400BB (4Mbit)\n");
-		break;
-	case (AMD_ID_LV800B & FLASH_TYPEMASK):
-		printf ("1x Amd29LV800BB (8Mbit)\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		goto Done;
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; i++) {
-		if ((i % 5) == 0) {
-			printf ("\n   ");
-		}
-		printf (" %08lX%s", info->start[i],
-			info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-
-      Done:;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	ushort result;
-	int iflag, cflag, prot, sect;
-	int rc = ERR_OK;
-	int chip;
-	ulong start;
-
-	/* first look for protection bits */
-
-	if (info->flash_id == FLASH_UNKNOWN)
-		return ERR_UNKNOWN_FLASH_TYPE;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		return ERR_INVAL;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) !=
-	    (AMD_MANUFACT & FLASH_VENDMASK)) {
-		return ERR_UNKNOWN_FLASH_VENDOR;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-	if (prot)
-		return ERR_PROTECTED;
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-	cflag = icache_status ();
-	icache_disable ();
-	iflag = disable_interrupts ();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
-		printf ("Erasing sector %2d ... ", sect);
-
-		/* arm simple, non interrupt dependent timer */
-		start = get_timer(0);
-
-		if (info->protect[sect] == 0) {	/* not protected */
-			vu_short *addr = (vu_short *) (info->start[sect]);
-
-			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-			MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
-
-			MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-			MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-			*addr = CMD_ERASE_CONFIRM;
-
-			/* wait until flash is ready */
-			chip = 0;
-
-			do {
-				result = *addr;
-
-				/* check timeout */
-				if (get_timer(start) >
-				    CONFIG_SYS_FLASH_ERASE_TOUT) {
-					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-					chip = TMO;
-					break;
-				}
-
-				if (!chip
-				    && (result & 0xFFFF) & BIT_ERASE_DONE)
-					chip = READY;
-
-				if (!chip
-				    && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
-					chip = ERR;
-
-			} while (!chip);
-
-			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
-
-			if (chip == ERR) {
-				rc = ERR_PROG_ERROR;
-				goto outahere;
-			}
-			if (chip == TMO) {
-				rc = ERR_TIMOUT;
-				goto outahere;
-			}
-
-			printf ("ok.\n");
-		} else {	/* it was protected */
-
-			printf ("protected!\n");
-		}
-	}
-
-	if (ctrlc ())
-		printf ("User Interrupt!\n");
-
-      outahere:
-	/* allow flash to settle - wait 10 ms */
-	udelay_masked (10000);
-
-	if (iflag)
-		enable_interrupts ();
-
-	if (cflag)
-		icache_enable ();
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash
- */
-
-static int write_hword (flash_info_t * info, ulong dest, ushort data)
-{
-	vu_short *addr = (vu_short *) dest;
-	ushort result;
-	int rc = ERR_OK;
-	int cflag, iflag;
-	int chip;
-	ulong start;
-
-	/*
-	 * Check if Flash is (sufficiently) erased
-	 */
-	result = *addr;
-	if ((result & data) != data)
-		return ERR_NOT_ERASED;
-
-
-	/*
-	 * Disable interrupts which might cause a timeout
-	 * here. Remember that our exception vectors are
-	 * at address 0 in the flash, and we don't want a
-	 * (ticker) exception to happen while the flash
-	 * chip is in programming mode.
-	 */
-	cflag = icache_status ();
-	icache_disable ();
-	iflag = disable_interrupts ();
-
-	MEM_FLASH_ADDR1 = CMD_UNLOCK1;
-	MEM_FLASH_ADDR2 = CMD_UNLOCK2;
-	MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
-	*addr = CMD_PROGRAM;
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	get_timer(start);
-
-	/* wait until flash is ready */
-	chip = 0;
-	do {
-		result = *addr;
-
-		/* check timeout */
-		if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			chip = ERR | TMO;
-			break;
-		}
-		if (!chip && ((result & 0x80) == (data & 0x80)))
-			chip = READY;
-
-		if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
-			result = *addr;
-
-			if ((result & 0x80) == (data & 0x80))
-				chip = READY;
-			else
-				chip = ERR;
-		}
-
-	} while (!chip);
-
-	*addr = CMD_READ_ARRAY;
-
-	if (chip == ERR || *addr != data)
-		rc = ERR_PROG_ERROR;
-
-	if (iflag)
-		enable_interrupts ();
-
-	if (cflag)
-		icache_enable ();
-
-	return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash.
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp;
-	int l;
-	int i, rc;
-	ushort data;
-
-	wp = (addr & ~1);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *) cp << 8);
-		}
-		for (; i < 2 && cnt > 0; ++i) {
-			data = (data >> 8) | (*src++ << 8);
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < 2; ++i, ++cp) {
-			data = (data >> 8) | (*(uchar *) cp << 8);
-		}
-
-		if ((rc = write_hword (info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 2;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 2) {
-		data = *((vu_short *) src);
-		if ((rc = write_hword (info, wp, data)) != 0) {
-			return (rc);
-		}
-		src += 2;
-		wp += 2;
-		cnt -= 2;
-	}
-
-	if (cnt == 0) {
-		return ERR_OK;
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
-		data = (data >> 8) | (*src++ << 8);
-		--cnt;
-	}
-	for (; i < 2; ++i, ++cp) {
-		data = (data >> 8) | (*(uchar *) cp << 8);
-	}
-
-	return write_hword (info, wp, data);
-}
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *                     Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the Samsung SMDK2410 by
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * Modified for the friendly-arm SBC-2410X by
- * (C) Copyright 2005
- * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-/*
- * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
- *
- * Copyright (C) 2002 Samsung Electronics SW.LEE  <hitchcar@sec.samsung.com>
- */
-
-#define BWSCON	0x48000000
-
-/* BWSCON */
-#define DW8			(0x0)
-#define DW16			(0x1)
-#define DW32			(0x2)
-#define WAIT			(0x1<<2)
-#define UBLB			(0x1<<3)
-
-#define B1_BWSCON		(DW16)
-#define B2_BWSCON		(DW16)
-#define B3_BWSCON		(DW16 + WAIT + UBLB)
-#define B4_BWSCON		(DW16)
-#define B5_BWSCON		(DW16)
-#define B6_BWSCON		(DW32)
-#define B7_BWSCON		(DW32)
-
-#define B0_Tacs			0x0
-#define B0_Tcos			0x0
-#define B0_Tacc			0x7
-#define B0_Tcoh			0x0
-#define B0_Tah			0x0
-#define B0_Tacp			0x0
-#define B0_PMC			0x0
-
-#define B1_Tacs			0x0
-#define B1_Tcos			0x0
-#define B1_Tacc			0x7
-#define B1_Tcoh			0x0
-#define B1_Tah			0x0
-#define B1_Tacp			0x0
-#define B1_PMC			0x0
-
-#define B2_Tacs			0x0
-#define B2_Tcos			0x0
-#define B2_Tacc			0x7
-#define B2_Tcoh			0x0
-#define B2_Tah			0x0
-#define B2_Tacp			0x0
-#define B2_PMC			0x0
-
-#define B3_Tacs			0xc
-#define B3_Tcos			0x7
-#define B3_Tacc			0xf
-#define B3_Tcoh			0x1
-#define B3_Tah			0x0
-#define B3_Tacp			0x0
-#define B3_PMC			0x0
-
-#define B4_Tacs			0x0
-#define B4_Tcos			0x0
-#define B4_Tacc			0x7
-#define B4_Tcoh			0x0
-#define B4_Tah			0x0
-#define B4_Tacp			0x0
-#define B4_PMC			0x0
-
-#define B5_Tacs			0xc
-#define B5_Tcos			0x7
-#define B5_Tacc			0xf
-#define B5_Tcoh			0x1
-#define B5_Tah			0x0
-#define B5_Tacp			0x0
-#define B5_PMC			0x0
-
-#define B6_MT			0x3	/* SDRAM */
-#define B6_Trcd			0x1
-#define B6_SCAN			0x1	/* 9bit */
-
-#define B7_MT			0x3	/* SDRAM */
-#define B7_Trcd			0x1	/* 3clk */
-#define B7_SCAN			0x1	/* 9bit */
-
-/* REFRESH parameter */
-#define REFEN			0x1	/* Refresh enable */
-#define TREFMD			0x0	/* CBR(CAS before RAS)/Auto refresh */
-#define Trp			0x0	/* 2clk */
-#define Trc			0x3	/* 7clk */
-#define Tchr			0x2	/* 3clk */
-#define REFCNT			0x0459
-/**************************************/
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE
-
-.globl lowlevel_init
-lowlevel_init:
-	/* memory control configuration */
-	/* make r0 relative the current location so that it */
-	/* reads SMRDATA out of FLASH rather than memory ! */
-	ldr     r0, =SMRDATA
-	ldr	r1, _TEXT_BASE
-	sub	r0, r0, r1
-	ldr	r1, =BWSCON	/* Bus Width Status Controller */
-	add     r2, r0, #13*4
-0:
-	ldr     r3, [r0], #4
-	str     r3, [r1], #4
-	cmp     r2, r0
-	bne     0b
-
-	/* everything is fine now */
-	mov	pc, lr
-
-	.ltorg
-/* the literal pools origin */
-
-SMRDATA:
-    .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
-    .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
-    .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
-    .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
-    .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
-    .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
-    .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
-    .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
-    .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
-    .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
-    .word 0xb2
-    .word 0x30
-    .word 0x30
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2005
- * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/arch/s3c24x0_cpu.h>
-
-#if defined(CONFIG_CMD_NAND)
-#include <linux/mtd/nand.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define FCLK_SPEED 1
-
-#if FCLK_SPEED==0		/* Fout = 203MHz, Fin = 12MHz for Audio */
-#define M_MDIV	0xC3
-#define M_PDIV	0x4
-#define M_SDIV	0x1
-#elif FCLK_SPEED==1		/* Fout = 202.8MHz */
-#define M_MDIV	0x5c
-#define M_PDIV	0x4
-#define M_SDIV	0x0
-#endif
-
-#define USB_CLOCK 1
-
-#if USB_CLOCK==0
-#define U_M_MDIV	0xA1
-#define U_M_PDIV	0x3
-#define U_M_SDIV	0x1
-#elif USB_CLOCK==1
-#define U_M_MDIV	0x48
-#define U_M_PDIV	0x3
-#define U_M_SDIV	0x2
-#endif
-
-static inline void delay (unsigned long loops)
-{
-	__asm__ volatile ("1:\n"
-			  "subs %0, %1, #1\n"
-			  "bne 1b":"=r" (loops):"0" (loops));
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-	struct s3c24x0_clock_power * const clk_power =
-					s3c24x0_get_base_clock_power();
-	struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
-
-	/* to reduce PLL lock time, adjust the LOCKTIME register */
-	clk_power->locktime = 0xFFFFFF;
-
-	/* configure MPLL */
-	clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
-
-	/* some delay between MPLL and UPLL */
-	delay (4000);
-
-	/* configure UPLL */
-	clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
-
-	/* some delay between MPLL and UPLL */
-	delay (8000);
-
-	/* set up the I/O ports */
-	gpio->gpacon = 0x007FFFFF;
-	gpio->gpbcon = 0x00044556;
-	gpio->gpbup = 0x000007FF;
-	gpio->gpccon = 0xAAAAAAAA;
-	gpio->gpcup = 0x0000FFFF;
-	gpio->gpdcon = 0xAAAAAAAA;
-	gpio->gpdup = 0x0000FFFF;
-	gpio->gpecon = 0xAAAAAAAA;
-	gpio->gpeup = 0x0000FFFF;
-	gpio->gpfcon = 0x000055AA;
-	gpio->gpfup = 0x000000FF;
-	gpio->gpgcon = 0xFF95FF3A;
-	gpio->gpgup = 0x0000FFFF;
-	gpio->gphcon = 0x0016FAAA;
-	gpio->gphup = 0x000007FF;
-
-	gpio->extint0 = 0x22222222;
-	gpio->extint1 = 0x22222222;
-	gpio->extint2 = 0x22222222;
-
-	/* arch number of SMDK2410-Board */
-	gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x30000100;
-
-	icache_enable();
-	dcache_enable();
-
-	return 0;
-}
-
-int dram_init (void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
-}
-
-#if defined(CONFIG_CMD_NAND)
-extern ulong nand_probe(ulong physadr);
-
-static inline void NF_Reset(void)
-{
-	int i;
-
-	NF_SetCE(NFCE_LOW);
-	NF_Cmd(0xFF);		/* reset command */
-	for(i = 0; i < 10; i++);	/* tWB = 100ns. */
-	NF_WaitRB();		/* wait 200~500us; */
-	NF_SetCE(NFCE_HIGH);
-}
-
-static inline void NF_Init(void)
-{
-#if 1
-#define TACLS   0
-#define TWRPH0  3
-#define TWRPH1  0
-#else
-#define TACLS   0
-#define TWRPH0  4
-#define TWRPH1  2
-#endif
-
-	NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
-	/*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
-	/* 1  1    1     1,   1      xxx,  r xxx,   r xxx */
-	/* En 512B 4step ECCR nFCE=H tACLS   tWRPH0   tWRPH1 */
-
-	NF_Reset();
-}
-
-void nand_init(void)
-{
-	struct s3c2410_nand * const nand = s3c2410_get_base_nand();
-
-	NF_Init();
-#ifdef DEBUG
-	printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
-#endif
-	printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
-}
-#endif
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_CS8900
-	rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
-	return rc;
-}
-#endif
@@ -66,7 +66,6 @@
 scb9328                      arm         arm920t     -                   -              imx
 cm4008                       arm         arm920t     -                   -              ks8695
 cm41xx                       arm         arm920t     -                   -              ks8695
-sbc2410x                     arm         arm920t     -                   -              s3c24x0
 VCMA9                        arm         arm920t     vcma9               mpl            s3c24x0
 smdk2400                     arm         arm920t     -                   samsung        s3c24x0
 smdk2410                     arm         arm920t     -                   samsung        s3c24x0
@@ -11,6 +11,7 @@
  
 Board	Arch	CPU	removed	    Commit	last known maintainer/contact
 =============================================================================
+sbc2410x arm	arm920t	-	  2011-07-17
 netstar	arm	arm925t	-	  2011-07-17
 mx1fs2	arm	arm920t	-	  2011-07-17
 lpd7a404 arm	lh7a40x	-	  2011-07-17
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Gary Jennejohn <garyj@denx.de>
- * David Mueller <d.mueller@elsoft.ch>
- *
- * Modified for the friendly-arm SBC-2410X by
- * (C) Copyright 2005
- * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
- *
- * Configuation settings for the friendly-arm SBC-2410X board.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * If we are developing, we might want to start armboot from ram
- * so we MUST NOT initialize critical regs like mem-timing ...
- */
-#undef CONFIG_SKIP_LOWLEVEL_INIT	/* undef for developing */
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_ARM920T	1	/* This is an ARM920T Core	*/
-#define CONFIG_S3C24X0	1	/* in a SAMSUNG S3C24x0-type SoC	*/
-#define CONFIG_S3C2410	1	/* specifically a SAMSUNG S3C2410 SoC	*/
-#define CONFIG_SBC2410X	1	/* on a friendly-arm SBC-2410X Board  */
-
-/* input clock of PLL */
-#define CONFIG_SYS_CLK_FREQ	12000000/* the SBC2410X has 12MHz input clock */
-
-
-#define USE_920T_MMU		1
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-#define CONFIG_NET_MULTI
-#define CONFIG_CS8900		/* we have a CS8900 on-board */
-#define CONFIG_CS8900_BASE	0x19000300
-#define CONFIG_CS8900_BUS16	/* the Linux driver does accesses as shorts */
-
-/*
- * select serial console configuration
- */
-#define CONFIG_S3C24X0_SERIAL
-#define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SBC2410X */
-
-/************************************************************
- * RTC
- ************************************************************/
-#define	CONFIG_RTC_S3C24X0	1
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_BAUDRATE		115200
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOOTDELAY	3
-#define CONFIG_BOOTARGS		"console=ttySAC0 root=/dev/nfs " \
-		"nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv " \
-		"ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
-#define CONFIG_ETHADDR	        08:00:3e:26:0a:5b
-#define CONFIG_NETMASK          255.255.255.0
-#define CONFIG_IPADDR		192.168.0.69
-#define CONFIG_SERVERIP		192.168.0.1
-/*#define CONFIG_BOOTFILE	"elinos-lart" */
-#define CONFIG_BOOTCOMMAND	"dhcp; bootm"
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	115200		/* speed to run kgdb serial port */
-/* what's this ? it's not used anywhere */
-#define CONFIG_KGDB_SER_INDEX	1		/* which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
-#define	CONFIG_SYS_PROMPT		"[ ~ljh@GDLC ]# "	/* Monitor Command Prompt	*/
-#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
-#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x30000000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x33F00000	/* 63 MB in DRAM	*/
-
-#define	CONFIG_SYS_LOAD_ADDR		0x33000000	/* default load address	*/
-
-#define	CONFIG_SYS_HZ			1000
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/*-----------------------------------------------------------------------
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		0x30000000 /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	0x04000000 /* 64 MB */
-
-#define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
-
-#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-/* #define CONFIG_AMD_LV400	1	/\* uncomment this if you have a LV400 flash *\/ */
-
-#define CONFIG_AMD_LV800	1	/* uncomment this if you have a LV800 flash */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
-
-#ifdef CONFIG_AMD_LV800
-#define PHYS_FLASH_SIZE		0x00100000 /* 1MB */
-#define CONFIG_SYS_MAX_FLASH_SECT	(19)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
-#endif
-
-#ifdef CONFIG_AMD_LV400
-#define PHYS_FLASH_SIZE		0x00080000 /* 512KB */
-#define CONFIG_SYS_MAX_FLASH_SECT	(11)	/* max number of sectors on one chip */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
-#endif
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	(5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define	CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector */
-
-/*-----------------------------------------------------------------------
- * NAND flash settings
- */
-#if defined(CONFIG_CMD_NAND)
-#define CONFIG_NAND_S3C2410
-#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices		*/
-#endif	/* CONFIG_CMD_NAND */
-
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_TAG
-
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2   "> "
-
-#define CONFIG_CMDLINE_EDITING
-
-#ifdef CONFIG_CMDLINE_EDITING
-#undef CONFIG_AUTO_COMPLETE
-#else
-#define CONFIG_AUTO_COMPLETE
-#endif
-
-#endif	/* __CONFIG_H */
...	...	@@ -338,7 +338,6 @@
338	338	openrd_ultimate \
339	339	portl2 \
340	340	rd6281a \
341		- sbc2410x \
342	341	scb9328 \
343	342	sheevaplug \
344	343	smdk2400 \
1		-#
2		-# (C) Copyright 2000-2006
3		-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4		-#
5		-# See file CREDITS for list of people who contributed to this
6		-# project.
7		-#
8		-# This program is free software; you can redistribute it and/or
9		-# modify it under the terms of the GNU General Public License as
10		-# published by the Free Software Foundation; either version 2 of
11		-# the License, or (at your option) any later version.
12		-#
13		-# This program is distributed in the hope that it will be useful,
14		-# but WITHOUT ANY WARRANTY; without even the implied warranty of
15		-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16		-# GNU General Public License for more details.
17		-#
18		-# You should have received a copy of the GNU General Public License
19		-# along with this program; if not, write to the Free Software
20		-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21		-# MA 02111-1307 USA
22		-#
23		-
24		-include $(TOPDIR)/config.mk
25		-
26		-LIB = $(obj)lib$(BOARD).o
27		-
28		-COBJS := sbc2410x.o flash.o
29		-SOBJS := lowlevel_init.o
30		-
31		-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
32		-OBJS := $(addprefix $(obj),$(COBJS))
33		-SOBJS := $(addprefix $(obj),$(SOBJS))
34		-
35		-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
36		- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
37		-
38		-clean:
39		- rm -f $(SOBJS) $(OBJS)
40		-
41		-distclean: clean
42		- rm -f $(LIB) core *.bak $(obj).depend
43		-
44		-#########################################################################
45		-
46		-# defines $(obj).depend target
47		-include $(SRCTREE)/rules.mk
48		-
49		-sinclude $(obj).depend
50		-
51		-#########################################################################
1		-#
2		-# (C) Copyright 2002
3		-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
4		-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
5		-#
6		-# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu
7		-#
8		-# see http://www.samsung.com/ for more information on SAMSUNG
9		-#
10		-
11		-#
12		-# SMDK2410 has 1 bank of 64 MB DRAM
13		-#
14		-# 3000'0000 to 3400'0000
15		-#
16		-# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000
17		-# optionally with a ramdisk at 3080'0000
18		-#
19		-# we load ourself to 33F8'0000
20		-#
21		-# download area is 3300'0000
22		-
23		-CONFIG_SYS_TEXT_BASE = 0x33F80000
1		-/*
2		- * (C) Copyright 2002
3		- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4		- * Alex Zuepke <azu@sysgo.de>
5		- *
6		- * See file CREDITS for list of people who contributed to this
7		- * project.
8		- *
9		- * This program is free software; you can redistribute it and/or
10		- * modify it under the terms of the GNU General Public License as
11		- * published by the Free Software Foundation; either version 2 of
12		- * the License, or (at your option) any later version.
13		- *
14		- * This program is distributed in the hope that it will be useful,
15		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
16		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17		- * GNU General Public License for more details.
18		- *
19		- * You should have received a copy of the GNU General Public License
20		- * along with this program; if not, write to the Free Software
21		- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22		- * MA 02111-1307 USA
23		- */
24		-
25		-#include <common.h>
26		-
27		-ulong myflush (void);
28		-
29		-#define FLASH_BANK_SIZE PHYS_FLASH_SIZE
30		-#define MAIN_SECT_SIZE 0x10000 /* 64 KB */
31		-
32		-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
33		-
34		-#define CMD_READ_ARRAY 0x000000F0
35		-#define CMD_UNLOCK1 0x000000AA
36		-#define CMD_UNLOCK2 0x00000055
37		-#define CMD_ERASE_SETUP 0x00000080
38		-#define CMD_ERASE_CONFIRM 0x00000030
39		-#define CMD_PROGRAM 0x000000A0
40		-#define CMD_UNLOCK_BYPASS 0x00000020
41		-
42		-#define MEM_FLASH_ADDR1 ((volatile u16 )(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1)))
43		-#define MEM_FLASH_ADDR2 ((volatile u16 )(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1)))
44		-
45		-#define BIT_ERASE_DONE 0x00000080
46		-#define BIT_RDY_MASK 0x00000080
47		-#define BIT_PROGRAM_ERROR 0x00000020
48		-#define BIT_TIMEOUT 0x80000000 /* our flag */
49		-
50		-#define READY 1
51		-#define ERR 2
52		-#define TMO 4
53		-
54		-/*-----------------------------------------------------------------------
55		- */
56		-
57		-ulong flash_init (void)
58		-{
59		- int i, j;
60		- ulong size = 0;
61		-
62		- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
63		- ulong flashbase = 0;
64		-
65		- flash_info[i].flash_id =
66		-#if defined(CONFIG_AMD_LV400)
67		- (AMD_MANUFACT & FLASH_VENDMASK) \|
68		- (AMD_ID_LV400B & FLASH_TYPEMASK);
69		-#elif defined(CONFIG_AMD_LV800)
70		- (AMD_MANUFACT & FLASH_VENDMASK) \|
71		- (AMD_ID_LV800B & FLASH_TYPEMASK);
72		-#else
73		-#error "Unknown flash configured"
74		-#endif
75		- flash_info[i].size = FLASH_BANK_SIZE;
76		- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
77		- memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
78		- if (i == 0)
79		- flashbase = PHYS_FLASH_1;
80		- else
81		- panic ("configured too many flash banks!\n");
82		- for (j = 0; j < flash_info[i].sector_count; j++) {
83		- if (j <= 3) {
84		- /* 1st one is 16 KB */
85		- if (j == 0) {
86		- flash_info[i].start[j] =
87		- flashbase + 0;
88		- }
89		-
90		- /* 2nd and 3rd are both 8 KB */
91		- if ((j == 1) \|\| (j == 2)) {
92		- flash_info[i].start[j] =
93		- flashbase + 0x4000 + (j -
94		- 1) *
95		- 0x2000;
96		- }
97		-
98		- /* 4th 32 KB */
99		- if (j == 3) {
100		- flash_info[i].start[j] =
101		- flashbase + 0x8000;
102		- }
103		- } else {
104		- flash_info[i].start[j] =
105		- flashbase + (j - 3) * MAIN_SECT_SIZE;
106		- }
107		- }
108		- size += flash_info[i].size;
109		- }
110		-
111		- flash_protect (FLAG_PROTECT_SET,
112		- CONFIG_SYS_FLASH_BASE,
113		- CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
114		- &flash_info[0]);
115		-
116		- flash_protect (FLAG_PROTECT_SET,
117		- CONFIG_ENV_ADDR,
118		- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
119		-
120		- return size;
121		-}
122		-
123		-/*-----------------------------------------------------------------------
124		- */
125		-void flash_print_info (flash_info_t * info)
126		-{
127		- int i;
128		-
129		- switch (info->flash_id & FLASH_VENDMASK) {
130		- case (AMD_MANUFACT & FLASH_VENDMASK):
131		- printf ("AMD: ");
132		- break;
133		- default:
134		- printf ("Unknown Vendor ");
135		- break;
136		- }
137		-
138		- switch (info->flash_id & FLASH_TYPEMASK) {
139		- case (AMD_ID_LV400B & FLASH_TYPEMASK):
140		- printf ("1x Amd29LV400BB (4Mbit)\n");
141		- break;
142		- case (AMD_ID_LV800B & FLASH_TYPEMASK):
143		- printf ("1x Amd29LV800BB (8Mbit)\n");
144		- break;
145		- default:
146		- printf ("Unknown Chip Type\n");
147		- goto Done;
148		- break;
149		- }
150		-
151		- printf (" Size: %ld MB in %d Sectors\n",
152		- info->size >> 20, info->sector_count);
153		-
154		- printf (" Sector Start Addresses:");
155		- for (i = 0; i < info->sector_count; i++) {
156		- if ((i % 5) == 0) {
157		- printf ("\n ");
158		- }
159		- printf (" %08lX%s", info->start[i],
160		- info->protect[i] ? " (RO)" : " ");
161		- }
162		- printf ("\n");
163		-
164		- Done:;
165		-}
166		-
167		-/*-----------------------------------------------------------------------
168		- */
169		-
170		-int flash_erase (flash_info_t * info, int s_first, int s_last)
171		-{
172		- ushort result;
173		- int iflag, cflag, prot, sect;
174		- int rc = ERR_OK;
175		- int chip;
176		- ulong start;
177		-
178		- /* first look for protection bits */
179		-
180		- if (info->flash_id == FLASH_UNKNOWN)
181		- return ERR_UNKNOWN_FLASH_TYPE;
182		-
183		- if ((s_first < 0) \|\| (s_first > s_last)) {
184		- return ERR_INVAL;
185		- }
186		-
187		- if ((info->flash_id & FLASH_VENDMASK) !=
188		- (AMD_MANUFACT & FLASH_VENDMASK)) {
189		- return ERR_UNKNOWN_FLASH_VENDOR;
190		- }
191		-
192		- prot = 0;
193		- for (sect = s_first; sect <= s_last; ++sect) {
194		- if (info->protect[sect]) {
195		- prot++;
196		- }
197		- }
198		- if (prot)
199		- return ERR_PROTECTED;
200		-
201		- /*
202		- * Disable interrupts which might cause a timeout
203		- * here. Remember that our exception vectors are
204		- * at address 0 in the flash, and we don't want a
205		- * (ticker) exception to happen while the flash
206		- * chip is in programming mode.
207		- */
208		- cflag = icache_status ();
209		- icache_disable ();
210		- iflag = disable_interrupts ();
211		-
212		- /* Start erase on unprotected sectors */
213		- for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
214		- printf ("Erasing sector %2d ... ", sect);
215		-
216		- /* arm simple, non interrupt dependent timer */
217		- start = get_timer(0);
218		-
219		- if (info->protect[sect] == 0) { /* not protected */
220		- vu_short addr = (vu_short ) (info->start[sect]);
221		-
222		- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
223		- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
224		- MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
225		-
226		- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
227		- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
228		- *addr = CMD_ERASE_CONFIRM;
229		-
230		- /* wait until flash is ready */
231		- chip = 0;
232		-
233		- do {
234		- result = *addr;
235		-
236		- /* check timeout */
237		- if (get_timer(start) >
238		- CONFIG_SYS_FLASH_ERASE_TOUT) {
239		- MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
240		- chip = TMO;
241		- break;
242		- }
243		-
244		- if (!chip
245		- && (result & 0xFFFF) & BIT_ERASE_DONE)
246		- chip = READY;
247		-
248		- if (!chip
249		- && (result & 0xFFFF) & BIT_PROGRAM_ERROR)
250		- chip = ERR;
251		-
252		- } while (!chip);
253		-
254		- MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
255		-
256		- if (chip == ERR) {
257		- rc = ERR_PROG_ERROR;
258		- goto outahere;
259		- }
260		- if (chip == TMO) {
261		- rc = ERR_TIMOUT;
262		- goto outahere;
263		- }
264		-
265		- printf ("ok.\n");
266		- } else { /* it was protected */
267		-
268		- printf ("protected!\n");
269		- }
270		- }
271		-
272		- if (ctrlc ())
273		- printf ("User Interrupt!\n");
274		-
275		- outahere:
276		- /* allow flash to settle - wait 10 ms */
277		- udelay_masked (10000);
278		-
279		- if (iflag)
280		- enable_interrupts ();
281		-
282		- if (cflag)
283		- icache_enable ();
284		-
285		- return rc;
286		-}
287		-
288		-/*-----------------------------------------------------------------------
289		- * Copy memory to flash
290		- */
291		-
292		-static int write_hword (flash_info_t * info, ulong dest, ushort data)
293		-{
294		- vu_short addr = (vu_short ) dest;
295		- ushort result;
296		- int rc = ERR_OK;
297		- int cflag, iflag;
298		- int chip;
299		- ulong start;
300		-
301		- /*
302		- * Check if Flash is (sufficiently) erased
303		- */
304		- result = *addr;
305		- if ((result & data) != data)
306		- return ERR_NOT_ERASED;
307		-
308		-
309		- /*
310		- * Disable interrupts which might cause a timeout
311		- * here. Remember that our exception vectors are
312		- * at address 0 in the flash, and we don't want a
313		- * (ticker) exception to happen while the flash
314		- * chip is in programming mode.
315		- */
316		- cflag = icache_status ();
317		- icache_disable ();
318		- iflag = disable_interrupts ();
319		-
320		- MEM_FLASH_ADDR1 = CMD_UNLOCK1;
321		- MEM_FLASH_ADDR2 = CMD_UNLOCK2;
322		- MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
323		- *addr = CMD_PROGRAM;
324		- *addr = data;
325		-
326		- /* arm simple, non interrupt dependent timer */
327		- get_timer(start);
328		-
329		- /* wait until flash is ready */
330		- chip = 0;
331		- do {
332		- result = *addr;
333		-
334		- /* check timeout */
335		- if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
336		- chip = ERR \| TMO;
337		- break;
338		- }
339		- if (!chip && ((result & 0x80) == (data & 0x80)))
340		- chip = READY;
341		-
342		- if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
343		- result = *addr;
344		-
345		- if ((result & 0x80) == (data & 0x80))
346		- chip = READY;
347		- else
348		- chip = ERR;
349		- }
350		-
351		- } while (!chip);
352		-
353		- *addr = CMD_READ_ARRAY;
354		-
355		- if (chip == ERR \|\| *addr != data)
356		- rc = ERR_PROG_ERROR;
357		-
358		- if (iflag)
359		- enable_interrupts ();
360		-
361		- if (cflag)
362		- icache_enable ();
363		-
364		- return rc;
365		-}
366		-
367		-/*-----------------------------------------------------------------------
368		- * Copy memory to flash.
369		- */
370		-
371		-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
372		-{
373		- ulong cp, wp;
374		- int l;
375		- int i, rc;
376		- ushort data;
377		-
378		- wp = (addr & ~1); /* get lower word aligned address */
379		-
380		- /*
381		- * handle unaligned start bytes
382		- */
383		- if ((l = addr - wp) != 0) {
384		- data = 0;
385		- for (i = 0, cp = wp; i < l; ++i, ++cp) {
386		- data = (data >> 8) \| ((uchar ) cp << 8);
387		- }
388		- for (; i < 2 && cnt > 0; ++i) {
389		- data = (data >> 8) \| (*src++ << 8);
390		- --cnt;
391		- ++cp;
392		- }
393		- for (; cnt == 0 && i < 2; ++i, ++cp) {
394		- data = (data >> 8) \| ((uchar ) cp << 8);
395		- }
396		-
397		- if ((rc = write_hword (info, wp, data)) != 0) {
398		- return (rc);
399		- }
400		- wp += 2;
401		- }
402		-
403		- /*
404		- * handle word aligned part
405		- */
406		- while (cnt >= 2) {
407		- data = ((vu_short ) src);
408		- if ((rc = write_hword (info, wp, data)) != 0) {
409		- return (rc);
410		- }
411		- src += 2;
412		- wp += 2;
413		- cnt -= 2;
414		- }
415		-
416		- if (cnt == 0) {
417		- return ERR_OK;
418		- }
419		-
420		- /*
421		- * handle unaligned tail bytes
422		- */
423		- data = 0;
424		- for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
425		- data = (data >> 8) \| (*src++ << 8);
426		- --cnt;
427		- }
428		- for (; i < 2; ++i, ++cp) {
429		- data = (data >> 8) \| ((uchar ) cp << 8);
430		- }
431		-
432		- return write_hword (info, wp, data);
433		-}
1		-/*
2		- * Memory Setup stuff - taken from blob memsetup.S
3		- *
4		- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5		- * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6		- *
7		- * Modified for the Samsung SMDK2410 by
8		- * (C) Copyright 2002
9		- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
10		- *
11		- * Modified for the friendly-arm SBC-2410X by
12		- * (C) Copyright 2005
13		- * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
14		- *
15		- * See file CREDITS for list of people who contributed to this
16		- * project.
17		- *
18		- * This program is free software; you can redistribute it and/or
19		- * modify it under the terms of the GNU General Public License as
20		- * published by the Free Software Foundation; either version 2 of
21		- * the License, or (at your option) any later version.
22		- *
23		- * This program is distributed in the hope that it will be useful,
24		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
25		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26		- * GNU General Public License for more details.
27		- *
28		- * You should have received a copy of the GNU General Public License
29		- * along with this program; if not, write to the Free Software
30		- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31		- * MA 02111-1307 USA
32		- */
33		-
34		-#include <config.h>
35		-#include <version.h>
36		-
37		-/*
38		- * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
39		- *
40		- * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com>
41		- */
42		-
43		-#define BWSCON 0x48000000
44		-
45		-/* BWSCON */
46		-#define DW8 (0x0)
47		-#define DW16 (0x1)
48		-#define DW32 (0x2)
49		-#define WAIT (0x1<<2)
50		-#define UBLB (0x1<<3)
51		-
52		-#define B1_BWSCON (DW16)
53		-#define B2_BWSCON (DW16)
54		-#define B3_BWSCON (DW16 + WAIT + UBLB)
55		-#define B4_BWSCON (DW16)
56		-#define B5_BWSCON (DW16)
57		-#define B6_BWSCON (DW32)
58		-#define B7_BWSCON (DW32)
59		-
60		-#define B0_Tacs 0x0
61		-#define B0_Tcos 0x0
62		-#define B0_Tacc 0x7
63		-#define B0_Tcoh 0x0
64		-#define B0_Tah 0x0
65		-#define B0_Tacp 0x0
66		-#define B0_PMC 0x0
67		-
68		-#define B1_Tacs 0x0
69		-#define B1_Tcos 0x0
70		-#define B1_Tacc 0x7
71		-#define B1_Tcoh 0x0
72		-#define B1_Tah 0x0
73		-#define B1_Tacp 0x0
74		-#define B1_PMC 0x0
75		-
76		-#define B2_Tacs 0x0
77		-#define B2_Tcos 0x0
78		-#define B2_Tacc 0x7
79		-#define B2_Tcoh 0x0
80		-#define B2_Tah 0x0
81		-#define B2_Tacp 0x0
82		-#define B2_PMC 0x0
83		-
84		-#define B3_Tacs 0xc
85		-#define B3_Tcos 0x7
86		-#define B3_Tacc 0xf
87		-#define B3_Tcoh 0x1
88		-#define B3_Tah 0x0
89		-#define B3_Tacp 0x0
90		-#define B3_PMC 0x0
91		-
92		-#define B4_Tacs 0x0
93		-#define B4_Tcos 0x0
94		-#define B4_Tacc 0x7
95		-#define B4_Tcoh 0x0
96		-#define B4_Tah 0x0
97		-#define B4_Tacp 0x0
98		-#define B4_PMC 0x0
99		-
100		-#define B5_Tacs 0xc
101		-#define B5_Tcos 0x7
102		-#define B5_Tacc 0xf
103		-#define B5_Tcoh 0x1
104		-#define B5_Tah 0x0
105		-#define B5_Tacp 0x0
106		-#define B5_PMC 0x0
107		-
108		-#define B6_MT 0x3 /* SDRAM */
109		-#define B6_Trcd 0x1
110		-#define B6_SCAN 0x1 /* 9bit */
111		-
112		-#define B7_MT 0x3 /* SDRAM */
113		-#define B7_Trcd 0x1 /* 3clk */
114		-#define B7_SCAN 0x1 /* 9bit */
115		-
116		-/* REFRESH parameter */
117		-#define REFEN 0x1 /* Refresh enable */
118		-#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
119		-#define Trp 0x0 /* 2clk */
120		-#define Trc 0x3 /* 7clk */
121		-#define Tchr 0x2 /* 3clk */
122		-#define REFCNT 0x0459
123		-/**************************************/
124		-
125		-_TEXT_BASE:
126		- .word CONFIG_SYS_TEXT_BASE
127		-
128		-.globl lowlevel_init
129		-lowlevel_init:
130		- /* memory control configuration */
131		- /* make r0 relative the current location so that it */
132		- /* reads SMRDATA out of FLASH rather than memory ! */
133		- ldr r0, =SMRDATA
134		- ldr r1, _TEXT_BASE
135		- sub r0, r0, r1
136		- ldr r1, =BWSCON /* Bus Width Status Controller */
137		- add r2, r0, #13*4
138		-0:
139		- ldr r3, [r0], #4
140		- str r3, [r1], #4
141		- cmp r2, r0
142		- bne 0b
143		-
144		- /* everything is fine now */
145		- mov pc, lr
146		-
147		- .ltorg
148		-/* the literal pools origin */
149		-
150		-SMRDATA:
151		- .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
152		- .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
153		- .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
154		- .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
155		- .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
156		- .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
157		- .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
158		- .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
159		- .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
160		- .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
161		- .word 0xb2
162		- .word 0x30
163		- .word 0x30
1		-/*
2		- * (C) Copyright 2002
3		- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4		- * Marius Groeger <mgroeger@sysgo.de>
5		- *
6		- * (C) Copyright 2002
7		- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8		- *
9		- * (C) Copyright 2005
10		- * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
11		- *
12		- * See file CREDITS for list of people who contributed to this
13		- * project.
14		- *
15		- * This program is free software; you can redistribute it and/or
16		- * modify it under the terms of the GNU General Public License as
17		- * published by the Free Software Foundation; either version 2 of
18		- * the License, or (at your option) any later version.
19		- *
20		- * This program is distributed in the hope that it will be useful,
21		- * but WITHOUT ANY WARRANTY; without even the implied warranty of
22		- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23		- * GNU General Public License for more details.
24		- *
25		- * You should have received a copy of the GNU General Public License
26		- * along with this program; if not, write to the Free Software
27		- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28		- * MA 02111-1307 USA
29		- */
30		-
31		-#include <common.h>
32		-#include <netdev.h>
33		-#include <asm/arch/s3c24x0_cpu.h>
34		-
35		-#if defined(CONFIG_CMD_NAND)
36		-#include <linux/mtd/nand.h>
37		-#endif
38		-
39		-DECLARE_GLOBAL_DATA_PTR;
40		-
41		-#define FCLK_SPEED 1
42		-
43		-#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
44		-#define M_MDIV 0xC3
45		-#define M_PDIV 0x4
46		-#define M_SDIV 0x1
47		-#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
48		-#define M_MDIV 0x5c
49		-#define M_PDIV 0x4
50		-#define M_SDIV 0x0
51		-#endif
52		-
53		-#define USB_CLOCK 1
54		-
55		-#if USB_CLOCK==0
56		-#define U_M_MDIV 0xA1
57		-#define U_M_PDIV 0x3
58		-#define U_M_SDIV 0x1
59		-#elif USB_CLOCK==1
60		-#define U_M_MDIV 0x48
61		-#define U_M_PDIV 0x3
62		-#define U_M_SDIV 0x2
63		-#endif
64		-
65		-static inline void delay (unsigned long loops)
66		-{
67		- __asm__ volatile ("1:\n"
68		- "subs %0, %1, #1\n"
69		- "bne 1b":"=r" (loops):"0" (loops));
70		-}
71		-
72		-/*
73		- * Miscellaneous platform dependent initialisations
74		- */
75		-
76		-int board_init (void)
77		-{
78		- struct s3c24x0_clock_power * const clk_power =
79		- s3c24x0_get_base_clock_power();
80		- struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
81		-
82		- /* to reduce PLL lock time, adjust the LOCKTIME register */
83		- clk_power->locktime = 0xFFFFFF;
84		-
85		- /* configure MPLL */
86		- clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
87		-
88		- /* some delay between MPLL and UPLL */
89		- delay (4000);
90		-
91		- /* configure UPLL */
92		- clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
93		-
94		- /* some delay between MPLL and UPLL */
95		- delay (8000);
96		-
97		- /* set up the I/O ports */
98		- gpio->gpacon = 0x007FFFFF;
99		- gpio->gpbcon = 0x00044556;
100		- gpio->gpbup = 0x000007FF;
101		- gpio->gpccon = 0xAAAAAAAA;
102		- gpio->gpcup = 0x0000FFFF;
103		- gpio->gpdcon = 0xAAAAAAAA;
104		- gpio->gpdup = 0x0000FFFF;
105		- gpio->gpecon = 0xAAAAAAAA;
106		- gpio->gpeup = 0x0000FFFF;
107		- gpio->gpfcon = 0x000055AA;
108		- gpio->gpfup = 0x000000FF;
109		- gpio->gpgcon = 0xFF95FF3A;
110		- gpio->gpgup = 0x0000FFFF;
111		- gpio->gphcon = 0x0016FAAA;
112		- gpio->gphup = 0x000007FF;
113		-
114		- gpio->extint0 = 0x22222222;
115		- gpio->extint1 = 0x22222222;
116		- gpio->extint2 = 0x22222222;
117		-
118		- /* arch number of SMDK2410-Board */
119		- gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
120		-
121		- /* adress of boot parameters */
122		- gd->bd->bi_boot_params = 0x30000100;
123		-
124		- icache_enable();
125		- dcache_enable();
126		-
127		- return 0;
128		-}
129		-
130		-int dram_init (void)
131		-{
132		- gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
133		- gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
134		-
135		- return 0;
136		-}
137		-
138		-#if defined(CONFIG_CMD_NAND)
139		-extern ulong nand_probe(ulong physadr);
140		-
141		-static inline void NF_Reset(void)
142		-{
143		- int i;
144		-
145		- NF_SetCE(NFCE_LOW);
146		- NF_Cmd(0xFF); /* reset command */
147		- for(i = 0; i < 10; i++); /* tWB = 100ns. */
148		- NF_WaitRB(); /* wait 200~500us; */
149		- NF_SetCE(NFCE_HIGH);
150		-}
151		-
152		-static inline void NF_Init(void)
153		-{
154		-#if 1
155		-#define TACLS 0
156		-#define TWRPH0 3
157		-#define TWRPH1 0
158		-#else
159		-#define TACLS 0
160		-#define TWRPH0 4
161		-#define TWRPH1 2
162		-#endif
163		-
164		- NF_Conf((1<<15)\|(0<<14)\|(0<<13)\|(1<<12)\|(1<<11)\|(TACLS<<8)\|(TWRPH0<<4)\|(TWRPH1<<0));
165		- /nand->NFCONF = (1<<15)\|(1<<14)\|(1<<13)\|(1<<12)\|(1<<11)\|(TACLS<<8)\|(TWRPH0<<4)\|(TWRPH1<<0); /
166		- /* 1 1 1 1, 1 xxx, r xxx, r xxx */
167		- /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */
168		-
169		- NF_Reset();
170		-}
171		-
172		-void nand_init(void)
173		-{
174		- struct s3c2410_nand * const nand = s3c2410_get_base_nand();
175		-
176		- NF_Init();
177		-#ifdef DEBUG
178		- printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
179		-#endif
180		- printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
181		-}
182		-#endif
183		-
184		-#ifdef CONFIG_CMD_NET
185		-int board_eth_init(bd_t *bis)
186		-{
187		- int rc = 0;
188		-#ifdef CONFIG_CS8900
189		- rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
190		-#endif
191		- return rc;
192		-}
193		-#endif
...	...	@@ -66,7 +66,6 @@
66	66	scb9328 arm arm920t - - imx
67	67	cm4008 arm arm920t - - ks8695
68	68	cm41xx arm arm920t - - ks8695
69		-sbc2410x arm arm920t - - s3c24x0
70	69	VCMA9 arm arm920t vcma9 mpl s3c24x0
71	70	smdk2400 arm arm920t - samsung s3c24x0
72	71	smdk2410 arm arm920t - samsung s3c24x0
...	...	@@ -11,6 +11,7 @@
11	11
12	12	Board Arch CPU removed Commit last known maintainer/contact
13	13	=============================================================================
	14	+sbc2410x arm arm920t - 2011-07-17
14	15	netstar arm arm925t - 2011-07-17
15	16	mx1fs2 arm arm920t - 2011-07-17
16	17	lpd7a404 arm lh7a40x - 2011-07-17