Eric Lee / smarc-uboot

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Commit 6ea24054897b5061efd9888989e6776b60d372af

Authored by Wolfgang Denk
Committed by Albert ARIBAUD
1 parent 69624195a3
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: remove broken "netstar" board 

Signed-off-by: Wolfgang Denk <wd@denx.de>

Showing 13 changed files with 1 additions and 1316 deletions Side-by-side Diff

... ... @@ -326,7 +326,6 @@
326 326 magnesium \
327 327 mv88f6281gtw_ge \
328 328 mx1ads \
329   - netstar \
330 329 nhk8815 \
331 330 nhk8815_onenand \
332 331 omap1510inn \
... ... @@ -932,7 +932,6 @@
932 932 $(obj)tools/ncb $(obj)tools/ubsha1
933 933 @rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \
934 934 $(obj)board/matrix_vision/*/bootscript.img \
935   - $(obj)board/netstar/{eeprom,crcek,crcit,*.srec,*.bin} \
936 935 $(obj)board/voiceblue/eeprom \
937 936 $(obj)u-boot.lds \
938 937 $(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \
board/netstar/Makefile
View file @ 6ea2405
1   -#
2   -# (C) Copyright 2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# (C) Copyright 2005
6   -# Ladislav Michl, 2N Telekomunikace, michl@2n.cz
7   -#
8   -# See file CREDITS for list of people who contributed to this
9   -# project.
10   -#
11   -# This program is free software; you can redistribute it and/or
12   -# modify it under the terms of the GNU General Public License as
13   -# published by the Free Software Foundation; either version 2 of
14   -# the License, or (at your option) any later version.
15   -#
16   -# This program is distributed in the hope that it will be useful,
17   -# but WITHOUT ANY WARRANTY; without even the implied warranty of
18   -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19   -# GNU General Public License for more details.
20   -#
21   -# You should have received a copy of the GNU General Public License
22   -# along with this program; if not, write to the Free Software
23   -# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24   -# MA 02111-1307 USA
25   -#
26   -
27   -include $(TOPDIR)/config.mk
28   -
29   -LIB = $(obj)lib$(BOARD).o
30   -
31   -COBJS := netstar.o
32   -SOBJS := setup.o
33   -
34   -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
35   -OBJS := $(addprefix $(obj),$(COBJS))
36   -SOBJS := $(addprefix $(obj),$(SOBJS))
37   -
38   -LOAD_ADDR = 0x10400000
39   -
40   -#########################################################################
41   -
42   -all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \
43   - $(obj)crcek.srec $(obj)crcek.bin $(obj)crcit
44   -
45   -$(LIB): $(OBJS) $(SOBJS)
46   - $(call cmd_link_o_target, $^)
47   -
48   -$(obj)eeprom_start.o:
49   - echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ -
50   -
51   -$(obj)eeprom: $(obj)eeprom_start.o $(obj)eeprom.o
52   - $(LD) -Ttext $(LOAD_ADDR) -e eeprom -o $@ $^ \
53   - -L$(obj)../../examples/standalone -lstubs \
54   - $(PLATFORM_LIBS)
55   -
56   -$(obj)eeprom.srec: $(obj)eeprom
57   - $(OBJCOPY) -S -O srec $(<:.o=) $@
58   -
59   -$(obj)eeprom.bin: $(obj)eeprom
60   - $(OBJCOPY) -S -O binary $< $@
61   -
62   -$(obj)crcek.srec: $(obj)crcek.o
63   - $(LD) -g -Ttext 0x00000000 -e crcek -o $(<:.o=) $^
64   - $(OBJCOPY) -S -O srec $(<:.o=) $@
65   -
66   -$(obj)crcek.bin: $(obj)crcek.srec
67   - $(OBJCOPY) -I srec -O binary $< $@
68   -
69   -$(obj)crcit: $(obj)crcit.o $(obj)crc32.o
70   - $(HOSTCC) $(HOSTCFLAGS) -o $@ $^
71   -
72   -$(obj)crcit.o: crcit.c
73   - $(HOSTCC) $(HOSTCFLAGS) -o $@ -c $<
74   -
75   -$(obj)crc32.o: $(SRCTREE)/lib/crc32.c
76   - $(HOSTCC) $(HOSTCFLAGS) -DUSE_HOSTCC -I$(TOPDIR)/include \
77   - -o $@ -c $<
78   -
79   -clean:
80   - rm -f $(SOBJS) $(OBJS) \
81   - $(obj)eeprom_start.o $(obj)eeprom.o \
82   - $(obj)eeprom $(obj)eeprom.srec $(obj)eeprom.bin \
83   - $(obj)crcek.o $(obj)crcek $(obj)crcek.srec $(obj)crcek.bin
84   -
85   -distclean: clean
86   - rm -f $(LIB) core *.bak $(obj).depend
87   -
88   -#########################################################################
89   -
90   -# defines $(obj).depend target
91   -include $(SRCTREE)/rules.mk
92   -
93   -sinclude $(obj).depend
94   -
95   -#########################################################################
board/netstar/config.mk
View file @ 6ea2405
1   -#
2   -# Linux-Kernel is expected to be at 1000'8000,
3   -# entry 1000'8000 (mem base + reserved)
4   -#
5   -# We load ourself to internal RAM at 2001'2000
6   -# Check map file when changing CONFIG_SYS_TEXT_BASE.
7   -# Everything has fit into 192kB internal SRAM!
8   -#
9   -
10   -# XXX CONFIG_SYS_TEXT_BASE = 0x20012000
11   -CONFIG_SYS_TEXT_BASE = 0x13FC0000
board/netstar/crcek.S
View file @ 6ea2405
1   -/**
2   - * (C) Copyright 2005
3   - * 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
4   - *
5   - * This program is free software; you can redistribute it and/or
6   - * modify it under the terms of the GNU General Public License
7   - * version 2.
8   - *
9   - * Image layout looks like following:
10   - * u32 - size
11   - * u32 - version
12   - * ... - data
13   - * u32 - crc32
14   - */
15   -
16   -#include <config.h>
17   -#include "crcek.h"
18   -
19   -/**
20   - * do_crc32 - calculate CRC32 of given buffer
21   - * r0 - crc
22   - * r1 - pointer to buffer
23   - * r2 - buffer len
24   - */
25   - .macro do_crc32
26   - ldr r5, FFFFFFFF
27   - eor r0, r0, r5
28   - adr r3, CRC32_TABLE
29   -1:
30   - ldrb r4, [r1], #1
31   - eor r4, r4, r0
32   - and r4, r4, #0xff
33   - ldr r4, [r3, r4, lsl#2]
34   - eor r0, r4, r0, lsr#8
35   - subs r2, r2, #0x1
36   - bne 1b
37   - eor r0, r0, r5
38   - .endm
39   -
40   - .macro crcuj, offset, size
41   - mov r0, #0
42   - ldr r1, \offset
43   - ldr r2, [r1], #4
44   - cmp r2, r0 @ no data, no problem
45   - beq 2f
46   - tst r2, #3 @ unaligned size
47   - bne 2f
48   - ldr r3, \size
49   - cmp r2, r3 @ bogus size
50   - bhi 2f
51   - do_crc32
52   - ldr r1, [r1]
53   -2:
54   - cmp r0, r1
55   - .endm
56   -
57   - .macro wait, reg
58   - mov \reg, #0x100000
59   -3:
60   - subs \reg, \reg, #0x1
61   - bne 3b
62   - .endm
63   -
64   -.text
65   -.globl crcek
66   -crcek:
67   - /* Enable I-cache */
68   - mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
69   - mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
70   - mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
71   - orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
72   - mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
73   - mov r1, #0x00
74   - mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
75   - nop
76   - nop
77   - nop
78   - nop
79   -
80   - /* Setup clocking mode */
81   - ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
82   - ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
83   - bic r1, r1, #(7 << 11) @ clear clock select
84   - orr r1, r1, #(2 << 11) @ set synchronous scalable
85   - mov r2, #0
86   -loop:
87   - cmp r2, #1 @ this loop will wait for at least 100 cycles
88   - streqh r1, [r0, #0x18] @ before issuing next request from MPU
89   - add r2, r2, #1 @ on the 1st run code is loaded into I-cache
90   - cmp r2, #16 @ and second run will set clocking mode
91   - bne loop
92   - nop
93   -
94   - /* Setup clock dividers */
95   - ldr r1, CKCTL_VAL
96   - orr r1, r1, #0x2000 @ enable DSP clock
97   - strh r1, [r0] @ setup clock divisors
98   -
99   - /* Setup DPLL to generate requested freq */
100   - ldr r0, DPLL1_BASE @ base of DPLL1 register
101   - mov r1, #0x0010 @ set PLL_ENABLE
102   - orr r1, r1, #0x2000 @ set IOB to new locking
103   - orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
104   - orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
105   - strh r1, [r0] @ write
106   -
107   -locking:
108   - ldrh r1, [r0] @ get DPLL value
109   - tst r1, #0x01
110   - beq locking @ while LOCK not set
111   -
112   - /* Enable clock */
113   - ldr r0, MPU_CLKM_BASE @ base of CLOCK unit
114   - mov r1, #(1 << 10) @ disable idle mode do not check
115   - @ nWAKEUP pin, other remain active
116   - strh r1, [r0, #0x04]
117   - ldr r1, EN_CLK_VAL
118   - strh r1, [r0, #0x08]
119   - mov r1, #0x003f @ FLASH.RP not enabled in idle and
120   - strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
121   -
122   -
123   - mov r6, #0
124   - crcuj _LOADER1_OFFSET, _LOADER_SIZE
125   - bne crc1_bad
126   - orr r6, r6, #1
127   -crc1_bad:
128   - crcuj _LOADER2_OFFSET, _LOADER_SIZE
129   - bne crc2_bad
130   - orr r6, r6, #2
131   -crc2_bad:
132   - ldr r3, _LOADER1_OFFSET
133   - ldr r4, _LOADER2_OFFSET
134   - teq r6, #3
135   - bne one_is_bad @ one of them (or both) has bad crc
136   - ldr r1, [r3, #4]
137   - ldr r2, [r4, #4]
138   - cmp r1, r2 @ boot 2nd loader if versions differ
139   - beq boot_1st
140   - b boot_2nd
141   -one_is_bad:
142   - tst r6, #1
143   - bne boot_1st
144   - tst r6, #2
145   - bne boot_2nd
146   -@ We are doomed, so let user know.
147   -hell:
148   - ldr r0, GPIO_BASE @ configure GPIO pins
149   - ldr r1, GPIO_DIRECTION
150   - strh r1, [r0, #0x08]
151   -blink_loop:
152   - mov r1, #0x08
153   - strh r1, [r0, #0x04]
154   - wait r3
155   - mov r1, #0x10
156   - strh r1, [r0, #0x04]
157   - wait r3
158   - b blink_loop
159   -boot_1st:
160   - add pc, r3, #8
161   -boot_2nd:
162   - add pc, r4, #8
163   -
164   -_LOADER_SIZE:
165   - .word LOADER_SIZE - 8 @ minus size and crc32
166   -_LOADER1_OFFSET:
167   - .word LOADER1_OFFSET
168   -_LOADER2_OFFSET:
169   - .word LOADER2_OFFSET
170   -
171   -FFFFFFFF:
172   - .word 0xffffffff
173   -CRC32_TABLE:
174   - .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419
175   - .word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4
176   - .word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07
177   - .word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de
178   - .word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856
179   - .word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9
180   - .word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4
181   - .word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b
182   - .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3
183   - .word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a
184   - .word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599
185   - .word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924
186   - .word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190
187   - .word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f
188   - .word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e
189   - .word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01
190   - .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed
191   - .word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950
192   - .word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3
193   - .word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2
194   - .word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a
195   - .word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5
196   - .word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010
197   - .word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f
198   - .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17
199   - .word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6
200   - .word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615
201   - .word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8
202   - .word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344
203   - .word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb
204   - .word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a
205   - .word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5
206   - .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1
207   - .word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c
208   - .word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef
209   - .word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236
210   - .word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe
211   - .word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31
212   - .word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c
213   - .word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713
214   - .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b
215   - .word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242
216   - .word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1
217   - .word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c
218   - .word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278
219   - .word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7
220   - .word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66
221   - .word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9
222   - .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605
223   - .word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8
224   - .word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b
225   - .word 0x2d02ef8d
226   -
227   -GPIO_BASE:
228   - .word 0xfffce000
229   -MPU_CLKM_BASE:
230   - .word 0xfffece00
231   -DPLL1_BASE:
232   - .word 0xfffecf00
233   -
234   -CKCTL_VAL:
235   - .word OMAP5910_ARM_CKCTL
236   -EN_CLK_VAL:
237   - .word OMAP5910_ARM_EN_CLK
238   -GPIO_DIRECTION:
239   - .word 0x0000ffe7
240   -
241   -.end
board/netstar/crcek.h
View file @ 6ea2405
1   -#define LOADER_SIZE (448 * 1024)
2   -#define LOADER1_OFFSET (128 * 1024)
3   -#define LOADER2_OFFSET (LOADER1_OFFSET + LOADER_SIZE)
board/netstar/crcit.c
View file @ 6ea2405
1   -/*
2   - * (C) Copyright 2005
3   - * 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or
9   - * modify it under the terms of the GNU General Public License as
10   - * published by the Free Software Foundation; either version 2 of
11   - * the License, or (at your option) any later version.
12   - *
13   - * This program is distributed in the hope that it will be useful,
14   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16   - * GNU General Public License for more details.
17   - *
18   - * You should have received a copy of the GNU General Public License
19   - * along with this program; if not, write to the Free Software
20   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21   - * MA 02111-1307 USA
22   - */
23   -
24   -#include <stdio.h>
25   -#include <stdlib.h>
26   -#include <stdint.h>
27   -#include <fcntl.h>
28   -#include <string.h>
29   -#include <unistd.h>
30   -#include <sys/types.h>
31   -#include <sys/stat.h>
32   -#include "crcek.h"
33   -
34   -extern uint32_t crc32(uint32_t, const unsigned char *, uint);
35   -
36   -static uint32_t data[LOADER_SIZE/4 + 3];
37   -
38   -static int do_crc(char *path, unsigned version)
39   -{
40   - uint32_t *p;
41   - ssize_t size;
42   - int fd;
43   -
44   - fd = open(path, O_RDONLY);
45   - if (fd == -1) {
46   - perror("Error opening file");
47   - return EXIT_FAILURE;
48   - }
49   - p = data + 2;
50   - size = read(fd, p, LOADER_SIZE + 4);
51   - if (size == -1) {
52   - perror("Error reading file");
53   - return EXIT_FAILURE;
54   - }
55   - if (size > LOADER_SIZE) {
56   - fprintf(stderr, "File too large\n");
57   - return EXIT_FAILURE;
58   - }
59   - size = (size + 3) & ~3; /* round up to 4 bytes */
60   - size += 4; /* add size of version field */
61   - data[0] = size;
62   - data[1] = version;
63   - data[size/4 + 1] = crc32(0, (unsigned char *)(data + 1), size);
64   - close(fd);
65   -
66   - if (write(STDOUT_FILENO, data, size + 4 /*size*/ + 4 /*crc*/) == -1) {
67   - perror("Error writing file");
68   - return EXIT_FAILURE;
69   - }
70   -
71   - return EXIT_SUCCESS;
72   -}
73   -
74   -int main(int argc, char * const *argv)
75   -{
76   - if (argc == 2) {
77   - return do_crc(argv[1], 0);
78   - } else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) {
79   - char *endptr, *nptr = argv[2];
80   - unsigned ver = strtoul(nptr, &endptr, 0);
81   - if (*nptr != '\0' && *endptr == '\0')
82   - return do_crc(argv[3], ver);
83   - }
84   - fprintf(stderr, "Usage: crcit [-v version] <image>\n");
85   -
86   - return EXIT_FAILURE;
87   -}
board/netstar/eeprom.c
View file @ 6ea2405
1   -/*
2   - * (C) Copyright 2005
3   - * Ladislav Michl, 2N Telekomunikace, michl@2n.cz
4   - *
5   - * See file CREDITS for list of people who contributed to this
6   - * project.
7   - *
8   - * This program is free software; you can redistribute it and/or modify
9   - * it under the terms of the GNU General Public License version 2 as
10   - * published by the Free Software Foundation.
11   - *
12   - * This program is distributed in the hope that it will be useful,
13   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
14   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15   - * GNU General Public License for more details.
16   - *
17   - * You should have received a copy of the GNU General Public License
18   - * along with this program; if not, write to the Free Software
19   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20   - * MA 02111-1307 USA
21   - *
22   - * Some code shamelessly stolen back from Robin Getz.
23   - */
24   -
25   -#include <common.h>
26   -#include <exports.h>
27   -#include <timestamp.h>
28   -#include <net.h>
29   -#include "../drivers/net/smc91111.h"
30   -
31   -static struct eth_device dev = {
32   - .iobase = CONFIG_SMC91111_BASE
33   -};
34   -
35   -static u16 read_eeprom_reg(u16 reg)
36   -{
37   - int timeout;
38   -
39   - SMC_SELECT_BANK(&dev, 2);
40   - SMC_outw(&dev, reg, PTR_REG);
41   -
42   - SMC_SELECT_BANK(&dev, 1);
43   - SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT |
44   - CTL_RELOAD, CTL_REG);
45   -
46   - timeout = 100;
47   -
48   - while ((SMC_inw(&dev, CTL_REG) & CTL_RELOAD) && --timeout)
49   - udelay(100);
50   - if (timeout == 0) {
51   - printf("Timeout reading register %02x\n", reg);
52   - return 0;
53   - }
54   -
55   - return SMC_inw(&dev, GP_REG);
56   -}
57   -
58   -static int write_eeprom_reg(u16 value, u16 reg)
59   -{
60   - int timeout;
61   -
62   - SMC_SELECT_BANK(&dev, 2);
63   - SMC_outw(&dev, reg, PTR_REG);
64   -
65   - SMC_SELECT_BANK(&dev, 1);
66   -
67   - SMC_outw(&dev, value, GP_REG);
68   - SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT |
69   - CTL_STORE, CTL_REG);
70   -
71   - timeout = 100;
72   -
73   - while ((SMC_inw(&dev, CTL_REG) & CTL_STORE) && --timeout)
74   - udelay(100);
75   - if (timeout == 0) {
76   - printf("Timeout writing register %02x\n", reg);
77   - return 0;
78   - }
79   -
80   - return 1;
81   -}
82   -
83   -static int write_data(u16 *buf, int len)
84   -{
85   - u16 reg = 0x23;
86   -
87   - while (len--)
88   - write_eeprom_reg(*buf++, reg++);
89   -
90   - return 0;
91   -}
92   -
93   -static int verify_macaddr(char *s)
94   -{
95   - u16 reg;
96   - int i, err = 0;
97   -
98   - puts("HWaddr: ");
99   - for (i = 0; i < 3; i++) {
100   - reg = read_eeprom_reg(0x20 + i);
101   - printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n');
102   - if (s)
103   - err |= reg != ((u16 *)s)[i];
104   - }
105   -
106   - return err ? 0 : 1;
107   -}
108   -
109   -static int set_mac(char *s)
110   -{
111   - int i;
112   - char *e, eaddr[6];
113   -
114   - /* turn string into mac value */
115   - for (i = 0; i < 6; i++) {
116   - eaddr[i] = simple_strtoul(s, &e, 16);
117   - s = (*e) ? e+1 : e;
118   - }
119   -
120   - for (i = 0; i < 3; i++)
121   - write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i);
122   -
123   - return 0;
124   -}
125   -
126   -static int parse_element(char *s, unsigned char *buf, int len)
127   -{
128   - int cnt;
129   - char *p, num[3];
130   - unsigned char id;
131   -
132   - id = simple_strtoul(s, &p, 16);
133   - if (*p++ != ':')
134   - return -1;
135   - cnt = 2;
136   - num[2] = 0;
137   - for (; *p; p += 2) {
138   - if (p[1] == 0)
139   - return -2;
140   - if (cnt + 3 > len)
141   - return -3;
142   - num[0] = p[0];
143   - num[1] = p[1];
144   - buf[cnt++] = simple_strtoul(num, NULL, 16);
145   - }
146   - buf[0] = id;
147   - buf[1] = cnt - 2;
148   -
149   - return cnt;
150   -}
151   -
152   -int eeprom(int argc, char * const argv[])
153   -{
154   - int i, len, ret;
155   - unsigned char buf[58], *p;
156   -
157   - app_startup(argv);
158   - i = get_version();
159   - if (i != XF_VERSION) {
160   - printf("Using ABI version %d, but U-Boot provides %d\n",
161   - XF_VERSION, i);
162   - return 1;
163   - }
164   -
165   - if ((SMC_inw(&dev, BANK_SELECT) & 0xFF00) != 0x3300) {
166   - puts("SMSC91111 not found\n");
167   - return 2;
168   - }
169   -
170   - /* Called without parameters - print MAC address */
171   - if (argc < 2) {
172   - verify_macaddr(NULL);
173   - return 0;
174   - }
175   -
176   - /* Print help message */
177   - if (argv[1][1] == 'h') {
178   - puts("NetStar EEPROM writer\n"
179   - "Built: " U_BOOT_DATE " at " U_BOOT_TIME "\n"
180   - "Usage:\n\t<mac_address> [<element_1>] [<...>]\n");
181   - return 0;
182   - }
183   -
184   - /* Try to parse information elements */
185   - len = sizeof(buf);
186   - p = buf;
187   - for (i = 2; i < argc; i++) {
188   - ret = parse_element(argv[i], p, len);
189   - switch (ret) {
190   - case -1:
191   - printf("Element %d: malformed\n", i - 1);
192   - return 3;
193   - case -2:
194   - printf("Element %d: odd character count\n", i - 1);
195   - return 3;
196   - case -3:
197   - puts("Out of EEPROM memory\n");
198   - return 3;
199   - default:
200   - p += ret;
201   - len -= ret;
202   - }
203   - }
204   -
205   - /* First argument (MAC) is mandatory */
206   - set_mac(argv[1]);
207   - if (verify_macaddr(argv[1])) {
208   - puts("*** HWaddr does not match! ***\n");
209   - return 4;
210   - }
211   -
212   - while (len--)
213   - *p++ = 0;
214   -
215   - write_data((u16 *)buf, sizeof(buf) >> 1);
216   -
217   - return 0;
218   -}
board/netstar/netstar.c
View file @ 6ea2405
1   -/*
2   - * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
3   - *
4   - * See file CREDITS for list of people who contributed to this
5   - * project.
6   - *
7   - * This program is free software; you can redistribute it and/or
8   - * modify it under the terms of the GNU General Public License as
9   - * published by the Free Software Foundation; either version 2 of
10   - * the License, or (at your option) any later version.
11   - *
12   - * This program is distributed in the hope that it will be useful,
13   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
14   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15   - * GNU General Public License for more details.
16   - *
17   - * You should have received a copy of the GNU General Public License
18   - * along with this program; if not, write to the Free Software
19   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20   - * MA 02111-1307 USA
21   - */
22   -
23   -#include <common.h>
24   -#include <netdev.h>
25   -#include <i2c.h>
26   -#include <flash.h>
27   -#include <nand.h>
28   -
29   -#include <asm/io.h>
30   -
31   -DECLARE_GLOBAL_DATA_PTR;
32   -
33   -int board_init(void)
34   -{
35   - /* arch number of NetStar board */
36   - gd->bd->bi_arch_number = MACH_TYPE_NETSTAR;
37   -
38   - /* adress of boot parameters */
39   - gd->bd->bi_boot_params = 0x10000100;
40   -
41   - return 0;
42   -}
43   -
44   -int dram_init(void)
45   -{
46   - gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
47   - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
48   -
49   - /* Take the Ethernet controller out of reset and wait
50   - * for the EEPROM load to complete. */
51   - *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80;
52   - udelay(10); /* doesn't work before timer_init call */
53   - *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80;
54   - udelay(500);
55   -
56   - return 0;
57   -}
58   -
59   -int misc_init_r(void)
60   -{
61   -#if defined(CONFIG_RTC_DS1307)
62   - /* enable trickle charge */
63   - i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0x10, 0xaa);
64   -#endif
65   - return 0;
66   -}
67   -
68   -int board_late_init(void)
69   -{
70   - return 0;
71   -}
72   -
73   -#if defined(CONFIG_CMD_FLASH)
74   -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t * info)
75   -{
76   - if (banknum == 0) { /* AM29LV800 boot flash */
77   - info->portwidth = FLASH_CFI_16BIT;
78   - info->chipwidth = FLASH_CFI_BY16;
79   - info->interface = FLASH_CFI_X16;
80   - return 1;
81   - }
82   -
83   - return 0;
84   -}
85   -#endif
86   -
87   -#if defined(CONFIG_CMD_NAND)
88   -/*
89   - * hardware specific access to control-lines
90   - *
91   - * NAND_NCE: bit 0 - don't care
92   - * NAND_CLE: bit 1 -> bit 1 (0x0002)
93   - * NAND_ALE: bit 2 -> bit 2 (0x0004)
94   - */
95   -static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd,
96   - unsigned int ctrl)
97   -{
98   - struct nand_chip *chip = mtd->priv;
99   - unsigned long mask;
100   -
101   - if (cmd == NAND_CMD_NONE)
102   - return;
103   -
104   - mask = (ctrl & NAND_CLE) ? 0x02 : 0;
105   - if (ctrl & NAND_ALE)
106   - mask |= 0x04;
107   - writeb(cmd, (unsigned long)chip->IO_ADDR_W | mask);
108   -}
109   -
110   -int board_nand_init(struct nand_chip *nand)
111   -{
112   - nand->options = NAND_SAMSUNG_LP_OPTIONS;
113   - nand->ecc.mode = NAND_ECC_SOFT;
114   - nand->cmd_ctrl = netstar_nand_hwcontrol;
115   - nand->chip_delay = 400;
116   - return 0;
117   -}
118   -#endif
119   -
120   -#ifdef CONFIG_CMD_NET
121   -int board_eth_init(bd_t *bis)
122   -{
123   - int rc = 0;
124   -#ifdef CONFIG_SMC91111
125   - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
126   -#endif
127   - return rc;
128   -}
129   -#endif
board/netstar/setup.S
View file @ 6ea2405
1   -/*
2   - * Board specific setup info
3   - *
4   - * (C) Copyright 2004 Ales Jindra <jindra@2n.cz>
5   - * (C) Copyright 2005 Ladislav Michl <michl@2n.cz>
6   - *
7   - * See file CREDITS for list of people who contributed to this
8   - * project.
9   - *
10   - * This program is free software; you can redistribute it and/or
11   - * modify it under the terms of the GNU General Public License as
12   - * published by the Free Software Foundation; either version 2 of
13   - * the License, or (at your option) any later version.
14   - *
15   - * This program is distributed in the hope that it will be useful,
16   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
17   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18   - * GNU General Public License for more details.
19   - *
20   - * You should have received a copy of the GNU General Public License
21   - * along with this program; if not, write to the Free Software
22   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23   - * MA 02111-1307 USA
24   - */
25   -
26   -#include <config.h>
27   -#include <version.h>
28   -
29   -_TEXT_BASE:
30   - .word CONFIG_SYS_TEXT_BASE /* SDRAM load addr from config.mk */
31   -
32   -OMAP5910_LPG1_BASE: .word 0xfffbd000
33   -OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800
34   -OMAP5910_MPU_TC_BASE: .word 0xfffecc00
35   -OMAP5910_MPU_CLKM_BASE: .word 0xfffece00
36   -OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800
37   -OMAP5910_DPLL1_BASE: .word 0xfffecf00
38   -OMAP5910_GPIO_BASE: .word 0xfffce000
39   -OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800
40   -OMAP5910_MPUI_BASE: .word 0xfffec900
41   -
42   -_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL
43   -_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK
44   -
45   -OMAP5910_MPUI_CTRL: .word 0x0000ff1b
46   -
47   -VAL_EMIFS_CS0_CONFIG: .word 0x00009090
48   -VAL_EMIFS_CS1_CONFIG: .word 0x00003031
49   -VAL_EMIFS_CS2_CONFIG: .word 0x0000a0a1
50   -VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0
51   -VAL_EMIFS_DYN_WAIT: .word 0x00000000
52   -/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */
53   - /* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */
54   -
55   -#if (PHYS_SDRAM_1_SIZE == SZ_32M)
56   -VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
57   -#else
58   -VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27))
59   -#endif
60   -
61   -VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003
62   -VAL_EMIFF_MRS: .word 0x00000037
63   -
64   -/*
65   - * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator)
66   - * GPIO07 - LAN91C111 reset
67   - */
68   -GPIO_DIRECTION:
69   - .word 0x0000ff6f
70   -/*
71   - * Disable everything (green LED is connected via invertor)
72   - */
73   -GPIO_OUTPUT:
74   - .word 0x00000010
75   -
76   -MUX_CONFIG_BASE:
77   - .word 0xfffe1000
78   -
79   -MUX_CONFIG_VALUES:
80   - .align 4
81   - .word 0x00000000 @ FUNC_MUX_CTRL_0
82   - .word 0x00000000 @ FUNC_MUX_CTRL_1
83   - .word 0x00000000 @ FUNC_MUX_CTRL_2
84   - .word 0x00000000 @ FUNC_MUX_CTRL_3
85   - .word 0x00000000 @ FUNC_MUX_CTRL_4
86   - .word 0x02080480 @ FUNC_MUX_CTRL_5
87   - .word 0x0100001c @ FUNC_MUX_CTRL_6
88   - .word 0x0004800b @ FUNC_MUX_CTRL_7
89   - .word 0x10001200 @ FUNC_MUX_CTRL_8
90   - .word 0x01201012 @ FUNC_MUX_CTRL_9
91   - .word 0x02082248 @ FUNC_MUX_CTRL_A
92   - .word 0x00000248 @ FUNC_MUX_CTRL_B
93   - .word 0x12240000 @ FUNC_MUX_CTRL_C
94   - .word 0x00002000 @ FUNC_MUX_CTRL_D
95   - .word 0x00000000 @ PULL_DWN_CTRL_0
96   - .word 0x00000800 @ PULL_DWN_CTRL_1
97   - .word 0x01801000 @ PULL_DWN_CTRL_2
98   - .word 0x00000000 @ PULL_DWN_CTRL_3
99   - .word 0x00000000 @ GATE_INH_CTRL_0
100   - .word 0x00000000 @ VOLTAGE_CTRL_0
101   - .word 0x00000000 @ TEST_DBG_CTRL_0
102   - .word 0x00000006 @ MOD_CONF_CTRL_0
103   - .word 0x0000eaef @ COMP_MODE_CTRL_0
104   -
105   -MUX_CONFIG_OFFSETS:
106   - .align 1
107   - .byte 0x00 @ FUNC_MUX_CTRL_0
108   - .byte 0x04 @ FUNC_MUX_CTRL_1
109   - .byte 0x08 @ FUNC_MUX_CTRL_2
110   - .byte 0x10 @ FUNC_MUX_CTRL_3
111   - .byte 0x14 @ FUNC_MUX_CTRL_4
112   - .byte 0x18 @ FUNC_MUX_CTRL_5
113   - .byte 0x1c @ FUNC_MUX_CTRL_6
114   - .byte 0x20 @ FUNC_MUX_CTRL_7
115   - .byte 0x24 @ FUNC_MUX_CTRL_8
116   - .byte 0x28 @ FUNC_MUX_CTRL_9
117   - .byte 0x2c @ FUNC_MUX_CTRL_A
118   - .byte 0x30 @ FUNC_MUX_CTRL_B
119   - .byte 0x34 @ FUNC_MUX_CTRL_C
120   - .byte 0x38 @ FUNC_MUX_CTRL_D
121   - .byte 0x40 @ PULL_DWN_CTRL_0
122   - .byte 0x44 @ PULL_DWN_CTRL_1
123   - .byte 0x48 @ PULL_DWN_CTRL_2
124   - .byte 0x4c @ PULL_DWN_CTRL_3
125   - .byte 0x50 @ GATE_INH_CTRL_0
126   - .byte 0x60 @ VOLTAGE_CTRL_0
127   - .byte 0x70 @ TEST_DBG_CTRL_0
128   - .byte 0x80 @ MOD_CONF_CTRL_0
129   - .byte 0x0c @ COMP_MODE_CTRL_0
130   - .byte 0xff
131   -
132   -.globl lowlevel_init
133   -lowlevel_init:
134   - /* Improve performance a bit... */
135   - mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register
136   - mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register
137   - mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register
138   - orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000
139   - mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register
140   - mov r1, #0x00
141   - mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache
142   - nop
143   - nop
144   - nop
145   - nop
146   -
147   - /* Setup clocking mode */
148   - ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
149   - ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status
150   - bic r1, r1, #(7 << 11) @ clear clock select
151   - orr r1, r1, #(2 << 11) @ set synchronous scalable
152   - mov r2, #0
153   -loop:
154   - cmp r2, #1 @ this loop will wait for at least 100 cycles
155   - streqh r1, [r0, #0x18] @ before issuing next request from MPU
156   - add r2, r2, #1 @ on the 1st run code is loaded into I-cache
157   - cmp r2, #16 @ and second run will set clocking mode
158   - bne loop
159   - nop
160   -
161   - /* Setup clock dividers */
162   - ldr r1, _OMAP5910_ARM_CKCTL
163   - orr r1, r1, #0x2000 @ enable DSP clock
164   - strh r1, [r0] @ setup clock divisors
165   -
166   - /* Setup DPLL to generate requested freq */
167   - ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register
168   - mov r1, #0x0010 @ set PLL_ENABLE
169   - orr r1, r1, #0x2000 @ set IOB to new locking
170   - orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF
171   - orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF
172   - strh r1, [r0] @ write
173   -
174   -locking:
175   - ldrh r1, [r0] @ get DPLL value
176   - tst r1, #0x01
177   - beq locking @ while LOCK not set
178   -
179   - /* Enable clock */
180   - ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit
181   - mov r1, #(1 << 10) @ disable idle mode do not check
182   - @ nWAKEUP pin, other remain active
183   - strh r1, [r0, #0x04]
184   - ldr r1, _OMAP5910_ARM_EN_CLK
185   - strh r1, [r0, #0x08]
186   - mov r1, #0x003f @ FLASH.RP not enabled in idle and
187   - strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN )
188   -
189   - /* Configure 5910 pins functions to match our board. */
190   - ldr r0, MUX_CONFIG_BASE
191   - adr r1, MUX_CONFIG_VALUES
192   - adr r2, MUX_CONFIG_OFFSETS
193   -next_mux_cfg:
194   - ldrb r3, [r2], #1
195   - ldr r4, [r1], #4
196   - cmp r3, #0xff
197   - strne r4, [r0, r3]
198   - bne next_mux_cfg
199   -
200   - /* Configure GPIO pins (also disables Green LED) */
201   - ldr r0, OMAP5910_GPIO_BASE
202   - ldr r1, GPIO_OUTPUT
203   - strh r1, [r0, #0x04]
204   - ldr r1, GPIO_DIRECTION
205   - strh r1, [r0, #0x08]
206   -
207   - /* EnablePeripherals */
208   - ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit
209   - mov r1, #0x0001 @ Peripheral enable
210   - strh r1, [r0, #0x14]
211   -
212   - /* Program LED Pulse Generator */
213   - ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator
214   - mov r1, #0x7F @ Set obscure frequency in
215   - strb r1, [r0, #0x00] @ LCR
216   - mov r1, #0x01 @ Enable clock (CLK_EN) in
217   - strb r1, [r0, #0x04] @ PMR
218   -
219   - /* TIPB Lock UART1 */
220   - ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches
221   - mov r1, #1 @ ARM allocated
222   - strh r1, [r0,#0x04] @ clear IRQ line and status bits
223   - strh r1, [r0,#0x00]
224   - ldrh r1, [r0,#0x04]
225   -
226   - /* Disable watchdog */
227   - ldr r0, OMAP5910_MPU_WD_TIMER_BASE
228   - mov r1, #0xf5
229   - strh r1, [r0, #0x8]
230   - mov r1, #0xa0
231   - strh r1, [r0, #0x8]
232   -
233   - /* Enable MCLK */
234   - ldr r0, OMAP5910_ULPD_PWR_MNG_BASE
235   - mov r1, #0x6
236   - strh r1, [r0, #0x34]
237   - strh r1, [r0, #0x34]
238   -
239   - /* Setup clock divisors */
240   - ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register
241   -
242   - mov r1, #0x0010 @ set PLL_ENABLE
243   - orr r1, r1, #0x2000 @ set IOB to new locking
244   - strh r1, [r0] @ write
245   -
246   -ulocking:
247   - ldrh r1, [r0] @ get DPLL value
248   - tst r1, #1
249   - beq ulocking @ while LOCK not set
250   -
251   - /* EMIF init */
252   - ldr r0, OMAP5910_MPU_TC_BASE
253   - ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG
254   - bic r1, r1, #0x0c @ pwr down disabled, flash WP
255   - orr r1, r1, #0x01
256   - str r1, [r0, #0x0c]
257   -
258   - ldr r1, VAL_EMIFS_CS0_CONFIG
259   - str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG
260   - ldr r1, VAL_EMIFS_CS1_CONFIG
261   - str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG
262   - ldr r1, VAL_EMIFS_CS2_CONFIG
263   - str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG
264   - ldr r1, VAL_EMIFS_CS3_CONFIG
265   - str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG
266   - ldr r1, VAL_EMIFS_DYN_WAIT
267   - str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT
268   -
269   - /* Setup SDRAM */
270   - ldr r1, VAL_EMIFF_SDRAM_CONFIG
271   - str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG
272   - ldr r1, VAL_EMIFF_SDRAM_CONFIG2
273   - str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2
274   - ldr r1, VAL_EMIFF_MRS
275   - str r1, [r0, #0x24] @ EMIFF_MRS
276   - /* SDRAM needs 100us to stabilize */
277   - mov r0, #0x4000
278   -sdelay:
279   - subs r0, r0, #0x1
280   - bne sdelay
281   -
282   - /* back to arch calling code */
283   - mov pc, lr
284   -.end
... ... @@ -70,7 +70,6 @@
70 70 VCMA9 arm arm920t vcma9 mpl s3c24x0
71 71 smdk2400 arm arm920t - samsung s3c24x0
72 72 smdk2410 arm arm920t - samsung s3c24x0
73   -netstar arm arm925t
74 73 voiceblue arm arm925t
75 74 omap1510inn arm arm925t - ti
76 75 integratorap_cm926ejs arm arm926ejs integrator armltd - integratorap
doc/README.scrapyard
Diff comments   View file @ 6ea2405
... ... @@ -11,6 +11,7 @@
11 11  
12 12 Board Arch CPU removed Commit last known maintainer/contact
13 13 =============================================================================
  14 +netstar arm arm925t - 2011-07-17
14 15 mx1fs2 arm arm920t - 2011-07-17
15 16 lpd7a404 arm lh7a40x - 2011-07-17
16 17 edb9301 arm arm920t - 2011-07-17
include/configs/netstar.h
View file @ 6ea2405
1   -/*
2   - * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
3   - *
4   - * Configuation settings for the TI OMAP NetStar board.
5   - *
6   - * See file CREDITS for list of people who contributed to this
7   - * project.
8   - *
9   - * This program is free software; you can redistribute it and/or
10   - * modify it under the terms of the GNU General Public License as
11   - * published by the Free Software Foundation; either version 2 of
12   - * the License, or (at your option) any later version.
13   - *
14   - * This program is distributed in the hope that it will be useful,
15   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
16   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17   - * GNU General Public License for more details.
18   - *
19   - * You should have received a copy of the GNU General Public License
20   - * along with this program; if not, write to the Free Software
21   - * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22   - * MA 02111-1307 USA
23   - */
24   -
25   -#ifndef __CONFIG_H
26   -#define __CONFIG_H
27   -
28   -#include <configs/omap1510.h>
29   -
30   -#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
31   -#define CONFIG_OMAP 1 /* in a TI OMAP core */
32   -#define CONFIG_OMAP1510 1 /* which is in a 5910 */
33   -
34   -/* Input clock of PLL */
35   -#define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz */
36   -#define CONFIG_XTAL_FREQ 12000000 /* 12MHz */
37   -
38   -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39   -
40   -#define CONFIG_MISC_INIT_R /* There is nothing to really init */
41   -#define BOARD_LATE_INIT /* but we flash the LEDs here */
42   -
43   -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
44   -#define CONFIG_SETUP_MEMORY_TAGS 1
45   -#define CONFIG_INITRD_TAG 1
46   -
47   -#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
48   -#define CONFIG_SYS_CONSOLE_INFO_QUIET
49   -
50   -/*
51   - * Physical Memory Map
52   - */
53   -#define CONFIG_NR_DRAM_BANKS 1
54   -#define PHYS_SDRAM_1 0x10000000
55   -#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
56   -#define PHYS_FLASH_1 0x00000000
57   -
58   -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
59   -#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
60   -
61   -/*
62   - * Environment settings
63   - */
64   -#define CONFIG_ENV_IS_IN_FLASH
65   -#define CONFIG_ENV_ADDR 0x4000
66   -#define CONFIG_ENV_SIZE (8 * 1024)
67   -#define CONFIG_ENV_SECT_SIZE (8 * 1024)
68   -#define CONFIG_ENV_ADDR_REDUND 0x6000
69   -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
70   -#define CONFIG_ENV_OVERWRITE
71   -
72   -/*
73   - * Size of malloc() pool
74   - */
75   -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
76   -
77   -/*
78   - * The stack size is set up in start.S using the settings below
79   - */
80   -#define CONFIG_STACKSIZE (1 * 1024 * 1024)
81   -
82   -/*
83   - * Hardware drivers
84   - */
85   -#define CONFIG_SYS_NS16550
86   -#define CONFIG_SYS_NS16550_SERIAL
87   -#define CONFIG_SYS_NS16550_REG_SIZE (-4)
88   -#define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ)
89   -#define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE
90   -
91   -#define CONFIG_NET_MULTI
92   -#define CONFIG_SMC91111
93   -#define CONFIG_SMC91111_BASE 0x04000300
94   -
95   -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
96   -#define CONFIG_SYS_MAX_FLASH_BANKS 1
97   -#define CONFIG_SYS_MAX_FLASH_SECT 19
98   -
99   -#define CONFIG_SYS_FLASH_CFI
100   -#define CONFIG_FLASH_CFI_DRIVER
101   -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
102   -#define CONFIG_FLASH_CFI_LEGACY
103   -#define CONFIG_SYS_FLASH_LEGACY_512Kx16
104   -
105   -#define CONFIG_SYS_MAX_NAND_DEVICE 1
106   -#define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23)
107   -#define NAND_ALLOW_ERASE_ALL 1
108   -
109   -#define CONFIG_HARD_I2C
110   -#define CONFIG_SYS_I2C_SPEED 100000
111   -#define CONFIG_SYS_I2C_SLAVE 1
112   -#define CONFIG_DRIVER_OMAP1510_I2C
113   -
114   -#define CONFIG_RTC_DS1307
115   -#define CONFIG_SYS_I2C_RTC_ADDR 0x68
116   -
117   -
118   -#define CONFIG_CONS_INDEX 1
119   -#define CONFIG_BAUDRATE 115200
120   -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
121   -
122   -/*
123   - * Partitions (mtdparts command line support)
124   - */
125   -#define CONFIG_CMD_MTDPARTS
126   -#define CONFIG_MTD_DEVICE
127   -#define CONFIG_FLASH_CFI_MTD
128   -#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=gen_nand.0"
129   -#define MTDPARTS_DEFAULT "mtdparts=" \
130   - "physmap-flash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \
131   - "gen_nand.0:4M(kernel0),40M(rootfs0),4M(kernel1),40M(rootfs1),-(data)"
132   -
133   -/*
134   - * Command line configuration
135   - */
136   -#define CONFIG_CMD_BDI
137   -#define CONFIG_CMD_BOOTD
138   -#define CONFIG_CMD_DATE
139   -#define CONFIG_CMD_DHCP
140   -#define CONFIG_CMD_SAVEENV
141   -#define CONFIG_CMD_FLASH
142   -#define CONFIG_CMD_IMI
143   -#define CONFIG_CMD_LOADB
144   -#define CONFIG_CMD_MEMORY
145   -#define CONFIG_CMD_NAND
146   -#define CONFIG_CMD_NET
147   -#define CONFIG_CMD_PING
148   -#define CONFIG_CMD_RUN
149   -
150   -/*
151   - * BOOTP options
152   - */
153   -#define CONFIG_BOOTP_SUBNETMASK
154   -#define CONFIG_BOOTP_GATEWAY
155   -#define CONFIG_BOOTP_HOSTNAME
156   -#define CONFIG_BOOTP_BOOTPATH
157   -
158   -#define CONFIG_LOOPW
159   -
160   -#define CONFIG_BOOTDELAY 3
161   -#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
162   -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
163   -#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */
164   -#define CONFIG_BOOTCOMMAND "run fboot"
165   -#define CONFIG_PREBOOT "run setup"
166   -#define CONFIG_EXTRA_ENV_SETTINGS \
167   - "autostart=yes\0" \
168   - "ospart=0\0" \
169   - "setup=setenv bootargs console=ttyS0,$baudrate $mtdparts\0" \
170   - "setpart=" \
171   - "if test -n $swapos; then " \
172   - "setenv swapos; saveenv; " \
173   - "if test $ospart -eq 0; then " \
174   - "setenv ospart 1; " \
175   - "else " \
176   - "setenv ospart 0; " \
177   - "fi; " \
178   - "fi\0" \
179   - "nfsargs=setenv bootargs $bootargs " \
180   - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
181   - "nfsroot=$rootpath root=/dev/nfs\0" \
182   - "flashargs=run setpart;setenv bootargs $bootargs " \
183   - "root=mtd:rootfs$ospart ro " \
184   - "rootfstype=jffs2\0" \
185   - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
186   - "fboot=run flashargs;nboot kernel$ospart\0" \
187   - "nboot=bootp;run nfsargs;tftp\0"
188   -
189   -#if 0 /* feel free to disable for development */
190   -#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
191   -#define CONFIG_AUTOBOOT_PROMPT \
192   - "\nNetStar PBX - boot in %d secs...\n", bootdelay
193   -#define CONFIG_AUTOBOOT_DELAY_STR "." /* 1st "password" */
194   -#endif
195   -
196   -/*
197   - * Miscellaneous configurable options
198   - */
199   -#define CONFIG_SYS_LONGHELP
200   -#define CONFIG_SYS_PROMPT "# "
201   -#define CONFIG_SYS_CBSIZE 256
202   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
203   - sizeof(CONFIG_SYS_PROMPT) + 16)
204   -#define CONFIG_SYS_MAXARGS 16
205   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
206   -
207   -#define CONFIG_SYS_HUSH_PARSER
208   -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
209   -#define CONFIG_AUTO_COMPLETE
210   -
211   -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
212   -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE - \
213   - (CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_MALLOC_LEN + CONFIG_STACKSIZE)
214   -
215   -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x400000)
216   -
217   -/* The 1510 has 3 timers, they can be driven by the RefClk (12MHz) or by DPLL1.
218   - * This time is further subdivided by a local divisor.
219   - */
220   -#define CONFIG_SYS_TIMERBASE OMAP1510_TIMER1_BASE
221   -#define CONFIG_SYS_PTV 7
222   -#define CONFIG_SYS_HZ 1000
223   -
224   -#define OMAP5910_DPLL_DIV 1
225   -#define OMAP5910_DPLL_MUL \
226   - ((CONFIG_SYS_CLK_FREQ * (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
227   -
228   -#define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */
229   -#define OMAP5910_LCD_DIV 2 /* CKL/4 */
230   -#define OMAP5910_ARM_DIV 0 /* CKL/1 */
231   -#define OMAP5910_DSP_DIV 0 /* CKL/1 */
232   -#define OMAP5910_TC_DIV 1 /* CKL/2 */
233   -#define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */
234   -#define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */
235   -
236   -#define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b */
237   -#define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \
238   - (OMAP5910_LCD_DIV << 2) | \
239   - (OMAP5910_ARM_DIV << 4) | \
240   - (OMAP5910_DSP_DIV << 6) | \
241   - (OMAP5910_TC_DIV << 8) | \
242   - (OMAP5910_DSP_MMU_DIV << 10) | \
243   - (OMAP5910_ARM_TIM_SEL << 12))
244   -
245   -#endif /* __CONFIG_H */