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Commit 247161b8160fc699b0a517f081220bb50bc502a8

Authored by Tom Rini
2 parents d57d60cf24 96ac18c9cc
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Showing 38 changed files Inline Diff

arch/powerpc/cpu/mpc85xx/b4860_serdes.c
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc. 2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <asm/fsl_serdes.h> 8 #include <asm/fsl_serdes.h>
9 #include <asm/processor.h> 9 #include <asm/processor.h>
10 #include <asm/io.h> 10 #include <asm/io.h>
11 #include "fsl_corenet2_serdes.h" 11 #include "fsl_corenet2_serdes.h"
12 12
13 struct serdes_config { 13 struct serdes_config {
14 u8 protocol; 14 u8 protocol;
15 u8 lanes[SRDS_MAX_LANES]; 15 u8 lanes[SRDS_MAX_LANES];
16 }; 16 };
17 17
18 #ifdef CONFIG_PPC_B4860 18 #ifdef CONFIG_PPC_B4860
19 static struct serdes_config serdes1_cfg_tbl[] = { 19 static struct serdes_config serdes1_cfg_tbl[] = {
20 /* SerDes 1 */ 20 /* SerDes 1 */
21 {0x02, {AURORA, AURORA, CPRI6, CPRI5,
22 CPRI4, CPRI3, CPRI2, CPRI1} },
23 {0x04, {AURORA, AURORA, CPRI6, CPRI5,
24 CPRI4, CPRI3, CPRI2, CPRI1} },
25 {0x05, {AURORA, AURORA, CPRI6, CPRI5,
26 CPRI4, CPRI3, CPRI2, CPRI1} },
27 {0x06, {AURORA, AURORA, CPRI6, CPRI5,
28 CPRI4, CPRI3, CPRI2, CPRI1} },
29 {0x08, {AURORA, AURORA, CPRI6, CPRI5,
30 CPRI4, CPRI3, CPRI2, CPRI1} },
31 {0x09, {AURORA, AURORA, CPRI6, CPRI5,
32 CPRI4, CPRI3, CPRI2, CPRI1} },
33 {0x0A, {AURORA, AURORA, CPRI6, CPRI5,
34 CPRI4, CPRI3, CPRI2, CPRI1} },
35 {0x0B, {AURORA, AURORA, CPRI6, CPRI5,
36 CPRI4, CPRI3, CPRI2, CPRI1} },
37 {0x0C, {AURORA, AURORA, CPRI6, CPRI5,
38 CPRI4, CPRI3, CPRI2, CPRI1} },
21 {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5, 39 {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
22 CPRI4, CPRI3, CPRI2, CPRI1}}, 40 CPRI4, CPRI3, CPRI2, CPRI1}},
23 {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5, 41 {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
24 CPRI4, CPRI3, CPRI2, CPRI1}}, 42 CPRI4, CPRI3, CPRI2, CPRI1}},
25 {0x12, {CPRI8, CPRI7, CPRI6, CPRI5, 43 {0x12, {CPRI8, CPRI7, CPRI6, CPRI5,
26 CPRI4, CPRI3, CPRI2, CPRI1}}, 44 CPRI4, CPRI3, CPRI2, CPRI1}},
45 {0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
46 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} },
27 {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 47 {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
28 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 48 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
29 {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 49 {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
30 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 50 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
31 {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 51 {0x2D, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
32 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 52 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
33 {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, 53 {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
34 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, 54 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
55 {0x2F, {AURORA, AURORA,
56 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
57 CPRI4, CPRI3, CPRI2, CPRI1} },
35 {0x30, {AURORA, AURORA, 58 {0x30, {AURORA, AURORA,
36 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 59 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
37 CPRI4, CPRI3, CPRI2, CPRI1}}, 60 CPRI4, CPRI3, CPRI2, CPRI1}},
38 {0x32, {AURORA, AURORA, 61 {0x32, {AURORA, AURORA,
39 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 62 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
40 CPRI4, CPRI3, CPRI2, CPRI1}}, 63 CPRI4, CPRI3, CPRI2, CPRI1}},
41 {0x33, {AURORA, AURORA, 64 {0x33, {AURORA, AURORA,
42 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 65 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
43 CPRI4, CPRI3, CPRI2, CPRI1}}, 66 CPRI4, CPRI3, CPRI2, CPRI1}},
44 {0x34, {AURORA, AURORA, 67 {0x34, {AURORA, AURORA,
45 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 68 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
46 CPRI4, CPRI3, CPRI2, CPRI1}}, 69 CPRI4, CPRI3, CPRI2, CPRI1}},
70 {0x39, {AURORA, AURORA, CPRI6, CPRI5,
71 CPRI4, CPRI3, CPRI2, CPRI1} },
72 {0x3A, {AURORA, AURORA, CPRI6, CPRI5,
73 CPRI4, CPRI3, CPRI2, CPRI1} },
74 {0x3C, {AURORA, AURORA, CPRI6, CPRI5,
75 CPRI4, CPRI3, CPRI2, CPRI1} },
76 {0x3D, {AURORA, AURORA, CPRI6, CPRI5,
77 CPRI4, CPRI3, CPRI2, CPRI1} },
47 {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5, 78 {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
48 CPRI4, CPRI3, CPRI2, CPRI1}}, 79 CPRI4, CPRI3, CPRI2, CPRI1}},
80 {0x5C, {AURORA, AURORA,
81 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
82 CPRI4, CPRI3, CPRI2, CPRI1} },
83 {0x5D, {AURORA, AURORA,
84 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
85 CPRI4, CPRI3, CPRI2, CPRI1} },
49 {} 86 {}
50 }; 87 };
51 static struct serdes_config serdes2_cfg_tbl[] = { 88 static struct serdes_config serdes2_cfg_tbl[] = {
52 /* SerDes 2 */ 89 /* SerDes 2 */
90 {0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
91 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
92 AURORA, AURORA, SRIO1, SRIO1} },
53 {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 93 {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
54 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 94 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
55 AURORA, AURORA, SRIO1, SRIO1}}, 95 AURORA, AURORA, SRIO1, SRIO1}},
56 {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 96 {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
57 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 97 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
58 AURORA, AURORA, SRIO1, SRIO1}}, 98 AURORA, AURORA, SRIO1, SRIO1}},
99 {0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
100 SRIO2, SRIO2,
101 AURORA, AURORA, SRIO1, SRIO1} },
59 {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 102 {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
60 SRIO2, SRIO2, 103 SRIO2, SRIO2,
61 AURORA, AURORA, SRIO1, SRIO1}}, 104 AURORA, AURORA, SRIO1, SRIO1}},
62 {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 105 {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
63 SRIO2, SRIO2, 106 SRIO2, SRIO2,
64 AURORA, AURORA, 107 AURORA, AURORA,
65 SRIO1, SRIO1}}, 108 SRIO1, SRIO1}},
109 {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
110 SGMII_FM1_DTSEC3, AURORA,
111 SRIO1, SRIO1, SRIO1, SRIO1} },
66 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 112 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
67 SGMII_FM1_DTSEC3, AURORA, 113 SGMII_FM1_DTSEC3, AURORA,
68 SRIO1, SRIO1, SRIO1, SRIO1}}, 114 SRIO1, SRIO1, SRIO1, SRIO1}},
69 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 115 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
70 SGMII_FM1_DTSEC3, AURORA, 116 SGMII_FM1_DTSEC3, AURORA,
71 SRIO1, SRIO1, SRIO1, SRIO1}}, 117 SRIO1, SRIO1, SRIO1, SRIO1}},
72 {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 118 {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
73 SGMII_FM1_DTSEC3, AURORA, 119 SGMII_FM1_DTSEC3, AURORA,
74 SRIO1, SRIO1, SRIO1, SRIO1}}, 120 SRIO1, SRIO1, SRIO1, SRIO1}},
75 {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 121 {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
76 SGMII_FM1_DTSEC3, AURORA, 122 SGMII_FM1_DTSEC3, AURORA,
77 SRIO1, SRIO1, SRIO1, SRIO1}}, 123 SRIO1, SRIO1, SRIO1, SRIO1}},
124 {0x79, {SRIO2, SRIO2, SRIO2, SRIO2,
125 SRIO1, SRIO1, SRIO1, SRIO1} },
78 {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2, 126 {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
79 SRIO1, SRIO1, SRIO1, SRIO1}}, 127 SRIO1, SRIO1, SRIO1, SRIO1}},
128 {0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
129 SRIO2, SRIO2, AURORA, AURORA,
130 XFI_FM1_MAC9, XFI_FM1_MAC10} },
80 {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 131 {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
81 SRIO2, SRIO2, AURORA, AURORA, 132 SRIO2, SRIO2, AURORA, AURORA,
82 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 133 XFI_FM1_MAC9, XFI_FM1_MAC10}},
83 {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 134 {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
84 SRIO2, SRIO2, AURORA, AURORA, 135 SRIO2, SRIO2, AURORA, AURORA,
85 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 136 XFI_FM1_MAC9, XFI_FM1_MAC10}},
137 {0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
138 SRIO2, SRIO2,
139 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
140 XFI_FM1_MAC9, XFI_FM1_MAC10} },
86 {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 141 {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
87 SRIO2, SRIO2, 142 SRIO2, SRIO2,
88 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 143 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
89 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 144 XFI_FM1_MAC9, XFI_FM1_MAC10}},
145 {0x8C, {SRIO2, SRIO2, SRIO2, SRIO2,
146 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
147 XFI_FM1_MAC9, XFI_FM1_MAC10} },
90 {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2, 148 {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
91 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 149 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
92 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 150 XFI_FM1_MAC9, XFI_FM1_MAC10}},
93 {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 151 {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
94 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 152 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
95 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 153 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
96 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 154 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
97 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, 155 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
98 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 156 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
99 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 157 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
100 {0x9A, {PCIE1, PCIE1, 158 {0x9A, {PCIE1, PCIE1,
101 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 159 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
102 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 160 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
103 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 161 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
162 {0xB1, {PCIE1, PCIE1, PCIE1, PCIE1,
163 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
164 XFI_FM1_MAC9, XFI_FM1_MAC10} },
104 {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1, 165 {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
105 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 166 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
106 XFI_FM1_MAC9, XFI_FM1_MAC10}}, 167 XFI_FM1_MAC9, XFI_FM1_MAC10}},
107 {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 168 {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
108 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 169 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
109 SRIO1, SRIO1, SRIO1, SRIO1}}, 170 SRIO1, SRIO1, SRIO1, SRIO1}},
110 {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, 171 {0x98, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
111 XAUI_FM1_MAC9, XAUI_FM1_MAC9, 172 XAUI_FM1_MAC9, XAUI_FM1_MAC9,
112 XAUI_FM1_MAC10, XAUI_FM1_MAC10, 173 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
113 XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, 174 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
114 {} 175 {}
115 }; 176 };
116 #endif 177 #endif
117 178
118 #ifdef CONFIG_PPC_B4420 179 #ifdef CONFIG_PPC_B4420
119 static struct serdes_config serdes1_cfg_tbl[] = { 180 static struct serdes_config serdes1_cfg_tbl[] = {
120 {0x0D, {NONE, NONE, CPRI6, CPRI5, 181 {0x0D, {NONE, NONE, CPRI6, CPRI5,
121 CPRI4, CPRI3, NONE, NONE} }, 182 CPRI4, CPRI3, NONE, NONE} },
122 {0x0E, {NONE, NONE, CPRI8, CPRI5, 183 {0x0E, {NONE, NONE, CPRI8, CPRI5,
123 CPRI4, CPRI3, NONE, NONE} }, 184 CPRI4, CPRI3, NONE, NONE} },
124 {0x0F, {NONE, NONE, CPRI6, CPRI5, 185 {0x0F, {NONE, NONE, CPRI6, CPRI5,
125 CPRI4, CPRI3, NONE, NONE} }, 186 CPRI4, CPRI3, NONE, NONE} },
126 {0x18, {NONE, NONE, 187 {0x18, {NONE, NONE,
127 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 188 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
128 NONE, NONE, NONE, NONE} }, 189 NONE, NONE, NONE, NONE} },
129 {0x1B, {NONE, NONE, 190 {0x1B, {NONE, NONE,
130 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 191 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
131 NONE, NONE, NONE, NONE} }, 192 NONE, NONE, NONE, NONE} },
132 {0x1E, {NONE, NONE, AURORA, AURORA, 193 {0x1E, {NONE, NONE, AURORA, AURORA,
133 NONE, NONE, NONE, NONE} }, 194 NONE, NONE, NONE, NONE} },
134 {0x21, {NONE, NONE, AURORA, AURORA, 195 {0x21, {NONE, NONE, AURORA, AURORA,
135 NONE, NONE, NONE, NONE} }, 196 NONE, NONE, NONE, NONE} },
136 {0x3E, {NONE, NONE, CPRI6, CPRI5, 197 {0x3E, {NONE, NONE, CPRI6, CPRI5,
137 CPRI4, CPRI3, NONE, NONE} }, 198 CPRI4, CPRI3, NONE, NONE} },
138 {} 199 {}
139 }; 200 };
140 static struct serdes_config serdes2_cfg_tbl[] = { 201 static struct serdes_config serdes2_cfg_tbl[] = {
141 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 202 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
142 SGMII_FM1_DTSEC3, AURORA, 203 SGMII_FM1_DTSEC3, AURORA,
143 NONE, NONE, NONE, NONE} }, 204 NONE, NONE, NONE, NONE} },
144 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 205 {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
145 SGMII_FM1_DTSEC3, AURORA, 206 SGMII_FM1_DTSEC3, AURORA,
146 NONE, NONE, NONE, NONE} }, 207 NONE, NONE, NONE, NONE} },
147 {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 208 {0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
148 AURORA, AURORA, NONE, NONE, NONE, NONE} }, 209 AURORA, AURORA, NONE, NONE, NONE, NONE} },
149 {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, 210 {0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
150 AURORA, AURORA, NONE, NONE, NONE, NONE} }, 211 AURORA, AURORA, NONE, NONE, NONE, NONE} },
151 {0x9A, {PCIE1, PCIE1, 212 {0x9A, {PCIE1, PCIE1,
152 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, 213 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
153 NONE, NONE, NONE, NONE} }, 214 NONE, NONE, NONE, NONE} },
154 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, 215 {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
155 NONE, NONE, NONE, NONE} }, 216 NONE, NONE, NONE, NONE} },
156 {} 217 {}
157 }; 218 };
158 #endif 219 #endif
159 220
160 static struct serdes_config *serdes_cfg_tbl[] = { 221 static struct serdes_config *serdes_cfg_tbl[] = {
161 serdes1_cfg_tbl, 222 serdes1_cfg_tbl,
162 serdes2_cfg_tbl, 223 serdes2_cfg_tbl,
163 }; 224 };
164 225
165 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) 226 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
166 { 227 {
167 struct serdes_config *ptr; 228 struct serdes_config *ptr;
168 229
169 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 230 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
170 return 0; 231 return 0;
171 232
172 ptr = serdes_cfg_tbl[serdes]; 233 ptr = serdes_cfg_tbl[serdes];
173 while (ptr->protocol) { 234 while (ptr->protocol) {
174 if (ptr->protocol == cfg) 235 if (ptr->protocol == cfg)
175 return ptr->lanes[lane]; 236 return ptr->lanes[lane];
176 ptr++; 237 ptr++;
177 } 238 }
178 239
179 return 0; 240 return 0;
180 } 241 }
181 242
182 int is_serdes_prtcl_valid(int serdes, u32 prtcl) 243 int is_serdes_prtcl_valid(int serdes, u32 prtcl)
183 { 244 {
184 int i; 245 int i;
185 struct serdes_config *ptr; 246 struct serdes_config *ptr;
186 247
187 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) 248 if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
188 return 0; 249 return 0;
189 250
190 ptr = serdes_cfg_tbl[serdes]; 251 ptr = serdes_cfg_tbl[serdes];
191 while (ptr->protocol) { 252 while (ptr->protocol) {
192 if (ptr->protocol == prtcl) 253 if (ptr->protocol == prtcl)
193 break; 254 break;
194 ptr++; 255 ptr++;
195 } 256 }
196 257
197 if (!ptr->protocol) 258 if (!ptr->protocol)
198 return 0; 259 return 0;
199 260
200 for (i = 0; i < SRDS_MAX_LANES; i++) { 261 for (i = 0; i < SRDS_MAX_LANES; i++) {
201 if (ptr->lanes[i] != NONE) 262 if (ptr->lanes[i] != NONE)
202 return 1; 263 return 1;
203 } 264 }
204 265
205 return 0; 266 return 0;
206 } 267 }
207 268
arch/powerpc/cpu/mpc85xx/cmd_errata.c
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc. 2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <command.h> 8 #include <command.h>
9 #include <linux/compiler.h> 9 #include <linux/compiler.h>
10 #include <asm/fsl_errata.h> 10 #include <asm/fsl_errata.h>
11 #include <asm/processor.h> 11 #include <asm/processor.h>
12 #include "fsl_corenet_serdes.h" 12 #include "fsl_corenet_serdes.h"
13 13
14 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 14 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
15 /* 15 /*
16 * This work-around is implemented in PBI, so just check to see if the 16 * This work-around is implemented in PBI, so just check to see if the
17 * work-around was actually applied. To do this, we check for specific data 17 * work-around was actually applied. To do this, we check for specific data
18 * at specific addresses in DCSR. 18 * at specific addresses in DCSR.
19 * 19 *
20 * Array offsets[] contains a list of offsets within DCSR. According to the 20 * Array offsets[] contains a list of offsets within DCSR. According to the
21 * erratum document, the value at each offset should be 2. 21 * erratum document, the value at each offset should be 2.
22 */ 22 */
23 static void check_erratum_a4849(uint32_t svr) 23 static void check_erratum_a4849(uint32_t svr)
24 { 24 {
25 void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000; 25 void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
26 unsigned int i; 26 unsigned int i;
27 27
28 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) 28 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
29 static const uint8_t offsets[] = { 29 static const uint8_t offsets[] = {
30 0x50, 0x54, 0x58, 0x90, 0x94, 0x98 30 0x50, 0x54, 0x58, 0x90, 0x94, 0x98
31 }; 31 };
32 #endif 32 #endif
33 #ifdef CONFIG_PPC_P4080 33 #ifdef CONFIG_PPC_P4080
34 static const uint8_t offsets[] = { 34 static const uint8_t offsets[] = {
35 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac 35 0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
36 }; 36 };
37 #endif 37 #endif
38 uint32_t x108; /* The value that should be at offset 0x108 */ 38 uint32_t x108; /* The value that should be at offset 0x108 */
39 39
40 for (i = 0; i < ARRAY_SIZE(offsets); i++) { 40 for (i = 0; i < ARRAY_SIZE(offsets); i++) {
41 if (in_be32(dcsr + offsets[i]) != 2) { 41 if (in_be32(dcsr + offsets[i]) != 2) {
42 printf("Work-around for Erratum A004849 is not enabled\n"); 42 printf("Work-around for Erratum A004849 is not enabled\n");
43 return; 43 return;
44 } 44 }
45 } 45 }
46 46
47 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041) 47 #if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
48 x108 = 0x12; 48 x108 = 0x12;
49 #endif 49 #endif
50 50
51 #ifdef CONFIG_PPC_P4080 51 #ifdef CONFIG_PPC_P4080
52 /* 52 /*
53 * For P4080, the erratum document says that the value at offset 0x108 53 * For P4080, the erratum document says that the value at offset 0x108
54 * should be 0x12 on rev2, or 0x1c on rev3. 54 * should be 0x12 on rev2, or 0x1c on rev3.
55 */ 55 */
56 if (SVR_MAJ(svr) == 2) 56 if (SVR_MAJ(svr) == 2)
57 x108 = 0x12; 57 x108 = 0x12;
58 if (SVR_MAJ(svr) == 3) 58 if (SVR_MAJ(svr) == 3)
59 x108 = 0x1c; 59 x108 = 0x1c;
60 #endif 60 #endif
61 61
62 if (in_be32(dcsr + 0x108) != x108) { 62 if (in_be32(dcsr + 0x108) != x108) {
63 printf("Work-around for Erratum A004849 is not enabled\n"); 63 printf("Work-around for Erratum A004849 is not enabled\n");
64 return; 64 return;
65 } 65 }
66 66
67 /* Everything matches, so the erratum work-around was applied */ 67 /* Everything matches, so the erratum work-around was applied */
68 68
69 printf("Work-around for Erratum A004849 enabled\n"); 69 printf("Work-around for Erratum A004849 enabled\n");
70 } 70 }
71 #endif 71 #endif
72 72
73 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580 73 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580
74 /* 74 /*
75 * This work-around is implemented in PBI, so just check to see if the 75 * This work-around is implemented in PBI, so just check to see if the
76 * work-around was actually applied. To do this, we check for specific data 76 * work-around was actually applied. To do this, we check for specific data
77 * at specific addresses in the SerDes register block. 77 * at specific addresses in the SerDes register block.
78 * 78 *
79 * The work-around says that for each SerDes lane, write BnTTLCRy0 = 79 * The work-around says that for each SerDes lane, write BnTTLCRy0 =
80 * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000. 80 * 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000.
81 81
82 */ 82 */
83 static void check_erratum_a4580(uint32_t svr) 83 static void check_erratum_a4580(uint32_t svr)
84 { 84 {
85 const serdes_corenet_t __iomem *srds_regs = 85 const serdes_corenet_t __iomem *srds_regs =
86 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 86 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
87 unsigned int lane; 87 unsigned int lane;
88 88
89 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 89 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
90 if (serdes_lane_enabled(lane)) { 90 if (serdes_lane_enabled(lane)) {
91 const struct serdes_lane __iomem *srds_lane = 91 const struct serdes_lane __iomem *srds_lane =
92 &srds_regs->lane[serdes_get_lane_idx(lane)]; 92 &srds_regs->lane[serdes_get_lane_idx(lane)];
93 93
94 /* 94 /*
95 * Verify that the values we were supposed to write in 95 * Verify that the values we were supposed to write in
96 * the PBI are actually there. Also, the lower 15 96 * the PBI are actually there. Also, the lower 15
97 * bits of res4[3] should be the same as the upper 15 97 * bits of res4[3] should be the same as the upper 15
98 * bits of res4[1]. 98 * bits of res4[1].
99 */ 99 */
100 if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) || 100 if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) ||
101 (in_be32(&srds_lane->res4[1]) != 0x880000) || 101 (in_be32(&srds_lane->res4[1]) != 0x880000) ||
102 (in_be32(&srds_lane->res4[3]) != 0x40000044)) { 102 (in_be32(&srds_lane->res4[3]) != 0x40000044)) {
103 printf("Work-around for Erratum A004580 is " 103 printf("Work-around for Erratum A004580 is "
104 "not enabled\n"); 104 "not enabled\n");
105 return; 105 return;
106 } 106 }
107 } 107 }
108 } 108 }
109 109
110 /* Everything matches, so the erratum work-around was applied */ 110 /* Everything matches, so the erratum work-around was applied */
111 111
112 printf("Work-around for Erratum A004580 enabled\n"); 112 printf("Work-around for Erratum A004580 enabled\n");
113 } 113 }
114 #endif 114 #endif
115 115
116 static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 116 static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
117 { 117 {
118 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 118 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
119 extern int enable_cpu_a011_workaround; 119 extern int enable_cpu_a011_workaround;
120 #endif 120 #endif
121 __maybe_unused u32 svr = get_svr(); 121 __maybe_unused u32 svr = get_svr();
122 122
123 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 123 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
124 if (IS_SVR_REV(svr, 1, 0)) { 124 if (IS_SVR_REV(svr, 1, 0)) {
125 switch (SVR_SOC_VER(svr)) { 125 switch (SVR_SOC_VER(svr)) {
126 case SVR_P1013: 126 case SVR_P1013:
127 case SVR_P1022: 127 case SVR_P1022:
128 puts("Work-around for Erratum SATA A001 enabled\n"); 128 puts("Work-around for Erratum SATA A001 enabled\n");
129 } 129 }
130 } 130 }
131 #endif 131 #endif
132 132
133 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8) 133 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
134 puts("Work-around for Erratum SERDES8 enabled\n"); 134 puts("Work-around for Erratum SERDES8 enabled\n");
135 #endif 135 #endif
136 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) 136 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
137 puts("Work-around for Erratum SERDES9 enabled\n"); 137 puts("Work-around for Erratum SERDES9 enabled\n");
138 #endif 138 #endif
139 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005) 139 #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
140 puts("Work-around for Erratum SERDES-A005 enabled\n"); 140 puts("Work-around for Erratum SERDES-A005 enabled\n");
141 #endif 141 #endif
142 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) 142 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
143 if (SVR_MAJ(svr) < 3) 143 if (SVR_MAJ(svr) < 3)
144 puts("Work-around for Erratum CPU22 enabled\n"); 144 puts("Work-around for Erratum CPU22 enabled\n");
145 #endif 145 #endif
146 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 146 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
147 /* 147 /*
148 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 148 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
149 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1 149 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
150 * The SVR has been checked by cpu_init_r(). 150 * The SVR has been checked by cpu_init_r().
151 */ 151 */
152 if (enable_cpu_a011_workaround) 152 if (enable_cpu_a011_workaround)
153 puts("Work-around for Erratum CPU-A011 enabled\n"); 153 puts("Work-around for Erratum CPU-A011 enabled\n");
154 #endif 154 #endif
155 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999) 155 #if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
156 puts("Work-around for Erratum CPU-A003999 enabled\n"); 156 puts("Work-around for Erratum CPU-A003999 enabled\n");
157 #endif 157 #endif
158 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474) 158 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
159 puts("Work-around for Erratum DDR-A003474 enabled\n"); 159 puts("Work-around for Erratum DDR-A003474 enabled\n");
160 #endif 160 #endif
161 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) 161 #if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
162 puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); 162 puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
163 #endif 163 #endif
164 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111) 164 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
165 puts("Work-around for Erratum ESDHC111 enabled\n"); 165 puts("Work-around for Erratum ESDHC111 enabled\n");
166 #endif 166 #endif
167 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468 167 #ifdef CONFIG_SYS_FSL_ERRATUM_A004468
168 puts("Work-around for Erratum A004468 enabled\n"); 168 puts("Work-around for Erratum A004468 enabled\n");
169 #endif 169 #endif
170 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135) 170 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
171 puts("Work-around for Erratum ESDHC135 enabled\n"); 171 puts("Work-around for Erratum ESDHC135 enabled\n");
172 #endif 172 #endif
173 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13) 173 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
174 if (SVR_MAJ(svr) < 3) 174 if (SVR_MAJ(svr) < 3)
175 puts("Work-around for Erratum ESDHC13 enabled\n"); 175 puts("Work-around for Erratum ESDHC13 enabled\n");
176 #endif 176 #endif
177 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001) 177 #if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
178 puts("Work-around for Erratum ESDHC-A001 enabled\n"); 178 puts("Work-around for Erratum ESDHC-A001 enabled\n");
179 #endif 179 #endif
180 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 180 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
181 puts("Work-around for Erratum CPC-A002 enabled\n"); 181 puts("Work-around for Erratum CPC-A002 enabled\n");
182 #endif 182 #endif
183 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 183 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
184 puts("Work-around for Erratum CPC-A003 enabled\n"); 184 puts("Work-around for Erratum CPC-A003 enabled\n");
185 #endif 185 #endif
186 #ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001 186 #ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
187 puts("Work-around for Erratum ELBC-A001 enabled\n"); 187 puts("Work-around for Erratum ELBC-A001 enabled\n");
188 #endif 188 #endif
189 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003 189 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
190 puts("Work-around for Erratum DDR-A003 enabled\n"); 190 puts("Work-around for Erratum DDR-A003 enabled\n");
191 #endif 191 #endif
192 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115 192 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
193 puts("Work-around for Erratum DDR115 enabled\n"); 193 puts("Work-around for Erratum DDR115 enabled\n");
194 #endif 194 #endif
195 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 195 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
196 puts("Work-around for Erratum DDR111 enabled\n"); 196 puts("Work-around for Erratum DDR111 enabled\n");
197 puts("Work-around for Erratum DDR134 enabled\n"); 197 puts("Work-around for Erratum DDR134 enabled\n");
198 #endif 198 #endif
199 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769 199 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
200 puts("Work-around for Erratum IFC-A002769 enabled\n"); 200 puts("Work-around for Erratum IFC-A002769 enabled\n");
201 #endif 201 #endif
202 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 202 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
203 puts("Work-around for Erratum P1010-A003549 enabled\n"); 203 puts("Work-around for Erratum P1010-A003549 enabled\n");
204 #endif 204 #endif
205 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 205 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
206 puts("Work-around for Erratum IFC A-003399 enabled\n"); 206 puts("Work-around for Erratum IFC A-003399 enabled\n");
207 #endif 207 #endif
208 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 208 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
209 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) 209 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
210 puts("Work-around for Erratum NMG DDR120 enabled\n"); 210 puts("Work-around for Erratum NMG DDR120 enabled\n");
211 #endif 211 #endif
212 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 212 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
213 puts("Work-around for Erratum NMG_LBC103 enabled\n"); 213 puts("Work-around for Erratum NMG_LBC103 enabled\n");
214 #endif 214 #endif
215 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 215 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
216 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) 216 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
217 puts("Work-around for Erratum NMG ETSEC129 enabled\n"); 217 puts("Work-around for Erratum NMG ETSEC129 enabled\n");
218 #endif 218 #endif
219 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510 219 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
220 puts("Work-around for Erratum A004510 enabled\n"); 220 puts("Work-around for Erratum A004510 enabled\n");
221 #endif 221 #endif
222 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 222 #ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
223 puts("Work-around for Erratum SRIO-A004034 enabled\n"); 223 puts("Work-around for Erratum SRIO-A004034 enabled\n");
224 #endif 224 #endif
225 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934 225 #ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
226 puts("Work-around for Erratum A004934 enabled\n"); 226 puts("Work-around for Erratum A004934 enabled\n");
227 #endif 227 #endif
228 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 228 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
229 if (IS_SVR_REV(svr, 1, 0)) 229 if (IS_SVR_REV(svr, 1, 0))
230 puts("Work-around for Erratum A005871 enabled\n"); 230 puts("Work-around for Erratum A005871 enabled\n");
231 #endif 231 #endif
232 #ifdef CONFIG_SYS_FSL_ERRATUM_A006475
233 if (SVR_MAJ(get_svr()) == 1)
234 puts("Work-around for Erratum A006475 enabled\n");
235 #endif
236 #ifdef CONFIG_SYS_FSL_ERRATUM_A006384
237 if (SVR_MAJ(get_svr()) == 1)
238 puts("Work-around for Erratum A006384 enabled\n");
239 #endif
232 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849 240 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
233 /* This work-around is implemented in PBI, so just check for it */ 241 /* This work-around is implemented in PBI, so just check for it */
234 check_erratum_a4849(svr); 242 check_erratum_a4849(svr);
235 #endif 243 #endif
236 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580 244 #ifdef CONFIG_SYS_FSL_ERRATUM_A004580
237 /* This work-around is implemented in PBI, so just check for it */ 245 /* This work-around is implemented in PBI, so just check for it */
238 check_erratum_a4580(svr); 246 check_erratum_a4580(svr);
239 #endif 247 #endif
240 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003 248 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
241 puts("Work-around for Erratum PCIe-A003 enabled\n"); 249 puts("Work-around for Erratum PCIe-A003 enabled\n");
242 #endif 250 #endif
243 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 251 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
244 puts("Work-around for Erratum USB14 enabled\n"); 252 puts("Work-around for Erratum USB14 enabled\n");
245 #endif 253 #endif
246 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 254 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
247 puts("Work-around for Erratum A006593 enabled\n"); 255 puts("Work-around for Erratum A006593 enabled\n");
248 #endif 256 #endif
249 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 257 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
250 if (has_erratum_a006379()) 258 if (has_erratum_a006379())
251 puts("Work-around for Erratum A006379 enabled\n"); 259 puts("Work-around for Erratum A006379 enabled\n");
252 #endif 260 #endif
253 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 261 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
254 if (IS_SVR_REV(svr, 1, 0)) 262 if (IS_SVR_REV(svr, 1, 0))
255 puts("Work-around for Erratum A003571 enabled\n"); 263 puts("Work-around for Erratum A003571 enabled\n");
256 #endif 264 #endif
257 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 265 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
258 puts("Work-around for Erratum A-005812 enabled\n"); 266 puts("Work-around for Erratum A-005812 enabled\n");
259 #endif 267 #endif
260 #ifdef CONFIG_SYS_FSL_ERRATUM_A005125 268 #ifdef CONFIG_SYS_FSL_ERRATUM_A005125
261 puts("Work-around for Erratum A005125 enabled\n"); 269 puts("Work-around for Erratum A005125 enabled\n");
262 #endif 270 #endif
263 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447 271 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
264 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) || 272 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
265 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV)) 273 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
266 puts("Work-around for Erratum I2C-A004447 enabled\n"); 274 puts("Work-around for Erratum I2C-A004447 enabled\n");
275 #endif
276 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
277 if (has_erratum_a006261())
278 puts("Work-around for Erratum A006261 enabled\n");
267 #endif 279 #endif
268 return 0; 280 return 0;
269 } 281 }
270 282
271 U_BOOT_CMD( 283 U_BOOT_CMD(
272 errata, 1, 0, do_errata, 284 errata, 1, 0, do_errata,
273 "Report errata workarounds", 285 "Report errata workarounds",
274 "" 286 ""
275 ); 287 );
276 288
arch/powerpc/cpu/mpc85xx/cpu_init.c
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2007-2011 Freescale Semiconductor, Inc. 2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
3 * 3 *
4 * (C) Copyright 2003 Motorola Inc. 4 * (C) Copyright 2003 Motorola Inc.
5 * Modified by Xianghua Xiao, X.Xiao@motorola.com 5 * Modified by Xianghua Xiao, X.Xiao@motorola.com
6 * 6 *
7 * (C) Copyright 2000 7 * (C) Copyright 2000
8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * 9 *
10 * SPDX-License-Identifier: GPL-2.0+ 10 * SPDX-License-Identifier: GPL-2.0+
11 */ 11 */
12 12
13 #include <common.h> 13 #include <common.h>
14 #include <watchdog.h> 14 #include <watchdog.h>
15 #include <asm/processor.h> 15 #include <asm/processor.h>
16 #include <ioports.h> 16 #include <ioports.h>
17 #include <sata.h> 17 #include <sata.h>
18 #include <fm_eth.h> 18 #include <fm_eth.h>
19 #include <asm/io.h> 19 #include <asm/io.h>
20 #include <asm/cache.h> 20 #include <asm/cache.h>
21 #include <asm/mmu.h> 21 #include <asm/mmu.h>
22 #include <asm/fsl_errata.h> 22 #include <asm/fsl_errata.h>
23 #include <asm/fsl_law.h> 23 #include <asm/fsl_law.h>
24 #include <asm/fsl_serdes.h> 24 #include <asm/fsl_serdes.h>
25 #include <asm/fsl_srio.h> 25 #include <asm/fsl_srio.h>
26 #include <fsl_usb.h> 26 #include <fsl_usb.h>
27 #include <hwconfig.h> 27 #include <hwconfig.h>
28 #include <linux/compiler.h> 28 #include <linux/compiler.h>
29 #include "mp.h" 29 #include "mp.h"
30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 30 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
31 #include <nand.h> 31 #include <nand.h>
32 #include <errno.h> 32 #include <errno.h>
33 #endif 33 #endif
34 34
35 #include "../../../../drivers/block/fsl_sata.h" 35 #include "../../../../drivers/block/fsl_sata.h"
36 36
37 DECLARE_GLOBAL_DATA_PTR; 37 DECLARE_GLOBAL_DATA_PTR;
38 38
39 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
40 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
41 {
42 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
43 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
44
45 /* Increase Disconnect Threshold by 50mV */
46 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
47 INC_DCNT_THRESHOLD_50MV;
48 /* Enable programming of USB High speed Disconnect threshold */
49 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
50 out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
51
52 xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
53 /* Increase Disconnect Threshold by 50mV */
54 xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
55 INC_DCNT_THRESHOLD_50MV;
56 /* Enable programming of USB High speed Disconnect threshold */
57 xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
58 out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
59 #else
60
61 u32 temp = 0;
62 u32 status = in_be32(&usb_phy->status1);
63
64 u32 squelch_prog_rd_0_2 =
65 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
66 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
67
68 u32 squelch_prog_rd_3_5 =
69 (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
70 & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
71
72 setbits_be32(&usb_phy->config1,
73 CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
74 setbits_be32(&usb_phy->config2,
75 CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
76
77 temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
78 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
79
80 temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
81 out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
82 #endif
83 }
84 #endif
85
86
39 #ifdef CONFIG_QE 87 #ifdef CONFIG_QE
40 extern qe_iop_conf_t qe_iop_conf_tab[]; 88 extern qe_iop_conf_t qe_iop_conf_tab[];
41 extern void qe_config_iopin(u8 port, u8 pin, int dir, 89 extern void qe_config_iopin(u8 port, u8 pin, int dir,
42 int open_drain, int assign); 90 int open_drain, int assign);
43 extern void qe_init(uint qe_base); 91 extern void qe_init(uint qe_base);
44 extern void qe_reset(void); 92 extern void qe_reset(void);
45 93
46 static void config_qe_ioports(void) 94 static void config_qe_ioports(void)
47 { 95 {
48 u8 port, pin; 96 u8 port, pin;
49 int dir, open_drain, assign; 97 int dir, open_drain, assign;
50 int i; 98 int i;
51 99
52 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { 100 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
53 port = qe_iop_conf_tab[i].port; 101 port = qe_iop_conf_tab[i].port;
54 pin = qe_iop_conf_tab[i].pin; 102 pin = qe_iop_conf_tab[i].pin;
55 dir = qe_iop_conf_tab[i].dir; 103 dir = qe_iop_conf_tab[i].dir;
56 open_drain = qe_iop_conf_tab[i].open_drain; 104 open_drain = qe_iop_conf_tab[i].open_drain;
57 assign = qe_iop_conf_tab[i].assign; 105 assign = qe_iop_conf_tab[i].assign;
58 qe_config_iopin(port, pin, dir, open_drain, assign); 106 qe_config_iopin(port, pin, dir, open_drain, assign);
59 } 107 }
60 } 108 }
61 #endif 109 #endif
62 110
63 #ifdef CONFIG_CPM2 111 #ifdef CONFIG_CPM2
64 void config_8560_ioports (volatile ccsr_cpm_t * cpm) 112 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
65 { 113 {
66 int portnum; 114 int portnum;
67 115
68 for (portnum = 0; portnum < 4; portnum++) { 116 for (portnum = 0; portnum < 4; portnum++) {
69 uint pmsk = 0, 117 uint pmsk = 0,
70 ppar = 0, 118 ppar = 0,
71 psor = 0, 119 psor = 0,
72 pdir = 0, 120 pdir = 0,
73 podr = 0, 121 podr = 0,
74 pdat = 0; 122 pdat = 0;
75 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0]; 123 iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
76 iop_conf_t *eiopc = iopc + 32; 124 iop_conf_t *eiopc = iopc + 32;
77 uint msk = 1; 125 uint msk = 1;
78 126
79 /* 127 /*
80 * NOTE: 128 * NOTE:
81 * index 0 refers to pin 31, 129 * index 0 refers to pin 31,
82 * index 31 refers to pin 0 130 * index 31 refers to pin 0
83 */ 131 */
84 while (iopc < eiopc) { 132 while (iopc < eiopc) {
85 if (iopc->conf) { 133 if (iopc->conf) {
86 pmsk |= msk; 134 pmsk |= msk;
87 if (iopc->ppar) 135 if (iopc->ppar)
88 ppar |= msk; 136 ppar |= msk;
89 if (iopc->psor) 137 if (iopc->psor)
90 psor |= msk; 138 psor |= msk;
91 if (iopc->pdir) 139 if (iopc->pdir)
92 pdir |= msk; 140 pdir |= msk;
93 if (iopc->podr) 141 if (iopc->podr)
94 podr |= msk; 142 podr |= msk;
95 if (iopc->pdat) 143 if (iopc->pdat)
96 pdat |= msk; 144 pdat |= msk;
97 } 145 }
98 146
99 msk <<= 1; 147 msk <<= 1;
100 iopc++; 148 iopc++;
101 } 149 }
102 150
103 if (pmsk != 0) { 151 if (pmsk != 0) {
104 volatile ioport_t *iop = ioport_addr (cpm, portnum); 152 volatile ioport_t *iop = ioport_addr (cpm, portnum);
105 uint tpmsk = ~pmsk; 153 uint tpmsk = ~pmsk;
106 154
107 /* 155 /*
108 * the (somewhat confused) paragraph at the 156 * the (somewhat confused) paragraph at the
109 * bottom of page 35-5 warns that there might 157 * bottom of page 35-5 warns that there might
110 * be "unknown behaviour" when programming 158 * be "unknown behaviour" when programming
111 * PSORx and PDIRx, if PPARx = 1, so I 159 * PSORx and PDIRx, if PPARx = 1, so I
112 * decided this meant I had to disable the 160 * decided this meant I had to disable the
113 * dedicated function first, and enable it 161 * dedicated function first, and enable it
114 * last. 162 * last.
115 */ 163 */
116 iop->ppar &= tpmsk; 164 iop->ppar &= tpmsk;
117 iop->psor = (iop->psor & tpmsk) | psor; 165 iop->psor = (iop->psor & tpmsk) | psor;
118 iop->podr = (iop->podr & tpmsk) | podr; 166 iop->podr = (iop->podr & tpmsk) | podr;
119 iop->pdat = (iop->pdat & tpmsk) | pdat; 167 iop->pdat = (iop->pdat & tpmsk) | pdat;
120 iop->pdir = (iop->pdir & tpmsk) | pdir; 168 iop->pdir = (iop->pdir & tpmsk) | pdir;
121 iop->ppar |= ppar; 169 iop->ppar |= ppar;
122 } 170 }
123 } 171 }
124 } 172 }
125 #endif 173 #endif
126 174
127 #ifdef CONFIG_SYS_FSL_CPC 175 #ifdef CONFIG_SYS_FSL_CPC
128 static void enable_cpc(void) 176 static void enable_cpc(void)
129 { 177 {
130 int i; 178 int i;
131 u32 size = 0; 179 u32 size = 0;
132 180
133 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 181 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
134 182
135 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 183 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
136 u32 cpccfg0 = in_be32(&cpc->cpccfg0); 184 u32 cpccfg0 = in_be32(&cpc->cpccfg0);
137 size += CPC_CFG0_SZ_K(cpccfg0); 185 size += CPC_CFG0_SZ_K(cpccfg0);
138 #ifdef CONFIG_RAMBOOT_PBL 186 #ifdef CONFIG_RAMBOOT_PBL
139 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { 187 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
140 /* find and disable LAW of SRAM */ 188 /* find and disable LAW of SRAM */
141 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR); 189 struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
142 190
143 if (law.index == -1) { 191 if (law.index == -1) {
144 printf("\nFatal error happened\n"); 192 printf("\nFatal error happened\n");
145 return; 193 return;
146 } 194 }
147 disable_law(law.index); 195 disable_law(law.index);
148 196
149 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS); 197 clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
150 out_be32(&cpc->cpccsr0, 0); 198 out_be32(&cpc->cpccsr0, 0);
151 out_be32(&cpc->cpcsrcr0, 0); 199 out_be32(&cpc->cpcsrcr0, 0);
152 } 200 }
153 #endif 201 #endif
154 202
155 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002 203 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
156 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS); 204 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
157 #endif 205 #endif
158 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003 206 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
159 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS); 207 setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
160 #endif 208 #endif
161 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593 209 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
162 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21)); 210 setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
163 #endif 211 #endif
164 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 212 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
165 if (has_erratum_a006379()) { 213 if (has_erratum_a006379()) {
166 setbits_be32(&cpc->cpchdbcr0, 214 setbits_be32(&cpc->cpchdbcr0,
167 CPC_HDBCR0_SPLRU_LEVEL_EN); 215 CPC_HDBCR0_SPLRU_LEVEL_EN);
168 } 216 }
169 #endif 217 #endif
170 218
171 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE); 219 out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
172 /* Read back to sync write */ 220 /* Read back to sync write */
173 in_be32(&cpc->cpccsr0); 221 in_be32(&cpc->cpccsr0);
174 222
175 } 223 }
176 224
177 puts("Corenet Platform Cache: "); 225 puts("Corenet Platform Cache: ");
178 print_size(size * 1024, " enabled\n"); 226 print_size(size * 1024, " enabled\n");
179 } 227 }
180 228
181 static void invalidate_cpc(void) 229 static void invalidate_cpc(void)
182 { 230 {
183 int i; 231 int i;
184 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; 232 cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
185 233
186 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { 234 for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
187 /* skip CPC when it used as all SRAM */ 235 /* skip CPC when it used as all SRAM */
188 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) 236 if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
189 continue; 237 continue;
190 /* Flash invalidate the CPC and clear all the locks */ 238 /* Flash invalidate the CPC and clear all the locks */
191 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC); 239 out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
192 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC)) 240 while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
193 ; 241 ;
194 } 242 }
195 } 243 }
196 #else 244 #else
197 #define enable_cpc() 245 #define enable_cpc()
198 #define invalidate_cpc() 246 #define invalidate_cpc()
199 #endif /* CONFIG_SYS_FSL_CPC */ 247 #endif /* CONFIG_SYS_FSL_CPC */
200 248
201 /* 249 /*
202 * Breathe some life into the CPU... 250 * Breathe some life into the CPU...
203 * 251 *
204 * Set up the memory map 252 * Set up the memory map
205 * initialize a bunch of registers 253 * initialize a bunch of registers
206 */ 254 */
207 255
208 #ifdef CONFIG_FSL_CORENET 256 #ifdef CONFIG_FSL_CORENET
209 static void corenet_tb_init(void) 257 static void corenet_tb_init(void)
210 { 258 {
211 volatile ccsr_rcpm_t *rcpm = 259 volatile ccsr_rcpm_t *rcpm =
212 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); 260 (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
213 volatile ccsr_pic_t *pic = 261 volatile ccsr_pic_t *pic =
214 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); 262 (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
215 u32 whoami = in_be32(&pic->whoami); 263 u32 whoami = in_be32(&pic->whoami);
216 264
217 /* Enable the timebase register for this core */ 265 /* Enable the timebase register for this core */
218 out_be32(&rcpm->ctbenrl, (1 << whoami)); 266 out_be32(&rcpm->ctbenrl, (1 << whoami));
219 } 267 }
220 #endif 268 #endif
221 269
222 void cpu_init_f (void) 270 void cpu_init_f (void)
223 { 271 {
224 extern void m8560_cpm_reset (void); 272 extern void m8560_cpm_reset (void);
225 #ifdef CONFIG_SYS_DCSRBAR_PHYS 273 #ifdef CONFIG_SYS_DCSRBAR_PHYS
226 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 274 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
227 #endif 275 #endif
228 #if defined(CONFIG_SECURE_BOOT) 276 #if defined(CONFIG_SECURE_BOOT)
229 struct law_entry law; 277 struct law_entry law;
230 #endif 278 #endif
231 #ifdef CONFIG_MPC8548 279 #ifdef CONFIG_MPC8548
232 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); 280 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
233 uint svr = get_svr(); 281 uint svr = get_svr();
234 282
235 /* 283 /*
236 * CPU2 errata workaround: A core hang possible while executing 284 * CPU2 errata workaround: A core hang possible while executing
237 * a msync instruction and a snoopable transaction from an I/O 285 * a msync instruction and a snoopable transaction from an I/O
238 * master tagged to make quick forward progress is present. 286 * master tagged to make quick forward progress is present.
239 * Fixed in silicon rev 2.1. 287 * Fixed in silicon rev 2.1.
240 */ 288 */
241 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0))) 289 if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
242 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16)); 290 out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
243 #endif 291 #endif
244 292
245 disable_tlb(14); 293 disable_tlb(14);
246 disable_tlb(15); 294 disable_tlb(15);
247 295
248 #if defined(CONFIG_SECURE_BOOT) 296 #if defined(CONFIG_SECURE_BOOT)
249 /* Disable the LAW created for NOR flash by the PBI commands */ 297 /* Disable the LAW created for NOR flash by the PBI commands */
250 law = find_law(CONFIG_SYS_PBI_FLASH_BASE); 298 law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
251 if (law.index != -1) 299 if (law.index != -1)
252 disable_law(law.index); 300 disable_law(law.index);
253 #endif 301 #endif
254 302
255 #ifdef CONFIG_CPM2 303 #ifdef CONFIG_CPM2
256 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR); 304 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
257 #endif 305 #endif
258 306
259 init_early_memctl_regs(); 307 init_early_memctl_regs();
260 308
261 #if defined(CONFIG_CPM2) 309 #if defined(CONFIG_CPM2)
262 m8560_cpm_reset(); 310 m8560_cpm_reset();
263 #endif 311 #endif
264 #ifdef CONFIG_QE 312 #ifdef CONFIG_QE
265 /* Config QE ioports */ 313 /* Config QE ioports */
266 config_qe_ioports(); 314 config_qe_ioports();
267 #endif 315 #endif
268 #if defined(CONFIG_FSL_DMA) 316 #if defined(CONFIG_FSL_DMA)
269 dma_init(); 317 dma_init();
270 #endif 318 #endif
271 #ifdef CONFIG_FSL_CORENET 319 #ifdef CONFIG_FSL_CORENET
272 corenet_tb_init(); 320 corenet_tb_init();
273 #endif 321 #endif
274 init_used_tlb_cams(); 322 init_used_tlb_cams();
275 323
276 /* Invalidate the CPC before DDR gets enabled */ 324 /* Invalidate the CPC before DDR gets enabled */
277 invalidate_cpc(); 325 invalidate_cpc();
278 326
279 #ifdef CONFIG_SYS_DCSRBAR_PHYS 327 #ifdef CONFIG_SYS_DCSRBAR_PHYS
280 /* set DCSRCR so that DCSR space is 1G */ 328 /* set DCSRCR so that DCSR space is 1G */
281 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G); 329 setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
282 in_be32(&gur->dcsrcr); 330 in_be32(&gur->dcsrcr);
283 #endif 331 #endif
284 332
285 } 333 }
286 334
287 /* Implement a dummy function for those platforms w/o SERDES */ 335 /* Implement a dummy function for those platforms w/o SERDES */
288 static void __fsl_serdes__init(void) 336 static void __fsl_serdes__init(void)
289 { 337 {
290 return ; 338 return ;
291 } 339 }
292 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void); 340 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
293 341
294 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 342 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
295 int enable_cluster_l2(void) 343 int enable_cluster_l2(void)
296 { 344 {
297 int i = 0; 345 int i = 0;
298 u32 cluster; 346 u32 cluster;
299 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 347 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
300 struct ccsr_cluster_l2 __iomem *l2cache; 348 struct ccsr_cluster_l2 __iomem *l2cache;
301 349
302 cluster = in_be32(&gur->tp_cluster[i].lower); 350 cluster = in_be32(&gur->tp_cluster[i].lower);
303 if (cluster & TP_CLUSTER_EOC) 351 if (cluster & TP_CLUSTER_EOC)
304 return 0; 352 return 0;
305 353
306 /* The first cache has already been set up, so skip it */ 354 /* The first cache has already been set up, so skip it */
307 i++; 355 i++;
308 356
309 /* Look through the remaining clusters, and set up their caches */ 357 /* Look through the remaining clusters, and set up their caches */
310 do { 358 do {
311 int j, cluster_valid = 0; 359 int j, cluster_valid = 0;
312 360
313 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); 361 l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
314 362
315 cluster = in_be32(&gur->tp_cluster[i].lower); 363 cluster = in_be32(&gur->tp_cluster[i].lower);
316 364
317 /* check that at least one core/accel is enabled in cluster */ 365 /* check that at least one core/accel is enabled in cluster */
318 for (j = 0; j < 4; j++) { 366 for (j = 0; j < 4; j++) {
319 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; 367 u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
320 u32 type = in_be32(&gur->tp_ityp[idx]); 368 u32 type = in_be32(&gur->tp_ityp[idx]);
321 369
322 if (type & TP_ITYP_AV) 370 if (type & TP_ITYP_AV)
323 cluster_valid = 1; 371 cluster_valid = 1;
324 } 372 }
325 373
326 if (cluster_valid) { 374 if (cluster_valid) {
327 /* set stash ID to (cluster) * 2 + 32 + 1 */ 375 /* set stash ID to (cluster) * 2 + 32 + 1 */
328 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1); 376 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
329 377
330 printf("enable l2 for cluster %d %p\n", i, l2cache); 378 printf("enable l2 for cluster %d %p\n", i, l2cache);
331 379
332 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC); 380 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
333 while ((in_be32(&l2cache->l2csr0) 381 while ((in_be32(&l2cache->l2csr0)
334 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0) 382 & (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
335 ; 383 ;
336 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE); 384 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
337 } 385 }
338 i++; 386 i++;
339 } while (!(cluster & TP_CLUSTER_EOC)); 387 } while (!(cluster & TP_CLUSTER_EOC));
340 388
341 return 0; 389 return 0;
342 } 390 }
343 #endif 391 #endif
344 392
345 /* 393 /*
346 * Initialize L2 as cache. 394 * Initialize L2 as cache.
347 * 395 *
348 * The newer 8548, etc, parts have twice as much cache, but 396 * The newer 8548, etc, parts have twice as much cache, but
349 * use the same bit-encoding as the older 8555, etc, parts. 397 * use the same bit-encoding as the older 8555, etc, parts.
350 * 398 *
351 */ 399 */
352 int cpu_init_r(void) 400 int cpu_init_r(void)
353 { 401 {
354 __maybe_unused u32 svr = get_svr(); 402 __maybe_unused u32 svr = get_svr();
355 #ifdef CONFIG_SYS_LBC_LCRR 403 #ifdef CONFIG_SYS_LBC_LCRR
356 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR; 404 fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
357 #endif 405 #endif
358 #ifdef CONFIG_L2_CACHE 406 #ifdef CONFIG_L2_CACHE
359 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; 407 ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
360 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 408 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
361 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; 409 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
362 #endif 410 #endif
363 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 411 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
364 extern int spin_table_compat; 412 extern int spin_table_compat;
365 const char *spin; 413 const char *spin;
366 #endif 414 #endif
367 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 415 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
368 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; 416 ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
369 #endif 417 #endif
370 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ 418 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
371 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) 419 defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
372 /* 420 /*
373 * CPU22 and NMG_CPU_A011 share the same workaround. 421 * CPU22 and NMG_CPU_A011 share the same workaround.
374 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0 422 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
375 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0 423 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
376 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both 424 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
377 * fixed in 2.0. NMG_CPU_A011 is activated by default and can 425 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
378 * be disabled by hwconfig with syntax: 426 * be disabled by hwconfig with syntax:
379 * 427 *
380 * fsl_cpu_a011:disable 428 * fsl_cpu_a011:disable
381 */ 429 */
382 extern int enable_cpu_a011_workaround; 430 extern int enable_cpu_a011_workaround;
383 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22 431 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
384 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3); 432 enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
385 #else 433 #else
386 char buffer[HWCONFIG_BUFFER_SIZE]; 434 char buffer[HWCONFIG_BUFFER_SIZE];
387 char *buf = NULL; 435 char *buf = NULL;
388 int n, res; 436 int n, res;
389 437
390 n = getenv_f("hwconfig", buffer, sizeof(buffer)); 438 n = getenv_f("hwconfig", buffer, sizeof(buffer));
391 if (n > 0) 439 if (n > 0)
392 buf = buffer; 440 buf = buffer;
393 441
394 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf); 442 res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
395 if (res > 0) 443 if (res > 0)
396 enable_cpu_a011_workaround = 0; 444 enable_cpu_a011_workaround = 0;
397 else { 445 else {
398 if (n >= HWCONFIG_BUFFER_SIZE) { 446 if (n >= HWCONFIG_BUFFER_SIZE) {
399 printf("fsl_cpu_a011 was not found. hwconfig variable " 447 printf("fsl_cpu_a011 was not found. hwconfig variable "
400 "may be too long\n"); 448 "may be too long\n");
401 } 449 }
402 enable_cpu_a011_workaround = 450 enable_cpu_a011_workaround =
403 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) || 451 (SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
404 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2); 452 (SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
405 } 453 }
406 #endif 454 #endif
407 if (enable_cpu_a011_workaround) { 455 if (enable_cpu_a011_workaround) {
408 flush_dcache(); 456 flush_dcache();
409 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); 457 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
410 sync(); 458 sync();
411 } 459 }
412 #endif 460 #endif
413 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812 461 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
414 /* 462 /*
415 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running 463 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
416 * in write shadow mode. Checking DCWS before setting SPR 976. 464 * in write shadow mode. Checking DCWS before setting SPR 976.
417 */ 465 */
418 if (mfspr(L1CSR2) & L1CSR2_DCWS) 466 if (mfspr(L1CSR2) & L1CSR2_DCWS)
419 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); 467 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
420 #endif 468 #endif
421 469
422 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) 470 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
423 spin = getenv("spin_table_compat"); 471 spin = getenv("spin_table_compat");
424 if (spin && (*spin == 'n')) 472 if (spin && (*spin == 'n'))
425 spin_table_compat = 0; 473 spin_table_compat = 0;
426 else 474 else
427 spin_table_compat = 1; 475 spin_table_compat = 1;
428 #endif 476 #endif
429 477
430 puts ("L2: "); 478 puts ("L2: ");
431 479
432 #if defined(CONFIG_L2_CACHE) 480 #if defined(CONFIG_L2_CACHE)
433 volatile uint cache_ctl; 481 volatile uint cache_ctl;
434 uint ver; 482 uint ver;
435 u32 l2siz_field; 483 u32 l2siz_field;
436 484
437 ver = SVR_SOC_VER(svr); 485 ver = SVR_SOC_VER(svr);
438 486
439 asm("msync;isync"); 487 asm("msync;isync");
440 cache_ctl = l2cache->l2ctl; 488 cache_ctl = l2cache->l2ctl;
441 489
442 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) 490 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
443 if (cache_ctl & MPC85xx_L2CTL_L2E) { 491 if (cache_ctl & MPC85xx_L2CTL_L2E) {
444 /* Clear L2 SRAM memory-mapped base address */ 492 /* Clear L2 SRAM memory-mapped base address */
445 out_be32(&l2cache->l2srbar0, 0x0); 493 out_be32(&l2cache->l2srbar0, 0x0);
446 out_be32(&l2cache->l2srbar1, 0x0); 494 out_be32(&l2cache->l2srbar1, 0x0);
447 495
448 /* set MBECCDIS=0, SBECCDIS=0 */ 496 /* set MBECCDIS=0, SBECCDIS=0 */
449 clrbits_be32(&l2cache->l2errdis, 497 clrbits_be32(&l2cache->l2errdis,
450 (MPC85xx_L2ERRDIS_MBECC | 498 (MPC85xx_L2ERRDIS_MBECC |
451 MPC85xx_L2ERRDIS_SBECC)); 499 MPC85xx_L2ERRDIS_SBECC));
452 500
453 /* set L2E=0, L2SRAM=0 */ 501 /* set L2E=0, L2SRAM=0 */
454 clrbits_be32(&l2cache->l2ctl, 502 clrbits_be32(&l2cache->l2ctl,
455 (MPC85xx_L2CTL_L2E | 503 (MPC85xx_L2CTL_L2E |
456 MPC85xx_L2CTL_L2SRAM_ENTIRE)); 504 MPC85xx_L2CTL_L2SRAM_ENTIRE));
457 } 505 }
458 #endif 506 #endif
459 507
460 l2siz_field = (cache_ctl >> 28) & 0x3; 508 l2siz_field = (cache_ctl >> 28) & 0x3;
461 509
462 switch (l2siz_field) { 510 switch (l2siz_field) {
463 case 0x0: 511 case 0x0:
464 printf(" unknown size (0x%08x)\n", cache_ctl); 512 printf(" unknown size (0x%08x)\n", cache_ctl);
465 return -1; 513 return -1;
466 break; 514 break;
467 case 0x1: 515 case 0x1:
468 if (ver == SVR_8540 || ver == SVR_8560 || 516 if (ver == SVR_8540 || ver == SVR_8560 ||
469 ver == SVR_8541 || ver == SVR_8555) { 517 ver == SVR_8541 || ver == SVR_8555) {
470 puts("128 KiB "); 518 puts("128 KiB ");
471 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */ 519 /* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
472 cache_ctl = 0xc4000000; 520 cache_ctl = 0xc4000000;
473 } else { 521 } else {
474 puts("256 KiB "); 522 puts("256 KiB ");
475 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ 523 cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
476 } 524 }
477 break; 525 break;
478 case 0x2: 526 case 0x2:
479 if (ver == SVR_8540 || ver == SVR_8560 || 527 if (ver == SVR_8540 || ver == SVR_8560 ||
480 ver == SVR_8541 || ver == SVR_8555) { 528 ver == SVR_8541 || ver == SVR_8555) {
481 puts("256 KiB "); 529 puts("256 KiB ");
482 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */ 530 /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
483 cache_ctl = 0xc8000000; 531 cache_ctl = 0xc8000000;
484 } else { 532 } else {
485 puts("512 KiB "); 533 puts("512 KiB ");
486 /* set L2E=1, L2I=1, & L2SRAM=0 */ 534 /* set L2E=1, L2I=1, & L2SRAM=0 */
487 cache_ctl = 0xc0000000; 535 cache_ctl = 0xc0000000;
488 } 536 }
489 break; 537 break;
490 case 0x3: 538 case 0x3:
491 puts("1024 KiB "); 539 puts("1024 KiB ");
492 /* set L2E=1, L2I=1, & L2SRAM=0 */ 540 /* set L2E=1, L2I=1, & L2SRAM=0 */
493 cache_ctl = 0xc0000000; 541 cache_ctl = 0xc0000000;
494 break; 542 break;
495 } 543 }
496 544
497 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) { 545 if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
498 puts("already enabled"); 546 puts("already enabled");
499 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE) 547 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
500 u32 l2srbar = l2cache->l2srbar0; 548 u32 l2srbar = l2cache->l2srbar0;
501 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE 549 if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
502 && l2srbar >= CONFIG_SYS_FLASH_BASE) { 550 && l2srbar >= CONFIG_SYS_FLASH_BASE) {
503 l2srbar = CONFIG_SYS_INIT_L2_ADDR; 551 l2srbar = CONFIG_SYS_INIT_L2_ADDR;
504 l2cache->l2srbar0 = l2srbar; 552 l2cache->l2srbar0 = l2srbar;
505 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR); 553 printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
506 } 554 }
507 #endif /* CONFIG_SYS_INIT_L2_ADDR */ 555 #endif /* CONFIG_SYS_INIT_L2_ADDR */
508 puts("\n"); 556 puts("\n");
509 } else { 557 } else {
510 asm("msync;isync"); 558 asm("msync;isync");
511 l2cache->l2ctl = cache_ctl; /* invalidate & enable */ 559 l2cache->l2ctl = cache_ctl; /* invalidate & enable */
512 asm("msync;isync"); 560 asm("msync;isync");
513 puts("enabled\n"); 561 puts("enabled\n");
514 } 562 }
515 #elif defined(CONFIG_BACKSIDE_L2_CACHE) 563 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
516 if (SVR_SOC_VER(svr) == SVR_P2040) { 564 if (SVR_SOC_VER(svr) == SVR_P2040) {
517 puts("N/A\n"); 565 puts("N/A\n");
518 goto skip_l2; 566 goto skip_l2;
519 } 567 }
520 568
521 u32 l2cfg0 = mfspr(SPRN_L2CFG0); 569 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
522 570
523 /* invalidate the L2 cache */ 571 /* invalidate the L2 cache */
524 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); 572 mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
525 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) 573 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
526 ; 574 ;
527 575
528 #ifdef CONFIG_SYS_CACHE_STASHING 576 #ifdef CONFIG_SYS_CACHE_STASHING
529 /* set stash id to (coreID) * 2 + 32 + L2 (1) */ 577 /* set stash id to (coreID) * 2 + 32 + L2 (1) */
530 mtspr(SPRN_L2CSR1, (32 + 1)); 578 mtspr(SPRN_L2CSR1, (32 + 1));
531 #endif 579 #endif
532 580
533 /* enable the cache */ 581 /* enable the cache */
534 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); 582 mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
535 583
536 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) { 584 if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
537 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) 585 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
538 ; 586 ;
539 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n"); 587 print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
540 } 588 }
541 589
542 skip_l2: 590 skip_l2:
543 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) 591 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
544 if (l2cache->l2csr0 & L2CSR0_L2E) 592 if (l2cache->l2csr0 & L2CSR0_L2E)
545 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024, 593 print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
546 " enabled\n"); 594 " enabled\n");
547 595
548 enable_cluster_l2(); 596 enable_cluster_l2();
549 #else 597 #else
550 puts("disabled\n"); 598 puts("disabled\n");
551 #endif 599 #endif
552 600
553 enable_cpc(); 601 enable_cpc();
554 602
555 #ifndef CONFIG_SYS_FSL_NO_SERDES 603 #ifndef CONFIG_SYS_FSL_NO_SERDES
556 /* needs to be in ram since code uses global static vars */ 604 /* needs to be in ram since code uses global static vars */
557 fsl_serdes_init(); 605 fsl_serdes_init();
558 #endif 606 #endif
559 607
560 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 608 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
561 #define MCFGR_AXIPIPE 0x000000f0 609 #define MCFGR_AXIPIPE 0x000000f0
562 if (IS_SVR_REV(svr, 1, 0)) 610 if (IS_SVR_REV(svr, 1, 0))
563 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE); 611 clrbits_be32(&sec->mcfgr, MCFGR_AXIPIPE);
564 #endif 612 #endif
565 613
566 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871 614 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
567 if (IS_SVR_REV(svr, 1, 0)) { 615 if (IS_SVR_REV(svr, 1, 0)) {
568 int i; 616 int i;
569 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c; 617 __be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
570 618
571 for (i = 0; i < 12; i++) { 619 for (i = 0; i < 12; i++) {
572 p += i + (i > 5 ? 11 : 0); 620 p += i + (i > 5 ? 11 : 0);
573 out_be32(p, 0x2); 621 out_be32(p, 0x2);
574 } 622 }
575 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108; 623 p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
576 out_be32(p, 0x34); 624 out_be32(p, 0x34);
577 } 625 }
578 #endif 626 #endif
579 627
580 #ifdef CONFIG_SYS_SRIO 628 #ifdef CONFIG_SYS_SRIO
581 srio_init(); 629 srio_init();
582 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER 630 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
583 char *s = getenv("bootmaster"); 631 char *s = getenv("bootmaster");
584 if (s) { 632 if (s) {
585 if (!strcmp(s, "SRIO1")) { 633 if (!strcmp(s, "SRIO1")) {
586 srio_boot_master(1); 634 srio_boot_master(1);
587 srio_boot_master_release_slave(1); 635 srio_boot_master_release_slave(1);
588 } 636 }
589 if (!strcmp(s, "SRIO2")) { 637 if (!strcmp(s, "SRIO2")) {
590 srio_boot_master(2); 638 srio_boot_master(2);
591 srio_boot_master_release_slave(2); 639 srio_boot_master_release_slave(2);
592 } 640 }
593 } 641 }
594 #endif 642 #endif
595 #endif 643 #endif
596 644
597 #if defined(CONFIG_MP) 645 #if defined(CONFIG_MP)
598 setup_mp(); 646 setup_mp();
599 #endif 647 #endif
600 648
601 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13 649 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
602 { 650 {
603 if (SVR_MAJ(svr) < 3) { 651 if (SVR_MAJ(svr) < 3) {
604 void *p; 652 void *p;
605 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520; 653 p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
606 setbits_be32(p, 1 << (31 - 14)); 654 setbits_be32(p, 1 << (31 - 14));
607 } 655 }
608 } 656 }
609 #endif 657 #endif
610 658
611 #ifdef CONFIG_SYS_LBC_LCRR 659 #ifdef CONFIG_SYS_LBC_LCRR
612 /* 660 /*
613 * Modify the CLKDIV field of LCRR register to improve the writing 661 * Modify the CLKDIV field of LCRR register to improve the writing
614 * speed for NOR flash. 662 * speed for NOR flash.
615 */ 663 */
616 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR); 664 clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
617 __raw_readl(&lbc->lcrr); 665 __raw_readl(&lbc->lcrr);
618 isync(); 666 isync();
619 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 667 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
620 udelay(100); 668 udelay(100);
621 #endif 669 #endif
622 #endif 670 #endif
623 671
624 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE 672 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
625 { 673 {
626 struct ccsr_usb_phy __iomem *usb_phy1 = 674 struct ccsr_usb_phy __iomem *usb_phy1 =
627 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 675 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
676 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
677 if (has_erratum_a006261())
678 fsl_erratum_a006261_workaround(usb_phy1);
679 #endif
628 out_be32(&usb_phy1->usb_enable_override, 680 out_be32(&usb_phy1->usb_enable_override,
629 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 681 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
630 } 682 }
631 #endif 683 #endif
632 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE 684 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
633 { 685 {
634 struct ccsr_usb_phy __iomem *usb_phy2 = 686 struct ccsr_usb_phy __iomem *usb_phy2 =
635 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; 687 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
688 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
689 if (has_erratum_a006261())
690 fsl_erratum_a006261_workaround(usb_phy2);
691 #endif
636 out_be32(&usb_phy2->usb_enable_override, 692 out_be32(&usb_phy2->usb_enable_override,
637 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); 693 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
638 } 694 }
639 #endif 695 #endif
640 696
641 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14 697 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
642 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal 698 /* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
643 * multi-bit ECC errors which has impact on performance, so software 699 * multi-bit ECC errors which has impact on performance, so software
644 * should disable all ECC reporting from USB1 and USB2. 700 * should disable all ECC reporting from USB1 and USB2.
645 */ 701 */
646 if (IS_SVR_REV(get_svr(), 1, 0)) { 702 if (IS_SVR_REV(get_svr(), 1, 0)) {
647 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *) 703 struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
648 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET); 704 (CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
649 setbits_be32(&dcfg->ecccr1, 705 setbits_be32(&dcfg->ecccr1,
650 (DCSR_DCFG_ECC_DISABLE_USB1 | 706 (DCSR_DCFG_ECC_DISABLE_USB1 |
651 DCSR_DCFG_ECC_DISABLE_USB2)); 707 DCSR_DCFG_ECC_DISABLE_USB2));
652 } 708 }
653 #endif 709 #endif
654 710
655 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) 711 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
656 struct ccsr_usb_phy __iomem *usb_phy = 712 struct ccsr_usb_phy __iomem *usb_phy =
657 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; 713 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
658 setbits_be32(&usb_phy->pllprg[1], 714 setbits_be32(&usb_phy->pllprg[1],
659 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | 715 CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
660 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | 716 CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
661 CONFIG_SYS_FSL_USB_PLLPRG2_MFI | 717 CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
662 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); 718 CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
663 setbits_be32(&usb_phy->port1.ctrl, 719 setbits_be32(&usb_phy->port1.ctrl,
664 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 720 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
665 setbits_be32(&usb_phy->port1.drvvbuscfg, 721 setbits_be32(&usb_phy->port1.drvvbuscfg,
666 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 722 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
667 setbits_be32(&usb_phy->port1.pwrfltcfg, 723 setbits_be32(&usb_phy->port1.pwrfltcfg,
668 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 724 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
669 setbits_be32(&usb_phy->port2.ctrl, 725 setbits_be32(&usb_phy->port2.ctrl,
670 CONFIG_SYS_FSL_USB_CTRL_PHY_EN); 726 CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
671 setbits_be32(&usb_phy->port2.drvvbuscfg, 727 setbits_be32(&usb_phy->port2.drvvbuscfg,
672 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); 728 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
673 setbits_be32(&usb_phy->port2.pwrfltcfg, 729 setbits_be32(&usb_phy->port2.pwrfltcfg,
674 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); 730 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
731
732 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
733 if (has_erratum_a006261())
734 fsl_erratum_a006261_workaround(usb_phy);
675 #endif 735 #endif
736
737 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
676 738
677 #ifdef CONFIG_FMAN_ENET 739 #ifdef CONFIG_FMAN_ENET
678 fman_enet_init(); 740 fman_enet_init();
679 #endif 741 #endif
680 742
681 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) 743 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
682 /* 744 /*
683 * For P1022/1013 Rev1.0 silicon, after power on SATA host 745 * For P1022/1013 Rev1.0 silicon, after power on SATA host
684 * controller is configured in legacy mode instead of the 746 * controller is configured in legacy mode instead of the
685 * expected enterprise mode. Software needs to clear bit[28] 747 * expected enterprise mode. Software needs to clear bit[28]
686 * of HControl register to change to enterprise mode from 748 * of HControl register to change to enterprise mode from
687 * legacy mode. We assume that the controller is offline. 749 * legacy mode. We assume that the controller is offline.
688 */ 750 */
689 if (IS_SVR_REV(svr, 1, 0) && 751 if (IS_SVR_REV(svr, 1, 0) &&
690 ((SVR_SOC_VER(svr) == SVR_P1022) || 752 ((SVR_SOC_VER(svr) == SVR_P1022) ||
691 (SVR_SOC_VER(svr) == SVR_P1013))) { 753 (SVR_SOC_VER(svr) == SVR_P1013))) {
692 fsl_sata_reg_t *reg; 754 fsl_sata_reg_t *reg;
693 755
694 /* first SATA controller */ 756 /* first SATA controller */
695 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; 757 reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
696 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN); 758 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
697 759
698 /* second SATA controller */ 760 /* second SATA controller */
699 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; 761 reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
700 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN); 762 clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
701 } 763 }
702 #endif 764 #endif
703 765
704 766
705 return 0; 767 return 0;
706 } 768 }
707 769
708 extern void setup_ivors(void); 770 extern void setup_ivors(void);
709 771
710 void arch_preboot_os(void) 772 void arch_preboot_os(void)
711 { 773 {
712 u32 msr; 774 u32 msr;
713 775
714 /* 776 /*
715 * We are changing interrupt offsets and are about to boot the OS so 777 * We are changing interrupt offsets and are about to boot the OS so
716 * we need to make sure we disable all async interrupts. EE is already 778 * we need to make sure we disable all async interrupts. EE is already
717 * disabled by the time we get called. 779 * disabled by the time we get called.
718 */ 780 */
719 msr = mfmsr(); 781 msr = mfmsr();
720 msr &= ~(MSR_ME|MSR_CE); 782 msr &= ~(MSR_ME|MSR_CE);
721 mtmsr(msr); 783 mtmsr(msr);
722 784
723 setup_ivors(); 785 setup_ivors();
724 } 786 }
725 787
726 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA) 788 #if defined(CONFIG_CMD_SATA) && defined(CONFIG_FSL_SATA)
727 int sata_initialize(void) 789 int sata_initialize(void)
728 { 790 {
729 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2)) 791 if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
730 return __sata_initialize(); 792 return __sata_initialize();
731 793
732 return 1; 794 return 1;
733 } 795 }
734 #endif 796 #endif
735 797
736 void cpu_secondary_init_r(void) 798 void cpu_secondary_init_r(void)
737 { 799 {
738 #ifdef CONFIG_QE 800 #ifdef CONFIG_QE
739 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */ 801 uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
740 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND 802 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
741 int ret; 803 int ret;
742 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH; 804 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
743 805
744 /* load QE firmware from NAND flash to DDR first */ 806 /* load QE firmware from NAND flash to DDR first */
745 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND, 807 ret = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_QE_FMAN_FW_IN_NAND,
746 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR); 808 &fw_length, (u_char *)CONFIG_SYS_QE_FMAN_FW_ADDR);
747 809
748 if (ret && ret == -EUCLEAN) { 810 if (ret && ret == -EUCLEAN) {
749 printf ("NAND read for QE firmware at offset %x failed %d\n", 811 printf ("NAND read for QE firmware at offset %x failed %d\n",
750 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret); 812 CONFIG_SYS_QE_FMAN_FW_IN_NAND, ret);
751 } 813 }
752 #endif 814 #endif
753 qe_init(qe_base); 815 qe_init(qe_base);
754 qe_reset(); 816 qe_reset();
755 #endif 817 #endif
756 } 818 }
757 819
arch/powerpc/include/asm/config_mpc85xx.h
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef _ASM_MPC85xx_CONFIG_H_ 7 #ifndef _ASM_MPC85xx_CONFIG_H_
8 #define _ASM_MPC85xx_CONFIG_H_ 8 #define _ASM_MPC85xx_CONFIG_H_
9 9
10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */ 10 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
11 11
12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT 12 #ifdef CONFIG_SYS_CCSRBAR_DEFAULT
13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file." 13 #error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
14 #endif 14 #endif
15 15
16 /* 16 /*
17 * This macro should be removed when we no longer care about backwards 17 * This macro should be removed when we no longer care about backwards
18 * compatibility with older operating systems. 18 * compatibility with older operating systems.
19 */ 19 */
20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE 20 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
21 21
22 #define FSL_DDR_VER_4_7 47 22 #define FSL_DDR_VER_4_7 47
23 #define FSL_DDR_VER_5_0 50 23 #define FSL_DDR_VER_5_0 50
24 24
25 /* IP endianness */ 25 /* IP endianness */
26 #define CONFIG_SYS_FSL_IFC_BE 26 #define CONFIG_SYS_FSL_IFC_BE
27 27
28 /* Number of TLB CAM entries we have on FSL Book-E chips */ 28 /* Number of TLB CAM entries we have on FSL Book-E chips */
29 #if defined(CONFIG_E500MC) 29 #if defined(CONFIG_E500MC)
30 #define CONFIG_SYS_NUM_TLBCAMS 64 30 #define CONFIG_SYS_NUM_TLBCAMS 64
31 #elif defined(CONFIG_E500) 31 #elif defined(CONFIG_E500)
32 #define CONFIG_SYS_NUM_TLBCAMS 16 32 #define CONFIG_SYS_NUM_TLBCAMS 16
33 #endif 33 #endif
34 34
35 #if defined(CONFIG_MPC8536) 35 #if defined(CONFIG_MPC8536)
36 #define CONFIG_MAX_CPUS 1 36 #define CONFIG_MAX_CPUS 1
37 #define CONFIG_SYS_FSL_NUM_LAWS 12 37 #define CONFIG_SYS_FSL_NUM_LAWS 12
38 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1 38 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
39 #define CONFIG_SYS_FSL_SEC_COMPAT 2 39 #define CONFIG_SYS_FSL_SEC_COMPAT 2
40 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 40 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
41 #define CONFIG_SYS_FSL_ERRATUM_A005125 41 #define CONFIG_SYS_FSL_ERRATUM_A005125
42 42
43 #elif defined(CONFIG_MPC8540) 43 #elif defined(CONFIG_MPC8540)
44 #define CONFIG_MAX_CPUS 1 44 #define CONFIG_MAX_CPUS 1
45 #define CONFIG_SYS_FSL_NUM_LAWS 8 45 #define CONFIG_SYS_FSL_NUM_LAWS 8
46 #define CONFIG_SYS_FSL_DDRC_GEN1 46 #define CONFIG_SYS_FSL_DDRC_GEN1
47 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 47 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
48 48
49 #elif defined(CONFIG_MPC8541) 49 #elif defined(CONFIG_MPC8541)
50 #define CONFIG_MAX_CPUS 1 50 #define CONFIG_MAX_CPUS 1
51 #define CONFIG_SYS_FSL_NUM_LAWS 8 51 #define CONFIG_SYS_FSL_NUM_LAWS 8
52 #define CONFIG_SYS_FSL_DDRC_GEN1 52 #define CONFIG_SYS_FSL_DDRC_GEN1
53 #define CONFIG_SYS_FSL_SEC_COMPAT 2 53 #define CONFIG_SYS_FSL_SEC_COMPAT 2
54 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 54 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
55 55
56 #elif defined(CONFIG_MPC8544) 56 #elif defined(CONFIG_MPC8544)
57 #define CONFIG_MAX_CPUS 1 57 #define CONFIG_MAX_CPUS 1
58 #define CONFIG_SYS_FSL_NUM_LAWS 10 58 #define CONFIG_SYS_FSL_NUM_LAWS 10
59 #define CONFIG_SYS_FSL_DDRC_GEN2 59 #define CONFIG_SYS_FSL_DDRC_GEN2
60 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 60 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
61 #define CONFIG_SYS_FSL_SEC_COMPAT 2 61 #define CONFIG_SYS_FSL_SEC_COMPAT 2
62 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 62 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
63 #define CONFIG_SYS_FSL_ERRATUM_A005125 63 #define CONFIG_SYS_FSL_ERRATUM_A005125
64 64
65 #elif defined(CONFIG_MPC8548) 65 #elif defined(CONFIG_MPC8548)
66 #define CONFIG_MAX_CPUS 1 66 #define CONFIG_MAX_CPUS 1
67 #define CONFIG_SYS_FSL_NUM_LAWS 10 67 #define CONFIG_SYS_FSL_NUM_LAWS 10
68 #define CONFIG_SYS_FSL_DDRC_GEN2 68 #define CONFIG_SYS_FSL_DDRC_GEN2
69 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0 69 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
70 #define CONFIG_SYS_FSL_SEC_COMPAT 2 70 #define CONFIG_SYS_FSL_SEC_COMPAT 2
71 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 71 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
72 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120 72 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
73 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103 73 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
74 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 74 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
75 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 75 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
76 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 76 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
77 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 77 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
78 #define CONFIG_SYS_FSL_RMU 78 #define CONFIG_SYS_FSL_RMU
79 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 79 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
80 #define CONFIG_SYS_FSL_ERRATUM_A005125 80 #define CONFIG_SYS_FSL_ERRATUM_A005125
81 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 81 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
82 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00 82 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x00
83 83
84 #elif defined(CONFIG_MPC8555) 84 #elif defined(CONFIG_MPC8555)
85 #define CONFIG_MAX_CPUS 1 85 #define CONFIG_MAX_CPUS 1
86 #define CONFIG_SYS_FSL_NUM_LAWS 8 86 #define CONFIG_SYS_FSL_NUM_LAWS 8
87 #define CONFIG_SYS_FSL_DDRC_GEN1 87 #define CONFIG_SYS_FSL_DDRC_GEN1
88 #define CONFIG_SYS_FSL_SEC_COMPAT 2 88 #define CONFIG_SYS_FSL_SEC_COMPAT 2
89 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 89 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
90 90
91 #elif defined(CONFIG_MPC8560) 91 #elif defined(CONFIG_MPC8560)
92 #define CONFIG_MAX_CPUS 1 92 #define CONFIG_MAX_CPUS 1
93 #define CONFIG_SYS_FSL_NUM_LAWS 8 93 #define CONFIG_SYS_FSL_NUM_LAWS 8
94 #define CONFIG_SYS_FSL_DDRC_GEN1 94 #define CONFIG_SYS_FSL_DDRC_GEN1
95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 95 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
96 96
97 #elif defined(CONFIG_MPC8568) 97 #elif defined(CONFIG_MPC8568)
98 #define CONFIG_MAX_CPUS 1 98 #define CONFIG_MAX_CPUS 1
99 #define CONFIG_SYS_FSL_NUM_LAWS 10 99 #define CONFIG_SYS_FSL_NUM_LAWS 10
100 #define CONFIG_SYS_FSL_DDRC_GEN2 100 #define CONFIG_SYS_FSL_DDRC_GEN2
101 #define CONFIG_SYS_FSL_SEC_COMPAT 2 101 #define CONFIG_SYS_FSL_SEC_COMPAT 2
102 #define QE_MURAM_SIZE 0x10000UL 102 #define QE_MURAM_SIZE 0x10000UL
103 #define MAX_QE_RISC 2 103 #define MAX_QE_RISC 2
104 #define QE_NUM_OF_SNUM 28 104 #define QE_NUM_OF_SNUM 28
105 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 105 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
106 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 106 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
107 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 107 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
108 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 108 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
109 #define CONFIG_SYS_FSL_RMU 109 #define CONFIG_SYS_FSL_RMU
110 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 110 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
111 111
112 #elif defined(CONFIG_MPC8569) 112 #elif defined(CONFIG_MPC8569)
113 #define CONFIG_MAX_CPUS 1 113 #define CONFIG_MAX_CPUS 1
114 #define CONFIG_SYS_FSL_NUM_LAWS 10 114 #define CONFIG_SYS_FSL_NUM_LAWS 10
115 #define CONFIG_SYS_FSL_SEC_COMPAT 2 115 #define CONFIG_SYS_FSL_SEC_COMPAT 2
116 #define QE_MURAM_SIZE 0x20000UL 116 #define QE_MURAM_SIZE 0x20000UL
117 #define MAX_QE_RISC 4 117 #define MAX_QE_RISC 4
118 #define QE_NUM_OF_SNUM 46 118 #define QE_NUM_OF_SNUM 46
119 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 119 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
120 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 120 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
121 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 121 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
122 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 122 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
123 #define CONFIG_SYS_FSL_RMU 123 #define CONFIG_SYS_FSL_RMU
124 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 124 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
125 #define CONFIG_SYS_FSL_ERRATUM_A005125 125 #define CONFIG_SYS_FSL_ERRATUM_A005125
126 126
127 #elif defined(CONFIG_MPC8572) 127 #elif defined(CONFIG_MPC8572)
128 #define CONFIG_MAX_CPUS 2 128 #define CONFIG_MAX_CPUS 2
129 #define CONFIG_SYS_FSL_NUM_LAWS 12 129 #define CONFIG_SYS_FSL_NUM_LAWS 12
130 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 130 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
131 #define CONFIG_SYS_FSL_SEC_COMPAT 2 131 #define CONFIG_SYS_FSL_SEC_COMPAT 2
132 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 132 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
133 #define CONFIG_SYS_FSL_ERRATUM_DDR_115 133 #define CONFIG_SYS_FSL_ERRATUM_DDR_115
134 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 134 #define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
135 #define CONFIG_SYS_FSL_ERRATUM_A005125 135 #define CONFIG_SYS_FSL_ERRATUM_A005125
136 136
137 #elif defined(CONFIG_P1010) 137 #elif defined(CONFIG_P1010)
138 #define CONFIG_MAX_CPUS 1 138 #define CONFIG_MAX_CPUS 1
139 #define CONFIG_FSL_SDHC_V2_3 139 #define CONFIG_FSL_SDHC_V2_3
140 #define CONFIG_SYS_FSL_NUM_LAWS 12 140 #define CONFIG_SYS_FSL_NUM_LAWS 12
141 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 141 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
142 #define CONFIG_TSECV2 142 #define CONFIG_TSECV2
143 #define CONFIG_SYS_FSL_SEC_COMPAT 4 143 #define CONFIG_SYS_FSL_SEC_COMPAT 4
144 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 144 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
145 #define CONFIG_NUM_DDR_CONTROLLERS 1 145 #define CONFIG_NUM_DDR_CONTROLLERS 1
146 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 146 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
147 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 147 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
148 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 148 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
149 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 149 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
150 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 150 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
151 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 151 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
152 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 152 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
153 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571 153 #define CONFIG_SYS_FSL_ERRATUM_SEC_A003571
154 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 154 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
155 #define CONFIG_SYS_FSL_ERRATUM_A005125 155 #define CONFIG_SYS_FSL_ERRATUM_A005125
156 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 156 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
157 #define CONFIG_SYS_FSL_ERRATUM_A006261
157 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10 158 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
158 #define CONFIG_ESDHC_HC_BLK_ADDR 159 #define CONFIG_ESDHC_HC_BLK_ADDR
159 160
160 /* P1011 is single core version of P1020 */ 161 /* P1011 is single core version of P1020 */
161 #elif defined(CONFIG_P1011) 162 #elif defined(CONFIG_P1011)
162 #define CONFIG_MAX_CPUS 1 163 #define CONFIG_MAX_CPUS 1
163 #define CONFIG_SYS_FSL_NUM_LAWS 12 164 #define CONFIG_SYS_FSL_NUM_LAWS 12
164 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 165 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
165 #define CONFIG_TSECV2 166 #define CONFIG_TSECV2
166 #define CONFIG_FSL_PCIE_DISABLE_ASPM 167 #define CONFIG_FSL_PCIE_DISABLE_ASPM
167 #define CONFIG_SYS_FSL_SEC_COMPAT 2 168 #define CONFIG_SYS_FSL_SEC_COMPAT 2
168 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 169 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
169 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 170 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
170 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 171 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
171 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 172 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
172 #define CONFIG_SYS_FSL_ERRATUM_A005125 173 #define CONFIG_SYS_FSL_ERRATUM_A005125
173 174
174 /* P1012 is single core version of P1021 */ 175 /* P1012 is single core version of P1021 */
175 #elif defined(CONFIG_P1012) 176 #elif defined(CONFIG_P1012)
176 #define CONFIG_MAX_CPUS 1 177 #define CONFIG_MAX_CPUS 1
177 #define CONFIG_SYS_FSL_NUM_LAWS 12 178 #define CONFIG_SYS_FSL_NUM_LAWS 12
178 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 179 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
179 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 180 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
180 #define CONFIG_TSECV2 181 #define CONFIG_TSECV2
181 #define CONFIG_FSL_PCIE_DISABLE_ASPM 182 #define CONFIG_FSL_PCIE_DISABLE_ASPM
182 #define CONFIG_SYS_FSL_SEC_COMPAT 2 183 #define CONFIG_SYS_FSL_SEC_COMPAT 2
183 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 184 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
184 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 185 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
185 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 186 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
186 #define QE_MURAM_SIZE 0x6000UL 187 #define QE_MURAM_SIZE 0x6000UL
187 #define MAX_QE_RISC 1 188 #define MAX_QE_RISC 1
188 #define QE_NUM_OF_SNUM 28 189 #define QE_NUM_OF_SNUM 28
189 #define CONFIG_SYS_FSL_ERRATUM_A005125 190 #define CONFIG_SYS_FSL_ERRATUM_A005125
190 191
191 /* P1013 is single core version of P1022 */ 192 /* P1013 is single core version of P1022 */
192 #elif defined(CONFIG_P1013) 193 #elif defined(CONFIG_P1013)
193 #define CONFIG_MAX_CPUS 1 194 #define CONFIG_MAX_CPUS 1
194 #define CONFIG_SYS_FSL_NUM_LAWS 12 195 #define CONFIG_SYS_FSL_NUM_LAWS 12
195 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 196 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
196 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 197 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
197 #define CONFIG_TSECV2 198 #define CONFIG_TSECV2
198 #define CONFIG_SYS_FSL_SEC_COMPAT 2 199 #define CONFIG_SYS_FSL_SEC_COMPAT 2
199 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 200 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
200 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 201 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
201 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 202 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
202 #define CONFIG_FSL_SATA_ERRATUM_A001 203 #define CONFIG_FSL_SATA_ERRATUM_A001
203 #define CONFIG_SYS_FSL_ERRATUM_A005125 204 #define CONFIG_SYS_FSL_ERRATUM_A005125
204 205
205 #elif defined(CONFIG_P1014) 206 #elif defined(CONFIG_P1014)
206 #define CONFIG_MAX_CPUS 1 207 #define CONFIG_MAX_CPUS 1
207 #define CONFIG_FSL_SDHC_V2_3 208 #define CONFIG_FSL_SDHC_V2_3
208 #define CONFIG_SYS_FSL_NUM_LAWS 12 209 #define CONFIG_SYS_FSL_NUM_LAWS 12
209 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 210 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
210 #define CONFIG_TSECV2 211 #define CONFIG_TSECV2
211 #define CONFIG_SYS_FSL_SEC_COMPAT 4 212 #define CONFIG_SYS_FSL_SEC_COMPAT 4
212 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 213 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
213 #define CONFIG_NUM_DDR_CONTROLLERS 1 214 #define CONFIG_NUM_DDR_CONTROLLERS 1
214 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 215 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
215 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 216 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
216 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 217 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
217 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 218 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
218 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549 219 #define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
219 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 220 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
220 221
221 /* P1017 is single core version of P1023 */ 222 /* P1017 is single core version of P1023 */
222 #elif defined(CONFIG_P1017) 223 #elif defined(CONFIG_P1017)
223 #define CONFIG_MAX_CPUS 1 224 #define CONFIG_MAX_CPUS 1
224 #define CONFIG_SYS_FSL_NUM_LAWS 12 225 #define CONFIG_SYS_FSL_NUM_LAWS 12
225 #define CONFIG_SYS_FSL_SEC_COMPAT 4 226 #define CONFIG_SYS_FSL_SEC_COMPAT 4
226 #define CONFIG_SYS_NUM_FMAN 1 227 #define CONFIG_SYS_NUM_FMAN 1
227 #define CONFIG_SYS_NUM_FM1_DTSEC 2 228 #define CONFIG_SYS_NUM_FM1_DTSEC 2
228 #define CONFIG_NUM_DDR_CONTROLLERS 1 229 #define CONFIG_NUM_DDR_CONTROLLERS 1
229 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 230 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
230 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 231 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
231 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 232 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
232 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 233 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
233 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 234 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
234 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 235 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
235 #define CONFIG_SYS_FSL_ERRATUM_A005125 236 #define CONFIG_SYS_FSL_ERRATUM_A005125
236 237
237 #elif defined(CONFIG_P1020) 238 #elif defined(CONFIG_P1020)
238 #define CONFIG_MAX_CPUS 2 239 #define CONFIG_MAX_CPUS 2
239 #define CONFIG_SYS_FSL_NUM_LAWS 12 240 #define CONFIG_SYS_FSL_NUM_LAWS 12
240 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 241 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
241 #define CONFIG_TSECV2 242 #define CONFIG_TSECV2
242 #define CONFIG_FSL_PCIE_DISABLE_ASPM 243 #define CONFIG_FSL_PCIE_DISABLE_ASPM
243 #define CONFIG_SYS_FSL_SEC_COMPAT 2 244 #define CONFIG_SYS_FSL_SEC_COMPAT 2
244 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 245 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
245 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 246 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
246 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 247 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
247 #define CONFIG_SYS_FSL_ERRATUM_A005125 248 #define CONFIG_SYS_FSL_ERRATUM_A005125
248 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 249 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
249 250
250 #elif defined(CONFIG_P1021) 251 #elif defined(CONFIG_P1021)
251 #define CONFIG_MAX_CPUS 2 252 #define CONFIG_MAX_CPUS 2
252 #define CONFIG_SYS_FSL_NUM_LAWS 12 253 #define CONFIG_SYS_FSL_NUM_LAWS 12
253 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 254 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
254 #define CONFIG_TSECV2 255 #define CONFIG_TSECV2
255 #define CONFIG_FSL_PCIE_DISABLE_ASPM 256 #define CONFIG_FSL_PCIE_DISABLE_ASPM
256 #define CONFIG_SYS_FSL_SEC_COMPAT 2 257 #define CONFIG_SYS_FSL_SEC_COMPAT 2
257 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 258 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
258 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 259 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
259 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 260 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
260 #define QE_MURAM_SIZE 0x6000UL 261 #define QE_MURAM_SIZE 0x6000UL
261 #define MAX_QE_RISC 1 262 #define MAX_QE_RISC 1
262 #define QE_NUM_OF_SNUM 28 263 #define QE_NUM_OF_SNUM 28
263 #define CONFIG_SYS_FSL_ERRATUM_A005125 264 #define CONFIG_SYS_FSL_ERRATUM_A005125
264 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 265 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
265 266
266 #elif defined(CONFIG_P1022) 267 #elif defined(CONFIG_P1022)
267 #define CONFIG_MAX_CPUS 2 268 #define CONFIG_MAX_CPUS 2
268 #define CONFIG_SYS_FSL_NUM_LAWS 12 269 #define CONFIG_SYS_FSL_NUM_LAWS 12
269 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 270 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
270 #define CONFIG_TSECV2 271 #define CONFIG_TSECV2
271 #define CONFIG_SYS_FSL_SEC_COMPAT 2 272 #define CONFIG_SYS_FSL_SEC_COMPAT 2
272 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 273 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
273 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 274 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
274 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 275 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
275 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 276 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
276 #define CONFIG_FSL_SATA_ERRATUM_A001 277 #define CONFIG_FSL_SATA_ERRATUM_A001
277 #define CONFIG_SYS_FSL_ERRATUM_A005125 278 #define CONFIG_SYS_FSL_ERRATUM_A005125
278 279
279 #elif defined(CONFIG_P1023) 280 #elif defined(CONFIG_P1023)
280 #define CONFIG_MAX_CPUS 2 281 #define CONFIG_MAX_CPUS 2
281 #define CONFIG_SYS_FSL_NUM_LAWS 12 282 #define CONFIG_SYS_FSL_NUM_LAWS 12
282 #define CONFIG_SYS_FSL_SEC_COMPAT 4 283 #define CONFIG_SYS_FSL_SEC_COMPAT 4
283 #define CONFIG_SYS_NUM_FMAN 1 284 #define CONFIG_SYS_NUM_FMAN 1
284 #define CONFIG_SYS_NUM_FM1_DTSEC 2 285 #define CONFIG_SYS_NUM_FM1_DTSEC 2
285 #define CONFIG_NUM_DDR_CONTROLLERS 1 286 #define CONFIG_NUM_DDR_CONTROLLERS 1
286 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 287 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
287 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 288 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
288 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 289 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
289 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 290 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
290 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 291 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
291 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000 292 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
292 #define CONFIG_SYS_FSL_ERRATUM_A005125 293 #define CONFIG_SYS_FSL_ERRATUM_A005125
293 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 294 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
294 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 295 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
295 296
296 /* P1024 is lower end variant of P1020 */ 297 /* P1024 is lower end variant of P1020 */
297 #elif defined(CONFIG_P1024) 298 #elif defined(CONFIG_P1024)
298 #define CONFIG_MAX_CPUS 2 299 #define CONFIG_MAX_CPUS 2
299 #define CONFIG_SYS_FSL_NUM_LAWS 12 300 #define CONFIG_SYS_FSL_NUM_LAWS 12
300 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 301 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
301 #define CONFIG_TSECV2 302 #define CONFIG_TSECV2
302 #define CONFIG_FSL_PCIE_DISABLE_ASPM 303 #define CONFIG_FSL_PCIE_DISABLE_ASPM
303 #define CONFIG_SYS_FSL_SEC_COMPAT 2 304 #define CONFIG_SYS_FSL_SEC_COMPAT 2
304 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 305 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
305 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 306 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
306 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 307 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
307 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 308 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
308 #define CONFIG_SYS_FSL_ERRATUM_A005125 309 #define CONFIG_SYS_FSL_ERRATUM_A005125
309 310
310 /* P1025 is lower end variant of P1021 */ 311 /* P1025 is lower end variant of P1021 */
311 #elif defined(CONFIG_P1025) 312 #elif defined(CONFIG_P1025)
312 #define CONFIG_MAX_CPUS 2 313 #define CONFIG_MAX_CPUS 2
313 #define CONFIG_SYS_FSL_NUM_LAWS 12 314 #define CONFIG_SYS_FSL_NUM_LAWS 12
314 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 315 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
315 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 316 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
316 #define CONFIG_TSECV2 317 #define CONFIG_TSECV2
317 #define CONFIG_FSL_PCIE_DISABLE_ASPM 318 #define CONFIG_FSL_PCIE_DISABLE_ASPM
318 #define CONFIG_SYS_FSL_SEC_COMPAT 2 319 #define CONFIG_SYS_FSL_SEC_COMPAT 2
319 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 320 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
320 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 321 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
321 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 322 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
322 #define QE_MURAM_SIZE 0x6000UL 323 #define QE_MURAM_SIZE 0x6000UL
323 #define MAX_QE_RISC 1 324 #define MAX_QE_RISC 1
324 #define QE_NUM_OF_SNUM 28 325 #define QE_NUM_OF_SNUM 28
325 #define CONFIG_SYS_FSL_ERRATUM_A005125 326 #define CONFIG_SYS_FSL_ERRATUM_A005125
326 327
327 /* P2010 is single core version of P2020 */ 328 /* P2010 is single core version of P2020 */
328 #elif defined(CONFIG_P2010) 329 #elif defined(CONFIG_P2010)
329 #define CONFIG_MAX_CPUS 1 330 #define CONFIG_MAX_CPUS 1
330 #define CONFIG_SYS_FSL_NUM_LAWS 12 331 #define CONFIG_SYS_FSL_NUM_LAWS 12
331 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 332 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
332 #define CONFIG_SYS_FSL_SEC_COMPAT 2 333 #define CONFIG_SYS_FSL_SEC_COMPAT 2
333 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 334 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
334 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 335 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
335 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 336 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
336 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 337 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
337 #define CONFIG_SYS_FSL_ERRATUM_A005125 338 #define CONFIG_SYS_FSL_ERRATUM_A005125
338 339
339 #elif defined(CONFIG_P2020) 340 #elif defined(CONFIG_P2020)
340 #define CONFIG_MAX_CPUS 2 341 #define CONFIG_MAX_CPUS 2
341 #define CONFIG_SYS_FSL_NUM_LAWS 12 342 #define CONFIG_SYS_FSL_NUM_LAWS 12
342 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 343 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
343 #define CONFIG_SYS_FSL_SEC_COMPAT 2 344 #define CONFIG_SYS_FSL_SEC_COMPAT 2
344 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 345 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
345 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 346 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
346 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 347 #define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
347 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 348 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
348 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 349 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
349 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 350 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
350 #define CONFIG_SYS_FSL_RMU 351 #define CONFIG_SYS_FSL_RMU
351 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 352 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
352 #define CONFIG_SYS_FSL_ERRATUM_A005125 353 #define CONFIG_SYS_FSL_ERRATUM_A005125
353 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 354 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
354 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */ 355 #elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
355 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 356 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
356 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 357 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
357 #define CONFIG_MAX_CPUS 4 358 #define CONFIG_MAX_CPUS 4
358 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 359 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
359 #define CONFIG_SYS_FSL_NUM_LAWS 32 360 #define CONFIG_SYS_FSL_NUM_LAWS 32
360 #define CONFIG_SYS_FSL_SEC_COMPAT 4 361 #define CONFIG_SYS_FSL_SEC_COMPAT 4
361 #define CONFIG_SYS_NUM_FMAN 1 362 #define CONFIG_SYS_NUM_FMAN 1
362 #define CONFIG_SYS_NUM_FM1_DTSEC 5 363 #define CONFIG_SYS_NUM_FM1_DTSEC 5
363 #define CONFIG_SYS_NUM_FM1_10GEC 1 364 #define CONFIG_SYS_NUM_FM1_10GEC 1
364 #define CONFIG_NUM_DDR_CONTROLLERS 1 365 #define CONFIG_NUM_DDR_CONTROLLERS 1
365 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 366 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
366 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 367 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
367 #define CONFIG_SYS_FSL_TBCLK_DIV 32 368 #define CONFIG_SYS_FSL_TBCLK_DIV 32
368 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 369 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
369 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 370 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
370 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 371 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
371 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 372 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
372 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 373 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
373 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 374 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
374 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 375 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
375 #define CONFIG_SYS_FSL_ERRATUM_USB14 376 #define CONFIG_SYS_FSL_ERRATUM_USB14
376 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 377 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
377 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 378 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
378 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 379 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
379 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 380 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
380 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 381 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
381 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 382 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
382 #define CONFIG_SYS_FSL_ERRATUM_A004510 383 #define CONFIG_SYS_FSL_ERRATUM_A004510
383 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 384 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
384 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 385 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
385 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 386 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
386 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 387 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
387 #define CONFIG_SYS_FSL_ERRATUM_A004849 388 #define CONFIG_SYS_FSL_ERRATUM_A004849
388 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 389 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
390 #define CONFIG_SYS_FSL_ERRATUM_A006261
389 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 391 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
390 392
391 #elif defined(CONFIG_PPC_P3041) 393 #elif defined(CONFIG_PPC_P3041)
392 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 394 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
393 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 395 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
394 #define CONFIG_MAX_CPUS 4 396 #define CONFIG_MAX_CPUS 4
395 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 397 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
396 #define CONFIG_SYS_FSL_NUM_LAWS 32 398 #define CONFIG_SYS_FSL_NUM_LAWS 32
397 #define CONFIG_SYS_FSL_SEC_COMPAT 4 399 #define CONFIG_SYS_FSL_SEC_COMPAT 4
398 #define CONFIG_SYS_NUM_FMAN 1 400 #define CONFIG_SYS_NUM_FMAN 1
399 #define CONFIG_SYS_NUM_FM1_DTSEC 5 401 #define CONFIG_SYS_NUM_FM1_DTSEC 5
400 #define CONFIG_SYS_NUM_FM1_10GEC 1 402 #define CONFIG_SYS_NUM_FM1_10GEC 1
401 #define CONFIG_NUM_DDR_CONTROLLERS 1 403 #define CONFIG_NUM_DDR_CONTROLLERS 1
402 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 404 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
403 #define CONFIG_SYS_FSL_TBCLK_DIV 32 405 #define CONFIG_SYS_FSL_TBCLK_DIV 32
404 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 406 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
405 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 407 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
406 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 408 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
407 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 409 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
408 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 410 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
409 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 411 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
410 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 412 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
411 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 413 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
412 #define CONFIG_SYS_FSL_ERRATUM_USB14 414 #define CONFIG_SYS_FSL_ERRATUM_USB14
413 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 415 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
414 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 416 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
415 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 417 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
416 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 418 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
417 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 419 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
418 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 420 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
419 #define CONFIG_SYS_FSL_ERRATUM_A004510 421 #define CONFIG_SYS_FSL_ERRATUM_A004510
420 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 422 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
421 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11 423 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
422 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 424 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
423 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 425 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
424 #define CONFIG_SYS_FSL_ERRATUM_A004849 426 #define CONFIG_SYS_FSL_ERRATUM_A004849
425 #define CONFIG_SYS_FSL_ERRATUM_A005812 427 #define CONFIG_SYS_FSL_ERRATUM_A005812
426 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 428 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
429 #define CONFIG_SYS_FSL_ERRATUM_A006261
427 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 430 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
428 431
429 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */ 432 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
430 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 433 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
431 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 434 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
432 #define CONFIG_MAX_CPUS 8 435 #define CONFIG_MAX_CPUS 8
433 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 436 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
434 #define CONFIG_SYS_FSL_NUM_LAWS 32 437 #define CONFIG_SYS_FSL_NUM_LAWS 32
435 #define CONFIG_SYS_FSL_SEC_COMPAT 4 438 #define CONFIG_SYS_FSL_SEC_COMPAT 4
436 #define CONFIG_SYS_NUM_FMAN 2 439 #define CONFIG_SYS_NUM_FMAN 2
437 #define CONFIG_SYS_NUM_FM1_DTSEC 4 440 #define CONFIG_SYS_NUM_FM1_DTSEC 4
438 #define CONFIG_SYS_NUM_FM2_DTSEC 4 441 #define CONFIG_SYS_NUM_FM2_DTSEC 4
439 #define CONFIG_SYS_NUM_FM1_10GEC 1 442 #define CONFIG_SYS_NUM_FM1_10GEC 1
440 #define CONFIG_SYS_NUM_FM2_10GEC 1 443 #define CONFIG_SYS_NUM_FM2_10GEC 1
441 #define CONFIG_NUM_DDR_CONTROLLERS 2 444 #define CONFIG_NUM_DDR_CONTROLLERS 2
442 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 445 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
443 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 446 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
444 #define CONFIG_SYS_FSL_TBCLK_DIV 16 447 #define CONFIG_SYS_FSL_TBCLK_DIV 16
445 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" 448 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
446 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 449 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
447 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 450 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002
448 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 451 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003
449 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 452 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
450 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 453 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
451 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 454 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
452 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135 455 #define CONFIG_SYS_FSL_ERRATUM_ESDHC135
453 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13 456 #define CONFIG_SYS_FSL_ERRATUM_ESDHC13
454 #define CONFIG_SYS_P4080_ERRATUM_CPU22 457 #define CONFIG_SYS_P4080_ERRATUM_CPU22
455 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011 458 #define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
456 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 459 #define CONFIG_SYS_P4080_ERRATUM_SERDES8
457 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 460 #define CONFIG_SYS_P4080_ERRATUM_SERDES9
458 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001 461 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
459 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 462 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
460 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 463 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
461 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 464 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
462 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 465 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
463 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 466 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
464 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 467 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
465 #define CONFIG_SYS_FSL_RMU 468 #define CONFIG_SYS_FSL_RMU
466 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 469 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
467 #define CONFIG_SYS_FSL_ERRATUM_A004510 470 #define CONFIG_SYS_FSL_ERRATUM_A004510
468 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20 471 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
469 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 472 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
470 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 473 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
471 #define CONFIG_SYS_FSL_ERRATUM_A004849 474 #define CONFIG_SYS_FSL_ERRATUM_A004849
472 #define CONFIG_SYS_FSL_ERRATUM_A004580 475 #define CONFIG_SYS_FSL_ERRATUM_A004580
473 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003 476 #define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
474 #define CONFIG_SYS_FSL_ERRATUM_A005812 477 #define CONFIG_SYS_FSL_ERRATUM_A005812
475 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 478 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
476 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 479 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
477 480
478 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */ 481 #elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
479 #define CONFIG_SYS_PPC64 /* 64-bit core */ 482 #define CONFIG_SYS_PPC64 /* 64-bit core */
480 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 483 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
481 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 484 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
482 #define CONFIG_MAX_CPUS 2 485 #define CONFIG_MAX_CPUS 2
483 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 486 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
484 #define CONFIG_SYS_FSL_NUM_LAWS 32 487 #define CONFIG_SYS_FSL_NUM_LAWS 32
485 #define CONFIG_SYS_FSL_SEC_COMPAT 4 488 #define CONFIG_SYS_FSL_SEC_COMPAT 4
486 #define CONFIG_SYS_NUM_FMAN 1 489 #define CONFIG_SYS_NUM_FMAN 1
487 #define CONFIG_SYS_NUM_FM1_DTSEC 5 490 #define CONFIG_SYS_NUM_FM1_DTSEC 5
488 #define CONFIG_SYS_NUM_FM1_10GEC 1 491 #define CONFIG_SYS_NUM_FM1_10GEC 1
489 #define CONFIG_NUM_DDR_CONTROLLERS 2 492 #define CONFIG_NUM_DDR_CONTROLLERS 2
490 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 493 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
491 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 494 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
492 #define CONFIG_SYS_FSL_TBCLK_DIV 32 495 #define CONFIG_SYS_FSL_TBCLK_DIV 32
493 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 496 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
494 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 497 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
495 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 498 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
496 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 499 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
497 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 500 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
498 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 501 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
499 #define CONFIG_SYS_FSL_ERRATUM_USB14 502 #define CONFIG_SYS_FSL_ERRATUM_USB14
500 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 503 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
501 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 504 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
502 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 505 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
503 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 506 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
504 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 507 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
505 #define CONFIG_SYS_FSL_ERRATUM_A004510 508 #define CONFIG_SYS_FSL_ERRATUM_A004510
506 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 509 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
507 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000 510 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
508 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034 511 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
509 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 512 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
513 #define CONFIG_SYS_FSL_ERRATUM_A006261
510 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20 514 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
511 515
512 #elif defined(CONFIG_PPC_P5040) 516 #elif defined(CONFIG_PPC_P5040)
513 #define CONFIG_SYS_PPC64 517 #define CONFIG_SYS_PPC64
514 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1 518 #define CONFIG_SYS_FSL_QORIQ_CHASSIS1
515 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 519 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
516 #define CONFIG_MAX_CPUS 4 520 #define CONFIG_MAX_CPUS 4
517 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3 521 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
518 #define CONFIG_SYS_FSL_NUM_LAWS 32 522 #define CONFIG_SYS_FSL_NUM_LAWS 32
519 #define CONFIG_SYS_FSL_SEC_COMPAT 4 523 #define CONFIG_SYS_FSL_SEC_COMPAT 4
520 #define CONFIG_SYS_NUM_FMAN 2 524 #define CONFIG_SYS_NUM_FMAN 2
521 #define CONFIG_SYS_NUM_FM1_DTSEC 5 525 #define CONFIG_SYS_NUM_FM1_DTSEC 5
522 #define CONFIG_SYS_NUM_FM1_10GEC 1 526 #define CONFIG_SYS_NUM_FM1_10GEC 1
523 #define CONFIG_SYS_NUM_FM2_DTSEC 5 527 #define CONFIG_SYS_NUM_FM2_DTSEC 5
524 #define CONFIG_SYS_NUM_FM2_10GEC 1 528 #define CONFIG_SYS_NUM_FM2_10GEC 1
525 #define CONFIG_NUM_DDR_CONTROLLERS 2 529 #define CONFIG_NUM_DDR_CONTROLLERS 2
526 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 530 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
527 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 531 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
528 #define CONFIG_SYS_FSL_TBCLK_DIV 16 532 #define CONFIG_SYS_FSL_TBCLK_DIV 16
529 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 533 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
530 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 534 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
531 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 535 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
532 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE 536 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
533 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 537 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
534 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 538 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
535 #define CONFIG_SYS_FSL_ERRATUM_USB14 539 #define CONFIG_SYS_FSL_ERRATUM_USB14
536 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 540 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
537 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 541 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
538 #define CONFIG_SYS_FSL_ERRATUM_A004699 542 #define CONFIG_SYS_FSL_ERRATUM_A004699
539 #define CONFIG_SYS_FSL_ERRATUM_A004510 543 #define CONFIG_SYS_FSL_ERRATUM_A004510
540 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10 544 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
545 #define CONFIG_SYS_FSL_ERRATUM_A006261
541 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 546 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
542 #define CONFIG_SYS_FSL_ERRATUM_A005812 547 #define CONFIG_SYS_FSL_ERRATUM_A005812
543 548
544 #elif defined(CONFIG_BSC9131) 549 #elif defined(CONFIG_BSC9131)
545 #define CONFIG_MAX_CPUS 1 550 #define CONFIG_MAX_CPUS 1
546 #define CONFIG_FSL_SDHC_V2_3 551 #define CONFIG_FSL_SDHC_V2_3
547 #define CONFIG_SYS_FSL_NUM_LAWS 12 552 #define CONFIG_SYS_FSL_NUM_LAWS 12
548 #define CONFIG_TSECV2 553 #define CONFIG_TSECV2
549 #define CONFIG_SYS_FSL_SEC_COMPAT 4 554 #define CONFIG_SYS_FSL_SEC_COMPAT 4
550 #define CONFIG_NUM_DDR_CONTROLLERS 1 555 #define CONFIG_NUM_DDR_CONTROLLERS 1
551 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 556 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
552 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 557 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
553 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 558 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
554 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 559 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
555 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 560 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
556 #define CONFIG_NAND_FSL_IFC 561 #define CONFIG_NAND_FSL_IFC
557 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 562 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
558 #define CONFIG_SYS_FSL_ERRATUM_A005125 563 #define CONFIG_SYS_FSL_ERRATUM_A005125
559 #define CONFIG_ESDHC_HC_BLK_ADDR 564 #define CONFIG_ESDHC_HC_BLK_ADDR
560 565
561 #elif defined(CONFIG_BSC9132) 566 #elif defined(CONFIG_BSC9132)
562 #define CONFIG_MAX_CPUS 2 567 #define CONFIG_MAX_CPUS 2
563 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 568 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
564 #define CONFIG_FSL_SDHC_V2_3 569 #define CONFIG_FSL_SDHC_V2_3
565 #define CONFIG_SYS_FSL_NUM_LAWS 12 570 #define CONFIG_SYS_FSL_NUM_LAWS 12
566 #define CONFIG_TSECV2 571 #define CONFIG_TSECV2
567 #define CONFIG_SYS_FSL_SEC_COMPAT 4 572 #define CONFIG_SYS_FSL_SEC_COMPAT 4
568 #define CONFIG_NUM_DDR_CONTROLLERS 2 573 #define CONFIG_NUM_DDR_CONTROLLERS 2
569 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 574 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
570 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000 575 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
571 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000 576 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
572 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000 577 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
573 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000 578 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
574 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 579 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
575 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 580 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
576 #define CONFIG_NAND_FSL_IFC 581 #define CONFIG_NAND_FSL_IFC
577 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 582 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
578 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK 583 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
579 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" 584 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
580 #define CONFIG_SYS_FSL_ERRATUM_A005125 585 #define CONFIG_SYS_FSL_ERRATUM_A005125
581 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447 586 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
582 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11 587 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
583 #define CONFIG_ESDHC_HC_BLK_ADDR 588 #define CONFIG_ESDHC_HC_BLK_ADDR
584 589
585 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 590 #elif defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
586 #define CONFIG_E6500 591 #define CONFIG_E6500
587 #define CONFIG_SYS_PPC64 /* 64-bit core */ 592 #define CONFIG_SYS_PPC64 /* 64-bit core */
588 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 593 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
589 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 594 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
590 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 595 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
591 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 596 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
592 #ifdef CONFIG_PPC_T4240 597 #ifdef CONFIG_PPC_T4240
593 #define CONFIG_MAX_CPUS 12 598 #define CONFIG_MAX_CPUS 12
594 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } 599 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
595 #define CONFIG_SYS_NUM_FM1_DTSEC 8 600 #define CONFIG_SYS_NUM_FM1_DTSEC 8
596 #define CONFIG_SYS_NUM_FM1_10GEC 2 601 #define CONFIG_SYS_NUM_FM1_10GEC 2
597 #define CONFIG_SYS_NUM_FM2_DTSEC 8 602 #define CONFIG_SYS_NUM_FM2_DTSEC 8
598 #define CONFIG_SYS_NUM_FM2_10GEC 2 603 #define CONFIG_SYS_NUM_FM2_10GEC 2
599 #define CONFIG_NUM_DDR_CONTROLLERS 3 604 #define CONFIG_NUM_DDR_CONTROLLERS 3
600 #else 605 #else
601 #define CONFIG_MAX_CPUS 8 606 #define CONFIG_MAX_CPUS 8
602 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } 607 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
603 #define CONFIG_SYS_NUM_FM1_DTSEC 7 608 #define CONFIG_SYS_NUM_FM1_DTSEC 7
604 #define CONFIG_SYS_NUM_FM1_10GEC 1 609 #define CONFIG_SYS_NUM_FM1_10GEC 1
605 #define CONFIG_SYS_NUM_FM2_DTSEC 7 610 #define CONFIG_SYS_NUM_FM2_DTSEC 7
606 #define CONFIG_SYS_NUM_FM2_10GEC 1 611 #define CONFIG_SYS_NUM_FM2_10GEC 1
607 #define CONFIG_NUM_DDR_CONTROLLERS 2 612 #define CONFIG_NUM_DDR_CONTROLLERS 2
608 #endif 613 #endif
609 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5 614 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
610 #define CONFIG_SYS_FSL_NUM_LAWS 32 615 #define CONFIG_SYS_FSL_NUM_LAWS 32
611 #define CONFIG_SYS_FSL_SRDS_1 616 #define CONFIG_SYS_FSL_SRDS_1
612 #define CONFIG_SYS_FSL_SRDS_2 617 #define CONFIG_SYS_FSL_SRDS_2
613 #define CONFIG_SYS_FSL_SRDS_3 618 #define CONFIG_SYS_FSL_SRDS_3
614 #define CONFIG_SYS_FSL_SRDS_4 619 #define CONFIG_SYS_FSL_SRDS_4
615 #define CONFIG_SYS_FSL_SEC_COMPAT 4 620 #define CONFIG_SYS_FSL_SEC_COMPAT 4
616 #define CONFIG_SYS_NUM_FMAN 2 621 #define CONFIG_SYS_NUM_FMAN 2
617 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 622 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
618 #define CONFIG_SYS_PME_CLK 0 623 #define CONFIG_SYS_PME_CLK 0
619 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 624 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
620 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 625 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
621 #define CONFIG_SYS_FMAN_V3 626 #define CONFIG_SYS_FMAN_V3
622 #define CONFIG_SYS_FM1_CLK 3 627 #define CONFIG_SYS_FM1_CLK 3
623 #define CONFIG_SYS_FM2_CLK 3 628 #define CONFIG_SYS_FM2_CLK 3
624 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 629 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
625 #define CONFIG_SYS_FSL_TBCLK_DIV 16 630 #define CONFIG_SYS_FSL_TBCLK_DIV 16
626 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 631 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
627 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 632 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
628 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 633 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
629 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 634 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
630 #define CONFIG_SYS_FSL_SRIO_LIODN 635 #define CONFIG_SYS_FSL_SRIO_LIODN
631 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 636 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
632 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 637 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
633 #define CONFIG_SYS_FSL_ERRATUM_A004468 638 #define CONFIG_SYS_FSL_ERRATUM_A004468
634 #define CONFIG_SYS_FSL_ERRATUM_A_004934 639 #define CONFIG_SYS_FSL_ERRATUM_A_004934
635 #define CONFIG_SYS_FSL_ERRATUM_A005871 640 #define CONFIG_SYS_FSL_ERRATUM_A005871
641 #define CONFIG_SYS_FSL_ERRATUM_A006261
636 #define CONFIG_SYS_FSL_ERRATUM_A006379 642 #define CONFIG_SYS_FSL_ERRATUM_A006379
637 #define CONFIG_SYS_FSL_ERRATUM_A006593 643 #define CONFIG_SYS_FSL_ERRATUM_A006593
638 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 644 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
639 #define CONFIG_SYS_FSL_PCI_VER_3_X 645 #define CONFIG_SYS_FSL_PCI_VER_3_X
640 646
641 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 647 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
642 #define CONFIG_E6500 648 #define CONFIG_E6500
643 #define CONFIG_SYS_PPC64 /* 64-bit core */ 649 #define CONFIG_SYS_PPC64 /* 64-bit core */
644 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 650 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
645 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 651 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
646 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 652 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
647 #define CONFIG_SYS_FSL_NUM_LAWS 32 653 #define CONFIG_SYS_FSL_NUM_LAWS 32
648 #define CONFIG_SYS_FSL_SRDS_1 654 #define CONFIG_SYS_FSL_SRDS_1
649 #define CONFIG_SYS_FSL_SRDS_2 655 #define CONFIG_SYS_FSL_SRDS_2
650 #define CONFIG_SYS_FSL_SEC_COMPAT 4 656 #define CONFIG_SYS_FSL_SEC_COMPAT 4
651 #define CONFIG_SYS_NUM_FMAN 1 657 #define CONFIG_SYS_NUM_FMAN 1
652 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 658 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
653 #define CONFIG_SYS_FM1_CLK 0 659 #define CONFIG_SYS_FM1_CLK 0
654 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 660 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
655 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 661 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
656 #define CONFIG_SYS_FMAN_V3 662 #define CONFIG_SYS_FMAN_V3
657 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 663 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
658 #define CONFIG_SYS_FSL_TBCLK_DIV 16 664 #define CONFIG_SYS_FSL_TBCLK_DIV 16
659 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 665 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
660 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE 666 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
661 #define CONFIG_SYS_FSL_ERRATUM_A_004934 667 #define CONFIG_SYS_FSL_ERRATUM_A_004934
662 #define CONFIG_SYS_FSL_ERRATUM_A005871 668 #define CONFIG_SYS_FSL_ERRATUM_A005871
663 #define CONFIG_SYS_FSL_ERRATUM_A006379 669 #define CONFIG_SYS_FSL_ERRATUM_A006379
664 #define CONFIG_SYS_FSL_ERRATUM_A006593 670 #define CONFIG_SYS_FSL_ERRATUM_A006593
671 #define CONFIG_SYS_FSL_ERRATUM_A006475
672 #define CONFIG_SYS_FSL_ERRATUM_A006384
665 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 673 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
666 674
667 #ifdef CONFIG_PPC_B4860 675 #ifdef CONFIG_PPC_B4860
668 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 676 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
669 #define CONFIG_MAX_CPUS 4 677 #define CONFIG_MAX_CPUS 4
678 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
670 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 679 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
671 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 680 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
672 #define CONFIG_SYS_NUM_FM1_DTSEC 6 681 #define CONFIG_SYS_NUM_FM1_DTSEC 6
673 #define CONFIG_SYS_NUM_FM1_10GEC 2 682 #define CONFIG_SYS_NUM_FM1_10GEC 2
674 #define CONFIG_NUM_DDR_CONTROLLERS 2 683 #define CONFIG_NUM_DDR_CONTROLLERS 2
675 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 684 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
676 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 685 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
677 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 686 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
678 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 687 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
679 #define CONFIG_SYS_FSL_SRIO_LIODN 688 #define CONFIG_SYS_FSL_SRIO_LIODN
680 #else 689 #else
681 #define CONFIG_MAX_CPUS 2 690 #define CONFIG_MAX_CPUS 2
691 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
682 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2 692 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
683 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4 693 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
684 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } 694 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
685 #define CONFIG_SYS_NUM_FM1_DTSEC 4 695 #define CONFIG_SYS_NUM_FM1_DTSEC 4
686 #define CONFIG_SYS_NUM_FM1_10GEC 0 696 #define CONFIG_SYS_NUM_FM1_10GEC 0
687 #define CONFIG_NUM_DDR_CONTROLLERS 1 697 #define CONFIG_NUM_DDR_CONTROLLERS 1
688 #endif 698 #endif
689 699
690 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 700 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
691 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 701 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
692 #define CONFIG_E5500 702 #define CONFIG_E5500
693 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 703 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
694 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 704 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
695 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1 705 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
696 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ 706 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
697 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) 707 #if defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042)
698 #define CONFIG_MAX_CPUS 4 708 #define CONFIG_MAX_CPUS 4
699 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 709 #elif defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
700 #define CONFIG_MAX_CPUS 2 710 #define CONFIG_MAX_CPUS 2
701 #endif 711 #endif
702 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 712 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
703 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } 713 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
704 #define CONFIG_SYS_SDHC_CLOCK 0 714 #define CONFIG_SYS_SDHC_CLOCK 0
705 #define CONFIG_SYS_FSL_NUM_LAWS 16 715 #define CONFIG_SYS_FSL_NUM_LAWS 16
706 #define CONFIG_SYS_FSL_SRDS_1 716 #define CONFIG_SYS_FSL_SRDS_1
707 #define CONFIG_SYS_FSL_SEC_COMPAT 5 717 #define CONFIG_SYS_FSL_SEC_COMPAT 5
708 #define CONFIG_SYS_NUM_FMAN 1 718 #define CONFIG_SYS_NUM_FMAN 1
709 #define CONFIG_SYS_NUM_FM1_DTSEC 5 719 #define CONFIG_SYS_NUM_FM1_DTSEC 5
710 #define CONFIG_NUM_DDR_CONTROLLERS 1 720 #define CONFIG_NUM_DDR_CONTROLLERS 1
711 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 721 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
712 #define CONFIG_PME_PLAT_CLK_DIV 2 722 #define CONFIG_PME_PLAT_CLK_DIV 2
713 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 723 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
714 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 724 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
715 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 725 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
716 #define CONFIG_SYS_FMAN_V3 726 #define CONFIG_SYS_FMAN_V3
717 #define CONFIG_FM_PLAT_CLK_DIV 1 727 #define CONFIG_FM_PLAT_CLK_DIV 1
718 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV 728 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
719 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 729 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
720 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK 730 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
721 #define CONFIG_SYS_FSL_TBCLK_DIV 16 731 #define CONFIG_SYS_FSL_TBCLK_DIV 16
722 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" 732 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
723 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 733 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
724 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 734 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
735 #define CONFIG_SYS_FSL_ERRATUM_A006261
725 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 736 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
726 737
727 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 738 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
728 #define CONFIG_E6500 739 #define CONFIG_E6500
729 #define CONFIG_SYS_PPC64 /* 64-bit core */ 740 #define CONFIG_SYS_PPC64 /* 64-bit core */
730 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 741 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
731 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ 742 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
732 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4 743 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
733 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 744 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
734 #define CONFIG_SYS_FSL_QMAN_V3 745 #define CONFIG_SYS_FSL_QMAN_V3
735 #define CONFIG_MAX_CPUS 4 746 #define CONFIG_MAX_CPUS 4
736 #define CONFIG_SYS_FSL_NUM_LAWS 32 747 #define CONFIG_SYS_FSL_NUM_LAWS 32
737 #define CONFIG_SYS_FSL_SEC_COMPAT 4 748 #define CONFIG_SYS_FSL_SEC_COMPAT 4
738 #define CONFIG_SYS_NUM_FMAN 1 749 #define CONFIG_SYS_NUM_FMAN 1
739 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } 750 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
740 #define CONFIG_SYS_FSL_SRDS_1 751 #define CONFIG_SYS_FSL_SRDS_1
741 #define CONFIG_SYS_FSL_PCI_VER_3_X 752 #define CONFIG_SYS_FSL_PCI_VER_3_X
742 #if defined(CONFIG_PPC_T2080) 753 #if defined(CONFIG_PPC_T2080)
743 #define CONFIG_SYS_NUM_FM1_DTSEC 8 754 #define CONFIG_SYS_NUM_FM1_DTSEC 8
744 #define CONFIG_SYS_NUM_FM1_10GEC 4 755 #define CONFIG_SYS_NUM_FM1_10GEC 4
745 #define CONFIG_SYS_FSL_SRDS_2 756 #define CONFIG_SYS_FSL_SRDS_2
746 #define CONFIG_SYS_FSL_SRIO_LIODN 757 #define CONFIG_SYS_FSL_SRIO_LIODN
747 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 758 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
748 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 759 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
749 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 760 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
750 #elif defined(CONFIG_PPC_T2081) 761 #elif defined(CONFIG_PPC_T2081)
751 #define CONFIG_SYS_NUM_FM1_DTSEC 6 762 #define CONFIG_SYS_NUM_FM1_DTSEC 6
752 #define CONFIG_SYS_NUM_FM1_10GEC 2 763 #define CONFIG_SYS_NUM_FM1_10GEC 2
753 #endif 764 #endif
754 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 765 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
755 #define CONFIG_NUM_DDR_CONTROLLERS 1 766 #define CONFIG_NUM_DDR_CONTROLLERS 1
756 #define CONFIG_PME_PLAT_CLK_DIV 1 767 #define CONFIG_PME_PLAT_CLK_DIV 1
757 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV 768 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
758 #define CONFIG_SYS_FM1_CLK 0 769 #define CONFIG_SYS_FM1_CLK 0
759 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 770 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
760 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 771 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
761 #define CONFIG_SYS_FMAN_V3 772 #define CONFIG_SYS_FMAN_V3
762 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 773 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
763 #define CONFIG_SYS_FSL_TBCLK_DIV 16 774 #define CONFIG_SYS_FSL_TBCLK_DIV 16
764 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" 775 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
765 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 776 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
766 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY 777 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
767 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 778 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
768 #define CONFIG_SYS_FSL_SFP_VER_3_0 779 #define CONFIG_SYS_FSL_SFP_VER_3_0
769 #define CONFIG_SYS_FSL_ISBC_VER 2 780 #define CONFIG_SYS_FSL_ISBC_VER 2
770 781
771 #elif defined(CONFIG_PPC_C29X) 782 #elif defined(CONFIG_PPC_C29X)
772 #define CONFIG_MAX_CPUS 1 783 #define CONFIG_MAX_CPUS 1
773 #define CONFIG_FSL_SDHC_V2_3 784 #define CONFIG_FSL_SDHC_V2_3
774 #define CONFIG_SYS_FSL_NUM_LAWS 12 785 #define CONFIG_SYS_FSL_NUM_LAWS 12
775 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 786 #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
776 #define CONFIG_TSECV2_1 787 #define CONFIG_TSECV2_1
777 #define CONFIG_SYS_FSL_SEC_COMPAT 6 788 #define CONFIG_SYS_FSL_SEC_COMPAT 6
778 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 789 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
779 #define CONFIG_NUM_DDR_CONTROLLERS 1 790 #define CONFIG_NUM_DDR_CONTROLLERS 1
780 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 791 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
781 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 792 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
782 #define CONFIG_SYS_FSL_ERRATUM_A005125 793 #define CONFIG_SYS_FSL_ERRATUM_A005125
783 794
784 #else 795 #else
785 #error Processor type not defined for this platform 796 #error Processor type not defined for this platform
786 #endif 797 #endif
787 798
788 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT 799 #ifndef CONFIG_SYS_CCSRBAR_DEFAULT
789 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform." 800 #error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
790 #endif 801 #endif
791 802
792 #ifdef CONFIG_E6500 803 #ifdef CONFIG_E6500
793 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2 804 #define CONFIG_SYS_FSL_THREADS_PER_CORE 2
794 #else 805 #else
795 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1 806 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
796 #endif 807 #endif
797 808
798 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \ 809 #if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
799 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \ 810 !defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
800 !defined(CONFIG_SYS_FSL_DDRC_GEN3) 811 !defined(CONFIG_SYS_FSL_DDRC_GEN3)
801 #define CONFIG_SYS_FSL_DDRC_GEN3 812 #define CONFIG_SYS_FSL_DDRC_GEN3
802 #endif 813 #endif
803 814
804 #endif /* _ASM_MPC85xx_CONFIG_H_ */ 815 #endif /* _ASM_MPC85xx_CONFIG_H_ */
805 816
arch/powerpc/include/asm/fsl_errata.h
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef _ASM_FSL_ERRATA_H 7 #ifndef _ASM_FSL_ERRATA_H
8 #define _ASM_FSL_ERRATA_H 8 #define _ASM_FSL_ERRATA_H
9 9
10 #include <common.h> 10 #include <common.h>
11 #include <asm/processor.h> 11 #include <asm/processor.h>
12 12
13 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379 13 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
14 static inline bool has_erratum_a006379(void) 14 static inline bool has_erratum_a006379(void)
15 { 15 {
16 u32 svr = get_svr(); 16 u32 svr = get_svr();
17 if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) || 17 if (((SVR_SOC_VER(svr) == SVR_T4240) && SVR_MAJ(svr) <= 1) ||
18 ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) || 18 ((SVR_SOC_VER(svr) == SVR_T4160) && SVR_MAJ(svr) <= 1) ||
19 ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) || 19 ((SVR_SOC_VER(svr) == SVR_B4860) && SVR_MAJ(svr) <= 2) ||
20 ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) || 20 ((SVR_SOC_VER(svr) == SVR_B4420) && SVR_MAJ(svr) <= 2) ||
21 ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) || 21 ((SVR_SOC_VER(svr) == SVR_T2080) && SVR_MAJ(svr) <= 1) ||
22 ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1)) 22 ((SVR_SOC_VER(svr) == SVR_T2081) && SVR_MAJ(svr) <= 1))
23 return true; 23 return true;
24 24
25 return false; 25 return false;
26 } 26 }
27 #endif 27 #endif
28 28
29 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
30 static inline bool has_erratum_a006261(void)
31 {
32 u32 svr = get_svr();
33 u32 soc = SVR_SOC_VER(svr);
34
35 switch (soc) {
36 case SVR_P1010:
37 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
38 case SVR_P2041:
39 case SVR_P2040:
40 return IS_SVR_REV(svr, 1, 0) ||
41 IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
42 case SVR_P3041:
43 return IS_SVR_REV(svr, 1, 0) ||
44 IS_SVR_REV(svr, 1, 1) ||
45 IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
46 case SVR_P5010:
47 case SVR_P5020:
48 case SVR_P5021:
49 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
50 case SVR_T4240:
51 case SVR_T4160:
52 return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
53 case SVR_T1040:
54 return IS_SVR_REV(svr, 1, 0);
55 case SVR_P5040:
56 return IS_SVR_REV(svr, 1, 0);
57 }
58
59 return false;
60 }
61 #endif
62
29 #endif 63 #endif
30 64
arch/powerpc/include/asm/immap_85xx.h
Diff comments   View file @ 247161b
1 /* 1 /*
2 * MPC85xx Internal Memory Map 2 * MPC85xx Internal Memory Map
3 * 3 *
4 * Copyright 2007-2012 Freescale Semiconductor, Inc. 4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
5 * 5 *
6 * Copyright(c) 2002,2003 Motorola Inc. 6 * Copyright(c) 2002,2003 Motorola Inc.
7 * Xianghua Xiao (x.xiao@motorola.com) 7 * Xianghua Xiao (x.xiao@motorola.com)
8 * 8 *
9 * SPDX-License-Identifier: GPL-2.0+ 9 * SPDX-License-Identifier: GPL-2.0+
10 */ 10 */
11 11
12 #ifndef __IMMAP_85xx__ 12 #ifndef __IMMAP_85xx__
13 #define __IMMAP_85xx__ 13 #define __IMMAP_85xx__
14 14
15 #include <asm/types.h> 15 #include <asm/types.h>
16 #include <asm/fsl_dma.h> 16 #include <asm/fsl_dma.h>
17 #include <asm/fsl_i2c.h> 17 #include <asm/fsl_i2c.h>
18 #include <fsl_ifc.h> 18 #include <fsl_ifc.h>
19 #include <asm/fsl_lbc.h> 19 #include <asm/fsl_lbc.h>
20 #include <asm/fsl_fman.h> 20 #include <asm/fsl_fman.h>
21 #include <fsl_immap.h> 21 #include <fsl_immap.h>
22 22
23 typedef struct ccsr_local { 23 typedef struct ccsr_local {
24 u32 ccsrbarh; /* CCSR Base Addr High */ 24 u32 ccsrbarh; /* CCSR Base Addr High */
25 u32 ccsrbarl; /* CCSR Base Addr Low */ 25 u32 ccsrbarl; /* CCSR Base Addr Low */
26 u32 ccsrar; /* CCSR Attr */ 26 u32 ccsrar; /* CCSR Attr */
27 #define CCSRAR_C 0x80000000 /* Commit */ 27 #define CCSRAR_C 0x80000000 /* Commit */
28 u8 res1[4]; 28 u8 res1[4];
29 u32 altcbarh; /* Alternate Configuration Base Addr High */ 29 u32 altcbarh; /* Alternate Configuration Base Addr High */
30 u32 altcbarl; /* Alternate Configuration Base Addr Low */ 30 u32 altcbarl; /* Alternate Configuration Base Addr Low */
31 u32 altcar; /* Alternate Configuration Attr */ 31 u32 altcar; /* Alternate Configuration Attr */
32 u8 res2[4]; 32 u8 res2[4];
33 u32 bstrh; /* Boot space translation high */ 33 u32 bstrh; /* Boot space translation high */
34 u32 bstrl; /* Boot space translation Low */ 34 u32 bstrl; /* Boot space translation Low */
35 u32 bstrar; /* Boot space translation attributes */ 35 u32 bstrar; /* Boot space translation attributes */
36 u8 res3[0xbd4]; 36 u8 res3[0xbd4];
37 struct { 37 struct {
38 u32 lawbarh; /* LAWn base addr high */ 38 u32 lawbarh; /* LAWn base addr high */
39 u32 lawbarl; /* LAWn base addr low */ 39 u32 lawbarl; /* LAWn base addr low */
40 u32 lawar; /* LAWn attributes */ 40 u32 lawar; /* LAWn attributes */
41 u8 res4[4]; 41 u8 res4[4];
42 } law[32]; 42 } law[32];
43 u8 res35[0x204]; 43 u8 res35[0x204];
44 } ccsr_local_t; 44 } ccsr_local_t;
45 45
46 /* Local-Access Registers & ECM Registers */ 46 /* Local-Access Registers & ECM Registers */
47 typedef struct ccsr_local_ecm { 47 typedef struct ccsr_local_ecm {
48 u32 ccsrbar; /* CCSR Base Addr */ 48 u32 ccsrbar; /* CCSR Base Addr */
49 u8 res1[4]; 49 u8 res1[4];
50 u32 altcbar; /* Alternate Configuration Base Addr */ 50 u32 altcbar; /* Alternate Configuration Base Addr */
51 u8 res2[4]; 51 u8 res2[4];
52 u32 altcar; /* Alternate Configuration Attr */ 52 u32 altcar; /* Alternate Configuration Attr */
53 u8 res3[12]; 53 u8 res3[12];
54 u32 bptr; /* Boot Page Translation */ 54 u32 bptr; /* Boot Page Translation */
55 u8 res4[3044]; 55 u8 res4[3044];
56 u32 lawbar0; /* Local Access Window 0 Base Addr */ 56 u32 lawbar0; /* Local Access Window 0 Base Addr */
57 u8 res5[4]; 57 u8 res5[4];
58 u32 lawar0; /* Local Access Window 0 Attrs */ 58 u32 lawar0; /* Local Access Window 0 Attrs */
59 u8 res6[20]; 59 u8 res6[20];
60 u32 lawbar1; /* Local Access Window 1 Base Addr */ 60 u32 lawbar1; /* Local Access Window 1 Base Addr */
61 u8 res7[4]; 61 u8 res7[4];
62 u32 lawar1; /* Local Access Window 1 Attrs */ 62 u32 lawar1; /* Local Access Window 1 Attrs */
63 u8 res8[20]; 63 u8 res8[20];
64 u32 lawbar2; /* Local Access Window 2 Base Addr */ 64 u32 lawbar2; /* Local Access Window 2 Base Addr */
65 u8 res9[4]; 65 u8 res9[4];
66 u32 lawar2; /* Local Access Window 2 Attrs */ 66 u32 lawar2; /* Local Access Window 2 Attrs */
67 u8 res10[20]; 67 u8 res10[20];
68 u32 lawbar3; /* Local Access Window 3 Base Addr */ 68 u32 lawbar3; /* Local Access Window 3 Base Addr */
69 u8 res11[4]; 69 u8 res11[4];
70 u32 lawar3; /* Local Access Window 3 Attrs */ 70 u32 lawar3; /* Local Access Window 3 Attrs */
71 u8 res12[20]; 71 u8 res12[20];
72 u32 lawbar4; /* Local Access Window 4 Base Addr */ 72 u32 lawbar4; /* Local Access Window 4 Base Addr */
73 u8 res13[4]; 73 u8 res13[4];
74 u32 lawar4; /* Local Access Window 4 Attrs */ 74 u32 lawar4; /* Local Access Window 4 Attrs */
75 u8 res14[20]; 75 u8 res14[20];
76 u32 lawbar5; /* Local Access Window 5 Base Addr */ 76 u32 lawbar5; /* Local Access Window 5 Base Addr */
77 u8 res15[4]; 77 u8 res15[4];
78 u32 lawar5; /* Local Access Window 5 Attrs */ 78 u32 lawar5; /* Local Access Window 5 Attrs */
79 u8 res16[20]; 79 u8 res16[20];
80 u32 lawbar6; /* Local Access Window 6 Base Addr */ 80 u32 lawbar6; /* Local Access Window 6 Base Addr */
81 u8 res17[4]; 81 u8 res17[4];
82 u32 lawar6; /* Local Access Window 6 Attrs */ 82 u32 lawar6; /* Local Access Window 6 Attrs */
83 u8 res18[20]; 83 u8 res18[20];
84 u32 lawbar7; /* Local Access Window 7 Base Addr */ 84 u32 lawbar7; /* Local Access Window 7 Base Addr */
85 u8 res19[4]; 85 u8 res19[4];
86 u32 lawar7; /* Local Access Window 7 Attrs */ 86 u32 lawar7; /* Local Access Window 7 Attrs */
87 u8 res19_8a[20]; 87 u8 res19_8a[20];
88 u32 lawbar8; /* Local Access Window 8 Base Addr */ 88 u32 lawbar8; /* Local Access Window 8 Base Addr */
89 u8 res19_8b[4]; 89 u8 res19_8b[4];
90 u32 lawar8; /* Local Access Window 8 Attrs */ 90 u32 lawar8; /* Local Access Window 8 Attrs */
91 u8 res19_9a[20]; 91 u8 res19_9a[20];
92 u32 lawbar9; /* Local Access Window 9 Base Addr */ 92 u32 lawbar9; /* Local Access Window 9 Base Addr */
93 u8 res19_9b[4]; 93 u8 res19_9b[4];
94 u32 lawar9; /* Local Access Window 9 Attrs */ 94 u32 lawar9; /* Local Access Window 9 Attrs */
95 u8 res19_10a[20]; 95 u8 res19_10a[20];
96 u32 lawbar10; /* Local Access Window 10 Base Addr */ 96 u32 lawbar10; /* Local Access Window 10 Base Addr */
97 u8 res19_10b[4]; 97 u8 res19_10b[4];
98 u32 lawar10; /* Local Access Window 10 Attrs */ 98 u32 lawar10; /* Local Access Window 10 Attrs */
99 u8 res19_11a[20]; 99 u8 res19_11a[20];
100 u32 lawbar11; /* Local Access Window 11 Base Addr */ 100 u32 lawbar11; /* Local Access Window 11 Base Addr */
101 u8 res19_11b[4]; 101 u8 res19_11b[4];
102 u32 lawar11; /* Local Access Window 11 Attrs */ 102 u32 lawar11; /* Local Access Window 11 Attrs */
103 u8 res20[652]; 103 u8 res20[652];
104 u32 eebacr; /* ECM CCB Addr Configuration */ 104 u32 eebacr; /* ECM CCB Addr Configuration */
105 u8 res21[12]; 105 u8 res21[12];
106 u32 eebpcr; /* ECM CCB Port Configuration */ 106 u32 eebpcr; /* ECM CCB Port Configuration */
107 u8 res22[3564]; 107 u8 res22[3564];
108 u32 eedr; /* ECM Error Detect */ 108 u32 eedr; /* ECM Error Detect */
109 u8 res23[4]; 109 u8 res23[4];
110 u32 eeer; /* ECM Error Enable */ 110 u32 eeer; /* ECM Error Enable */
111 u32 eeatr; /* ECM Error Attrs Capture */ 111 u32 eeatr; /* ECM Error Attrs Capture */
112 u32 eeadr; /* ECM Error Addr Capture */ 112 u32 eeadr; /* ECM Error Addr Capture */
113 u8 res24[492]; 113 u8 res24[492];
114 } ccsr_local_ecm_t; 114 } ccsr_local_ecm_t;
115 115
116 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */ 116 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
117 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */ 117 #define DDR_EOR_ADDR_HASH_EN 0x40000000 /* Address hash enabled */
118 118
119 /* I2C Registers */ 119 /* I2C Registers */
120 typedef struct ccsr_i2c { 120 typedef struct ccsr_i2c {
121 struct fsl_i2c i2c[1]; 121 struct fsl_i2c i2c[1];
122 u8 res[4096 - 1 * sizeof(struct fsl_i2c)]; 122 u8 res[4096 - 1 * sizeof(struct fsl_i2c)];
123 } ccsr_i2c_t; 123 } ccsr_i2c_t;
124 124
125 #if defined(CONFIG_MPC8540) \ 125 #if defined(CONFIG_MPC8540) \
126 || defined(CONFIG_MPC8541) \ 126 || defined(CONFIG_MPC8541) \
127 || defined(CONFIG_MPC8548) \ 127 || defined(CONFIG_MPC8548) \
128 || defined(CONFIG_MPC8555) 128 || defined(CONFIG_MPC8555)
129 /* DUART Registers */ 129 /* DUART Registers */
130 typedef struct ccsr_duart { 130 typedef struct ccsr_duart {
131 u8 res1[1280]; 131 u8 res1[1280];
132 /* URBR1, UTHR1, UDLB1 with the same addr */ 132 /* URBR1, UTHR1, UDLB1 with the same addr */
133 u8 urbr1_uthr1_udlb1; 133 u8 urbr1_uthr1_udlb1;
134 /* UIER1, UDMB1 with the same addr01 */ 134 /* UIER1, UDMB1 with the same addr01 */
135 u8 uier1_udmb1; 135 u8 uier1_udmb1;
136 /* UIIR1, UFCR1, UAFR1 with the same addr */ 136 /* UIIR1, UFCR1, UAFR1 with the same addr */
137 u8 uiir1_ufcr1_uafr1; 137 u8 uiir1_ufcr1_uafr1;
138 u8 ulcr1; /* UART1 Line Control */ 138 u8 ulcr1; /* UART1 Line Control */
139 u8 umcr1; /* UART1 Modem Control */ 139 u8 umcr1; /* UART1 Modem Control */
140 u8 ulsr1; /* UART1 Line Status */ 140 u8 ulsr1; /* UART1 Line Status */
141 u8 umsr1; /* UART1 Modem Status */ 141 u8 umsr1; /* UART1 Modem Status */
142 u8 uscr1; /* UART1 Scratch */ 142 u8 uscr1; /* UART1 Scratch */
143 u8 res2[8]; 143 u8 res2[8];
144 u8 udsr1; /* UART1 DMA Status */ 144 u8 udsr1; /* UART1 DMA Status */
145 u8 res3[239]; 145 u8 res3[239];
146 /* URBR2, UTHR2, UDLB2 with the same addr */ 146 /* URBR2, UTHR2, UDLB2 with the same addr */
147 u8 urbr2_uthr2_udlb2; 147 u8 urbr2_uthr2_udlb2;
148 /* UIER2, UDMB2 with the same addr */ 148 /* UIER2, UDMB2 with the same addr */
149 u8 uier2_udmb2; 149 u8 uier2_udmb2;
150 /* UIIR2, UFCR2, UAFR2 with the same addr */ 150 /* UIIR2, UFCR2, UAFR2 with the same addr */
151 u8 uiir2_ufcr2_uafr2; 151 u8 uiir2_ufcr2_uafr2;
152 u8 ulcr2; /* UART2 Line Control */ 152 u8 ulcr2; /* UART2 Line Control */
153 u8 umcr2; /* UART2 Modem Control */ 153 u8 umcr2; /* UART2 Modem Control */
154 u8 ulsr2; /* UART2 Line Status */ 154 u8 ulsr2; /* UART2 Line Status */
155 u8 umsr2; /* UART2 Modem Status */ 155 u8 umsr2; /* UART2 Modem Status */
156 u8 uscr2; /* UART2 Scratch */ 156 u8 uscr2; /* UART2 Scratch */
157 u8 res4[8]; 157 u8 res4[8];
158 u8 udsr2; /* UART2 DMA Status */ 158 u8 udsr2; /* UART2 DMA Status */
159 u8 res5[2543]; 159 u8 res5[2543];
160 } ccsr_duart_t; 160 } ccsr_duart_t;
161 #else /* MPC8560 uses UART on its CPM */ 161 #else /* MPC8560 uses UART on its CPM */
162 typedef struct ccsr_duart { 162 typedef struct ccsr_duart {
163 u8 res[4096]; 163 u8 res[4096];
164 } ccsr_duart_t; 164 } ccsr_duart_t;
165 #endif 165 #endif
166 166
167 /* eSPI Registers */ 167 /* eSPI Registers */
168 typedef struct ccsr_espi { 168 typedef struct ccsr_espi {
169 u32 mode; /* eSPI mode */ 169 u32 mode; /* eSPI mode */
170 u32 event; /* eSPI event */ 170 u32 event; /* eSPI event */
171 u32 mask; /* eSPI mask */ 171 u32 mask; /* eSPI mask */
172 u32 com; /* eSPI command */ 172 u32 com; /* eSPI command */
173 u32 tx; /* eSPI transmit FIFO access */ 173 u32 tx; /* eSPI transmit FIFO access */
174 u32 rx; /* eSPI receive FIFO access */ 174 u32 rx; /* eSPI receive FIFO access */
175 u8 res1[8]; /* reserved */ 175 u8 res1[8]; /* reserved */
176 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */ 176 u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */
177 u8 res2[4048]; /* fill up to 0x1000 */ 177 u8 res2[4048]; /* fill up to 0x1000 */
178 } ccsr_espi_t; 178 } ccsr_espi_t;
179 179
180 /* PCI Registers */ 180 /* PCI Registers */
181 typedef struct ccsr_pcix { 181 typedef struct ccsr_pcix {
182 u32 cfg_addr; /* PCIX Configuration Addr */ 182 u32 cfg_addr; /* PCIX Configuration Addr */
183 u32 cfg_data; /* PCIX Configuration Data */ 183 u32 cfg_data; /* PCIX Configuration Data */
184 u32 int_ack; /* PCIX IRQ Acknowledge */ 184 u32 int_ack; /* PCIX IRQ Acknowledge */
185 u8 res000c[52]; 185 u8 res000c[52];
186 u32 liodn_base; /* PCIX LIODN base register */ 186 u32 liodn_base; /* PCIX LIODN base register */
187 u8 res0044[2996]; 187 u8 res0044[2996];
188 u32 ipver1; /* PCIX IP block revision register 1 */ 188 u32 ipver1; /* PCIX IP block revision register 1 */
189 u32 ipver2; /* PCIX IP block revision register 2 */ 189 u32 ipver2; /* PCIX IP block revision register 2 */
190 u32 potar0; /* PCIX Outbound Transaction Addr 0 */ 190 u32 potar0; /* PCIX Outbound Transaction Addr 0 */
191 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ 191 u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
192 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ 192 u32 powbar0; /* PCIX Outbound Window Base Addr 0 */
193 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */ 193 u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */
194 u32 powar0; /* PCIX Outbound Window Attrs 0 */ 194 u32 powar0; /* PCIX Outbound Window Attrs 0 */
195 u8 res2[12]; 195 u8 res2[12];
196 u32 potar1; /* PCIX Outbound Transaction Addr 1 */ 196 u32 potar1; /* PCIX Outbound Transaction Addr 1 */
197 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */ 197 u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */
198 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */ 198 u32 powbar1; /* PCIX Outbound Window Base Addr 1 */
199 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */ 199 u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */
200 u32 powar1; /* PCIX Outbound Window Attrs 1 */ 200 u32 powar1; /* PCIX Outbound Window Attrs 1 */
201 u8 res3[12]; 201 u8 res3[12];
202 u32 potar2; /* PCIX Outbound Transaction Addr 2 */ 202 u32 potar2; /* PCIX Outbound Transaction Addr 2 */
203 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */ 203 u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */
204 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */ 204 u32 powbar2; /* PCIX Outbound Window Base Addr 2 */
205 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */ 205 u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */
206 u32 powar2; /* PCIX Outbound Window Attrs 2 */ 206 u32 powar2; /* PCIX Outbound Window Attrs 2 */
207 u8 res4[12]; 207 u8 res4[12];
208 u32 potar3; /* PCIX Outbound Transaction Addr 3 */ 208 u32 potar3; /* PCIX Outbound Transaction Addr 3 */
209 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */ 209 u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */
210 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */ 210 u32 powbar3; /* PCIX Outbound Window Base Addr 3 */
211 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */ 211 u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */
212 u32 powar3; /* PCIX Outbound Window Attrs 3 */ 212 u32 powar3; /* PCIX Outbound Window Attrs 3 */
213 u8 res5[12]; 213 u8 res5[12];
214 u32 potar4; /* PCIX Outbound Transaction Addr 4 */ 214 u32 potar4; /* PCIX Outbound Transaction Addr 4 */
215 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */ 215 u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */
216 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */ 216 u32 powbar4; /* PCIX Outbound Window Base Addr 4 */
217 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */ 217 u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */
218 u32 powar4; /* PCIX Outbound Window Attrs 4 */ 218 u32 powar4; /* PCIX Outbound Window Attrs 4 */
219 u8 res6[268]; 219 u8 res6[268];
220 u32 pitar3; /* PCIX Inbound Translation Addr 3 */ 220 u32 pitar3; /* PCIX Inbound Translation Addr 3 */
221 u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */ 221 u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */
222 u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */ 222 u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */
223 u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */ 223 u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */
224 u32 piwar3; /* PCIX Inbound Window Attrs 3 */ 224 u32 piwar3; /* PCIX Inbound Window Attrs 3 */
225 u8 res7[12]; 225 u8 res7[12];
226 u32 pitar2; /* PCIX Inbound Translation Addr 2 */ 226 u32 pitar2; /* PCIX Inbound Translation Addr 2 */
227 u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */ 227 u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */
228 u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */ 228 u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */
229 u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */ 229 u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */
230 u32 piwar2; /* PCIX Inbound Window Attrs 2 */ 230 u32 piwar2; /* PCIX Inbound Window Attrs 2 */
231 u8 res8[12]; 231 u8 res8[12];
232 u32 pitar1; /* PCIX Inbound Translation Addr 1 */ 232 u32 pitar1; /* PCIX Inbound Translation Addr 1 */
233 u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */ 233 u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */
234 u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */ 234 u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */
235 u8 res9[4]; 235 u8 res9[4];
236 u32 piwar1; /* PCIX Inbound Window Attrs 1 */ 236 u32 piwar1; /* PCIX Inbound Window Attrs 1 */
237 u8 res10[12]; 237 u8 res10[12];
238 u32 pedr; /* PCIX Error Detect */ 238 u32 pedr; /* PCIX Error Detect */
239 u32 pecdr; /* PCIX Error Capture Disable */ 239 u32 pecdr; /* PCIX Error Capture Disable */
240 u32 peer; /* PCIX Error Enable */ 240 u32 peer; /* PCIX Error Enable */
241 u32 peattrcr; /* PCIX Error Attrs Capture */ 241 u32 peattrcr; /* PCIX Error Attrs Capture */
242 u32 peaddrcr; /* PCIX Error Addr Capture */ 242 u32 peaddrcr; /* PCIX Error Addr Capture */
243 u32 peextaddrcr; /* PCIX Error Extended Addr Capture */ 243 u32 peextaddrcr; /* PCIX Error Extended Addr Capture */
244 u32 pedlcr; /* PCIX Error Data Low Capture */ 244 u32 pedlcr; /* PCIX Error Data Low Capture */
245 u32 pedhcr; /* PCIX Error Error Data High Capture */ 245 u32 pedhcr; /* PCIX Error Error Data High Capture */
246 u32 gas_timr; /* PCIX Gasket Timer */ 246 u32 gas_timr; /* PCIX Gasket Timer */
247 u8 res11[476]; 247 u8 res11[476];
248 } ccsr_pcix_t; 248 } ccsr_pcix_t;
249 249
250 #define PCIX_COMMAND 0x62 250 #define PCIX_COMMAND 0x62
251 #define POWAR_EN 0x80000000 251 #define POWAR_EN 0x80000000
252 #define POWAR_IO_READ 0x00080000 252 #define POWAR_IO_READ 0x00080000
253 #define POWAR_MEM_READ 0x00040000 253 #define POWAR_MEM_READ 0x00040000
254 #define POWAR_IO_WRITE 0x00008000 254 #define POWAR_IO_WRITE 0x00008000
255 #define POWAR_MEM_WRITE 0x00004000 255 #define POWAR_MEM_WRITE 0x00004000
256 #define POWAR_MEM_512M 0x0000001c 256 #define POWAR_MEM_512M 0x0000001c
257 #define POWAR_IO_1M 0x00000013 257 #define POWAR_IO_1M 0x00000013
258 258
259 #define PIWAR_EN 0x80000000 259 #define PIWAR_EN 0x80000000
260 #define PIWAR_PF 0x20000000 260 #define PIWAR_PF 0x20000000
261 #define PIWAR_LOCAL 0x00f00000 261 #define PIWAR_LOCAL 0x00f00000
262 #define PIWAR_READ_SNOOP 0x00050000 262 #define PIWAR_READ_SNOOP 0x00050000
263 #define PIWAR_WRITE_SNOOP 0x00005000 263 #define PIWAR_WRITE_SNOOP 0x00005000
264 #define PIWAR_MEM_2G 0x0000001e 264 #define PIWAR_MEM_2G 0x0000001e
265 265
266 typedef struct ccsr_gpio { 266 typedef struct ccsr_gpio {
267 u32 gpdir; 267 u32 gpdir;
268 u32 gpodr; 268 u32 gpodr;
269 u32 gpdat; 269 u32 gpdat;
270 u32 gpier; 270 u32 gpier;
271 u32 gpimr; 271 u32 gpimr;
272 u32 gpicr; 272 u32 gpicr;
273 } ccsr_gpio_t; 273 } ccsr_gpio_t;
274 274
275 /* L2 Cache Registers */ 275 /* L2 Cache Registers */
276 typedef struct ccsr_l2cache { 276 typedef struct ccsr_l2cache {
277 u32 l2ctl; /* L2 configuration 0 */ 277 u32 l2ctl; /* L2 configuration 0 */
278 u8 res1[12]; 278 u8 res1[12];
279 u32 l2cewar0; /* L2 cache external write addr 0 */ 279 u32 l2cewar0; /* L2 cache external write addr 0 */
280 u8 res2[4]; 280 u8 res2[4];
281 u32 l2cewcr0; /* L2 cache external write control 0 */ 281 u32 l2cewcr0; /* L2 cache external write control 0 */
282 u8 res3[4]; 282 u8 res3[4];
283 u32 l2cewar1; /* L2 cache external write addr 1 */ 283 u32 l2cewar1; /* L2 cache external write addr 1 */
284 u8 res4[4]; 284 u8 res4[4];
285 u32 l2cewcr1; /* L2 cache external write control 1 */ 285 u32 l2cewcr1; /* L2 cache external write control 1 */
286 u8 res5[4]; 286 u8 res5[4];
287 u32 l2cewar2; /* L2 cache external write addr 2 */ 287 u32 l2cewar2; /* L2 cache external write addr 2 */
288 u8 res6[4]; 288 u8 res6[4];
289 u32 l2cewcr2; /* L2 cache external write control 2 */ 289 u32 l2cewcr2; /* L2 cache external write control 2 */
290 u8 res7[4]; 290 u8 res7[4];
291 u32 l2cewar3; /* L2 cache external write addr 3 */ 291 u32 l2cewar3; /* L2 cache external write addr 3 */
292 u8 res8[4]; 292 u8 res8[4];
293 u32 l2cewcr3; /* L2 cache external write control 3 */ 293 u32 l2cewcr3; /* L2 cache external write control 3 */
294 u8 res9[180]; 294 u8 res9[180];
295 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */ 295 u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */
296 u8 res10[4]; 296 u8 res10[4];
297 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */ 297 u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */
298 u8 res11[3316]; 298 u8 res11[3316];
299 u32 l2errinjhi; /* L2 error injection mask high */ 299 u32 l2errinjhi; /* L2 error injection mask high */
300 u32 l2errinjlo; /* L2 error injection mask low */ 300 u32 l2errinjlo; /* L2 error injection mask low */
301 u32 l2errinjctl; /* L2 error injection tag/ECC control */ 301 u32 l2errinjctl; /* L2 error injection tag/ECC control */
302 u8 res12[20]; 302 u8 res12[20];
303 u32 l2captdatahi; /* L2 error data high capture */ 303 u32 l2captdatahi; /* L2 error data high capture */
304 u32 l2captdatalo; /* L2 error data low capture */ 304 u32 l2captdatalo; /* L2 error data low capture */
305 u32 l2captecc; /* L2 error ECC capture */ 305 u32 l2captecc; /* L2 error ECC capture */
306 u8 res13[20]; 306 u8 res13[20];
307 u32 l2errdet; /* L2 error detect */ 307 u32 l2errdet; /* L2 error detect */
308 u32 l2errdis; /* L2 error disable */ 308 u32 l2errdis; /* L2 error disable */
309 u32 l2errinten; /* L2 error interrupt enable */ 309 u32 l2errinten; /* L2 error interrupt enable */
310 u32 l2errattr; /* L2 error attributes capture */ 310 u32 l2errattr; /* L2 error attributes capture */
311 u32 l2erraddr; /* L2 error addr capture */ 311 u32 l2erraddr; /* L2 error addr capture */
312 u8 res14[4]; 312 u8 res14[4];
313 u32 l2errctl; /* L2 error control */ 313 u32 l2errctl; /* L2 error control */
314 u8 res15[420]; 314 u8 res15[420];
315 } ccsr_l2cache_t; 315 } ccsr_l2cache_t;
316 316
317 #define MPC85xx_L2CTL_L2E 0x80000000 317 #define MPC85xx_L2CTL_L2E 0x80000000
318 #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000 318 #define MPC85xx_L2CTL_L2SRAM_ENTIRE 0x00010000
319 #define MPC85xx_L2ERRDIS_MBECC 0x00000008 319 #define MPC85xx_L2ERRDIS_MBECC 0x00000008
320 #define MPC85xx_L2ERRDIS_SBECC 0x00000004 320 #define MPC85xx_L2ERRDIS_SBECC 0x00000004
321 321
322 /* DMA Registers */ 322 /* DMA Registers */
323 typedef struct ccsr_dma { 323 typedef struct ccsr_dma {
324 u8 res1[256]; 324 u8 res1[256];
325 struct fsl_dma dma[4]; 325 struct fsl_dma dma[4];
326 u32 dgsr; /* DMA General Status */ 326 u32 dgsr; /* DMA General Status */
327 u8 res2[11516]; 327 u8 res2[11516];
328 } ccsr_dma_t; 328 } ccsr_dma_t;
329 329
330 /* tsec */ 330 /* tsec */
331 typedef struct ccsr_tsec { 331 typedef struct ccsr_tsec {
332 u8 res1[16]; 332 u8 res1[16];
333 u32 ievent; /* IRQ Event */ 333 u32 ievent; /* IRQ Event */
334 u32 imask; /* IRQ Mask */ 334 u32 imask; /* IRQ Mask */
335 u32 edis; /* Error Disabled */ 335 u32 edis; /* Error Disabled */
336 u8 res2[4]; 336 u8 res2[4];
337 u32 ecntrl; /* Ethernet Control */ 337 u32 ecntrl; /* Ethernet Control */
338 u32 minflr; /* Minimum Frame Len */ 338 u32 minflr; /* Minimum Frame Len */
339 u32 ptv; /* Pause Time Value */ 339 u32 ptv; /* Pause Time Value */
340 u32 dmactrl; /* DMA Control */ 340 u32 dmactrl; /* DMA Control */
341 u32 tbipa; /* TBI PHY Addr */ 341 u32 tbipa; /* TBI PHY Addr */
342 u8 res3[88]; 342 u8 res3[88];
343 u32 fifo_tx_thr; /* FIFO transmit threshold */ 343 u32 fifo_tx_thr; /* FIFO transmit threshold */
344 u8 res4[8]; 344 u8 res4[8];
345 u32 fifo_tx_starve; /* FIFO transmit starve */ 345 u32 fifo_tx_starve; /* FIFO transmit starve */
346 u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */ 346 u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */
347 u8 res5[96]; 347 u8 res5[96];
348 u32 tctrl; /* TX Control */ 348 u32 tctrl; /* TX Control */
349 u32 tstat; /* TX Status */ 349 u32 tstat; /* TX Status */
350 u8 res6[4]; 350 u8 res6[4];
351 u32 tbdlen; /* TX Buffer Desc Data Len */ 351 u32 tbdlen; /* TX Buffer Desc Data Len */
352 u8 res7[16]; 352 u8 res7[16];
353 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */ 353 u32 ctbptrh; /* Current TX Buffer Desc Ptr High */
354 u32 ctbptr; /* Current TX Buffer Desc Ptr */ 354 u32 ctbptr; /* Current TX Buffer Desc Ptr */
355 u8 res8[88]; 355 u8 res8[88];
356 u32 tbptrh; /* TX Buffer Desc Ptr High */ 356 u32 tbptrh; /* TX Buffer Desc Ptr High */
357 u32 tbptr; /* TX Buffer Desc Ptr Low */ 357 u32 tbptr; /* TX Buffer Desc Ptr Low */
358 u8 res9[120]; 358 u8 res9[120];
359 u32 tbaseh; /* TX Desc Base Addr High */ 359 u32 tbaseh; /* TX Desc Base Addr High */
360 u32 tbase; /* TX Desc Base Addr */ 360 u32 tbase; /* TX Desc Base Addr */
361 u8 res10[168]; 361 u8 res10[168];
362 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */ 362 u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */
363 u32 ostbdp; /* OOS TX Data Buffer Ptr */ 363 u32 ostbdp; /* OOS TX Data Buffer Ptr */
364 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */ 364 u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */
365 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */ 365 u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */
366 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */ 366 u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */
367 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */ 367 u32 os32tbdr; /* OOS 32 Bytes TX Reserved */
368 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */ 368 u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */
369 u8 res11[52]; 369 u8 res11[52];
370 u32 rctrl; /* RX Control */ 370 u32 rctrl; /* RX Control */
371 u32 rstat; /* RX Status */ 371 u32 rstat; /* RX Status */
372 u8 res12[4]; 372 u8 res12[4];
373 u32 rbdlen; /* RxBD Data Len */ 373 u32 rbdlen; /* RxBD Data Len */
374 u8 res13[16]; 374 u8 res13[16];
375 u32 crbptrh; /* Current RX Buffer Desc Ptr High */ 375 u32 crbptrh; /* Current RX Buffer Desc Ptr High */
376 u32 crbptr; /* Current RX Buffer Desc Ptr */ 376 u32 crbptr; /* Current RX Buffer Desc Ptr */
377 u8 res14[24]; 377 u8 res14[24];
378 u32 mrblr; /* Maximum RX Buffer Len */ 378 u32 mrblr; /* Maximum RX Buffer Len */
379 u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */ 379 u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */
380 u8 res15[56]; 380 u8 res15[56];
381 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */ 381 u32 rbptrh; /* RX Buffer Desc Ptr High 0 */
382 u32 rbptr; /* RX Buffer Desc Ptr */ 382 u32 rbptr; /* RX Buffer Desc Ptr */
383 u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */ 383 u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */
384 u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */ 384 u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */
385 u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */ 385 u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */
386 u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */ 386 u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */
387 u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */ 387 u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */
388 u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */ 388 u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */
389 u8 res16[96]; 389 u8 res16[96];
390 u32 rbaseh; /* RX Desc Base Addr High 0 */ 390 u32 rbaseh; /* RX Desc Base Addr High 0 */
391 u32 rbase; /* RX Desc Base Addr */ 391 u32 rbase; /* RX Desc Base Addr */
392 u32 rbaseh1; /* RX Desc Base Addr High 1 */ 392 u32 rbaseh1; /* RX Desc Base Addr High 1 */
393 u32 rbasel1; /* RX Desc Base Addr Low 1 */ 393 u32 rbasel1; /* RX Desc Base Addr Low 1 */
394 u32 rbaseh2; /* RX Desc Base Addr High 2 */ 394 u32 rbaseh2; /* RX Desc Base Addr High 2 */
395 u32 rbasel2; /* RX Desc Base Addr Low 2 */ 395 u32 rbasel2; /* RX Desc Base Addr Low 2 */
396 u32 rbaseh3; /* RX Desc Base Addr High 3 */ 396 u32 rbaseh3; /* RX Desc Base Addr High 3 */
397 u32 rbasel3; /* RX Desc Base Addr Low 3 */ 397 u32 rbasel3; /* RX Desc Base Addr Low 3 */
398 u8 res17[224]; 398 u8 res17[224];
399 u32 maccfg1; /* MAC Configuration 1 */ 399 u32 maccfg1; /* MAC Configuration 1 */
400 u32 maccfg2; /* MAC Configuration 2 */ 400 u32 maccfg2; /* MAC Configuration 2 */
401 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */ 401 u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */
402 u32 hafdup; /* Half Duplex */ 402 u32 hafdup; /* Half Duplex */
403 u32 maxfrm; /* Maximum Frame Len */ 403 u32 maxfrm; /* Maximum Frame Len */
404 u8 res18[12]; 404 u8 res18[12];
405 u32 miimcfg; /* MII Management Configuration */ 405 u32 miimcfg; /* MII Management Configuration */
406 u32 miimcom; /* MII Management Cmd */ 406 u32 miimcom; /* MII Management Cmd */
407 u32 miimadd; /* MII Management Addr */ 407 u32 miimadd; /* MII Management Addr */
408 u32 miimcon; /* MII Management Control */ 408 u32 miimcon; /* MII Management Control */
409 u32 miimstat; /* MII Management Status */ 409 u32 miimstat; /* MII Management Status */
410 u32 miimind; /* MII Management Indicator */ 410 u32 miimind; /* MII Management Indicator */
411 u8 res19[4]; 411 u8 res19[4];
412 u32 ifstat; /* Interface Status */ 412 u32 ifstat; /* Interface Status */
413 u32 macstnaddr1; /* Station Addr Part 1 */ 413 u32 macstnaddr1; /* Station Addr Part 1 */
414 u32 macstnaddr2; /* Station Addr Part 2 */ 414 u32 macstnaddr2; /* Station Addr Part 2 */
415 u8 res20[312]; 415 u8 res20[312];
416 u32 tr64; /* TX & RX 64-byte Frame Counter */ 416 u32 tr64; /* TX & RX 64-byte Frame Counter */
417 u32 tr127; /* TX & RX 65-127 byte Frame Counter */ 417 u32 tr127; /* TX & RX 65-127 byte Frame Counter */
418 u32 tr255; /* TX & RX 128-255 byte Frame Counter */ 418 u32 tr255; /* TX & RX 128-255 byte Frame Counter */
419 u32 tr511; /* TX & RX 256-511 byte Frame Counter */ 419 u32 tr511; /* TX & RX 256-511 byte Frame Counter */
420 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */ 420 u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */
421 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */ 421 u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */
422 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */ 422 u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */
423 u32 rbyt; /* RX Byte Counter */ 423 u32 rbyt; /* RX Byte Counter */
424 u32 rpkt; /* RX Packet Counter */ 424 u32 rpkt; /* RX Packet Counter */
425 u32 rfcs; /* RX FCS Error Counter */ 425 u32 rfcs; /* RX FCS Error Counter */
426 u32 rmca; /* RX Multicast Packet Counter */ 426 u32 rmca; /* RX Multicast Packet Counter */
427 u32 rbca; /* RX Broadcast Packet Counter */ 427 u32 rbca; /* RX Broadcast Packet Counter */
428 u32 rxcf; /* RX Control Frame Packet Counter */ 428 u32 rxcf; /* RX Control Frame Packet Counter */
429 u32 rxpf; /* RX Pause Frame Packet Counter */ 429 u32 rxpf; /* RX Pause Frame Packet Counter */
430 u32 rxuo; /* RX Unknown OP Code Counter */ 430 u32 rxuo; /* RX Unknown OP Code Counter */
431 u32 raln; /* RX Alignment Error Counter */ 431 u32 raln; /* RX Alignment Error Counter */
432 u32 rflr; /* RX Frame Len Error Counter */ 432 u32 rflr; /* RX Frame Len Error Counter */
433 u32 rcde; /* RX Code Error Counter */ 433 u32 rcde; /* RX Code Error Counter */
434 u32 rcse; /* RX Carrier Sense Error Counter */ 434 u32 rcse; /* RX Carrier Sense Error Counter */
435 u32 rund; /* RX Undersize Packet Counter */ 435 u32 rund; /* RX Undersize Packet Counter */
436 u32 rovr; /* RX Oversize Packet Counter */ 436 u32 rovr; /* RX Oversize Packet Counter */
437 u32 rfrg; /* RX Fragments Counter */ 437 u32 rfrg; /* RX Fragments Counter */
438 u32 rjbr; /* RX Jabber Counter */ 438 u32 rjbr; /* RX Jabber Counter */
439 u32 rdrp; /* RX Drop Counter */ 439 u32 rdrp; /* RX Drop Counter */
440 u32 tbyt; /* TX Byte Counter Counter */ 440 u32 tbyt; /* TX Byte Counter Counter */
441 u32 tpkt; /* TX Packet Counter */ 441 u32 tpkt; /* TX Packet Counter */
442 u32 tmca; /* TX Multicast Packet Counter */ 442 u32 tmca; /* TX Multicast Packet Counter */
443 u32 tbca; /* TX Broadcast Packet Counter */ 443 u32 tbca; /* TX Broadcast Packet Counter */
444 u32 txpf; /* TX Pause Control Frame Counter */ 444 u32 txpf; /* TX Pause Control Frame Counter */
445 u32 tdfr; /* TX Deferral Packet Counter */ 445 u32 tdfr; /* TX Deferral Packet Counter */
446 u32 tedf; /* TX Excessive Deferral Packet Counter */ 446 u32 tedf; /* TX Excessive Deferral Packet Counter */
447 u32 tscl; /* TX Single Collision Packet Counter */ 447 u32 tscl; /* TX Single Collision Packet Counter */
448 u32 tmcl; /* TX Multiple Collision Packet Counter */ 448 u32 tmcl; /* TX Multiple Collision Packet Counter */
449 u32 tlcl; /* TX Late Collision Packet Counter */ 449 u32 tlcl; /* TX Late Collision Packet Counter */
450 u32 txcl; /* TX Excessive Collision Packet Counter */ 450 u32 txcl; /* TX Excessive Collision Packet Counter */
451 u32 tncl; /* TX Total Collision Counter */ 451 u32 tncl; /* TX Total Collision Counter */
452 u8 res21[4]; 452 u8 res21[4];
453 u32 tdrp; /* TX Drop Frame Counter */ 453 u32 tdrp; /* TX Drop Frame Counter */
454 u32 tjbr; /* TX Jabber Frame Counter */ 454 u32 tjbr; /* TX Jabber Frame Counter */
455 u32 tfcs; /* TX FCS Error Counter */ 455 u32 tfcs; /* TX FCS Error Counter */
456 u32 txcf; /* TX Control Frame Counter */ 456 u32 txcf; /* TX Control Frame Counter */
457 u32 tovr; /* TX Oversize Frame Counter */ 457 u32 tovr; /* TX Oversize Frame Counter */
458 u32 tund; /* TX Undersize Frame Counter */ 458 u32 tund; /* TX Undersize Frame Counter */
459 u32 tfrg; /* TX Fragments Frame Counter */ 459 u32 tfrg; /* TX Fragments Frame Counter */
460 u32 car1; /* Carry One */ 460 u32 car1; /* Carry One */
461 u32 car2; /* Carry Two */ 461 u32 car2; /* Carry Two */
462 u32 cam1; /* Carry Mask One */ 462 u32 cam1; /* Carry Mask One */
463 u32 cam2; /* Carry Mask Two */ 463 u32 cam2; /* Carry Mask Two */
464 u8 res22[192]; 464 u8 res22[192];
465 u32 iaddr0; /* Indivdual addr 0 */ 465 u32 iaddr0; /* Indivdual addr 0 */
466 u32 iaddr1; /* Indivdual addr 1 */ 466 u32 iaddr1; /* Indivdual addr 1 */
467 u32 iaddr2; /* Indivdual addr 2 */ 467 u32 iaddr2; /* Indivdual addr 2 */
468 u32 iaddr3; /* Indivdual addr 3 */ 468 u32 iaddr3; /* Indivdual addr 3 */
469 u32 iaddr4; /* Indivdual addr 4 */ 469 u32 iaddr4; /* Indivdual addr 4 */
470 u32 iaddr5; /* Indivdual addr 5 */ 470 u32 iaddr5; /* Indivdual addr 5 */
471 u32 iaddr6; /* Indivdual addr 6 */ 471 u32 iaddr6; /* Indivdual addr 6 */
472 u32 iaddr7; /* Indivdual addr 7 */ 472 u32 iaddr7; /* Indivdual addr 7 */
473 u8 res23[96]; 473 u8 res23[96];
474 u32 gaddr0; /* Global addr 0 */ 474 u32 gaddr0; /* Global addr 0 */
475 u32 gaddr1; /* Global addr 1 */ 475 u32 gaddr1; /* Global addr 1 */
476 u32 gaddr2; /* Global addr 2 */ 476 u32 gaddr2; /* Global addr 2 */
477 u32 gaddr3; /* Global addr 3 */ 477 u32 gaddr3; /* Global addr 3 */
478 u32 gaddr4; /* Global addr 4 */ 478 u32 gaddr4; /* Global addr 4 */
479 u32 gaddr5; /* Global addr 5 */ 479 u32 gaddr5; /* Global addr 5 */
480 u32 gaddr6; /* Global addr 6 */ 480 u32 gaddr6; /* Global addr 6 */
481 u32 gaddr7; /* Global addr 7 */ 481 u32 gaddr7; /* Global addr 7 */
482 u8 res24[96]; 482 u8 res24[96];
483 u32 pmd0; /* Pattern Match Data */ 483 u32 pmd0; /* Pattern Match Data */
484 u8 res25[4]; 484 u8 res25[4];
485 u32 pmask0; /* Pattern Mask */ 485 u32 pmask0; /* Pattern Mask */
486 u8 res26[4]; 486 u8 res26[4];
487 u32 pcntrl0; /* Pattern Match Control */ 487 u32 pcntrl0; /* Pattern Match Control */
488 u8 res27[4]; 488 u8 res27[4];
489 u32 pattrb0; /* Pattern Match Attrs */ 489 u32 pattrb0; /* Pattern Match Attrs */
490 u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */ 490 u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */
491 u32 pmd1; /* Pattern Match Data */ 491 u32 pmd1; /* Pattern Match Data */
492 u8 res28[4]; 492 u8 res28[4];
493 u32 pmask1; /* Pattern Mask */ 493 u32 pmask1; /* Pattern Mask */
494 u8 res29[4]; 494 u8 res29[4];
495 u32 pcntrl1; /* Pattern Match Control */ 495 u32 pcntrl1; /* Pattern Match Control */
496 u8 res30[4]; 496 u8 res30[4];
497 u32 pattrb1; /* Pattern Match Attrs */ 497 u32 pattrb1; /* Pattern Match Attrs */
498 u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */ 498 u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */
499 u32 pmd2; /* Pattern Match Data */ 499 u32 pmd2; /* Pattern Match Data */
500 u8 res31[4]; 500 u8 res31[4];
501 u32 pmask2; /* Pattern Mask */ 501 u32 pmask2; /* Pattern Mask */
502 u8 res32[4]; 502 u8 res32[4];
503 u32 pcntrl2; /* Pattern Match Control */ 503 u32 pcntrl2; /* Pattern Match Control */
504 u8 res33[4]; 504 u8 res33[4];
505 u32 pattrb2; /* Pattern Match Attrs */ 505 u32 pattrb2; /* Pattern Match Attrs */
506 u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */ 506 u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */
507 u32 pmd3; /* Pattern Match Data */ 507 u32 pmd3; /* Pattern Match Data */
508 u8 res34[4]; 508 u8 res34[4];
509 u32 pmask3; /* Pattern Mask */ 509 u32 pmask3; /* Pattern Mask */
510 u8 res35[4]; 510 u8 res35[4];
511 u32 pcntrl3; /* Pattern Match Control */ 511 u32 pcntrl3; /* Pattern Match Control */
512 u8 res36[4]; 512 u8 res36[4];
513 u32 pattrb3; /* Pattern Match Attrs */ 513 u32 pattrb3; /* Pattern Match Attrs */
514 u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */ 514 u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */
515 u32 pmd4; /* Pattern Match Data */ 515 u32 pmd4; /* Pattern Match Data */
516 u8 res37[4]; 516 u8 res37[4];
517 u32 pmask4; /* Pattern Mask */ 517 u32 pmask4; /* Pattern Mask */
518 u8 res38[4]; 518 u8 res38[4];
519 u32 pcntrl4; /* Pattern Match Control */ 519 u32 pcntrl4; /* Pattern Match Control */
520 u8 res39[4]; 520 u8 res39[4];
521 u32 pattrb4; /* Pattern Match Attrs */ 521 u32 pattrb4; /* Pattern Match Attrs */
522 u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */ 522 u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */
523 u32 pmd5; /* Pattern Match Data */ 523 u32 pmd5; /* Pattern Match Data */
524 u8 res40[4]; 524 u8 res40[4];
525 u32 pmask5; /* Pattern Mask */ 525 u32 pmask5; /* Pattern Mask */
526 u8 res41[4]; 526 u8 res41[4];
527 u32 pcntrl5; /* Pattern Match Control */ 527 u32 pcntrl5; /* Pattern Match Control */
528 u8 res42[4]; 528 u8 res42[4];
529 u32 pattrb5; /* Pattern Match Attrs */ 529 u32 pattrb5; /* Pattern Match Attrs */
530 u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */ 530 u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */
531 u32 pmd6; /* Pattern Match Data */ 531 u32 pmd6; /* Pattern Match Data */
532 u8 res43[4]; 532 u8 res43[4];
533 u32 pmask6; /* Pattern Mask */ 533 u32 pmask6; /* Pattern Mask */
534 u8 res44[4]; 534 u8 res44[4];
535 u32 pcntrl6; /* Pattern Match Control */ 535 u32 pcntrl6; /* Pattern Match Control */
536 u8 res45[4]; 536 u8 res45[4];
537 u32 pattrb6; /* Pattern Match Attrs */ 537 u32 pattrb6; /* Pattern Match Attrs */
538 u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */ 538 u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */
539 u32 pmd7; /* Pattern Match Data */ 539 u32 pmd7; /* Pattern Match Data */
540 u8 res46[4]; 540 u8 res46[4];
541 u32 pmask7; /* Pattern Mask */ 541 u32 pmask7; /* Pattern Mask */
542 u8 res47[4]; 542 u8 res47[4];
543 u32 pcntrl7; /* Pattern Match Control */ 543 u32 pcntrl7; /* Pattern Match Control */
544 u8 res48[4]; 544 u8 res48[4];
545 u32 pattrb7; /* Pattern Match Attrs */ 545 u32 pattrb7; /* Pattern Match Attrs */
546 u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */ 546 u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */
547 u32 pmd8; /* Pattern Match Data */ 547 u32 pmd8; /* Pattern Match Data */
548 u8 res49[4]; 548 u8 res49[4];
549 u32 pmask8; /* Pattern Mask */ 549 u32 pmask8; /* Pattern Mask */
550 u8 res50[4]; 550 u8 res50[4];
551 u32 pcntrl8; /* Pattern Match Control */ 551 u32 pcntrl8; /* Pattern Match Control */
552 u8 res51[4]; 552 u8 res51[4];
553 u32 pattrb8; /* Pattern Match Attrs */ 553 u32 pattrb8; /* Pattern Match Attrs */
554 u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */ 554 u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */
555 u32 pmd9; /* Pattern Match Data */ 555 u32 pmd9; /* Pattern Match Data */
556 u8 res52[4]; 556 u8 res52[4];
557 u32 pmask9; /* Pattern Mask */ 557 u32 pmask9; /* Pattern Mask */
558 u8 res53[4]; 558 u8 res53[4];
559 u32 pcntrl9; /* Pattern Match Control */ 559 u32 pcntrl9; /* Pattern Match Control */
560 u8 res54[4]; 560 u8 res54[4];
561 u32 pattrb9; /* Pattern Match Attrs */ 561 u32 pattrb9; /* Pattern Match Attrs */
562 u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */ 562 u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */
563 u32 pmd10; /* Pattern Match Data */ 563 u32 pmd10; /* Pattern Match Data */
564 u8 res55[4]; 564 u8 res55[4];
565 u32 pmask10; /* Pattern Mask */ 565 u32 pmask10; /* Pattern Mask */
566 u8 res56[4]; 566 u8 res56[4];
567 u32 pcntrl10; /* Pattern Match Control */ 567 u32 pcntrl10; /* Pattern Match Control */
568 u8 res57[4]; 568 u8 res57[4];
569 u32 pattrb10; /* Pattern Match Attrs */ 569 u32 pattrb10; /* Pattern Match Attrs */
570 u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */ 570 u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */
571 u32 pmd11; /* Pattern Match Data */ 571 u32 pmd11; /* Pattern Match Data */
572 u8 res58[4]; 572 u8 res58[4];
573 u32 pmask11; /* Pattern Mask */ 573 u32 pmask11; /* Pattern Mask */
574 u8 res59[4]; 574 u8 res59[4];
575 u32 pcntrl11; /* Pattern Match Control */ 575 u32 pcntrl11; /* Pattern Match Control */
576 u8 res60[4]; 576 u8 res60[4];
577 u32 pattrb11; /* Pattern Match Attrs */ 577 u32 pattrb11; /* Pattern Match Attrs */
578 u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */ 578 u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */
579 u32 pmd12; /* Pattern Match Data */ 579 u32 pmd12; /* Pattern Match Data */
580 u8 res61[4]; 580 u8 res61[4];
581 u32 pmask12; /* Pattern Mask */ 581 u32 pmask12; /* Pattern Mask */
582 u8 res62[4]; 582 u8 res62[4];
583 u32 pcntrl12; /* Pattern Match Control */ 583 u32 pcntrl12; /* Pattern Match Control */
584 u8 res63[4]; 584 u8 res63[4];
585 u32 pattrb12; /* Pattern Match Attrs */ 585 u32 pattrb12; /* Pattern Match Attrs */
586 u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */ 586 u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */
587 u32 pmd13; /* Pattern Match Data */ 587 u32 pmd13; /* Pattern Match Data */
588 u8 res64[4]; 588 u8 res64[4];
589 u32 pmask13; /* Pattern Mask */ 589 u32 pmask13; /* Pattern Mask */
590 u8 res65[4]; 590 u8 res65[4];
591 u32 pcntrl13; /* Pattern Match Control */ 591 u32 pcntrl13; /* Pattern Match Control */
592 u8 res66[4]; 592 u8 res66[4];
593 u32 pattrb13; /* Pattern Match Attrs */ 593 u32 pattrb13; /* Pattern Match Attrs */
594 u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */ 594 u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */
595 u32 pmd14; /* Pattern Match Data */ 595 u32 pmd14; /* Pattern Match Data */
596 u8 res67[4]; 596 u8 res67[4];
597 u32 pmask14; /* Pattern Mask */ 597 u32 pmask14; /* Pattern Mask */
598 u8 res68[4]; 598 u8 res68[4];
599 u32 pcntrl14; /* Pattern Match Control */ 599 u32 pcntrl14; /* Pattern Match Control */
600 u8 res69[4]; 600 u8 res69[4];
601 u32 pattrb14; /* Pattern Match Attrs */ 601 u32 pattrb14; /* Pattern Match Attrs */
602 u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */ 602 u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */
603 u32 pmd15; /* Pattern Match Data */ 603 u32 pmd15; /* Pattern Match Data */
604 u8 res70[4]; 604 u8 res70[4];
605 u32 pmask15; /* Pattern Mask */ 605 u32 pmask15; /* Pattern Mask */
606 u8 res71[4]; 606 u8 res71[4];
607 u32 pcntrl15; /* Pattern Match Control */ 607 u32 pcntrl15; /* Pattern Match Control */
608 u8 res72[4]; 608 u8 res72[4];
609 u32 pattrb15; /* Pattern Match Attrs */ 609 u32 pattrb15; /* Pattern Match Attrs */
610 u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */ 610 u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */
611 u8 res73[248]; 611 u8 res73[248];
612 u32 attr; /* Attrs */ 612 u32 attr; /* Attrs */
613 u32 attreli; /* Attrs Extract Len & Idx */ 613 u32 attreli; /* Attrs Extract Len & Idx */
614 u8 res74[1024]; 614 u8 res74[1024];
615 } ccsr_tsec_t; 615 } ccsr_tsec_t;
616 616
617 /* PIC Registers */ 617 /* PIC Registers */
618 typedef struct ccsr_pic { 618 typedef struct ccsr_pic {
619 u8 res1[64]; 619 u8 res1[64];
620 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */ 620 u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */
621 u8 res2[12]; 621 u8 res2[12];
622 u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */ 622 u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */
623 u8 res3[12]; 623 u8 res3[12];
624 u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */ 624 u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */
625 u8 res4[12]; 625 u8 res4[12];
626 u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */ 626 u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */
627 u8 res5[12]; 627 u8 res5[12];
628 u32 ctpr; /* Current Task Priority */ 628 u32 ctpr; /* Current Task Priority */
629 u8 res6[12]; 629 u8 res6[12];
630 u32 whoami; /* Who Am I */ 630 u32 whoami; /* Who Am I */
631 u8 res7[12]; 631 u8 res7[12];
632 u32 iack; /* IRQ Acknowledge */ 632 u32 iack; /* IRQ Acknowledge */
633 u8 res8[12]; 633 u8 res8[12];
634 u32 eoi; /* End Of IRQ */ 634 u32 eoi; /* End Of IRQ */
635 u8 res9[3916]; 635 u8 res9[3916];
636 u32 frr; /* Feature Reporting */ 636 u32 frr; /* Feature Reporting */
637 u8 res10[28]; 637 u8 res10[28];
638 u32 gcr; /* Global Configuration */ 638 u32 gcr; /* Global Configuration */
639 #define MPC85xx_PICGCR_RST 0x80000000 639 #define MPC85xx_PICGCR_RST 0x80000000
640 #define MPC85xx_PICGCR_M 0x20000000 640 #define MPC85xx_PICGCR_M 0x20000000
641 u8 res11[92]; 641 u8 res11[92];
642 u32 vir; /* Vendor Identification */ 642 u32 vir; /* Vendor Identification */
643 u8 res12[12]; 643 u8 res12[12];
644 u32 pir; /* Processor Initialization */ 644 u32 pir; /* Processor Initialization */
645 u8 res13[12]; 645 u8 res13[12];
646 u32 ipivpr0; /* IPI Vector/Priority 0 */ 646 u32 ipivpr0; /* IPI Vector/Priority 0 */
647 u8 res14[12]; 647 u8 res14[12];
648 u32 ipivpr1; /* IPI Vector/Priority 1 */ 648 u32 ipivpr1; /* IPI Vector/Priority 1 */
649 u8 res15[12]; 649 u8 res15[12];
650 u32 ipivpr2; /* IPI Vector/Priority 2 */ 650 u32 ipivpr2; /* IPI Vector/Priority 2 */
651 u8 res16[12]; 651 u8 res16[12];
652 u32 ipivpr3; /* IPI Vector/Priority 3 */ 652 u32 ipivpr3; /* IPI Vector/Priority 3 */
653 u8 res17[12]; 653 u8 res17[12];
654 u32 svr; /* Spurious Vector */ 654 u32 svr; /* Spurious Vector */
655 u8 res18[12]; 655 u8 res18[12];
656 u32 tfrr; /* Timer Frequency Reporting */ 656 u32 tfrr; /* Timer Frequency Reporting */
657 u8 res19[12]; 657 u8 res19[12];
658 u32 gtccr0; /* Global Timer Current Count 0 */ 658 u32 gtccr0; /* Global Timer Current Count 0 */
659 u8 res20[12]; 659 u8 res20[12];
660 u32 gtbcr0; /* Global Timer Base Count 0 */ 660 u32 gtbcr0; /* Global Timer Base Count 0 */
661 u8 res21[12]; 661 u8 res21[12];
662 u32 gtvpr0; /* Global Timer Vector/Priority 0 */ 662 u32 gtvpr0; /* Global Timer Vector/Priority 0 */
663 u8 res22[12]; 663 u8 res22[12];
664 u32 gtdr0; /* Global Timer Destination 0 */ 664 u32 gtdr0; /* Global Timer Destination 0 */
665 u8 res23[12]; 665 u8 res23[12];
666 u32 gtccr1; /* Global Timer Current Count 1 */ 666 u32 gtccr1; /* Global Timer Current Count 1 */
667 u8 res24[12]; 667 u8 res24[12];
668 u32 gtbcr1; /* Global Timer Base Count 1 */ 668 u32 gtbcr1; /* Global Timer Base Count 1 */
669 u8 res25[12]; 669 u8 res25[12];
670 u32 gtvpr1; /* Global Timer Vector/Priority 1 */ 670 u32 gtvpr1; /* Global Timer Vector/Priority 1 */
671 u8 res26[12]; 671 u8 res26[12];
672 u32 gtdr1; /* Global Timer Destination 1 */ 672 u32 gtdr1; /* Global Timer Destination 1 */
673 u8 res27[12]; 673 u8 res27[12];
674 u32 gtccr2; /* Global Timer Current Count 2 */ 674 u32 gtccr2; /* Global Timer Current Count 2 */
675 u8 res28[12]; 675 u8 res28[12];
676 u32 gtbcr2; /* Global Timer Base Count 2 */ 676 u32 gtbcr2; /* Global Timer Base Count 2 */
677 u8 res29[12]; 677 u8 res29[12];
678 u32 gtvpr2; /* Global Timer Vector/Priority 2 */ 678 u32 gtvpr2; /* Global Timer Vector/Priority 2 */
679 u8 res30[12]; 679 u8 res30[12];
680 u32 gtdr2; /* Global Timer Destination 2 */ 680 u32 gtdr2; /* Global Timer Destination 2 */
681 u8 res31[12]; 681 u8 res31[12];
682 u32 gtccr3; /* Global Timer Current Count 3 */ 682 u32 gtccr3; /* Global Timer Current Count 3 */
683 u8 res32[12]; 683 u8 res32[12];
684 u32 gtbcr3; /* Global Timer Base Count 3 */ 684 u32 gtbcr3; /* Global Timer Base Count 3 */
685 u8 res33[12]; 685 u8 res33[12];
686 u32 gtvpr3; /* Global Timer Vector/Priority 3 */ 686 u32 gtvpr3; /* Global Timer Vector/Priority 3 */
687 u8 res34[12]; 687 u8 res34[12];
688 u32 gtdr3; /* Global Timer Destination 3 */ 688 u32 gtdr3; /* Global Timer Destination 3 */
689 u8 res35[268]; 689 u8 res35[268];
690 u32 tcr; /* Timer Control */ 690 u32 tcr; /* Timer Control */
691 u8 res36[12]; 691 u8 res36[12];
692 u32 irqsr0; /* IRQ_OUT Summary 0 */ 692 u32 irqsr0; /* IRQ_OUT Summary 0 */
693 u8 res37[12]; 693 u8 res37[12];
694 u32 irqsr1; /* IRQ_OUT Summary 1 */ 694 u32 irqsr1; /* IRQ_OUT Summary 1 */
695 u8 res38[12]; 695 u8 res38[12];
696 u32 cisr0; /* Critical IRQ Summary 0 */ 696 u32 cisr0; /* Critical IRQ Summary 0 */
697 u8 res39[12]; 697 u8 res39[12];
698 u32 cisr1; /* Critical IRQ Summary 1 */ 698 u32 cisr1; /* Critical IRQ Summary 1 */
699 u8 res40[188]; 699 u8 res40[188];
700 u32 msgr0; /* Message 0 */ 700 u32 msgr0; /* Message 0 */
701 u8 res41[12]; 701 u8 res41[12];
702 u32 msgr1; /* Message 1 */ 702 u32 msgr1; /* Message 1 */
703 u8 res42[12]; 703 u8 res42[12];
704 u32 msgr2; /* Message 2 */ 704 u32 msgr2; /* Message 2 */
705 u8 res43[12]; 705 u8 res43[12];
706 u32 msgr3; /* Message 3 */ 706 u32 msgr3; /* Message 3 */
707 u8 res44[204]; 707 u8 res44[204];
708 u32 mer; /* Message Enable */ 708 u32 mer; /* Message Enable */
709 u8 res45[12]; 709 u8 res45[12];
710 u32 msr; /* Message Status */ 710 u32 msr; /* Message Status */
711 u8 res46[60140]; 711 u8 res46[60140];
712 u32 eivpr0; /* External IRQ Vector/Priority 0 */ 712 u32 eivpr0; /* External IRQ Vector/Priority 0 */
713 u8 res47[12]; 713 u8 res47[12];
714 u32 eidr0; /* External IRQ Destination 0 */ 714 u32 eidr0; /* External IRQ Destination 0 */
715 u8 res48[12]; 715 u8 res48[12];
716 u32 eivpr1; /* External IRQ Vector/Priority 1 */ 716 u32 eivpr1; /* External IRQ Vector/Priority 1 */
717 u8 res49[12]; 717 u8 res49[12];
718 u32 eidr1; /* External IRQ Destination 1 */ 718 u32 eidr1; /* External IRQ Destination 1 */
719 u8 res50[12]; 719 u8 res50[12];
720 u32 eivpr2; /* External IRQ Vector/Priority 2 */ 720 u32 eivpr2; /* External IRQ Vector/Priority 2 */
721 u8 res51[12]; 721 u8 res51[12];
722 u32 eidr2; /* External IRQ Destination 2 */ 722 u32 eidr2; /* External IRQ Destination 2 */
723 u8 res52[12]; 723 u8 res52[12];
724 u32 eivpr3; /* External IRQ Vector/Priority 3 */ 724 u32 eivpr3; /* External IRQ Vector/Priority 3 */
725 u8 res53[12]; 725 u8 res53[12];
726 u32 eidr3; /* External IRQ Destination 3 */ 726 u32 eidr3; /* External IRQ Destination 3 */
727 u8 res54[12]; 727 u8 res54[12];
728 u32 eivpr4; /* External IRQ Vector/Priority 4 */ 728 u32 eivpr4; /* External IRQ Vector/Priority 4 */
729 u8 res55[12]; 729 u8 res55[12];
730 u32 eidr4; /* External IRQ Destination 4 */ 730 u32 eidr4; /* External IRQ Destination 4 */
731 u8 res56[12]; 731 u8 res56[12];
732 u32 eivpr5; /* External IRQ Vector/Priority 5 */ 732 u32 eivpr5; /* External IRQ Vector/Priority 5 */
733 u8 res57[12]; 733 u8 res57[12];
734 u32 eidr5; /* External IRQ Destination 5 */ 734 u32 eidr5; /* External IRQ Destination 5 */
735 u8 res58[12]; 735 u8 res58[12];
736 u32 eivpr6; /* External IRQ Vector/Priority 6 */ 736 u32 eivpr6; /* External IRQ Vector/Priority 6 */
737 u8 res59[12]; 737 u8 res59[12];
738 u32 eidr6; /* External IRQ Destination 6 */ 738 u32 eidr6; /* External IRQ Destination 6 */
739 u8 res60[12]; 739 u8 res60[12];
740 u32 eivpr7; /* External IRQ Vector/Priority 7 */ 740 u32 eivpr7; /* External IRQ Vector/Priority 7 */
741 u8 res61[12]; 741 u8 res61[12];
742 u32 eidr7; /* External IRQ Destination 7 */ 742 u32 eidr7; /* External IRQ Destination 7 */
743 u8 res62[12]; 743 u8 res62[12];
744 u32 eivpr8; /* External IRQ Vector/Priority 8 */ 744 u32 eivpr8; /* External IRQ Vector/Priority 8 */
745 u8 res63[12]; 745 u8 res63[12];
746 u32 eidr8; /* External IRQ Destination 8 */ 746 u32 eidr8; /* External IRQ Destination 8 */
747 u8 res64[12]; 747 u8 res64[12];
748 u32 eivpr9; /* External IRQ Vector/Priority 9 */ 748 u32 eivpr9; /* External IRQ Vector/Priority 9 */
749 u8 res65[12]; 749 u8 res65[12];
750 u32 eidr9; /* External IRQ Destination 9 */ 750 u32 eidr9; /* External IRQ Destination 9 */
751 u8 res66[12]; 751 u8 res66[12];
752 u32 eivpr10; /* External IRQ Vector/Priority 10 */ 752 u32 eivpr10; /* External IRQ Vector/Priority 10 */
753 u8 res67[12]; 753 u8 res67[12];
754 u32 eidr10; /* External IRQ Destination 10 */ 754 u32 eidr10; /* External IRQ Destination 10 */
755 u8 res68[12]; 755 u8 res68[12];
756 u32 eivpr11; /* External IRQ Vector/Priority 11 */ 756 u32 eivpr11; /* External IRQ Vector/Priority 11 */
757 u8 res69[12]; 757 u8 res69[12];
758 u32 eidr11; /* External IRQ Destination 11 */ 758 u32 eidr11; /* External IRQ Destination 11 */
759 u8 res70[140]; 759 u8 res70[140];
760 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */ 760 u32 iivpr0; /* Internal IRQ Vector/Priority 0 */
761 u8 res71[12]; 761 u8 res71[12];
762 u32 iidr0; /* Internal IRQ Destination 0 */ 762 u32 iidr0; /* Internal IRQ Destination 0 */
763 u8 res72[12]; 763 u8 res72[12];
764 u32 iivpr1; /* Internal IRQ Vector/Priority 1 */ 764 u32 iivpr1; /* Internal IRQ Vector/Priority 1 */
765 u8 res73[12]; 765 u8 res73[12];
766 u32 iidr1; /* Internal IRQ Destination 1 */ 766 u32 iidr1; /* Internal IRQ Destination 1 */
767 u8 res74[12]; 767 u8 res74[12];
768 u32 iivpr2; /* Internal IRQ Vector/Priority 2 */ 768 u32 iivpr2; /* Internal IRQ Vector/Priority 2 */
769 u8 res75[12]; 769 u8 res75[12];
770 u32 iidr2; /* Internal IRQ Destination 2 */ 770 u32 iidr2; /* Internal IRQ Destination 2 */
771 u8 res76[12]; 771 u8 res76[12];
772 u32 iivpr3; /* Internal IRQ Vector/Priority 3 */ 772 u32 iivpr3; /* Internal IRQ Vector/Priority 3 */
773 u8 res77[12]; 773 u8 res77[12];
774 u32 iidr3; /* Internal IRQ Destination 3 */ 774 u32 iidr3; /* Internal IRQ Destination 3 */
775 u8 res78[12]; 775 u8 res78[12];
776 u32 iivpr4; /* Internal IRQ Vector/Priority 4 */ 776 u32 iivpr4; /* Internal IRQ Vector/Priority 4 */
777 u8 res79[12]; 777 u8 res79[12];
778 u32 iidr4; /* Internal IRQ Destination 4 */ 778 u32 iidr4; /* Internal IRQ Destination 4 */
779 u8 res80[12]; 779 u8 res80[12];
780 u32 iivpr5; /* Internal IRQ Vector/Priority 5 */ 780 u32 iivpr5; /* Internal IRQ Vector/Priority 5 */
781 u8 res81[12]; 781 u8 res81[12];
782 u32 iidr5; /* Internal IRQ Destination 5 */ 782 u32 iidr5; /* Internal IRQ Destination 5 */
783 u8 res82[12]; 783 u8 res82[12];
784 u32 iivpr6; /* Internal IRQ Vector/Priority 6 */ 784 u32 iivpr6; /* Internal IRQ Vector/Priority 6 */
785 u8 res83[12]; 785 u8 res83[12];
786 u32 iidr6; /* Internal IRQ Destination 6 */ 786 u32 iidr6; /* Internal IRQ Destination 6 */
787 u8 res84[12]; 787 u8 res84[12];
788 u32 iivpr7; /* Internal IRQ Vector/Priority 7 */ 788 u32 iivpr7; /* Internal IRQ Vector/Priority 7 */
789 u8 res85[12]; 789 u8 res85[12];
790 u32 iidr7; /* Internal IRQ Destination 7 */ 790 u32 iidr7; /* Internal IRQ Destination 7 */
791 u8 res86[12]; 791 u8 res86[12];
792 u32 iivpr8; /* Internal IRQ Vector/Priority 8 */ 792 u32 iivpr8; /* Internal IRQ Vector/Priority 8 */
793 u8 res87[12]; 793 u8 res87[12];
794 u32 iidr8; /* Internal IRQ Destination 8 */ 794 u32 iidr8; /* Internal IRQ Destination 8 */
795 u8 res88[12]; 795 u8 res88[12];
796 u32 iivpr9; /* Internal IRQ Vector/Priority 9 */ 796 u32 iivpr9; /* Internal IRQ Vector/Priority 9 */
797 u8 res89[12]; 797 u8 res89[12];
798 u32 iidr9; /* Internal IRQ Destination 9 */ 798 u32 iidr9; /* Internal IRQ Destination 9 */
799 u8 res90[12]; 799 u8 res90[12];
800 u32 iivpr10; /* Internal IRQ Vector/Priority 10 */ 800 u32 iivpr10; /* Internal IRQ Vector/Priority 10 */
801 u8 res91[12]; 801 u8 res91[12];
802 u32 iidr10; /* Internal IRQ Destination 10 */ 802 u32 iidr10; /* Internal IRQ Destination 10 */
803 u8 res92[12]; 803 u8 res92[12];
804 u32 iivpr11; /* Internal IRQ Vector/Priority 11 */ 804 u32 iivpr11; /* Internal IRQ Vector/Priority 11 */
805 u8 res93[12]; 805 u8 res93[12];
806 u32 iidr11; /* Internal IRQ Destination 11 */ 806 u32 iidr11; /* Internal IRQ Destination 11 */
807 u8 res94[12]; 807 u8 res94[12];
808 u32 iivpr12; /* Internal IRQ Vector/Priority 12 */ 808 u32 iivpr12; /* Internal IRQ Vector/Priority 12 */
809 u8 res95[12]; 809 u8 res95[12];
810 u32 iidr12; /* Internal IRQ Destination 12 */ 810 u32 iidr12; /* Internal IRQ Destination 12 */
811 u8 res96[12]; 811 u8 res96[12];
812 u32 iivpr13; /* Internal IRQ Vector/Priority 13 */ 812 u32 iivpr13; /* Internal IRQ Vector/Priority 13 */
813 u8 res97[12]; 813 u8 res97[12];
814 u32 iidr13; /* Internal IRQ Destination 13 */ 814 u32 iidr13; /* Internal IRQ Destination 13 */
815 u8 res98[12]; 815 u8 res98[12];
816 u32 iivpr14; /* Internal IRQ Vector/Priority 14 */ 816 u32 iivpr14; /* Internal IRQ Vector/Priority 14 */
817 u8 res99[12]; 817 u8 res99[12];
818 u32 iidr14; /* Internal IRQ Destination 14 */ 818 u32 iidr14; /* Internal IRQ Destination 14 */
819 u8 res100[12]; 819 u8 res100[12];
820 u32 iivpr15; /* Internal IRQ Vector/Priority 15 */ 820 u32 iivpr15; /* Internal IRQ Vector/Priority 15 */
821 u8 res101[12]; 821 u8 res101[12];
822 u32 iidr15; /* Internal IRQ Destination 15 */ 822 u32 iidr15; /* Internal IRQ Destination 15 */
823 u8 res102[12]; 823 u8 res102[12];
824 u32 iivpr16; /* Internal IRQ Vector/Priority 16 */ 824 u32 iivpr16; /* Internal IRQ Vector/Priority 16 */
825 u8 res103[12]; 825 u8 res103[12];
826 u32 iidr16; /* Internal IRQ Destination 16 */ 826 u32 iidr16; /* Internal IRQ Destination 16 */
827 u8 res104[12]; 827 u8 res104[12];
828 u32 iivpr17; /* Internal IRQ Vector/Priority 17 */ 828 u32 iivpr17; /* Internal IRQ Vector/Priority 17 */
829 u8 res105[12]; 829 u8 res105[12];
830 u32 iidr17; /* Internal IRQ Destination 17 */ 830 u32 iidr17; /* Internal IRQ Destination 17 */
831 u8 res106[12]; 831 u8 res106[12];
832 u32 iivpr18; /* Internal IRQ Vector/Priority 18 */ 832 u32 iivpr18; /* Internal IRQ Vector/Priority 18 */
833 u8 res107[12]; 833 u8 res107[12];
834 u32 iidr18; /* Internal IRQ Destination 18 */ 834 u32 iidr18; /* Internal IRQ Destination 18 */
835 u8 res108[12]; 835 u8 res108[12];
836 u32 iivpr19; /* Internal IRQ Vector/Priority 19 */ 836 u32 iivpr19; /* Internal IRQ Vector/Priority 19 */
837 u8 res109[12]; 837 u8 res109[12];
838 u32 iidr19; /* Internal IRQ Destination 19 */ 838 u32 iidr19; /* Internal IRQ Destination 19 */
839 u8 res110[12]; 839 u8 res110[12];
840 u32 iivpr20; /* Internal IRQ Vector/Priority 20 */ 840 u32 iivpr20; /* Internal IRQ Vector/Priority 20 */
841 u8 res111[12]; 841 u8 res111[12];
842 u32 iidr20; /* Internal IRQ Destination 20 */ 842 u32 iidr20; /* Internal IRQ Destination 20 */
843 u8 res112[12]; 843 u8 res112[12];
844 u32 iivpr21; /* Internal IRQ Vector/Priority 21 */ 844 u32 iivpr21; /* Internal IRQ Vector/Priority 21 */
845 u8 res113[12]; 845 u8 res113[12];
846 u32 iidr21; /* Internal IRQ Destination 21 */ 846 u32 iidr21; /* Internal IRQ Destination 21 */
847 u8 res114[12]; 847 u8 res114[12];
848 u32 iivpr22; /* Internal IRQ Vector/Priority 22 */ 848 u32 iivpr22; /* Internal IRQ Vector/Priority 22 */
849 u8 res115[12]; 849 u8 res115[12];
850 u32 iidr22; /* Internal IRQ Destination 22 */ 850 u32 iidr22; /* Internal IRQ Destination 22 */
851 u8 res116[12]; 851 u8 res116[12];
852 u32 iivpr23; /* Internal IRQ Vector/Priority 23 */ 852 u32 iivpr23; /* Internal IRQ Vector/Priority 23 */
853 u8 res117[12]; 853 u8 res117[12];
854 u32 iidr23; /* Internal IRQ Destination 23 */ 854 u32 iidr23; /* Internal IRQ Destination 23 */
855 u8 res118[12]; 855 u8 res118[12];
856 u32 iivpr24; /* Internal IRQ Vector/Priority 24 */ 856 u32 iivpr24; /* Internal IRQ Vector/Priority 24 */
857 u8 res119[12]; 857 u8 res119[12];
858 u32 iidr24; /* Internal IRQ Destination 24 */ 858 u32 iidr24; /* Internal IRQ Destination 24 */
859 u8 res120[12]; 859 u8 res120[12];
860 u32 iivpr25; /* Internal IRQ Vector/Priority 25 */ 860 u32 iivpr25; /* Internal IRQ Vector/Priority 25 */
861 u8 res121[12]; 861 u8 res121[12];
862 u32 iidr25; /* Internal IRQ Destination 25 */ 862 u32 iidr25; /* Internal IRQ Destination 25 */
863 u8 res122[12]; 863 u8 res122[12];
864 u32 iivpr26; /* Internal IRQ Vector/Priority 26 */ 864 u32 iivpr26; /* Internal IRQ Vector/Priority 26 */
865 u8 res123[12]; 865 u8 res123[12];
866 u32 iidr26; /* Internal IRQ Destination 26 */ 866 u32 iidr26; /* Internal IRQ Destination 26 */
867 u8 res124[12]; 867 u8 res124[12];
868 u32 iivpr27; /* Internal IRQ Vector/Priority 27 */ 868 u32 iivpr27; /* Internal IRQ Vector/Priority 27 */
869 u8 res125[12]; 869 u8 res125[12];
870 u32 iidr27; /* Internal IRQ Destination 27 */ 870 u32 iidr27; /* Internal IRQ Destination 27 */
871 u8 res126[12]; 871 u8 res126[12];
872 u32 iivpr28; /* Internal IRQ Vector/Priority 28 */ 872 u32 iivpr28; /* Internal IRQ Vector/Priority 28 */
873 u8 res127[12]; 873 u8 res127[12];
874 u32 iidr28; /* Internal IRQ Destination 28 */ 874 u32 iidr28; /* Internal IRQ Destination 28 */
875 u8 res128[12]; 875 u8 res128[12];
876 u32 iivpr29; /* Internal IRQ Vector/Priority 29 */ 876 u32 iivpr29; /* Internal IRQ Vector/Priority 29 */
877 u8 res129[12]; 877 u8 res129[12];
878 u32 iidr29; /* Internal IRQ Destination 29 */ 878 u32 iidr29; /* Internal IRQ Destination 29 */
879 u8 res130[12]; 879 u8 res130[12];
880 u32 iivpr30; /* Internal IRQ Vector/Priority 30 */ 880 u32 iivpr30; /* Internal IRQ Vector/Priority 30 */
881 u8 res131[12]; 881 u8 res131[12];
882 u32 iidr30; /* Internal IRQ Destination 30 */ 882 u32 iidr30; /* Internal IRQ Destination 30 */
883 u8 res132[12]; 883 u8 res132[12];
884 u32 iivpr31; /* Internal IRQ Vector/Priority 31 */ 884 u32 iivpr31; /* Internal IRQ Vector/Priority 31 */
885 u8 res133[12]; 885 u8 res133[12];
886 u32 iidr31; /* Internal IRQ Destination 31 */ 886 u32 iidr31; /* Internal IRQ Destination 31 */
887 u8 res134[4108]; 887 u8 res134[4108];
888 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */ 888 u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */
889 u8 res135[12]; 889 u8 res135[12];
890 u32 midr0; /* Messaging IRQ Destination 0 */ 890 u32 midr0; /* Messaging IRQ Destination 0 */
891 u8 res136[12]; 891 u8 res136[12];
892 u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */ 892 u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */
893 u8 res137[12]; 893 u8 res137[12];
894 u32 midr1; /* Messaging IRQ Destination 1 */ 894 u32 midr1; /* Messaging IRQ Destination 1 */
895 u8 res138[12]; 895 u8 res138[12];
896 u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */ 896 u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */
897 u8 res139[12]; 897 u8 res139[12];
898 u32 midr2; /* Messaging IRQ Destination 2 */ 898 u32 midr2; /* Messaging IRQ Destination 2 */
899 u8 res140[12]; 899 u8 res140[12];
900 u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */ 900 u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */
901 u8 res141[12]; 901 u8 res141[12];
902 u32 midr3; /* Messaging IRQ Destination 3 */ 902 u32 midr3; /* Messaging IRQ Destination 3 */
903 u8 res142[59852]; 903 u8 res142[59852];
904 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */ 904 u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */
905 u8 res143[12]; 905 u8 res143[12];
906 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */ 906 u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */
907 u8 res144[12]; 907 u8 res144[12];
908 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */ 908 u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */
909 u8 res145[12]; 909 u8 res145[12];
910 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */ 910 u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */
911 u8 res146[12]; 911 u8 res146[12];
912 u32 ctpr0; /* Current Task Priority for Processor 0 */ 912 u32 ctpr0; /* Current Task Priority for Processor 0 */
913 u8 res147[12]; 913 u8 res147[12];
914 u32 whoami0; /* Who Am I for Processor 0 */ 914 u32 whoami0; /* Who Am I for Processor 0 */
915 u8 res148[12]; 915 u8 res148[12];
916 u32 iack0; /* IRQ Acknowledge for Processor 0 */ 916 u32 iack0; /* IRQ Acknowledge for Processor 0 */
917 u8 res149[12]; 917 u8 res149[12];
918 u32 eoi0; /* End Of IRQ for Processor 0 */ 918 u32 eoi0; /* End Of IRQ for Processor 0 */
919 u8 res150[130892]; 919 u8 res150[130892];
920 } ccsr_pic_t; 920 } ccsr_pic_t;
921 921
922 /* CPM Block */ 922 /* CPM Block */
923 #ifndef CONFIG_CPM2 923 #ifndef CONFIG_CPM2
924 typedef struct ccsr_cpm { 924 typedef struct ccsr_cpm {
925 u8 res[262144]; 925 u8 res[262144];
926 } ccsr_cpm_t; 926 } ccsr_cpm_t;
927 #else 927 #else
928 /* 928 /*
929 * DPARM 929 * DPARM
930 * General SIU 930 * General SIU
931 */ 931 */
932 typedef struct ccsr_cpm_siu { 932 typedef struct ccsr_cpm_siu {
933 u8 res1[80]; 933 u8 res1[80];
934 u32 smaer; 934 u32 smaer;
935 u32 smser; 935 u32 smser;
936 u32 smevr; 936 u32 smevr;
937 u8 res2[4]; 937 u8 res2[4];
938 u32 lmaer; 938 u32 lmaer;
939 u32 lmser; 939 u32 lmser;
940 u32 lmevr; 940 u32 lmevr;
941 u8 res3[2964]; 941 u8 res3[2964];
942 } ccsr_cpm_siu_t; 942 } ccsr_cpm_siu_t;
943 943
944 /* IRQ Controller */ 944 /* IRQ Controller */
945 typedef struct ccsr_cpm_intctl { 945 typedef struct ccsr_cpm_intctl {
946 u16 sicr; 946 u16 sicr;
947 u8 res1[2]; 947 u8 res1[2];
948 u32 sivec; 948 u32 sivec;
949 u32 sipnrh; 949 u32 sipnrh;
950 u32 sipnrl; 950 u32 sipnrl;
951 u32 siprr; 951 u32 siprr;
952 u32 scprrh; 952 u32 scprrh;
953 u32 scprrl; 953 u32 scprrl;
954 u32 simrh; 954 u32 simrh;
955 u32 simrl; 955 u32 simrl;
956 u32 siexr; 956 u32 siexr;
957 u8 res2[88]; 957 u8 res2[88];
958 u32 sccr; 958 u32 sccr;
959 u8 res3[124]; 959 u8 res3[124];
960 } ccsr_cpm_intctl_t; 960 } ccsr_cpm_intctl_t;
961 961
962 /* input/output port */ 962 /* input/output port */
963 typedef struct ccsr_cpm_iop { 963 typedef struct ccsr_cpm_iop {
964 u32 pdira; 964 u32 pdira;
965 u32 ppara; 965 u32 ppara;
966 u32 psora; 966 u32 psora;
967 u32 podra; 967 u32 podra;
968 u32 pdata; 968 u32 pdata;
969 u8 res1[12]; 969 u8 res1[12];
970 u32 pdirb; 970 u32 pdirb;
971 u32 pparb; 971 u32 pparb;
972 u32 psorb; 972 u32 psorb;
973 u32 podrb; 973 u32 podrb;
974 u32 pdatb; 974 u32 pdatb;
975 u8 res2[12]; 975 u8 res2[12];
976 u32 pdirc; 976 u32 pdirc;
977 u32 pparc; 977 u32 pparc;
978 u32 psorc; 978 u32 psorc;
979 u32 podrc; 979 u32 podrc;
980 u32 pdatc; 980 u32 pdatc;
981 u8 res3[12]; 981 u8 res3[12];
982 u32 pdird; 982 u32 pdird;
983 u32 ppard; 983 u32 ppard;
984 u32 psord; 984 u32 psord;
985 u32 podrd; 985 u32 podrd;
986 u32 pdatd; 986 u32 pdatd;
987 u8 res4[12]; 987 u8 res4[12];
988 } ccsr_cpm_iop_t; 988 } ccsr_cpm_iop_t;
989 989
990 /* CPM timers */ 990 /* CPM timers */
991 typedef struct ccsr_cpm_timer { 991 typedef struct ccsr_cpm_timer {
992 u8 tgcr1; 992 u8 tgcr1;
993 u8 res1[3]; 993 u8 res1[3];
994 u8 tgcr2; 994 u8 tgcr2;
995 u8 res2[11]; 995 u8 res2[11];
996 u16 tmr1; 996 u16 tmr1;
997 u16 tmr2; 997 u16 tmr2;
998 u16 trr1; 998 u16 trr1;
999 u16 trr2; 999 u16 trr2;
1000 u16 tcr1; 1000 u16 tcr1;
1001 u16 tcr2; 1001 u16 tcr2;
1002 u16 tcn1; 1002 u16 tcn1;
1003 u16 tcn2; 1003 u16 tcn2;
1004 u16 tmr3; 1004 u16 tmr3;
1005 u16 tmr4; 1005 u16 tmr4;
1006 u16 trr3; 1006 u16 trr3;
1007 u16 trr4; 1007 u16 trr4;
1008 u16 tcr3; 1008 u16 tcr3;
1009 u16 tcr4; 1009 u16 tcr4;
1010 u16 tcn3; 1010 u16 tcn3;
1011 u16 tcn4; 1011 u16 tcn4;
1012 u16 ter1; 1012 u16 ter1;
1013 u16 ter2; 1013 u16 ter2;
1014 u16 ter3; 1014 u16 ter3;
1015 u16 ter4; 1015 u16 ter4;
1016 u8 res3[608]; 1016 u8 res3[608];
1017 } ccsr_cpm_timer_t; 1017 } ccsr_cpm_timer_t;
1018 1018
1019 /* SDMA */ 1019 /* SDMA */
1020 typedef struct ccsr_cpm_sdma { 1020 typedef struct ccsr_cpm_sdma {
1021 u8 sdsr; 1021 u8 sdsr;
1022 u8 res1[3]; 1022 u8 res1[3];
1023 u8 sdmr; 1023 u8 sdmr;
1024 u8 res2[739]; 1024 u8 res2[739];
1025 } ccsr_cpm_sdma_t; 1025 } ccsr_cpm_sdma_t;
1026 1026
1027 /* FCC1 */ 1027 /* FCC1 */
1028 typedef struct ccsr_cpm_fcc1 { 1028 typedef struct ccsr_cpm_fcc1 {
1029 u32 gfmr; 1029 u32 gfmr;
1030 u32 fpsmr; 1030 u32 fpsmr;
1031 u16 ftodr; 1031 u16 ftodr;
1032 u8 res1[2]; 1032 u8 res1[2];
1033 u16 fdsr; 1033 u16 fdsr;
1034 u8 res2[2]; 1034 u8 res2[2];
1035 u16 fcce; 1035 u16 fcce;
1036 u8 res3[2]; 1036 u8 res3[2];
1037 u16 fccm; 1037 u16 fccm;
1038 u8 res4[2]; 1038 u8 res4[2];
1039 u8 fccs; 1039 u8 fccs;
1040 u8 res5[3]; 1040 u8 res5[3];
1041 u8 ftirr_phy[4]; 1041 u8 ftirr_phy[4];
1042 } ccsr_cpm_fcc1_t; 1042 } ccsr_cpm_fcc1_t;
1043 1043
1044 /* FCC2 */ 1044 /* FCC2 */
1045 typedef struct ccsr_cpm_fcc2 { 1045 typedef struct ccsr_cpm_fcc2 {
1046 u32 gfmr; 1046 u32 gfmr;
1047 u32 fpsmr; 1047 u32 fpsmr;
1048 u16 ftodr; 1048 u16 ftodr;
1049 u8 res1[2]; 1049 u8 res1[2];
1050 u16 fdsr; 1050 u16 fdsr;
1051 u8 res2[2]; 1051 u8 res2[2];
1052 u16 fcce; 1052 u16 fcce;
1053 u8 res3[2]; 1053 u8 res3[2];
1054 u16 fccm; 1054 u16 fccm;
1055 u8 res4[2]; 1055 u8 res4[2];
1056 u8 fccs; 1056 u8 fccs;
1057 u8 res5[3]; 1057 u8 res5[3];
1058 u8 ftirr_phy[4]; 1058 u8 ftirr_phy[4];
1059 } ccsr_cpm_fcc2_t; 1059 } ccsr_cpm_fcc2_t;
1060 1060
1061 /* FCC3 */ 1061 /* FCC3 */
1062 typedef struct ccsr_cpm_fcc3 { 1062 typedef struct ccsr_cpm_fcc3 {
1063 u32 gfmr; 1063 u32 gfmr;
1064 u32 fpsmr; 1064 u32 fpsmr;
1065 u16 ftodr; 1065 u16 ftodr;
1066 u8 res1[2]; 1066 u8 res1[2];
1067 u16 fdsr; 1067 u16 fdsr;
1068 u8 res2[2]; 1068 u8 res2[2];
1069 u16 fcce; 1069 u16 fcce;
1070 u8 res3[2]; 1070 u8 res3[2];
1071 u16 fccm; 1071 u16 fccm;
1072 u8 res4[2]; 1072 u8 res4[2];
1073 u8 fccs; 1073 u8 fccs;
1074 u8 res5[3]; 1074 u8 res5[3];
1075 u8 res[36]; 1075 u8 res[36];
1076 } ccsr_cpm_fcc3_t; 1076 } ccsr_cpm_fcc3_t;
1077 1077
1078 /* FCC1 extended */ 1078 /* FCC1 extended */
1079 typedef struct ccsr_cpm_fcc1_ext { 1079 typedef struct ccsr_cpm_fcc1_ext {
1080 u32 firper; 1080 u32 firper;
1081 u32 firer; 1081 u32 firer;
1082 u32 firsr_h; 1082 u32 firsr_h;
1083 u32 firsr_l; 1083 u32 firsr_l;
1084 u8 gfemr; 1084 u8 gfemr;
1085 u8 res[15]; 1085 u8 res[15];
1086 1086
1087 } ccsr_cpm_fcc1_ext_t; 1087 } ccsr_cpm_fcc1_ext_t;
1088 1088
1089 /* FCC2 extended */ 1089 /* FCC2 extended */
1090 typedef struct ccsr_cpm_fcc2_ext { 1090 typedef struct ccsr_cpm_fcc2_ext {
1091 u32 firper; 1091 u32 firper;
1092 u32 firer; 1092 u32 firer;
1093 u32 firsr_h; 1093 u32 firsr_h;
1094 u32 firsr_l; 1094 u32 firsr_l;
1095 u8 gfemr; 1095 u8 gfemr;
1096 u8 res[31]; 1096 u8 res[31];
1097 } ccsr_cpm_fcc2_ext_t; 1097 } ccsr_cpm_fcc2_ext_t;
1098 1098
1099 /* FCC3 extended */ 1099 /* FCC3 extended */
1100 typedef struct ccsr_cpm_fcc3_ext { 1100 typedef struct ccsr_cpm_fcc3_ext {
1101 u8 gfemr; 1101 u8 gfemr;
1102 u8 res[47]; 1102 u8 res[47];
1103 } ccsr_cpm_fcc3_ext_t; 1103 } ccsr_cpm_fcc3_ext_t;
1104 1104
1105 /* TC layers */ 1105 /* TC layers */
1106 typedef struct ccsr_cpm_tmp1 { 1106 typedef struct ccsr_cpm_tmp1 {
1107 u8 res[496]; 1107 u8 res[496];
1108 } ccsr_cpm_tmp1_t; 1108 } ccsr_cpm_tmp1_t;
1109 1109
1110 /* BRGs:5,6,7,8 */ 1110 /* BRGs:5,6,7,8 */
1111 typedef struct ccsr_cpm_brg2 { 1111 typedef struct ccsr_cpm_brg2 {
1112 u32 brgc5; 1112 u32 brgc5;
1113 u32 brgc6; 1113 u32 brgc6;
1114 u32 brgc7; 1114 u32 brgc7;
1115 u32 brgc8; 1115 u32 brgc8;
1116 u8 res[608]; 1116 u8 res[608];
1117 } ccsr_cpm_brg2_t; 1117 } ccsr_cpm_brg2_t;
1118 1118
1119 /* I2C */ 1119 /* I2C */
1120 typedef struct ccsr_cpm_i2c { 1120 typedef struct ccsr_cpm_i2c {
1121 u8 i2mod; 1121 u8 i2mod;
1122 u8 res1[3]; 1122 u8 res1[3];
1123 u8 i2add; 1123 u8 i2add;
1124 u8 res2[3]; 1124 u8 res2[3];
1125 u8 i2brg; 1125 u8 i2brg;
1126 u8 res3[3]; 1126 u8 res3[3];
1127 u8 i2com; 1127 u8 i2com;
1128 u8 res4[3]; 1128 u8 res4[3];
1129 u8 i2cer; 1129 u8 i2cer;
1130 u8 res5[3]; 1130 u8 res5[3];
1131 u8 i2cmr; 1131 u8 i2cmr;
1132 u8 res6[331]; 1132 u8 res6[331];
1133 } ccsr_cpm_i2c_t; 1133 } ccsr_cpm_i2c_t;
1134 1134
1135 /* CPM core */ 1135 /* CPM core */
1136 typedef struct ccsr_cpm_cp { 1136 typedef struct ccsr_cpm_cp {
1137 u32 cpcr; 1137 u32 cpcr;
1138 u32 rccr; 1138 u32 rccr;
1139 u8 res1[14]; 1139 u8 res1[14];
1140 u16 rter; 1140 u16 rter;
1141 u8 res2[2]; 1141 u8 res2[2];
1142 u16 rtmr; 1142 u16 rtmr;
1143 u16 rtscr; 1143 u16 rtscr;
1144 u8 res3[2]; 1144 u8 res3[2];
1145 u32 rtsr; 1145 u32 rtsr;
1146 u8 res4[12]; 1146 u8 res4[12];
1147 } ccsr_cpm_cp_t; 1147 } ccsr_cpm_cp_t;
1148 1148
1149 /* BRGs:1,2,3,4 */ 1149 /* BRGs:1,2,3,4 */
1150 typedef struct ccsr_cpm_brg1 { 1150 typedef struct ccsr_cpm_brg1 {
1151 u32 brgc1; 1151 u32 brgc1;
1152 u32 brgc2; 1152 u32 brgc2;
1153 u32 brgc3; 1153 u32 brgc3;
1154 u32 brgc4; 1154 u32 brgc4;
1155 } ccsr_cpm_brg1_t; 1155 } ccsr_cpm_brg1_t;
1156 1156
1157 /* SCC1-SCC4 */ 1157 /* SCC1-SCC4 */
1158 typedef struct ccsr_cpm_scc { 1158 typedef struct ccsr_cpm_scc {
1159 u32 gsmrl; 1159 u32 gsmrl;
1160 u32 gsmrh; 1160 u32 gsmrh;
1161 u16 psmr; 1161 u16 psmr;
1162 u8 res1[2]; 1162 u8 res1[2];
1163 u16 todr; 1163 u16 todr;
1164 u16 dsr; 1164 u16 dsr;
1165 u16 scce; 1165 u16 scce;
1166 u8 res2[2]; 1166 u8 res2[2];
1167 u16 sccm; 1167 u16 sccm;
1168 u8 res3; 1168 u8 res3;
1169 u8 sccs; 1169 u8 sccs;
1170 u8 res4[8]; 1170 u8 res4[8];
1171 } ccsr_cpm_scc_t; 1171 } ccsr_cpm_scc_t;
1172 1172
1173 typedef struct ccsr_cpm_tmp2 { 1173 typedef struct ccsr_cpm_tmp2 {
1174 u8 res[32]; 1174 u8 res[32];
1175 } ccsr_cpm_tmp2_t; 1175 } ccsr_cpm_tmp2_t;
1176 1176
1177 /* SPI */ 1177 /* SPI */
1178 typedef struct ccsr_cpm_spi { 1178 typedef struct ccsr_cpm_spi {
1179 u16 spmode; 1179 u16 spmode;
1180 u8 res1[4]; 1180 u8 res1[4];
1181 u8 spie; 1181 u8 spie;
1182 u8 res2[3]; 1182 u8 res2[3];
1183 u8 spim; 1183 u8 spim;
1184 u8 res3[2]; 1184 u8 res3[2];
1185 u8 spcom; 1185 u8 spcom;
1186 u8 res4[82]; 1186 u8 res4[82];
1187 } ccsr_cpm_spi_t; 1187 } ccsr_cpm_spi_t;
1188 1188
1189 /* CPM MUX */ 1189 /* CPM MUX */
1190 typedef struct ccsr_cpm_mux { 1190 typedef struct ccsr_cpm_mux {
1191 u8 cmxsi1cr; 1191 u8 cmxsi1cr;
1192 u8 res1; 1192 u8 res1;
1193 u8 cmxsi2cr; 1193 u8 cmxsi2cr;
1194 u8 res2; 1194 u8 res2;
1195 u32 cmxfcr; 1195 u32 cmxfcr;
1196 u32 cmxscr; 1196 u32 cmxscr;
1197 u8 res3[2]; 1197 u8 res3[2];
1198 u16 cmxuar; 1198 u16 cmxuar;
1199 u8 res4[16]; 1199 u8 res4[16];
1200 } ccsr_cpm_mux_t; 1200 } ccsr_cpm_mux_t;
1201 1201
1202 /* SI,MCC,etc */ 1202 /* SI,MCC,etc */
1203 typedef struct ccsr_cpm_tmp3 { 1203 typedef struct ccsr_cpm_tmp3 {
1204 u8 res[58592]; 1204 u8 res[58592];
1205 } ccsr_cpm_tmp3_t; 1205 } ccsr_cpm_tmp3_t;
1206 1206
1207 typedef struct ccsr_cpm_iram { 1207 typedef struct ccsr_cpm_iram {
1208 u32 iram[8192]; 1208 u32 iram[8192];
1209 u8 res[98304]; 1209 u8 res[98304];
1210 } ccsr_cpm_iram_t; 1210 } ccsr_cpm_iram_t;
1211 1211
1212 typedef struct ccsr_cpm { 1212 typedef struct ccsr_cpm {
1213 /* Some references are into the unique & known dpram spaces, 1213 /* Some references are into the unique & known dpram spaces,
1214 * others are from the generic base. 1214 * others are from the generic base.
1215 */ 1215 */
1216 #define im_dprambase im_dpram1 1216 #define im_dprambase im_dpram1
1217 u8 im_dpram1[16*1024]; 1217 u8 im_dpram1[16*1024];
1218 u8 res1[16*1024]; 1218 u8 res1[16*1024];
1219 u8 im_dpram2[16*1024]; 1219 u8 im_dpram2[16*1024];
1220 u8 res2[16*1024]; 1220 u8 res2[16*1024];
1221 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ 1221 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
1222 ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */ 1222 ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */
1223 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ 1223 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
1224 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ 1224 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */
1225 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ 1225 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */
1226 ccsr_cpm_fcc1_t im_cpm_fcc1; 1226 ccsr_cpm_fcc1_t im_cpm_fcc1;
1227 ccsr_cpm_fcc2_t im_cpm_fcc2; 1227 ccsr_cpm_fcc2_t im_cpm_fcc2;
1228 ccsr_cpm_fcc3_t im_cpm_fcc3; 1228 ccsr_cpm_fcc3_t im_cpm_fcc3;
1229 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext; 1229 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext;
1230 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext; 1230 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext;
1231 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext; 1231 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext;
1232 ccsr_cpm_tmp1_t im_cpm_tmp1; 1232 ccsr_cpm_tmp1_t im_cpm_tmp1;
1233 ccsr_cpm_brg2_t im_cpm_brg2; 1233 ccsr_cpm_brg2_t im_cpm_brg2;
1234 ccsr_cpm_i2c_t im_cpm_i2c; 1234 ccsr_cpm_i2c_t im_cpm_i2c;
1235 ccsr_cpm_cp_t im_cpm_cp; 1235 ccsr_cpm_cp_t im_cpm_cp;
1236 ccsr_cpm_brg1_t im_cpm_brg1; 1236 ccsr_cpm_brg1_t im_cpm_brg1;
1237 ccsr_cpm_scc_t im_cpm_scc[4]; 1237 ccsr_cpm_scc_t im_cpm_scc[4];
1238 ccsr_cpm_tmp2_t im_cpm_tmp2; 1238 ccsr_cpm_tmp2_t im_cpm_tmp2;
1239 ccsr_cpm_spi_t im_cpm_spi; 1239 ccsr_cpm_spi_t im_cpm_spi;
1240 ccsr_cpm_mux_t im_cpm_mux; 1240 ccsr_cpm_mux_t im_cpm_mux;
1241 ccsr_cpm_tmp3_t im_cpm_tmp3; 1241 ccsr_cpm_tmp3_t im_cpm_tmp3;
1242 ccsr_cpm_iram_t im_cpm_iram; 1242 ccsr_cpm_iram_t im_cpm_iram;
1243 } ccsr_cpm_t; 1243 } ccsr_cpm_t;
1244 #endif 1244 #endif
1245 1245
1246 #ifdef CONFIG_SYS_SRIO 1246 #ifdef CONFIG_SYS_SRIO
1247 /* Architectural regsiters */ 1247 /* Architectural regsiters */
1248 struct rio_arch { 1248 struct rio_arch {
1249 u32 didcar; /* Device Identity CAR */ 1249 u32 didcar; /* Device Identity CAR */
1250 u32 dicar; /* Device Information CAR */ 1250 u32 dicar; /* Device Information CAR */
1251 u32 aidcar; /* Assembly Identity CAR */ 1251 u32 aidcar; /* Assembly Identity CAR */
1252 u32 aicar; /* Assembly Information CAR */ 1252 u32 aicar; /* Assembly Information CAR */
1253 u32 pefcar; /* Processing Element Features CAR */ 1253 u32 pefcar; /* Processing Element Features CAR */
1254 u8 res0[4]; 1254 u8 res0[4];
1255 u32 socar; /* Source Operations CAR */ 1255 u32 socar; /* Source Operations CAR */
1256 u32 docar; /* Destination Operations CAR */ 1256 u32 docar; /* Destination Operations CAR */
1257 u8 res1[32]; 1257 u8 res1[32];
1258 u32 mcsr; /* Mailbox CSR */ 1258 u32 mcsr; /* Mailbox CSR */
1259 u32 pwdcsr; /* Port-Write and Doorbell CSR */ 1259 u32 pwdcsr; /* Port-Write and Doorbell CSR */
1260 u8 res2[4]; 1260 u8 res2[4];
1261 u32 pellccsr; /* Processing Element Logic Layer CCSR */ 1261 u32 pellccsr; /* Processing Element Logic Layer CCSR */
1262 u8 res3[12]; 1262 u8 res3[12];
1263 u32 lcsbacsr; /* Local Configuration Space BACSR */ 1263 u32 lcsbacsr; /* Local Configuration Space BACSR */
1264 u32 bdidcsr; /* Base Device ID CSR */ 1264 u32 bdidcsr; /* Base Device ID CSR */
1265 u8 res4[4]; 1265 u8 res4[4];
1266 u32 hbdidlcsr; /* Host Base Device ID Lock CSR */ 1266 u32 hbdidlcsr; /* Host Base Device ID Lock CSR */
1267 u32 ctcsr; /* Component Tag CSR */ 1267 u32 ctcsr; /* Component Tag CSR */
1268 }; 1268 };
1269 1269
1270 /* Extended Features Space: 1x/4x LP-Serial Port registers */ 1270 /* Extended Features Space: 1x/4x LP-Serial Port registers */
1271 struct rio_lp_serial_port { 1271 struct rio_lp_serial_port {
1272 u32 plmreqcsr; /* Port Link Maintenance Request CSR */ 1272 u32 plmreqcsr; /* Port Link Maintenance Request CSR */
1273 u32 plmrespcsr; /* Port Link Maintenance Response CS */ 1273 u32 plmrespcsr; /* Port Link Maintenance Response CS */
1274 u32 plascsr; /* Port Local Ackid Status CSR */ 1274 u32 plascsr; /* Port Local Ackid Status CSR */
1275 u8 res0[12]; 1275 u8 res0[12];
1276 u32 pescsr; /* Port Error and Status CSR */ 1276 u32 pescsr; /* Port Error and Status CSR */
1277 u32 pccsr; /* Port Control CSR */ 1277 u32 pccsr; /* Port Control CSR */
1278 }; 1278 };
1279 1279
1280 /* Extended Features Space: 1x/4x LP-Serial registers */ 1280 /* Extended Features Space: 1x/4x LP-Serial registers */
1281 struct rio_lp_serial { 1281 struct rio_lp_serial {
1282 u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */ 1282 u32 pmbh0csr; /* Port Maintenance Block Header 0 CSR */
1283 u8 res0[28]; 1283 u8 res0[28];
1284 u32 pltoccsr; /* Port Link Time-out CCSR */ 1284 u32 pltoccsr; /* Port Link Time-out CCSR */
1285 u32 prtoccsr; /* Port Response Time-out CCSR */ 1285 u32 prtoccsr; /* Port Response Time-out CCSR */
1286 u8 res1[20]; 1286 u8 res1[20];
1287 u32 pgccsr; /* Port General CSR */ 1287 u32 pgccsr; /* Port General CSR */
1288 struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1288 struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1289 }; 1289 };
1290 1290
1291 /* Logical error reporting registers */ 1291 /* Logical error reporting registers */
1292 struct rio_logical_err { 1292 struct rio_logical_err {
1293 u32 erbh; /* Error Reporting Block Header Register */ 1293 u32 erbh; /* Error Reporting Block Header Register */
1294 u8 res0[4]; 1294 u8 res0[4];
1295 u32 ltledcsr; /* Logical/Transport layer error DCSR */ 1295 u32 ltledcsr; /* Logical/Transport layer error DCSR */
1296 u32 ltleecsr; /* Logical/Transport layer error ECSR */ 1296 u32 ltleecsr; /* Logical/Transport layer error ECSR */
1297 u8 res1[4]; 1297 u8 res1[4];
1298 u32 ltlaccsr; /* Logical/Transport layer ACCSR */ 1298 u32 ltlaccsr; /* Logical/Transport layer ACCSR */
1299 u32 ltldidccsr; /* Logical/Transport layer DID CCSR */ 1299 u32 ltldidccsr; /* Logical/Transport layer DID CCSR */
1300 u32 ltlcccsr; /* Logical/Transport layer control CCSR */ 1300 u32 ltlcccsr; /* Logical/Transport layer control CCSR */
1301 }; 1301 };
1302 1302
1303 /* Physical error reporting port registers */ 1303 /* Physical error reporting port registers */
1304 struct rio_phys_err_port { 1304 struct rio_phys_err_port {
1305 u32 edcsr; /* Port error detect CSR */ 1305 u32 edcsr; /* Port error detect CSR */
1306 u32 erecsr; /* Port error rate enable CSR */ 1306 u32 erecsr; /* Port error rate enable CSR */
1307 u32 ecacsr; /* Port error capture attributes CSR */ 1307 u32 ecacsr; /* Port error capture attributes CSR */
1308 u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */ 1308 u32 pcseccsr0; /* Port packet/control symbol ECCSR 0 */
1309 u32 peccsr[3]; /* Port error capture CSR */ 1309 u32 peccsr[3]; /* Port error capture CSR */
1310 u8 res0[12]; 1310 u8 res0[12];
1311 u32 ercsr; /* Port error rate CSR */ 1311 u32 ercsr; /* Port error rate CSR */
1312 u32 ertcsr; /* Port error rate threshold CSR */ 1312 u32 ertcsr; /* Port error rate threshold CSR */
1313 u8 res1[16]; 1313 u8 res1[16];
1314 }; 1314 };
1315 1315
1316 /* Physical error reporting registers */ 1316 /* Physical error reporting registers */
1317 struct rio_phys_err { 1317 struct rio_phys_err {
1318 struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1318 struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1319 }; 1319 };
1320 1320
1321 /* Implementation Space: General Port-Common */ 1321 /* Implementation Space: General Port-Common */
1322 struct rio_impl_common { 1322 struct rio_impl_common {
1323 u8 res0[4]; 1323 u8 res0[4];
1324 u32 llcr; /* Logical Layer Configuration Register */ 1324 u32 llcr; /* Logical Layer Configuration Register */
1325 u8 res1[8]; 1325 u8 res1[8];
1326 u32 epwisr; /* Error / Port-Write Interrupt SR */ 1326 u32 epwisr; /* Error / Port-Write Interrupt SR */
1327 u8 res2[12]; 1327 u8 res2[12];
1328 u32 lretcr; /* Logical Retry Error Threshold CR */ 1328 u32 lretcr; /* Logical Retry Error Threshold CR */
1329 u8 res3[92]; 1329 u8 res3[92];
1330 u32 pretcr; /* Physical Retry Erorr Threshold CR */ 1330 u32 pretcr; /* Physical Retry Erorr Threshold CR */
1331 u8 res4[124]; 1331 u8 res4[124];
1332 }; 1332 };
1333 1333
1334 /* Implementation Space: Port Specific */ 1334 /* Implementation Space: Port Specific */
1335 struct rio_impl_port_spec { 1335 struct rio_impl_port_spec {
1336 u32 adidcsr; /* Port Alt. Device ID CSR */ 1336 u32 adidcsr; /* Port Alt. Device ID CSR */
1337 u8 res0[28]; 1337 u8 res0[28];
1338 u32 ptaacr; /* Port Pass-Through/Accept-All CR */ 1338 u32 ptaacr; /* Port Pass-Through/Accept-All CR */
1339 u32 lopttlcr; 1339 u32 lopttlcr;
1340 u8 res1[8]; 1340 u8 res1[8];
1341 u32 iecsr; /* Port Implementation Error CSR */ 1341 u32 iecsr; /* Port Implementation Error CSR */
1342 u8 res2[12]; 1342 u8 res2[12];
1343 u32 pcr; /* Port Phsyical Configuration Register */ 1343 u32 pcr; /* Port Phsyical Configuration Register */
1344 u8 res3[20]; 1344 u8 res3[20];
1345 u32 slcsr; /* Port Serial Link CSR */ 1345 u32 slcsr; /* Port Serial Link CSR */
1346 u8 res4[4]; 1346 u8 res4[4];
1347 u32 sleicr; /* Port Serial Link Error Injection */ 1347 u32 sleicr; /* Port Serial Link Error Injection */
1348 u32 a0txcr; /* Port Arbitration 0 Tx CR */ 1348 u32 a0txcr; /* Port Arbitration 0 Tx CR */
1349 u32 a1txcr; /* Port Arbitration 1 Tx CR */ 1349 u32 a1txcr; /* Port Arbitration 1 Tx CR */
1350 u32 a2txcr; /* Port Arbitration 2 Tx CR */ 1350 u32 a2txcr; /* Port Arbitration 2 Tx CR */
1351 u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */ 1351 u32 mreqtxbacr[3]; /* Port Request Tx Buffer ACR */
1352 u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */ 1352 u32 mrspfctxbacr; /* Port Response/Flow Control Tx Buffer ACR */
1353 }; 1353 };
1354 1354
1355 /* Implementation Space: register */ 1355 /* Implementation Space: register */
1356 struct rio_implement { 1356 struct rio_implement {
1357 struct rio_impl_common com; 1357 struct rio_impl_common com;
1358 struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1358 struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1359 }; 1359 };
1360 1360
1361 /* Revision Control Register */ 1361 /* Revision Control Register */
1362 struct rio_rev_ctrl { 1362 struct rio_rev_ctrl {
1363 u32 ipbrr[2]; /* IP Block Revision Register */ 1363 u32 ipbrr[2]; /* IP Block Revision Register */
1364 }; 1364 };
1365 1365
1366 struct rio_atmu_row { 1366 struct rio_atmu_row {
1367 u32 rowtar; /* RapidIO Outbound Window TAR */ 1367 u32 rowtar; /* RapidIO Outbound Window TAR */
1368 u32 rowtear; /* RapidIO Outbound Window TEAR */ 1368 u32 rowtear; /* RapidIO Outbound Window TEAR */
1369 u32 rowbar; 1369 u32 rowbar;
1370 u8 res0[4]; 1370 u8 res0[4];
1371 u32 rowar; /* RapidIO Outbound Attributes Register */ 1371 u32 rowar; /* RapidIO Outbound Attributes Register */
1372 u32 rowsr[3]; /* Port RapidIO outbound window segment register */ 1372 u32 rowsr[3]; /* Port RapidIO outbound window segment register */
1373 }; 1373 };
1374 1374
1375 struct rio_atmu_riw { 1375 struct rio_atmu_riw {
1376 u32 riwtar; /* RapidIO Inbound Window Translation AR */ 1376 u32 riwtar; /* RapidIO Inbound Window Translation AR */
1377 u8 res0[4]; 1377 u8 res0[4];
1378 u32 riwbar; /* RapidIO Inbound Window Base AR */ 1378 u32 riwbar; /* RapidIO Inbound Window Base AR */
1379 u8 res1[4]; 1379 u8 res1[4];
1380 u32 riwar; /* RapidIO Inbound Attributes Register */ 1380 u32 riwar; /* RapidIO Inbound Attributes Register */
1381 u8 res2[12]; 1381 u8 res2[12];
1382 }; 1382 };
1383 1383
1384 /* ATMU window registers */ 1384 /* ATMU window registers */
1385 struct rio_atmu_win { 1385 struct rio_atmu_win {
1386 struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM]; 1386 struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
1387 u8 res0[64]; 1387 u8 res0[64];
1388 struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM]; 1388 struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
1389 }; 1389 };
1390 1390
1391 struct rio_atmu { 1391 struct rio_atmu {
1392 struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1392 struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1393 }; 1393 };
1394 1394
1395 #ifdef CONFIG_SYS_FSL_RMU 1395 #ifdef CONFIG_SYS_FSL_RMU
1396 struct rio_msg { 1396 struct rio_msg {
1397 u32 omr; /* Outbound Mode Register */ 1397 u32 omr; /* Outbound Mode Register */
1398 u32 osr; /* Outbound Status Register */ 1398 u32 osr; /* Outbound Status Register */
1399 u32 eodqdpar; /* Extended Outbound DQ DPAR */ 1399 u32 eodqdpar; /* Extended Outbound DQ DPAR */
1400 u32 odqdpar; /* Outbound Descriptor Queue DPAR */ 1400 u32 odqdpar; /* Outbound Descriptor Queue DPAR */
1401 u32 eosar; /* Extended Outbound Unit Source AR */ 1401 u32 eosar; /* Extended Outbound Unit Source AR */
1402 u32 osar; /* Outbound Unit Source AR */ 1402 u32 osar; /* Outbound Unit Source AR */
1403 u32 odpr; /* Outbound Destination Port Register */ 1403 u32 odpr; /* Outbound Destination Port Register */
1404 u32 odatr; /* Outbound Destination Attributes Register */ 1404 u32 odatr; /* Outbound Destination Attributes Register */
1405 u32 odcr; /* Outbound Doubleword Count Register */ 1405 u32 odcr; /* Outbound Doubleword Count Register */
1406 u32 eodqepar; /* Extended Outbound DQ EPAR */ 1406 u32 eodqepar; /* Extended Outbound DQ EPAR */
1407 u32 odqepar; /* Outbound Descriptor Queue EPAR */ 1407 u32 odqepar; /* Outbound Descriptor Queue EPAR */
1408 u32 oretr; /* Outbound Retry Error Threshold Register */ 1408 u32 oretr; /* Outbound Retry Error Threshold Register */
1409 u32 omgr; /* Outbound Multicast Group Register */ 1409 u32 omgr; /* Outbound Multicast Group Register */
1410 u32 omlr; /* Outbound Multicast List Register */ 1410 u32 omlr; /* Outbound Multicast List Register */
1411 u8 res0[40]; 1411 u8 res0[40];
1412 u32 imr; /* Outbound Mode Register */ 1412 u32 imr; /* Outbound Mode Register */
1413 u32 isr; /* Inbound Status Register */ 1413 u32 isr; /* Inbound Status Register */
1414 u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */ 1414 u32 eidqdpar; /* Extended Inbound Descriptor Queue DPAR */
1415 u32 idqdpar; /* Inbound Descriptor Queue DPAR */ 1415 u32 idqdpar; /* Inbound Descriptor Queue DPAR */
1416 u32 eifqepar; /* Extended Inbound Frame Queue EPAR */ 1416 u32 eifqepar; /* Extended Inbound Frame Queue EPAR */
1417 u32 ifqepar; /* Inbound Frame Queue EPAR */ 1417 u32 ifqepar; /* Inbound Frame Queue EPAR */
1418 u32 imirir; /* Inbound Maximum Interrutp RIR */ 1418 u32 imirir; /* Inbound Maximum Interrutp RIR */
1419 u8 res1[4]; 1419 u8 res1[4];
1420 u32 eihqepar; /* Extended inbound message header queue EPAR */ 1420 u32 eihqepar; /* Extended inbound message header queue EPAR */
1421 u32 ihqepar; /* Inbound message header queue EPAR */ 1421 u32 ihqepar; /* Inbound message header queue EPAR */
1422 u8 res2[120]; 1422 u8 res2[120];
1423 }; 1423 };
1424 1424
1425 struct rio_dbell { 1425 struct rio_dbell {
1426 u32 odmr; /* Outbound Doorbell Mode Register */ 1426 u32 odmr; /* Outbound Doorbell Mode Register */
1427 u32 odsr; /* Outbound Doorbell Status Register */ 1427 u32 odsr; /* Outbound Doorbell Status Register */
1428 u8 res0[16]; 1428 u8 res0[16];
1429 u32 oddpr; /* Outbound Doorbell Destination Port */ 1429 u32 oddpr; /* Outbound Doorbell Destination Port */
1430 u32 oddatr; /* Outbound Doorbell Destination AR */ 1430 u32 oddatr; /* Outbound Doorbell Destination AR */
1431 u8 res1[12]; 1431 u8 res1[12];
1432 u32 oddretr; /* Outbound Doorbell Retry Threshold CR */ 1432 u32 oddretr; /* Outbound Doorbell Retry Threshold CR */
1433 u8 res2[48]; 1433 u8 res2[48];
1434 u32 idmr; /* Inbound Doorbell Mode Register */ 1434 u32 idmr; /* Inbound Doorbell Mode Register */
1435 u32 idsr; /* Inbound Doorbell Status Register */ 1435 u32 idsr; /* Inbound Doorbell Status Register */
1436 u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */ 1436 u32 iedqdpar; /* Extended Inbound Doorbell Queue DPAR */
1437 u32 iqdpar; /* Inbound Doorbell Queue DPAR */ 1437 u32 iqdpar; /* Inbound Doorbell Queue DPAR */
1438 u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */ 1438 u32 iedqepar; /* Extended Inbound Doorbell Queue EPAR */
1439 u32 idqepar; /* Inbound Doorbell Queue EPAR */ 1439 u32 idqepar; /* Inbound Doorbell Queue EPAR */
1440 u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */ 1440 u32 idmirir; /* Inbound Doorbell Max Interrupt RIR */
1441 }; 1441 };
1442 1442
1443 struct rio_pw { 1443 struct rio_pw {
1444 u32 pwmr; /* Port-Write Mode Register */ 1444 u32 pwmr; /* Port-Write Mode Register */
1445 u32 pwsr; /* Port-Write Status Register */ 1445 u32 pwsr; /* Port-Write Status Register */
1446 u32 epwqbar; /* Extended Port-Write Queue BAR */ 1446 u32 epwqbar; /* Extended Port-Write Queue BAR */
1447 u32 pwqbar; /* Port-Write Queue Base Address Register */ 1447 u32 pwqbar; /* Port-Write Queue Base Address Register */
1448 }; 1448 };
1449 #endif 1449 #endif
1450 1450
1451 #ifdef CONFIG_SYS_FSL_SRIO_LIODN 1451 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
1452 struct rio_liodn { 1452 struct rio_liodn {
1453 u32 plbr; 1453 u32 plbr;
1454 u8 res0[28]; 1454 u8 res0[28];
1455 u32 plaor; 1455 u32 plaor;
1456 u8 res1[12]; 1456 u8 res1[12];
1457 u32 pludr; 1457 u32 pludr;
1458 u32 plldr; 1458 u32 plldr;
1459 u8 res2[456]; 1459 u8 res2[456];
1460 }; 1460 };
1461 #endif 1461 #endif
1462 1462
1463 /* RapidIO Registers */ 1463 /* RapidIO Registers */
1464 struct ccsr_rio { 1464 struct ccsr_rio {
1465 struct rio_arch arch; 1465 struct rio_arch arch;
1466 u8 res0[144]; 1466 u8 res0[144];
1467 struct rio_lp_serial lp_serial; 1467 struct rio_lp_serial lp_serial;
1468 u8 res1[1152]; 1468 u8 res1[1152];
1469 struct rio_logical_err logical_err; 1469 struct rio_logical_err logical_err;
1470 u8 res2[32]; 1470 u8 res2[32];
1471 struct rio_phys_err phys_err; 1471 struct rio_phys_err phys_err;
1472 u8 res3[63808]; 1472 u8 res3[63808];
1473 struct rio_implement impl; 1473 struct rio_implement impl;
1474 u8 res4[2552]; 1474 u8 res4[2552];
1475 struct rio_rev_ctrl rev; 1475 struct rio_rev_ctrl rev;
1476 struct rio_atmu atmu; 1476 struct rio_atmu atmu;
1477 #ifdef CONFIG_SYS_FSL_RMU 1477 #ifdef CONFIG_SYS_FSL_RMU
1478 u8 res5[8192]; 1478 u8 res5[8192];
1479 struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM]; 1479 struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
1480 u8 res6[512]; 1480 u8 res6[512];
1481 struct rio_dbell dbell; 1481 struct rio_dbell dbell;
1482 u8 res7[100]; 1482 u8 res7[100];
1483 struct rio_pw pw; 1483 struct rio_pw pw;
1484 #endif 1484 #endif
1485 #ifdef CONFIG_SYS_FSL_SRIO_LIODN 1485 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
1486 u8 res5[8192]; 1486 u8 res5[8192];
1487 struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; 1487 struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
1488 #endif 1488 #endif
1489 }; 1489 };
1490 #endif 1490 #endif
1491 1491
1492 /* Quick Engine Block Pin Muxing Registers */ 1492 /* Quick Engine Block Pin Muxing Registers */
1493 typedef struct par_io { 1493 typedef struct par_io {
1494 u32 cpodr; 1494 u32 cpodr;
1495 u32 cpdat; 1495 u32 cpdat;
1496 u32 cpdir1; 1496 u32 cpdir1;
1497 u32 cpdir2; 1497 u32 cpdir2;
1498 u32 cppar1; 1498 u32 cppar1;
1499 u32 cppar2; 1499 u32 cppar2;
1500 u8 res[8]; 1500 u8 res[8];
1501 } par_io_t; 1501 } par_io_t;
1502 1502
1503 #ifdef CONFIG_SYS_FSL_CPC 1503 #ifdef CONFIG_SYS_FSL_CPC
1504 /* 1504 /*
1505 * Define a single offset that is the start of all the CPC register 1505 * Define a single offset that is the start of all the CPC register
1506 * blocks - if there is more than one CPC, we expect these to be 1506 * blocks - if there is more than one CPC, we expect these to be
1507 * contiguous 4k regions 1507 * contiguous 4k regions
1508 */ 1508 */
1509 1509
1510 typedef struct cpc_corenet { 1510 typedef struct cpc_corenet {
1511 u32 cpccsr0; /* Config/status reg */ 1511 u32 cpccsr0; /* Config/status reg */
1512 u32 res1; 1512 u32 res1;
1513 u32 cpccfg0; /* Configuration register */ 1513 u32 cpccfg0; /* Configuration register */
1514 u32 res2; 1514 u32 res2;
1515 u32 cpcewcr0; /* External Write reg 0 */ 1515 u32 cpcewcr0; /* External Write reg 0 */
1516 u32 cpcewabr0; /* External write base reg 0 */ 1516 u32 cpcewabr0; /* External write base reg 0 */
1517 u32 res3[2]; 1517 u32 res3[2];
1518 u32 cpcewcr1; /* External Write reg 1 */ 1518 u32 cpcewcr1; /* External Write reg 1 */
1519 u32 cpcewabr1; /* External write base reg 1 */ 1519 u32 cpcewabr1; /* External write base reg 1 */
1520 u32 res4[54]; 1520 u32 res4[54];
1521 u32 cpcsrcr1; /* SRAM control reg 1 */ 1521 u32 cpcsrcr1; /* SRAM control reg 1 */
1522 u32 cpcsrcr0; /* SRAM control reg 0 */ 1522 u32 cpcsrcr0; /* SRAM control reg 0 */
1523 u32 res5[62]; 1523 u32 res5[62];
1524 struct { 1524 struct {
1525 u32 id; /* partition ID */ 1525 u32 id; /* partition ID */
1526 u32 res; 1526 u32 res;
1527 u32 alloc; /* partition allocation */ 1527 u32 alloc; /* partition allocation */
1528 u32 way; /* partition way */ 1528 u32 way; /* partition way */
1529 } partition_regs[16]; 1529 } partition_regs[16];
1530 u32 res6[704]; 1530 u32 res6[704];
1531 u32 cpcerrinjhi; /* Error injection high */ 1531 u32 cpcerrinjhi; /* Error injection high */
1532 u32 cpcerrinjlo; /* Error injection lo */ 1532 u32 cpcerrinjlo; /* Error injection lo */
1533 u32 cpcerrinjctl; /* Error injection control */ 1533 u32 cpcerrinjctl; /* Error injection control */
1534 u32 res7[5]; 1534 u32 res7[5];
1535 u32 cpccaptdatahi; /* capture data high */ 1535 u32 cpccaptdatahi; /* capture data high */
1536 u32 cpccaptdatalo; /* capture data low */ 1536 u32 cpccaptdatalo; /* capture data low */
1537 u32 cpcaptecc; /* capture ECC */ 1537 u32 cpcaptecc; /* capture ECC */
1538 u32 res8[5]; 1538 u32 res8[5];
1539 u32 cpcerrdet; /* error detect */ 1539 u32 cpcerrdet; /* error detect */
1540 u32 cpcerrdis; /* error disable */ 1540 u32 cpcerrdis; /* error disable */
1541 u32 cpcerrinten; /* errir interrupt enable */ 1541 u32 cpcerrinten; /* errir interrupt enable */
1542 u32 cpcerrattr; /* error attribute */ 1542 u32 cpcerrattr; /* error attribute */
1543 u32 cpcerreaddr; /* error extended address */ 1543 u32 cpcerreaddr; /* error extended address */
1544 u32 cpcerraddr; /* error address */ 1544 u32 cpcerraddr; /* error address */
1545 u32 cpcerrctl; /* error control */ 1545 u32 cpcerrctl; /* error control */
1546 u32 res9[41]; /* pad out to 4k */ 1546 u32 res9[41]; /* pad out to 4k */
1547 u32 cpchdbcr0; /* hardware debug control register 0 */ 1547 u32 cpchdbcr0; /* hardware debug control register 0 */
1548 u32 res10[63]; /* pad out to 4k */ 1548 u32 res10[63]; /* pad out to 4k */
1549 } cpc_corenet_t; 1549 } cpc_corenet_t;
1550 1550
1551 #define CPC_CSR0_CE 0x80000000 /* Cache Enable */ 1551 #define CPC_CSR0_CE 0x80000000 /* Cache Enable */
1552 #define CPC_CSR0_PE 0x40000000 /* Enable ECC */ 1552 #define CPC_CSR0_PE 0x40000000 /* Enable ECC */
1553 #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */ 1553 #define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */
1554 #define CPC_CSR0_WT 0x00080000 /* Write-through mode */ 1554 #define CPC_CSR0_WT 0x00080000 /* Write-through mode */
1555 #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */ 1555 #define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */
1556 #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */ 1556 #define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */
1557 #define CPC_CFG0_SZ_MASK 0x00003fff 1557 #define CPC_CFG0_SZ_MASK 0x00003fff
1558 #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6) 1558 #define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6)
1559 #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1) 1559 #define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1)
1560 #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32) 1560 #define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32)
1561 #define CPC_SRCR1_SRBARU_MASK 0x0000ffff 1561 #define CPC_SRCR1_SRBARU_MASK 0x0000ffff
1562 #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \ 1562 #define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \
1563 & CPC_SRCR1_SRBARU_MASK) 1563 & CPC_SRCR1_SRBARU_MASK)
1564 #define CPC_SRCR0_SRBARL_MASK 0xffff8000 1564 #define CPC_SRCR0_SRBARL_MASK 0xffff8000
1565 #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK) 1565 #define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK)
1566 #define CPC_SRCR0_INTLVEN 0x00000100 1566 #define CPC_SRCR0_INTLVEN 0x00000100
1567 #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000 1567 #define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000
1568 #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002 1568 #define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002
1569 #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004 1569 #define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004
1570 #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006 1570 #define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006
1571 #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008 1571 #define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008
1572 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a 1572 #define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
1573 #define CPC_SRCR0_SRAMEN 0x00000001 1573 #define CPC_SRCR0_SRAMEN 0x00000001
1574 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ 1574 #define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
1575 #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 1575 #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
1576 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 1576 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
1577 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 1577 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
1578 #define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000 1578 #define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000
1579 #endif /* CONFIG_SYS_FSL_CPC */ 1579 #endif /* CONFIG_SYS_FSL_CPC */
1580 1580
1581 /* Global Utilities Block */ 1581 /* Global Utilities Block */
1582 #ifdef CONFIG_FSL_CORENET 1582 #ifdef CONFIG_FSL_CORENET
1583 typedef struct ccsr_gur { 1583 typedef struct ccsr_gur {
1584 u32 porsr1; /* POR status 1 */ 1584 u32 porsr1; /* POR status 1 */
1585 u32 porsr2; /* POR status 2 */ 1585 u32 porsr2; /* POR status 2 */
1586 u8 res_008[0x20-0x8]; 1586 u8 res_008[0x20-0x8];
1587 u32 gpporcr1; /* General-purpose POR configuration */ 1587 u32 gpporcr1; /* General-purpose POR configuration */
1588 u32 gpporcr2; /* General-purpose POR configuration 2 */ 1588 u32 gpporcr2; /* General-purpose POR configuration 2 */
1589 u32 dcfg_fusesr; /* Fuse status register */ 1589 u32 dcfg_fusesr; /* Fuse status register */
1590 #define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25 1590 #define FSL_CORENET_DCFG_FUSESR_VID_SHIFT 25
1591 #define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F 1591 #define FSL_CORENET_DCFG_FUSESR_VID_MASK 0x1F
1592 #define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20 1592 #define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT 20
1593 #define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F 1593 #define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK 0x1F
1594 u8 res_02c[0x70-0x2c]; 1594 u8 res_02c[0x70-0x2c];
1595 u32 devdisr; /* Device disable control */ 1595 u32 devdisr; /* Device disable control */
1596 u32 devdisr2; /* Device disable control 2 */ 1596 u32 devdisr2; /* Device disable control 2 */
1597 u32 devdisr3; /* Device disable control 3 */ 1597 u32 devdisr3; /* Device disable control 3 */
1598 u32 devdisr4; /* Device disable control 4 */ 1598 u32 devdisr4; /* Device disable control 4 */
1599 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 1599 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1600 u32 devdisr5; /* Device disable control 5 */ 1600 u32 devdisr5; /* Device disable control 5 */
1601 #define FSL_CORENET_DEVDISR_PBL 0x80000000 1601 #define FSL_CORENET_DEVDISR_PBL 0x80000000
1602 #define FSL_CORENET_DEVDISR_PMAN 0x40000000 1602 #define FSL_CORENET_DEVDISR_PMAN 0x40000000
1603 #define FSL_CORENET_DEVDISR_ESDHC 0x20000000 1603 #define FSL_CORENET_DEVDISR_ESDHC 0x20000000
1604 #define FSL_CORENET_DEVDISR_DMA1 0x00800000 1604 #define FSL_CORENET_DEVDISR_DMA1 0x00800000
1605 #define FSL_CORENET_DEVDISR_DMA2 0x00400000 1605 #define FSL_CORENET_DEVDISR_DMA2 0x00400000
1606 #define FSL_CORENET_DEVDISR_USB1 0x00080000 1606 #define FSL_CORENET_DEVDISR_USB1 0x00080000
1607 #define FSL_CORENET_DEVDISR_USB2 0x00040000 1607 #define FSL_CORENET_DEVDISR_USB2 0x00040000
1608 #define FSL_CORENET_DEVDISR_SATA1 0x00008000 1608 #define FSL_CORENET_DEVDISR_SATA1 0x00008000
1609 #define FSL_CORENET_DEVDISR_SATA2 0x00004000 1609 #define FSL_CORENET_DEVDISR_SATA2 0x00004000
1610 #define FSL_CORENET_DEVDISR_PME 0x00000800 1610 #define FSL_CORENET_DEVDISR_PME 0x00000800
1611 #define FSL_CORENET_DEVDISR_SEC 0x00000200 1611 #define FSL_CORENET_DEVDISR_SEC 0x00000200
1612 #define FSL_CORENET_DEVDISR_RMU 0x00000080 1612 #define FSL_CORENET_DEVDISR_RMU 0x00000080
1613 #define FSL_CORENET_DEVDISR_DCE 0x00000040 1613 #define FSL_CORENET_DEVDISR_DCE 0x00000040
1614 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000 1614 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x80000000
1615 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000 1615 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x40000000
1616 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000 1616 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x20000000
1617 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000 1617 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x10000000
1618 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000 1618 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x08000000
1619 #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000 1619 #define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
1620 #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000 1620 #define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
1621 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000 1621 #define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
1622 #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000 1622 #define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
1623 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000 1623 #define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
1624 #define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000 1624 #define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
1625 #define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000 1625 #define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
1626 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000 1626 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
1627 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000 1627 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
1628 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000 1628 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
1629 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000 1629 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00010000
1630 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000 1630 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00008000
1631 #define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000 1631 #define FSL_CORENET_DEVDISR2_DTSEC2_6 0x00004000
1632 #define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800 1632 #define FSL_CORENET_DEVDISR2_DTSEC2_9 0x00000800
1633 #define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400 1633 #define FSL_CORENET_DEVDISR2_DTSEC2_10 0x00000400
1634 #define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800 1634 #define FSL_CORENET_DEVDISR2_10GEC2_1 0x00000800
1635 #define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400 1635 #define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400
1636 #define FSL_CORENET_DEVDISR2_FM1 0x00000080 1636 #define FSL_CORENET_DEVDISR2_FM1 0x00000080
1637 #define FSL_CORENET_DEVDISR2_FM2 0x00000040 1637 #define FSL_CORENET_DEVDISR2_FM2 0x00000040
1638 #define FSL_CORENET_DEVDISR2_CPRI 0x00000008 1638 #define FSL_CORENET_DEVDISR2_CPRI 0x00000008
1639 #define FSL_CORENET_DEVDISR3_PCIE1 0x80000000 1639 #define FSL_CORENET_DEVDISR3_PCIE1 0x80000000
1640 #define FSL_CORENET_DEVDISR3_PCIE2 0x40000000 1640 #define FSL_CORENET_DEVDISR3_PCIE2 0x40000000
1641 #define FSL_CORENET_DEVDISR3_PCIE3 0x20000000 1641 #define FSL_CORENET_DEVDISR3_PCIE3 0x20000000
1642 #define FSL_CORENET_DEVDISR3_PCIE4 0x10000000 1642 #define FSL_CORENET_DEVDISR3_PCIE4 0x10000000
1643 #define FSL_CORENET_DEVDISR3_SRIO1 0x08000000 1643 #define FSL_CORENET_DEVDISR3_SRIO1 0x08000000
1644 #define FSL_CORENET_DEVDISR3_SRIO2 0x04000000 1644 #define FSL_CORENET_DEVDISR3_SRIO2 0x04000000
1645 #define FSL_CORENET_DEVDISR3_QMAN 0x00080000 1645 #define FSL_CORENET_DEVDISR3_QMAN 0x00080000
1646 #define FSL_CORENET_DEVDISR3_BMAN 0x00040000 1646 #define FSL_CORENET_DEVDISR3_BMAN 0x00040000
1647 #define FSL_CORENET_DEVDISR3_LA1 0x00008000 1647 #define FSL_CORENET_DEVDISR3_LA1 0x00008000
1648 #define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800 1648 #define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800
1649 #define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400 1649 #define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400
1650 #define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200 1650 #define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200
1651 #define FSL_CORENET_DEVDISR4_I2C1 0x80000000 1651 #define FSL_CORENET_DEVDISR4_I2C1 0x80000000
1652 #define FSL_CORENET_DEVDISR4_I2C2 0x40000000 1652 #define FSL_CORENET_DEVDISR4_I2C2 0x40000000
1653 #define FSL_CORENET_DEVDISR4_DUART1 0x20000000 1653 #define FSL_CORENET_DEVDISR4_DUART1 0x20000000
1654 #define FSL_CORENET_DEVDISR4_DUART2 0x10000000 1654 #define FSL_CORENET_DEVDISR4_DUART2 0x10000000
1655 #define FSL_CORENET_DEVDISR4_ESPI 0x08000000 1655 #define FSL_CORENET_DEVDISR4_ESPI 0x08000000
1656 #define FSL_CORENET_DEVDISR5_DDR1 0x80000000 1656 #define FSL_CORENET_DEVDISR5_DDR1 0x80000000
1657 #define FSL_CORENET_DEVDISR5_DDR2 0x40000000 1657 #define FSL_CORENET_DEVDISR5_DDR2 0x40000000
1658 #define FSL_CORENET_DEVDISR5_DDR3 0x20000000 1658 #define FSL_CORENET_DEVDISR5_DDR3 0x20000000
1659 #define FSL_CORENET_DEVDISR5_CPC1 0x08000000 1659 #define FSL_CORENET_DEVDISR5_CPC1 0x08000000
1660 #define FSL_CORENET_DEVDISR5_CPC2 0x04000000 1660 #define FSL_CORENET_DEVDISR5_CPC2 0x04000000
1661 #define FSL_CORENET_DEVDISR5_CPC3 0x02000000 1661 #define FSL_CORENET_DEVDISR5_CPC3 0x02000000
1662 #define FSL_CORENET_DEVDISR5_IFC 0x00800000 1662 #define FSL_CORENET_DEVDISR5_IFC 0x00800000
1663 #define FSL_CORENET_DEVDISR5_GPIO 0x00400000 1663 #define FSL_CORENET_DEVDISR5_GPIO 0x00400000
1664 #define FSL_CORENET_DEVDISR5_DBG 0x00200000 1664 #define FSL_CORENET_DEVDISR5_DBG 0x00200000
1665 #define FSL_CORENET_DEVDISR5_NAL 0x00100000 1665 #define FSL_CORENET_DEVDISR5_NAL 0x00100000
1666 #define FSL_CORENET_DEVDISR5_TIMERS 0x00020000 1666 #define FSL_CORENET_DEVDISR5_TIMERS 0x00020000
1667 #define FSL_CORENET_NUM_DEVDISR 5 1667 #define FSL_CORENET_NUM_DEVDISR 5
1668 #else 1668 #else
1669 #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 1669 #define FSL_CORENET_DEVDISR_PCIE1 0x80000000
1670 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000 1670 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000
1671 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000 1671 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000
1672 #define FSL_CORENET_DEVDISR_PCIE4 0x10000000 1672 #define FSL_CORENET_DEVDISR_PCIE4 0x10000000
1673 #define FSL_CORENET_DEVDISR_RMU 0x08000000 1673 #define FSL_CORENET_DEVDISR_RMU 0x08000000
1674 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000 1674 #define FSL_CORENET_DEVDISR_SRIO1 0x04000000
1675 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000 1675 #define FSL_CORENET_DEVDISR_SRIO2 0x02000000
1676 #define FSL_CORENET_DEVDISR_DMA1 0x00400000 1676 #define FSL_CORENET_DEVDISR_DMA1 0x00400000
1677 #define FSL_CORENET_DEVDISR_DMA2 0x00200000 1677 #define FSL_CORENET_DEVDISR_DMA2 0x00200000
1678 #define FSL_CORENET_DEVDISR_DDR1 0x00100000 1678 #define FSL_CORENET_DEVDISR_DDR1 0x00100000
1679 #define FSL_CORENET_DEVDISR_DDR2 0x00080000 1679 #define FSL_CORENET_DEVDISR_DDR2 0x00080000
1680 #define FSL_CORENET_DEVDISR_DBG 0x00010000 1680 #define FSL_CORENET_DEVDISR_DBG 0x00010000
1681 #define FSL_CORENET_DEVDISR_NAL 0x00008000 1681 #define FSL_CORENET_DEVDISR_NAL 0x00008000
1682 #define FSL_CORENET_DEVDISR_SATA1 0x00004000 1682 #define FSL_CORENET_DEVDISR_SATA1 0x00004000
1683 #define FSL_CORENET_DEVDISR_SATA2 0x00002000 1683 #define FSL_CORENET_DEVDISR_SATA2 0x00002000
1684 #define FSL_CORENET_DEVDISR_ELBC 0x00001000 1684 #define FSL_CORENET_DEVDISR_ELBC 0x00001000
1685 #define FSL_CORENET_DEVDISR_USB1 0x00000800 1685 #define FSL_CORENET_DEVDISR_USB1 0x00000800
1686 #define FSL_CORENET_DEVDISR_USB2 0x00000400 1686 #define FSL_CORENET_DEVDISR_USB2 0x00000400
1687 #define FSL_CORENET_DEVDISR_ESDHC 0x00000100 1687 #define FSL_CORENET_DEVDISR_ESDHC 0x00000100
1688 #define FSL_CORENET_DEVDISR_GPIO 0x00000080 1688 #define FSL_CORENET_DEVDISR_GPIO 0x00000080
1689 #define FSL_CORENET_DEVDISR_ESPI 0x00000040 1689 #define FSL_CORENET_DEVDISR_ESPI 0x00000040
1690 #define FSL_CORENET_DEVDISR_I2C1 0x00000020 1690 #define FSL_CORENET_DEVDISR_I2C1 0x00000020
1691 #define FSL_CORENET_DEVDISR_I2C2 0x00000010 1691 #define FSL_CORENET_DEVDISR_I2C2 0x00000010
1692 #define FSL_CORENET_DEVDISR_DUART1 0x00000002 1692 #define FSL_CORENET_DEVDISR_DUART1 0x00000002
1693 #define FSL_CORENET_DEVDISR_DUART2 0x00000001 1693 #define FSL_CORENET_DEVDISR_DUART2 0x00000001
1694 #define FSL_CORENET_DEVDISR2_PME 0x80000000 1694 #define FSL_CORENET_DEVDISR2_PME 0x80000000
1695 #define FSL_CORENET_DEVDISR2_SEC 0x40000000 1695 #define FSL_CORENET_DEVDISR2_SEC 0x40000000
1696 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000 1696 #define FSL_CORENET_DEVDISR2_QMBM 0x08000000
1697 #define FSL_CORENET_DEVDISR2_FM1 0x02000000 1697 #define FSL_CORENET_DEVDISR2_FM1 0x02000000
1698 #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000 1698 #define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
1699 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000 1699 #define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
1700 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000 1700 #define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
1701 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000 1701 #define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
1702 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000 1702 #define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
1703 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000 1703 #define FSL_CORENET_DEVDISR2_DTSEC1_5 0x00080000
1704 #define FSL_CORENET_DEVDISR2_FM2 0x00020000 1704 #define FSL_CORENET_DEVDISR2_FM2 0x00020000
1705 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000 1705 #define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
1706 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000 1706 #define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
1707 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000 1707 #define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
1708 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000 1708 #define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
1709 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000 1709 #define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
1710 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800 1710 #define FSL_CORENET_DEVDISR2_DTSEC2_5 0x00000800
1711 #define FSL_CORENET_NUM_DEVDISR 2 1711 #define FSL_CORENET_NUM_DEVDISR 2
1712 u32 powmgtcsr; /* Power management status & control */ 1712 u32 powmgtcsr; /* Power management status & control */
1713 #endif 1713 #endif
1714 u8 res8[12]; 1714 u8 res8[12];
1715 u32 coredisru; /* uppper portion for support of 64 cores */ 1715 u32 coredisru; /* uppper portion for support of 64 cores */
1716 u32 coredisrl; /* lower portion for support of 64 cores */ 1716 u32 coredisrl; /* lower portion for support of 64 cores */
1717 u8 res9[8]; 1717 u8 res9[8];
1718 u32 pvr; /* Processor version */ 1718 u32 pvr; /* Processor version */
1719 u32 svr; /* System version */ 1719 u32 svr; /* System version */
1720 u8 res10[8]; 1720 u8 res10[8];
1721 u32 rstcr; /* Reset control */ 1721 u32 rstcr; /* Reset control */
1722 u32 rstrqpblsr; /* Reset request preboot loader status */ 1722 u32 rstrqpblsr; /* Reset request preboot loader status */
1723 u8 res11[8]; 1723 u8 res11[8];
1724 u32 rstrqmr1; /* Reset request mask */ 1724 u32 rstrqmr1; /* Reset request mask */
1725 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1726 #define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800
1727 #endif
1725 u8 res12[4]; 1728 u8 res12[4];
1726 u32 rstrqsr1; /* Reset request status */ 1729 u32 rstrqsr1; /* Reset request status */
1727 u8 res13[4]; 1730 u8 res13[4];
1728 u8 res14[4]; 1731 u8 res14[4];
1729 u32 rstrqwdtmrl; /* Reset request WDT mask */ 1732 u32 rstrqwdtmrl; /* Reset request WDT mask */
1730 u8 res15[4]; 1733 u8 res15[4];
1731 u32 rstrqwdtsrl; /* Reset request WDT status */ 1734 u32 rstrqwdtsrl; /* Reset request WDT status */
1732 u8 res16[4]; 1735 u8 res16[4];
1733 u32 brrl; /* Boot release */ 1736 u32 brrl; /* Boot release */
1734 u8 res17[24]; 1737 u8 res17[24];
1735 u32 rcwsr[16]; /* Reset control word status */ 1738 u32 rcwsr[16]; /* Reset control word status */
1736 1739
1737 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 1740 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1738 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16 1741 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
1739 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f 1742 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
1740 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 1743 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
1741 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000 1744 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
1742 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26 1745 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
1743 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 1746 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1744 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 1747 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1745 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800 1748 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL 0x0000f800
1746 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11 1749 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11
1747 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 1750 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8
1748 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 1751 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3
1749 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1752 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1750 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420) 1753 #elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
1751 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000 1754 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000
1752 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 1755 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25
1753 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 1756 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1754 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 1757 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1755 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1758 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1756 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\ 1759 #elif defined(CONFIG_PPC_T1040) || defined(CONFIG_PPC_T1042) ||\
1757 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) 1760 defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
1758 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 1761 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1759 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 1762 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1760 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000 1763 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00fe0000
1761 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17 1764 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 17
1762 #define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */ 1765 #define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
1763 #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000 1766 #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII 0x00000000
1764 #define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000 1767 #define FSL_CORENET_RCWSR13_EC1_FM1_GPIO 0x10000000
1765 #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000 1768 #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
1766 #define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */ 1769 #define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */
1767 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 1770 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1768 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 1771 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1769 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000 1772 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000
1770 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080 1773 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
1771 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000 1774 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
1772 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000 1775 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000
1776 #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
1777 #define PXCKEN_MASK 0x80000000
1778 #define PXCK_MASK 0x00FF0000
1779 #define PXCK_BITS_START 16
1773 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 1780 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
1774 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000 1781 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1775 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24 1782 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
1776 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 1783 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000
1777 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 1784 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16
1778 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1785 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1779 #endif 1786 #endif
1780 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000 1787 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000
1781 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000 1788 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000
1782 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000 1789 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1 0x00200000
1783 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000 1790 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2 0x00100000
1784 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000 1791 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1 0x00080000
1785 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000 1792 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
1786 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000 1793 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
1787 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000 1794 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
1788 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4 1795 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
1789 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011 1796 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011
1790 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1 1797 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1
1791 1798
1792 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 1799 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1793 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 1800 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17
1794 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f 1801 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x1f
1795 #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 1802 #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
1796 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080 1803 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
1797 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7 1804 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
1798 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000 1805 #define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
1799 #define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000 1806 #define FSL_CORENET_RCWSR5_SRDS2_EN 0x00001000
1800 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000 1807 #define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
1801 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */ 1808 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2 0x3c000000 /* bits 162..165 */
1802 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */ 1809 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3 0x003c0000 /* bits 170..173 */
1803 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 1810 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
1804 1811
1805 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 1812 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
1806 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 1813 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
1807 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 1814 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
1808 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */ 1815 #define FSL_CORENET_RCWSR11_EC1 0x00c00000 /* bits 360..361 */
1809 #ifdef CONFIG_PPC_P4080 1816 #ifdef CONFIG_PPC_P4080
1810 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000 1817 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1 0x00000000
1811 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000 1818 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1 0x00800000
1812 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */ 1819 #define FSL_CORENET_RCWSR11_EC2 0x001c0000 /* bits 363..365 */
1813 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000 1820 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1 0x00000000
1814 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000 1821 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2 0x00080000
1815 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000 1822 #define FSL_CORENET_RCWSR11_EC2_USB2 0x00100000
1816 #endif 1823 #endif
1817 #if defined(CONFIG_PPC_P2041) \ 1824 #if defined(CONFIG_PPC_P2041) \
1818 || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020) 1825 || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
1819 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000 1826 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII 0x00000000
1820 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000 1827 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII 0x00800000
1821 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000 1828 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE 0x00c00000
1822 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */ 1829 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1823 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000 1830 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII 0x00000000
1824 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000 1831 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII 0x00100000
1825 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000 1832 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE 0x00180000
1826 #endif 1833 #endif
1827 #if defined(CONFIG_PPC_P5040) 1834 #if defined(CONFIG_PPC_P5040)
1828 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000 1835 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII 0x00000000
1829 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000 1836 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII 0x00800000
1830 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000 1837 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE 0x00c00000
1831 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */ 1838 #define FSL_CORENET_RCWSR11_EC2 0x00180000 /* bits 363..364 */
1832 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000 1839 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII 0x00000000
1833 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000 1840 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
1834 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000 1841 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
1835 #endif 1842 #endif
1836 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) 1843 #if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
1837 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ 1844 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1838 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 1845 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
1839 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 1846 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000
1840 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ 1847 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1841 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 1848 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
1842 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000 1849 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII 0x08000000
1843 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 1850 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
1844 #endif 1851 #endif
1845 #if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081) 1852 #if defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
1846 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ 1853 #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
1847 #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 1854 #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII 0x00000000
1848 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000 1855 #define FSL_CORENET_RCWSR13_EC1_GPIO 0x40000000
1849 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ 1856 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */
1850 #define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000 1857 #define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII 0x00000000
1851 #define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000 1858 #define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII 0x08000000
1852 #define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000 1859 #define FSL_CORENET_RCWSR13_EC2_GPIO 0x10000000
1853 #endif 1860 #endif
1854 u8 res18[192]; 1861 u8 res18[192];
1855 u32 scratchrw[4]; /* Scratch Read/Write */ 1862 u32 scratchrw[4]; /* Scratch Read/Write */
1856 u8 res19[240]; 1863 u8 res19[240];
1857 u32 scratchw1r[4]; /* Scratch Read (Write once) */ 1864 u32 scratchw1r[4]; /* Scratch Read (Write once) */
1858 u8 res20[240]; 1865 u8 res20[240];
1859 u32 scrtsr[8]; /* Core reset status */ 1866 u32 scrtsr[8]; /* Core reset status */
1860 u8 res21[224]; 1867 u8 res21[224];
1861 u32 pex1liodnr; /* PCI Express 1 LIODN */ 1868 u32 pex1liodnr; /* PCI Express 1 LIODN */
1862 u32 pex2liodnr; /* PCI Express 2 LIODN */ 1869 u32 pex2liodnr; /* PCI Express 2 LIODN */
1863 u32 pex3liodnr; /* PCI Express 3 LIODN */ 1870 u32 pex3liodnr; /* PCI Express 3 LIODN */
1864 u32 pex4liodnr; /* PCI Express 4 LIODN */ 1871 u32 pex4liodnr; /* PCI Express 4 LIODN */
1865 u32 rio1liodnr; /* RIO 1 LIODN */ 1872 u32 rio1liodnr; /* RIO 1 LIODN */
1866 u32 rio2liodnr; /* RIO 2 LIODN */ 1873 u32 rio2liodnr; /* RIO 2 LIODN */
1867 u32 rio3liodnr; /* RIO 3 LIODN */ 1874 u32 rio3liodnr; /* RIO 3 LIODN */
1868 u32 rio4liodnr; /* RIO 4 LIODN */ 1875 u32 rio4liodnr; /* RIO 4 LIODN */
1869 u32 usb1liodnr; /* USB 1 LIODN */ 1876 u32 usb1liodnr; /* USB 1 LIODN */
1870 u32 usb2liodnr; /* USB 2 LIODN */ 1877 u32 usb2liodnr; /* USB 2 LIODN */
1871 u32 usb3liodnr; /* USB 3 LIODN */ 1878 u32 usb3liodnr; /* USB 3 LIODN */
1872 u32 usb4liodnr; /* USB 4 LIODN */ 1879 u32 usb4liodnr; /* USB 4 LIODN */
1873 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */ 1880 u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */
1874 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */ 1881 u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */
1875 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */ 1882 u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */
1876 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */ 1883 u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */
1877 u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */ 1884 u32 rio1maintliodnr;/* RIO 1 Maintenance LIODN */
1878 u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */ 1885 u32 rio2maintliodnr;/* RIO 2 Maintenance LIODN */
1879 u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */ 1886 u32 rio3maintliodnr;/* RIO 3 Maintenance LIODN */
1880 u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */ 1887 u32 rio4maintliodnr;/* RIO 4 Maintenance LIODN */
1881 u32 sata1liodnr; /* SATA 1 LIODN */ 1888 u32 sata1liodnr; /* SATA 1 LIODN */
1882 u32 sata2liodnr; /* SATA 2 LIODN */ 1889 u32 sata2liodnr; /* SATA 2 LIODN */
1883 u32 sata3liodnr; /* SATA 3 LIODN */ 1890 u32 sata3liodnr; /* SATA 3 LIODN */
1884 u32 sata4liodnr; /* SATA 4 LIODN */ 1891 u32 sata4liodnr; /* SATA 4 LIODN */
1885 u8 res22[32]; 1892 u8 res22[32];
1886 u32 dma1liodnr; /* DMA 1 LIODN */ 1893 u32 dma1liodnr; /* DMA 1 LIODN */
1887 u32 dma2liodnr; /* DMA 2 LIODN */ 1894 u32 dma2liodnr; /* DMA 2 LIODN */
1888 u32 dma3liodnr; /* DMA 3 LIODN */ 1895 u32 dma3liodnr; /* DMA 3 LIODN */
1889 u32 dma4liodnr; /* DMA 4 LIODN */ 1896 u32 dma4liodnr; /* DMA 4 LIODN */
1890 u8 res23[48]; 1897 u8 res23[48];
1891 u8 res24[64]; 1898 u8 res24[64];
1892 u32 pblsr; /* Preboot loader status */ 1899 u32 pblsr; /* Preboot loader status */
1893 u32 pamubypenr; /* PAMU bypass enable */ 1900 u32 pamubypenr; /* PAMU bypass enable */
1894 u32 dmacr1; /* DMA control */ 1901 u32 dmacr1; /* DMA control */
1895 u8 res25[4]; 1902 u8 res25[4];
1896 u32 gensr1; /* General status */ 1903 u32 gensr1; /* General status */
1897 u8 res26[12]; 1904 u8 res26[12];
1898 u32 gencr1; /* General control */ 1905 u32 gencr1; /* General control */
1899 u8 res27[12]; 1906 u8 res27[12];
1900 u8 res28[4]; 1907 u8 res28[4];
1901 u32 cgensrl; /* Core general status */ 1908 u32 cgensrl; /* Core general status */
1902 u8 res29[8]; 1909 u8 res29[8];
1903 u8 res30[4]; 1910 u8 res30[4];
1904 u32 cgencrl; /* Core general control */ 1911 u32 cgencrl; /* Core general control */
1905 u8 res31[184]; 1912 u8 res31[184];
1906 u32 sriopstecr; /* SRIO prescaler timer enable control */ 1913 u32 sriopstecr; /* SRIO prescaler timer enable control */
1907 u32 dcsrcr; /* DCSR Control register */ 1914 u32 dcsrcr; /* DCSR Control register */
1908 u8 res31a[56]; 1915 u8 res31a[56];
1909 u32 tp_ityp[64]; /* Topology Initiator Type Register */ 1916 u32 tp_ityp[64]; /* Topology Initiator Type Register */
1910 struct { 1917 struct {
1911 u32 upper; 1918 u32 upper;
1912 u32 lower; 1919 u32 lower;
1913 } tp_cluster[16]; /* Core Cluster n Topology Register */ 1920 } tp_cluster[16]; /* Core Cluster n Topology Register */
1914 u8 res32[1344]; 1921 u8 res32[1344];
1915 u32 pmuxcr; /* Pin multiplexing control */ 1922 u32 pmuxcr; /* Pin multiplexing control */
1916 u8 res33[60]; 1923 u8 res33[60];
1917 u32 iovselsr; /* I/O voltage selection status */ 1924 u32 iovselsr; /* I/O voltage selection status */
1918 u8 res34[28]; 1925 u8 res34[28];
1919 u32 ddrclkdr; /* DDR clock disable */ 1926 u32 ddrclkdr; /* DDR clock disable */
1920 u8 res35; 1927 u8 res35;
1921 u32 elbcclkdr; /* eLBC clock disable */ 1928 u32 elbcclkdr; /* eLBC clock disable */
1922 u8 res36[20]; 1929 u8 res36[20];
1923 u32 sdhcpcr; /* eSDHC polarity configuration */ 1930 u32 sdhcpcr; /* eSDHC polarity configuration */
1924 u8 res37[380]; 1931 u8 res37[380];
1925 } ccsr_gur_t; 1932 } ccsr_gur_t;
1926 1933
1927 #define TP_ITYP_AV 0x00000001 /* Initiator available */ 1934 #define TP_ITYP_AV 0x00000001 /* Initiator available */
1928 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */ 1935 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
1929 #define TP_ITYP_TYPE_OTHER 0x0 1936 #define TP_ITYP_TYPE_OTHER 0x0
1930 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */ 1937 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
1931 #define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */ 1938 #define TP_ITYP_TYPE_SC 0x2 /* StarCore DSP */
1932 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */ 1939 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
1933 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */ 1940 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
1934 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */ 1941 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
1935 1942
1936 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ 1943 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
1937 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ 1944 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
1938 #define TP_INIT_PER_CLUSTER 4 1945 #define TP_INIT_PER_CLUSTER 4
1939 1946
1940 #define FSL_CORENET_DCSR_SZ_MASK 0x00000003 1947 #define FSL_CORENET_DCSR_SZ_MASK 0x00000003
1941 #define FSL_CORENET_DCSR_SZ_4M 0x0 1948 #define FSL_CORENET_DCSR_SZ_4M 0x0
1942 #define FSL_CORENET_DCSR_SZ_1G 0x3 1949 #define FSL_CORENET_DCSR_SZ_1G 0x3
1943 1950
1944 /* 1951 /*
1945 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance 1952 * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
1946 * everything after has RMan thus msg unit LIODN is used for maintenance 1953 * everything after has RMan thus msg unit LIODN is used for maintenance
1947 */ 1954 */
1948 #define rmuliodnr rio1maintliodnr 1955 #define rmuliodnr rio1maintliodnr
1949 1956
1950 typedef struct ccsr_clk { 1957 typedef struct ccsr_clk {
1951 struct { 1958 struct {
1952 u32 clkcncsr; /* core cluster n clock control status */ 1959 u32 clkcncsr; /* core cluster n clock control status */
1953 u8 res_004[0x0c]; 1960 u8 res_004[0x0c];
1954 u32 clkcgnhwacsr;/* clock generator n hardware accelerator */ 1961 u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
1955 u8 res_014[0x0c]; 1962 u8 res_014[0x0c];
1956 } clkcsr[12]; 1963 } clkcsr[12];
1957 u8 res_100[0x680]; /* 0x100 */ 1964 u8 res_100[0x680]; /* 0x100 */
1958 struct { 1965 struct {
1959 u32 pllcngsr; 1966 u32 pllcngsr;
1960 u8 res10[0x1c]; 1967 u8 res10[0x1c];
1961 } pllcgsr[12]; 1968 } pllcgsr[12];
1962 u8 res21[0x280]; 1969 u8 res21[0x280];
1963 u32 pllpgsr; /* 0xc00 Platform PLL General Status */ 1970 u32 pllpgsr; /* 0xc00 Platform PLL General Status */
1964 u8 res16[0x1c]; 1971 u8 res16[0x1c];
1965 u32 plldgsr; /* 0xc20 DDR PLL General Status */ 1972 u32 plldgsr; /* 0xc20 DDR PLL General Status */
1966 u8 res17[0x3dc]; 1973 u8 res17[0x3dc];
1967 } ccsr_clk_t; 1974 } ccsr_clk_t;
1968 1975
1969 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 1976 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
1970 typedef struct ccsr_rcpm { 1977 typedef struct ccsr_rcpm {
1971 u8 res_00[12]; 1978 u8 res_00[12];
1972 u32 tph10sr0; /* Thread PH10 Status Register */ 1979 u32 tph10sr0; /* Thread PH10 Status Register */
1973 u8 res_10[12]; 1980 u8 res_10[12];
1974 u32 tph10setr0; /* Thread PH10 Set Control Register */ 1981 u32 tph10setr0; /* Thread PH10 Set Control Register */
1975 u8 res_20[12]; 1982 u8 res_20[12];
1976 u32 tph10clrr0; /* Thread PH10 Clear Control Register */ 1983 u32 tph10clrr0; /* Thread PH10 Clear Control Register */
1977 u8 res_30[12]; 1984 u8 res_30[12];
1978 u32 tph10psr0; /* Thread PH10 Previous Status Register */ 1985 u32 tph10psr0; /* Thread PH10 Previous Status Register */
1979 u8 res_40[12]; 1986 u8 res_40[12];
1980 u32 twaitsr0; /* Thread Wait Status Register */ 1987 u32 twaitsr0; /* Thread Wait Status Register */
1981 u8 res_50[96]; 1988 u8 res_50[96];
1982 u32 pcph15sr; /* Physical Core PH15 Status Register */ 1989 u32 pcph15sr; /* Physical Core PH15 Status Register */
1983 u32 pcph15setr; /* Physical Core PH15 Set Control Register */ 1990 u32 pcph15setr; /* Physical Core PH15 Set Control Register */
1984 u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */ 1991 u32 pcph15clrr; /* Physical Core PH15 Clear Control Register */
1985 u32 pcph15psr; /* Physical Core PH15 Prev Status Register */ 1992 u32 pcph15psr; /* Physical Core PH15 Prev Status Register */
1986 u8 res_c0[16]; 1993 u8 res_c0[16];
1987 u32 pcph20sr; /* Physical Core PH20 Status Register */ 1994 u32 pcph20sr; /* Physical Core PH20 Status Register */
1988 u32 pcph20setr; /* Physical Core PH20 Set Control Register */ 1995 u32 pcph20setr; /* Physical Core PH20 Set Control Register */
1989 u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */ 1996 u32 pcph20clrr; /* Physical Core PH20 Clear Control Register */
1990 u32 pcph20psr; /* Physical Core PH20 Prev Status Register */ 1997 u32 pcph20psr; /* Physical Core PH20 Prev Status Register */
1991 u32 pcpw20sr; /* Physical Core PW20 Status Register */ 1998 u32 pcpw20sr; /* Physical Core PW20 Status Register */
1992 u8 res_e0[12]; 1999 u8 res_e0[12];
1993 u32 pcph30sr; /* Physical Core PH30 Status Register */ 2000 u32 pcph30sr; /* Physical Core PH30 Status Register */
1994 u32 pcph30setr; /* Physical Core PH30 Set Control Register */ 2001 u32 pcph30setr; /* Physical Core PH30 Set Control Register */
1995 u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */ 2002 u32 pcph30clrr; /* Physical Core PH30 Clear Control Register */
1996 u32 pcph30psr; /* Physical Core PH30 Prev Status Register */ 2003 u32 pcph30psr; /* Physical Core PH30 Prev Status Register */
1997 u8 res_100[32]; 2004 u8 res_100[32];
1998 u32 ippwrgatecr; /* IP Power Gating Control Register */ 2005 u32 ippwrgatecr; /* IP Power Gating Control Register */
1999 u8 res_124[12]; 2006 u8 res_124[12];
2000 u32 powmgtcsr; /* Power Management Control & Status Reg */ 2007 u32 powmgtcsr; /* Power Management Control & Status Reg */
2001 u8 res_134[12]; 2008 u8 res_134[12];
2002 u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */ 2009 u32 ippdexpcr[4]; /* IP Powerdown Exception Control Reg */
2003 u8 res_150[12]; 2010 u8 res_150[12];
2004 u32 tpmimr0; /* Thread PM Interrupt Mask Reg */ 2011 u32 tpmimr0; /* Thread PM Interrupt Mask Reg */
2005 u8 res_160[12]; 2012 u8 res_160[12];
2006 u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */ 2013 u32 tpmcimr0; /* Thread PM Crit Interrupt Mask Reg */
2007 u8 res_170[12]; 2014 u8 res_170[12];
2008 u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */ 2015 u32 tpmmcmr0; /* Thread PM Machine Check Interrupt Mask Reg */
2009 u8 res_180[12]; 2016 u8 res_180[12];
2010 u32 tpmnmimr0; /* Thread PM NMI Mask Reg */ 2017 u32 tpmnmimr0; /* Thread PM NMI Mask Reg */
2011 u8 res_190[12]; 2018 u8 res_190[12];
2012 u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */ 2019 u32 tmcpmaskcr0; /* Thread Machine Check Mask Control Reg */
2013 u32 pctbenr; /* Physical Core Time Base Enable Reg */ 2020 u32 pctbenr; /* Physical Core Time Base Enable Reg */
2014 u32 pctbclkselr; /* Physical Core Time Base Clock Select */ 2021 u32 pctbclkselr; /* Physical Core Time Base Clock Select */
2015 u32 tbclkdivr; /* Time Base Clock Divider Register */ 2022 u32 tbclkdivr; /* Time Base Clock Divider Register */
2016 u8 res_1ac[4]; 2023 u8 res_1ac[4];
2017 u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */ 2024 u32 ttbhltcr[4]; /* Thread Time Base Halt Control Register */
2018 u32 clpcl10sr; /* Cluster PCL10 Status Register */ 2025 u32 clpcl10sr; /* Cluster PCL10 Status Register */
2019 u32 clpcl10setr; /* Cluster PCL30 Set Control Register */ 2026 u32 clpcl10setr; /* Cluster PCL30 Set Control Register */
2020 u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */ 2027 u32 clpcl10clrr; /* Cluster PCL30 Clear Control Register */
2021 u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */ 2028 u32 clpcl10psr; /* Cluster PCL30 Prev Status Register */
2022 u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */ 2029 u32 cddslpsetr; /* Core Domain Deep Sleep Set Register */
2023 u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */ 2030 u32 cddslpclrr; /* Core Domain Deep Sleep Clear Register */
2024 u32 cdpwroksetr; /* Core Domain Power OK Set Register */ 2031 u32 cdpwroksetr; /* Core Domain Power OK Set Register */
2025 u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */ 2032 u32 cdpwrokclrr; /* Core Domain Power OK Clear Register */
2026 u32 cdpwrensr; /* Core Domain Power Enable Status Register */ 2033 u32 cdpwrensr; /* Core Domain Power Enable Status Register */
2027 u32 cddslsr; /* Core Domain Deep Sleep Status Register */ 2034 u32 cddslsr; /* Core Domain Deep Sleep Status Register */
2028 u8 res_1e8[8]; 2035 u8 res_1e8[8];
2029 u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */ 2036 u32 dslpcntcr[8]; /* Deep Sleep Counter Cfg Register */
2030 u8 res_300[3568]; 2037 u8 res_300[3568];
2031 } ccsr_rcpm_t; 2038 } ccsr_rcpm_t;
2032 2039
2033 #define ctbenrl pctbenr 2040 #define ctbenrl pctbenr
2034 2041
2035 #else 2042 #else
2036 typedef struct ccsr_rcpm { 2043 typedef struct ccsr_rcpm {
2037 u8 res1[4]; 2044 u8 res1[4];
2038 u32 cdozsrl; /* Core Doze Status */ 2045 u32 cdozsrl; /* Core Doze Status */
2039 u8 res2[4]; 2046 u8 res2[4];
2040 u32 cdozcrl; /* Core Doze Control */ 2047 u32 cdozcrl; /* Core Doze Control */
2041 u8 res3[4]; 2048 u8 res3[4];
2042 u32 cnapsrl; /* Core Nap Status */ 2049 u32 cnapsrl; /* Core Nap Status */
2043 u8 res4[4]; 2050 u8 res4[4];
2044 u32 cnapcrl; /* Core Nap Control */ 2051 u32 cnapcrl; /* Core Nap Control */
2045 u8 res5[4]; 2052 u8 res5[4];
2046 u32 cdozpsrl; /* Core Doze Previous Status */ 2053 u32 cdozpsrl; /* Core Doze Previous Status */
2047 u8 res6[4]; 2054 u8 res6[4];
2048 u32 cdozpcrl; /* Core Doze Previous Control */ 2055 u32 cdozpcrl; /* Core Doze Previous Control */
2049 u8 res7[4]; 2056 u8 res7[4];
2050 u32 cwaitsrl; /* Core Wait Status */ 2057 u32 cwaitsrl; /* Core Wait Status */
2051 u8 res8[8]; 2058 u8 res8[8];
2052 u32 powmgtcsr; /* Power Mangement Control & Status */ 2059 u32 powmgtcsr; /* Power Mangement Control & Status */
2053 u8 res9[12]; 2060 u8 res9[12];
2054 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */ 2061 u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */
2055 u8 res10[12]; 2062 u8 res10[12];
2056 u8 res11[4]; 2063 u8 res11[4];
2057 u32 cpmimrl; /* Core PM IRQ Masking */ 2064 u32 cpmimrl; /* Core PM IRQ Masking */
2058 u8 res12[4]; 2065 u8 res12[4];
2059 u32 cpmcimrl; /* Core PM Critical IRQ Masking */ 2066 u32 cpmcimrl; /* Core PM Critical IRQ Masking */
2060 u8 res13[4]; 2067 u8 res13[4];
2061 u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */ 2068 u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */
2062 u8 res14[4]; 2069 u8 res14[4];
2063 u32 cpmnmimrl; /* Core PM NMI Masking */ 2070 u32 cpmnmimrl; /* Core PM NMI Masking */
2064 u8 res15[4]; 2071 u8 res15[4];
2065 u32 ctbenrl; /* Core Time Base Enable */ 2072 u32 ctbenrl; /* Core Time Base Enable */
2066 u8 res16[4]; 2073 u8 res16[4];
2067 u32 ctbclkselrl; /* Core Time Base Clock Select */ 2074 u32 ctbclkselrl; /* Core Time Base Clock Select */
2068 u8 res17[4]; 2075 u8 res17[4];
2069 u32 ctbhltcrl; /* Core Time Base Halt Control */ 2076 u32 ctbhltcrl; /* Core Time Base Halt Control */
2070 u8 res18[0xf68]; 2077 u8 res18[0xf68];
2071 } ccsr_rcpm_t; 2078 } ccsr_rcpm_t;
2072 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 2079 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2073 2080
2074 #else 2081 #else
2075 typedef struct ccsr_gur { 2082 typedef struct ccsr_gur {
2076 u32 porpllsr; /* POR PLL ratio status */ 2083 u32 porpllsr; /* POR PLL ratio status */
2077 #ifdef CONFIG_MPC8536 2084 #ifdef CONFIG_MPC8536
2078 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 2085 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000
2079 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 2086 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25
2080 #elif defined(CONFIG_PPC_C29X) 2087 #elif defined(CONFIG_PPC_C29X)
2081 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 2088 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2082 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \ 2089 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \
2083 & MPC85xx_PORDEVSR2_DDR_SPD_0) \ 2090 & MPC85xx_PORDEVSR2_DDR_SPD_0) \
2084 >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT)) 2091 >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
2085 #else 2092 #else
2086 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) 2093 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
2087 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 2094 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00
2088 #else 2095 #else
2089 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 2096 #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00
2090 #endif 2097 #endif
2091 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 2098 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9
2092 #endif 2099 #endif
2093 #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 2100 #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000
2094 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 2101 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25
2095 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e 2102 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e
2096 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 2103 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1
2097 u32 porbmsr; /* POR boot mode status */ 2104 u32 porbmsr; /* POR boot mode status */
2098 #define MPC85xx_PORBMSR_HA 0x00070000 2105 #define MPC85xx_PORBMSR_HA 0x00070000
2099 #define MPC85xx_PORBMSR_HA_SHIFT 16 2106 #define MPC85xx_PORBMSR_HA_SHIFT 16
2100 #define MPC85xx_PORBMSR_ROMLOC_SHIFT 24 2107 #define MPC85xx_PORBMSR_ROMLOC_SHIFT 24
2101 #define PORBMSR_ROMLOC_SPI 0x6 2108 #define PORBMSR_ROMLOC_SPI 0x6
2102 #define PORBMSR_ROMLOC_SDHC 0x7 2109 #define PORBMSR_ROMLOC_SDHC 0x7
2103 #define PORBMSR_ROMLOC_NAND_2K 0x9 2110 #define PORBMSR_ROMLOC_NAND_2K 0x9
2104 #define PORBMSR_ROMLOC_NOR 0xf 2111 #define PORBMSR_ROMLOC_NOR 0xf
2105 u32 porimpscr; /* POR I/O impedance status & control */ 2112 u32 porimpscr; /* POR I/O impedance status & control */
2106 u32 pordevsr; /* POR I/O device status regsiter */ 2113 u32 pordevsr; /* POR I/O device status regsiter */
2107 #if defined(CONFIG_P1017) || defined(CONFIG_P1023) 2114 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
2108 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000 2115 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
2109 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000 2116 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
2110 #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000 2117 #define MPC85xx_PORDEVSR_TSEC1_PRTC 0x02000000
2111 #else 2118 #else
2112 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 2119 #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
2113 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 2120 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
2114 #endif 2121 #endif
2115 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 2122 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
2116 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 2123 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
2117 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 2124 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
2118 #define MPC85xx_PORDEVSR_PCI1 0x00800000 2125 #define MPC85xx_PORDEVSR_PCI1 0x00800000
2119 #if defined(CONFIG_P1013) || defined(CONFIG_P1022) 2126 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2120 #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000 2127 #define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
2121 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18 2128 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
2122 #elif defined(CONFIG_P1017) || defined(CONFIG_P1023) 2129 #elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
2123 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 2130 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2124 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 2131 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2125 #else 2132 #else
2126 #if defined(CONFIG_P1010) 2133 #if defined(CONFIG_P1010)
2127 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000 2134 #define MPC85xx_PORDEVSR_IO_SEL 0x00600000
2128 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 2135 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2129 #elif defined(CONFIG_BSC9132) 2136 #elif defined(CONFIG_BSC9132)
2130 #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000 2137 #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000
2131 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17 2138 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17
2132 #elif defined(CONFIG_PPC_C29X) 2139 #elif defined(CONFIG_PPC_C29X)
2133 #define MPC85xx_PORDEVSR_IO_SEL 0x00e00000 2140 #define MPC85xx_PORDEVSR_IO_SEL 0x00e00000
2134 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 2141 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
2135 #else 2142 #else
2136 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 2143 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000
2137 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 2144 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
2138 #endif /* if defined(CONFIG_P1010) */ 2145 #endif /* if defined(CONFIG_P1010) */
2139 #endif 2146 #endif
2140 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 2147 #define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
2141 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 2148 #define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
2142 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 2149 #define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
2143 #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 2150 #define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
2144 #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 2151 #define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
2145 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 2152 #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
2146 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 2153 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
2147 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 2154 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
2148 u32 pordbgmsr; /* POR debug mode status */ 2155 u32 pordbgmsr; /* POR debug mode status */
2149 u32 pordevsr2; /* POR I/O device status 2 */ 2156 u32 pordevsr2; /* POR I/O device status 2 */
2150 #if defined(CONFIG_PPC_C29X) 2157 #if defined(CONFIG_PPC_C29X)
2151 #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 2158 #define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
2152 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 2159 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
2153 #endif 2160 #endif
2154 /* The 8544 RM says this is bit 26, but it's really bit 24 */ 2161 /* The 8544 RM says this is bit 26, but it's really bit 24 */
2155 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 2162 #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
2156 u8 res1[8]; 2163 u8 res1[8];
2157 u32 gpporcr; /* General-purpose POR configuration */ 2164 u32 gpporcr; /* General-purpose POR configuration */
2158 u8 res2[12]; 2165 u8 res2[12];
2159 #if defined(CONFIG_MPC8536) 2166 #if defined(CONFIG_MPC8536)
2160 u32 gencfgr; /* General Configuration Register */ 2167 u32 gencfgr; /* General Configuration Register */
2161 #define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000 2168 #define MPC85xx_GENCFGR_SDHC_WP_INV 0x20000000
2162 #else 2169 #else
2163 u32 gpiocr; /* GPIO control */ 2170 u32 gpiocr; /* GPIO control */
2164 #endif 2171 #endif
2165 u8 res3[12]; 2172 u8 res3[12];
2166 #if defined(CONFIG_MPC8569) 2173 #if defined(CONFIG_MPC8569)
2167 u32 plppar1; /* Platform port pin assignment 1 */ 2174 u32 plppar1; /* Platform port pin assignment 1 */
2168 u32 plppar2; /* Platform port pin assignment 2 */ 2175 u32 plppar2; /* Platform port pin assignment 2 */
2169 u32 plpdir1; /* Platform port pin direction 1 */ 2176 u32 plpdir1; /* Platform port pin direction 1 */
2170 u32 plpdir2; /* Platform port pin direction 2 */ 2177 u32 plpdir2; /* Platform port pin direction 2 */
2171 #else 2178 #else
2172 u32 gpoutdr; /* General-purpose output data */ 2179 u32 gpoutdr; /* General-purpose output data */
2173 u8 res4[12]; 2180 u8 res4[12];
2174 #endif 2181 #endif
2175 u32 gpindr; /* General-purpose input data */ 2182 u32 gpindr; /* General-purpose input data */
2176 u8 res5[12]; 2183 u8 res5[12];
2177 u32 pmuxcr; /* Alt. function signal multiplex control */ 2184 u32 pmuxcr; /* Alt. function signal multiplex control */
2178 #if defined(CONFIG_P1010) || defined(CONFIG_P1014) 2185 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
2179 #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000 2186 #define MPC85xx_PMUXCR_TSEC1_0_1588 0x40000000
2180 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000 2187 #define MPC85xx_PMUXCR_TSEC1_0_RES 0xC0000000
2181 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000 2188 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG 0x10000000
2182 #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000 2189 #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12 0x20000000
2183 #define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000 2190 #define MPC85xx_PMUXCR_TSEC1_1_RES 0x30000000
2184 #define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000 2191 #define MPC85xx_PMUXCR_TSEC1_2_DMA 0x04000000
2185 #define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000 2192 #define MPC85xx_PMUXCR_TSEC1_2_GPIO 0x08000000
2186 #define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000 2193 #define MPC85xx_PMUXCR_TSEC1_2_RES 0x0C000000
2187 #define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000 2194 #define MPC85xx_PMUXCR_TSEC1_3_RES 0x01000000
2188 #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000 2195 #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15 0x02000000
2189 #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000 2196 #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC 0x00400000
2190 #define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000 2197 #define MPC85xx_PMUXCR_IFC_ADDR16_USB 0x00800000
2191 #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000 2198 #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2 0x00C00000
2192 #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000 2199 #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC 0x00100000
2193 #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000 2200 #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB 0x00200000
2194 #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000 2201 #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA 0x00300000
2195 #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000 2202 #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA 0x00040000
2196 #define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000 2203 #define MPC85xx_PMUXCR_IFC_ADDR19_USB 0x00080000
2197 #define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000 2204 #define MPC85xx_PMUXCR_IFC_ADDR19_DMA 0x000C0000
2198 #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000 2205 #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA 0x00010000
2199 #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000 2206 #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB 0x00020000
2200 #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000 2207 #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES 0x00030000
2201 #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000 2208 #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC 0x00004000
2202 #define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000 2209 #define MPC85xx_PMUXCR_IFC_ADDR22_USB 0x00008000
2203 #define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000 2210 #define MPC85xx_PMUXCR_IFC_ADDR22_RES 0x0000C000
2204 #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000 2211 #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC 0x00001000
2205 #define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000 2212 #define MPC85xx_PMUXCR_IFC_ADDR23_USB 0x00002000
2206 #define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000 2213 #define MPC85xx_PMUXCR_IFC_ADDR23_RES 0x00003000
2207 #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400 2214 #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC 0x00000400
2208 #define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800 2215 #define MPC85xx_PMUXCR_IFC_ADDR24_USB 0x00000800
2209 #define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00 2216 #define MPC85xx_PMUXCR_IFC_ADDR24_RES 0x00000C00
2210 #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300 2217 #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES 0x00000300
2211 #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200 2218 #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB 0x00000200
2212 #define MPC85xx_PMUXCR_LCLK_RES 0x00000040 2219 #define MPC85xx_PMUXCR_LCLK_RES 0x00000040
2213 #define MPC85xx_PMUXCR_LCLK_USB 0x00000080 2220 #define MPC85xx_PMUXCR_LCLK_USB 0x00000080
2214 #define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0 2221 #define MPC85xx_PMUXCR_LCLK_IFC_CS3 0x000000C0
2215 #define MPC85xx_PMUXCR_SPI_RES 0x00000030 2222 #define MPC85xx_PMUXCR_SPI_RES 0x00000030
2216 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000020 2223 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000020
2217 #define MPC85xx_PMUXCR_CAN1_UART 0x00000004 2224 #define MPC85xx_PMUXCR_CAN1_UART 0x00000004
2218 #define MPC85xx_PMUXCR_CAN1_TDM 0x00000008 2225 #define MPC85xx_PMUXCR_CAN1_TDM 0x00000008
2219 #define MPC85xx_PMUXCR_CAN1_RES 0x0000000C 2226 #define MPC85xx_PMUXCR_CAN1_RES 0x0000000C
2220 #define MPC85xx_PMUXCR_CAN2_UART 0x00000001 2227 #define MPC85xx_PMUXCR_CAN2_UART 0x00000001
2221 #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002 2228 #define MPC85xx_PMUXCR_CAN2_TDM 0x00000002
2222 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003 2229 #define MPC85xx_PMUXCR_CAN2_RES 0x00000003
2223 #endif 2230 #endif
2224 #if defined(CONFIG_P1017) || defined(CONFIG_P1023) 2231 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
2225 #define MPC85xx_PMUXCR_TSEC1_1 0x10000000 2232 #define MPC85xx_PMUXCR_TSEC1_1 0x10000000
2226 #else 2233 #else
2227 #define MPC85xx_PMUXCR_SD_DATA 0x80000000 2234 #define MPC85xx_PMUXCR_SD_DATA 0x80000000
2228 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 2235 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000
2229 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 2236 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000
2230 #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000 2237 #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON 0x01000000
2231 #define MPC85xx_PMUXCR_TDM_ENA 0x00800000 2238 #define MPC85xx_PMUXCR_TDM_ENA 0x00800000
2232 #define MPC85xx_PMUXCR_QE0 0x00008000 2239 #define MPC85xx_PMUXCR_QE0 0x00008000
2233 #define MPC85xx_PMUXCR_QE1 0x00004000 2240 #define MPC85xx_PMUXCR_QE1 0x00004000
2234 #define MPC85xx_PMUXCR_QE2 0x00002000 2241 #define MPC85xx_PMUXCR_QE2 0x00002000
2235 #define MPC85xx_PMUXCR_QE3 0x00001000 2242 #define MPC85xx_PMUXCR_QE3 0x00001000
2236 #define MPC85xx_PMUXCR_QE4 0x00000800 2243 #define MPC85xx_PMUXCR_QE4 0x00000800
2237 #define MPC85xx_PMUXCR_QE5 0x00000400 2244 #define MPC85xx_PMUXCR_QE5 0x00000400
2238 #define MPC85xx_PMUXCR_QE6 0x00000200 2245 #define MPC85xx_PMUXCR_QE6 0x00000200
2239 #define MPC85xx_PMUXCR_QE7 0x00000100 2246 #define MPC85xx_PMUXCR_QE7 0x00000100
2240 #define MPC85xx_PMUXCR_QE8 0x00000080 2247 #define MPC85xx_PMUXCR_QE8 0x00000080
2241 #define MPC85xx_PMUXCR_QE9 0x00000040 2248 #define MPC85xx_PMUXCR_QE9 0x00000040
2242 #define MPC85xx_PMUXCR_QE10 0x00000020 2249 #define MPC85xx_PMUXCR_QE10 0x00000020
2243 #define MPC85xx_PMUXCR_QE11 0x00000010 2250 #define MPC85xx_PMUXCR_QE11 0x00000010
2244 #define MPC85xx_PMUXCR_QE12 0x00000008 2251 #define MPC85xx_PMUXCR_QE12 0x00000008
2245 #endif 2252 #endif
2246 #if defined(CONFIG_P1013) || defined(CONFIG_P1022) 2253 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2247 #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00 2254 #define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
2248 #define MPC85xx_PMUXCR_TDM 0x00014800 2255 #define MPC85xx_PMUXCR_TDM 0x00014800
2249 #define MPC85xx_PMUXCR_SPI_MASK 0x00600000 2256 #define MPC85xx_PMUXCR_SPI_MASK 0x00600000
2250 #define MPC85xx_PMUXCR_SPI 0x00000000 2257 #define MPC85xx_PMUXCR_SPI 0x00000000
2251 #endif 2258 #endif
2252 #if defined(CONFIG_BSC9131) 2259 #if defined(CONFIG_BSC9131)
2253 #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 2260 #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000
2254 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 2261 #define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000
2255 #define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000 2262 #define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000
2256 #define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000 2263 #define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000
2257 #define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000 2264 #define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000
2258 #define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000 2265 #define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000
2259 #define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000 2266 #define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000
2260 #define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000 2267 #define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000
2261 #define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000 2268 #define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000
2262 #define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000 2269 #define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000
2263 #define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000 2270 #define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000
2264 #define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000 2271 #define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000
2265 #define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000 2272 #define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000
2266 #define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000 2273 #define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000
2267 #define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000 2274 #define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000
2268 #define MPC85xx_PMUXCR_SDHC_USIM 0x00010000 2275 #define MPC85xx_PMUXCR_SDHC_USIM 0x00010000
2269 #define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000 2276 #define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000
2270 #define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000 2277 #define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000
2271 #define MPC85xx_PMUXCR_SDHC_RESV 0x00004000 2278 #define MPC85xx_PMUXCR_SDHC_RESV 0x00004000
2272 #define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000 2279 #define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000
2273 #define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000 2280 #define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000
2274 #define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000 2281 #define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000
2275 #define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000 2282 #define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000
2276 #define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000 2283 #define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000
2277 #define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400 2284 #define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400
2278 #define MPC85xx_PMUXCR_USB_RSVD 0x00000C00 2285 #define MPC85xx_PMUXCR_USB_RSVD 0x00000C00
2279 #define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800 2286 #define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800
2280 #define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100 2287 #define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100
2281 #define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200 2288 #define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200
2282 #define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300 2289 #define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300
2283 #define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040 2290 #define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040
2284 #define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080 2291 #define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080
2285 #define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0 2292 #define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0
2286 #define MPC85xx_PMUXCR_SPI1_UART3 0x00000010 2293 #define MPC85xx_PMUXCR_SPI1_UART3 0x00000010
2287 #define MPC85xx_PMUXCR_SPI1_SIM 0x00000020 2294 #define MPC85xx_PMUXCR_SPI1_SIM 0x00000020
2288 #define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030 2295 #define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030
2289 #define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004 2296 #define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004
2290 #define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008 2297 #define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008
2291 #define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C 2298 #define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C
2292 #define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001 2299 #define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001
2293 #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002 2300 #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002
2294 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003 2301 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003
2295 #endif 2302 #endif
2296 #ifdef CONFIG_BSC9132 2303 #ifdef CONFIG_BSC9132
2297 #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000 2304 #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000
2298 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000 2305 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000
2299 #endif 2306 #endif
2300 #if defined(CONFIG_PPC_C29X) 2307 #if defined(CONFIG_PPC_C29X)
2301 #define MPC85xx_PMUXCR_SPI_MASK 0x00000300 2308 #define MPC85xx_PMUXCR_SPI_MASK 0x00000300
2302 #define MPC85xx_PMUXCR_SPI 0x00000000 2309 #define MPC85xx_PMUXCR_SPI 0x00000000
2303 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100 2310 #define MPC85xx_PMUXCR_SPI_GPIO 0x00000100
2304 #endif 2311 #endif
2305 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ 2312 u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
2306 #if defined(CONFIG_P1010) || defined(CONFIG_P1014) 2313 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
2307 #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 2314 #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000
2308 #define MPC85xx_PMUXCR2_UART_TDM 0x80000000 2315 #define MPC85xx_PMUXCR2_UART_TDM 0x80000000
2309 #define MPC85xx_PMUXCR2_UART_RES 0xC0000000 2316 #define MPC85xx_PMUXCR2_UART_RES 0xC0000000
2310 #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000 2317 #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN 0x10000000
2311 #define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000 2318 #define MPC85xx_PMUXCR2_IRQ2_RES 0x30000000
2312 #define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000 2319 #define MPC85xx_PMUXCR2_IRQ3_SRESET 0x04000000
2313 #define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000 2320 #define MPC85xx_PMUXCR2_IRQ3_RES 0x0C000000
2314 #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000 2321 #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS 0x01000000
2315 #define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000 2322 #define MPC85xx_PMUXCR2_GPIO01_RES 0x03000000
2316 #define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000 2323 #define MPC85xx_PMUXCR2_GPIO23_CKSTP 0x00400000
2317 #define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000 2324 #define MPC85xx_PMUXCR2_GPIO23_RES 0x00800000
2318 #define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000 2325 #define MPC85xx_PMUXCR2_GPIO23_USB 0x00C00000
2319 #define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000 2326 #define MPC85xx_PMUXCR2_GPIO4_MCP 0x00100000
2320 #define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000 2327 #define MPC85xx_PMUXCR2_GPIO4_RES 0x00200000
2321 #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000 2328 #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT 0x00300000
2322 #define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000 2329 #define MPC85xx_PMUXCR2_GPIO5_UDE 0x00040000
2323 #define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000 2330 #define MPC85xx_PMUXCR2_GPIO5_RES 0x00080000
2324 #define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000 2331 #define MPC85xx_PMUXCR2_READY_ASLEEP 0x00020000
2325 #define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000 2332 #define MPC85xx_PMUXCR2_DDR_ECC_MUX 0x00010000
2326 #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000 2333 #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE 0x00008000
2327 #define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000 2334 #define MPC85xx_PMUXCR2_POST_EXPOSE 0x00004000
2328 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000 2335 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY 0x00002000
2329 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000 2336 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE 0x00001000
2330 #endif 2337 #endif
2331 #if defined(CONFIG_P1013) || defined(CONFIG_P1022) 2338 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
2332 #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 2339 #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000
2333 #define MPC85xx_PMUXCR2_USB 0x00150000 2340 #define MPC85xx_PMUXCR2_USB 0x00150000
2334 #endif 2341 #endif
2335 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) 2342 #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
2336 #if defined(CONFIG_BSC9131) 2343 #if defined(CONFIG_BSC9131)
2337 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 2344 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000
2338 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000 2345 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000
2339 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000 2346 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000
2340 #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000 2347 #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000
2341 #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000 2348 #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000
2342 #define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000 2349 #define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000
2343 #define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000 2350 #define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000
2344 #define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000 2351 #define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000
2345 #define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000 2352 #define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000
2346 #define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000 2353 #define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000
2347 #define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000 2354 #define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000
2348 #define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000 2355 #define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000
2349 #define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000 2356 #define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000
2350 #define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000 2357 #define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000
2351 #define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000 2358 #define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000
2352 #define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000 2359 #define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000
2353 #define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000 2360 #define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000
2354 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000 2361 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000
2355 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000 2362 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000
2356 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000 2363 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000
2357 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000 2364 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000
2358 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000 2365 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000
2359 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000 2366 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000
2360 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000 2367 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000
2361 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000 2368 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000
2362 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000 2369 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000
2363 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000 2370 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000
2364 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000 2371 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000
2365 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000 2372 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000
2366 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400 2373 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400
2367 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800 2374 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800
2368 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00 2375 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00
2369 #define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100 2376 #define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100
2370 #define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300 2377 #define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300
2371 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040 2378 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040
2372 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0 2379 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0
2373 #define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010 2380 #define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010
2374 #define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020 2381 #define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020
2375 #define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030 2382 #define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030
2376 #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004 2383 #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004
2377 #define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001 2384 #define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001
2378 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002 2385 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002
2379 #endif 2386 #endif
2380 u32 pmuxcr3; 2387 u32 pmuxcr3;
2381 #if defined(CONFIG_BSC9131) 2388 #if defined(CONFIG_BSC9131)
2382 #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000 2389 #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000
2383 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000 2390 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000
2384 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000 2391 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000
2385 #define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000 2392 #define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000
2386 #define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000 2393 #define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000
2387 #define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000 2394 #define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000
2388 #define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000 2395 #define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000
2389 #define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000 2396 #define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000
2390 #define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000 2397 #define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000
2391 #define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000 2398 #define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000
2392 #define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000 2399 #define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000
2393 #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000 2400 #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000
2394 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000 2401 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000
2395 #define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000 2402 #define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000
2396 #endif 2403 #endif
2397 #ifdef CONFIG_BSC9132 2404 #ifdef CONFIG_BSC9132
2398 #define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00 2405 #define MPC85xx_PMUXCR3_USB_SEL_MASK 0x0000ff00
2399 #define MPC85xx_PMUXCR3_UART2_SEL 0x00005000 2406 #define MPC85xx_PMUXCR3_UART2_SEL 0x00005000
2400 #define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000 2407 #define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
2401 #define MPC85xx_PMUXCR3_UART3_SEL 0x40000000 2408 #define MPC85xx_PMUXCR3_UART3_SEL 0x40000000
2402 #endif 2409 #endif
2403 u32 pmuxcr4; 2410 u32 pmuxcr4;
2404 #else 2411 #else
2405 u8 res6[8]; 2412 u8 res6[8];
2406 #endif 2413 #endif
2407 u32 devdisr; /* Device disable control */ 2414 u32 devdisr; /* Device disable control */
2408 #define MPC85xx_DEVDISR_PCI1 0x80000000 2415 #define MPC85xx_DEVDISR_PCI1 0x80000000
2409 #define MPC85xx_DEVDISR_PCI2 0x40000000 2416 #define MPC85xx_DEVDISR_PCI2 0x40000000
2410 #define MPC85xx_DEVDISR_PCIE 0x20000000 2417 #define MPC85xx_DEVDISR_PCIE 0x20000000
2411 #define MPC85xx_DEVDISR_LBC 0x08000000 2418 #define MPC85xx_DEVDISR_LBC 0x08000000
2412 #define MPC85xx_DEVDISR_PCIE2 0x04000000 2419 #define MPC85xx_DEVDISR_PCIE2 0x04000000
2413 #define MPC85xx_DEVDISR_PCIE3 0x02000000 2420 #define MPC85xx_DEVDISR_PCIE3 0x02000000
2414 #define MPC85xx_DEVDISR_SEC 0x01000000 2421 #define MPC85xx_DEVDISR_SEC 0x01000000
2415 #define MPC85xx_DEVDISR_SRIO 0x00080000 2422 #define MPC85xx_DEVDISR_SRIO 0x00080000
2416 #define MPC85xx_DEVDISR_RMSG 0x00040000 2423 #define MPC85xx_DEVDISR_RMSG 0x00040000
2417 #define MPC85xx_DEVDISR_DDR 0x00010000 2424 #define MPC85xx_DEVDISR_DDR 0x00010000
2418 #define MPC85xx_DEVDISR_CPU 0x00008000 2425 #define MPC85xx_DEVDISR_CPU 0x00008000
2419 #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU 2426 #define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU
2420 #define MPC85xx_DEVDISR_TB 0x00004000 2427 #define MPC85xx_DEVDISR_TB 0x00004000
2421 #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB 2428 #define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB
2422 #define MPC85xx_DEVDISR_CPU1 0x00002000 2429 #define MPC85xx_DEVDISR_CPU1 0x00002000
2423 #define MPC85xx_DEVDISR_TB1 0x00001000 2430 #define MPC85xx_DEVDISR_TB1 0x00001000
2424 #define MPC85xx_DEVDISR_DMA 0x00000400 2431 #define MPC85xx_DEVDISR_DMA 0x00000400
2425 #define MPC85xx_DEVDISR_TSEC1 0x00000080 2432 #define MPC85xx_DEVDISR_TSEC1 0x00000080
2426 #define MPC85xx_DEVDISR_TSEC2 0x00000040 2433 #define MPC85xx_DEVDISR_TSEC2 0x00000040
2427 #define MPC85xx_DEVDISR_TSEC3 0x00000020 2434 #define MPC85xx_DEVDISR_TSEC3 0x00000020
2428 #define MPC85xx_DEVDISR_TSEC4 0x00000010 2435 #define MPC85xx_DEVDISR_TSEC4 0x00000010
2429 #define MPC85xx_DEVDISR_I2C 0x00000004 2436 #define MPC85xx_DEVDISR_I2C 0x00000004
2430 #define MPC85xx_DEVDISR_DUART 0x00000002 2437 #define MPC85xx_DEVDISR_DUART 0x00000002
2431 u8 res7[12]; 2438 u8 res7[12];
2432 u32 powmgtcsr; /* Power management status & control */ 2439 u32 powmgtcsr; /* Power management status & control */
2433 u8 res8[12]; 2440 u8 res8[12];
2434 u32 mcpsumr; /* Machine check summary */ 2441 u32 mcpsumr; /* Machine check summary */
2435 u8 res9[12]; 2442 u8 res9[12];
2436 u32 pvr; /* Processor version */ 2443 u32 pvr; /* Processor version */
2437 u32 svr; /* System version */ 2444 u32 svr; /* System version */
2438 u8 res10[8]; 2445 u8 res10[8];
2439 u32 rstcr; /* Reset control */ 2446 u32 rstcr; /* Reset control */
2440 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) 2447 #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
2441 u8 res11a[76]; 2448 u8 res11a[76];
2442 par_io_t qe_par_io[7]; 2449 par_io_t qe_par_io[7];
2443 u8 res11b[1600]; 2450 u8 res11b[1600];
2444 #elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) 2451 #elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
2445 u8 res11a[12]; 2452 u8 res11a[12];
2446 u32 iovselsr; 2453 u32 iovselsr;
2447 u8 res11b[60]; 2454 u8 res11b[60];
2448 par_io_t qe_par_io[3]; 2455 par_io_t qe_par_io[3];
2449 u8 res11c[1496]; 2456 u8 res11c[1496];
2450 #else 2457 #else
2451 u8 res11a[1868]; 2458 u8 res11a[1868];
2452 #endif 2459 #endif
2453 u32 clkdvdr; /* Clock Divide register */ 2460 u32 clkdvdr; /* Clock Divide register */
2454 u8 res12[1532]; 2461 u8 res12[1532];
2455 u32 clkocr; /* Clock out select */ 2462 u32 clkocr; /* Clock out select */
2456 u8 res13[12]; 2463 u8 res13[12];
2457 u32 ddrdllcr; /* DDR DLL control */ 2464 u32 ddrdllcr; /* DDR DLL control */
2458 u8 res14[12]; 2465 u8 res14[12];
2459 u32 lbcdllcr; /* LBC DLL control */ 2466 u32 lbcdllcr; /* LBC DLL control */
2460 #if defined(CONFIG_BSC9131) 2467 #if defined(CONFIG_BSC9131)
2461 u8 res15[12]; 2468 u8 res15[12];
2462 u32 halt_req_mask; 2469 u32 halt_req_mask;
2463 #define HALTED_TO_HALT_REQ_MASK_0 0x80000000 2470 #define HALTED_TO_HALT_REQ_MASK_0 0x80000000
2464 u8 res18[232]; 2471 u8 res18[232];
2465 #else 2472 #else
2466 u8 res15[248]; 2473 u8 res15[248];
2467 #endif 2474 #endif
2468 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ 2475 u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
2469 u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ 2476 u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
2470 u32 ddrioovcr; /* DDR IO Override Control */ 2477 u32 ddrioovcr; /* DDR IO Override Control */
2471 u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */ 2478 u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
2472 u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */ 2479 u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
2473 u8 res16[52]; 2480 u8 res16[52];
2474 u32 sdhcdcr; /* SDHC debug control register */ 2481 u32 sdhcdcr; /* SDHC debug control register */
2475 u8 res17[61592]; 2482 u8 res17[61592];
2476 } ccsr_gur_t; 2483 } ccsr_gur_t;
2477 #endif 2484 #endif
2478 2485
2479 #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */ 2486 #define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
2480 2487
2481 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 2488 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
2482 #define MAX_SERDES 4 2489 #define MAX_SERDES 4
2483 #define SRDS_MAX_LANES 8 2490 #define SRDS_MAX_LANES 8
2484 #define SRDS_MAX_BANK 2 2491 #define SRDS_MAX_BANK 2
2485 typedef struct serdes_corenet { 2492 typedef struct serdes_corenet {
2486 struct { 2493 struct {
2487 u32 rstctl; /* Reset Control Register */ 2494 u32 rstctl; /* Reset Control Register */
2488 #define SRDS_RSTCTL_RST 0x80000000 2495 #define SRDS_RSTCTL_RST 0x80000000
2489 #define SRDS_RSTCTL_RSTDONE 0x40000000 2496 #define SRDS_RSTCTL_RSTDONE 0x40000000
2490 #define SRDS_RSTCTL_RSTERR 0x20000000 2497 #define SRDS_RSTCTL_RSTERR 0x20000000
2491 #define SRDS_RSTCTL_SWRST 0x10000000 2498 #define SRDS_RSTCTL_SWRST 0x10000000
2492 #define SRDS_RSTCTL_SDEN 0x00000020 2499 #define SRDS_RSTCTL_SDEN 0x00000020
2493 #define SRDS_RSTCTL_SDRST_B 0x00000040 2500 #define SRDS_RSTCTL_SDRST_B 0x00000040
2494 #define SRDS_RSTCTL_PLLRST_B 0x00000080 2501 #define SRDS_RSTCTL_PLLRST_B 0x00000080
2502 #define SRDS_RSTCTL_RSTERR_SHIFT 29
2495 u32 pllcr0; /* PLL Control Register 0 */ 2503 u32 pllcr0; /* PLL Control Register 0 */
2496 #define SRDS_PLLCR0_POFF 0x80000000 2504 #define SRDS_PLLCR0_POFF 0x80000000
2497 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 2505 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2498 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 2506 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2499 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 2507 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2500 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 2508 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2501 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 2509 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2502 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 2510 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2503 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000 2511 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
2512 #define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
2504 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000 2513 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
2505 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 2514 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2506 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 2515 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
2507 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 2516 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
2508 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000 2517 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
2509 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000 2518 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
2510 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000 2519 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
2520 #define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
2521 #define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
2511 u32 pllcr1; /* PLL Control Register 1 */ 2522 u32 pllcr1; /* PLL Control Register 1 */
2512 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 2523 #define SRDS_PLLCR1_BCAP_EN 0x20000000
2513 u32 res_0c; /* 0x00c */ 2524 #define SRDS_PLLCR1_BCAP_OVD 0x10000000
2525 #define SRDS_PLLCR1_PLL_FCAP 0x001F8000
2526 #define SRDS_PLLCR1_PLL_FCAP_SHIFT 15
2527 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2528 #define SRDS_PLLCR1_BYP_CAL 0x02000000
2529 u32 pllsr2; /* At 0x00c, PLL Status Register 2 */
2530 #define SRDS_PLLSR2_BCAP_EN 0x00800000
2531 #define SRDS_PLLSR2_BCAP_EN_SHIFT 23
2532 #define SRDS_PLLSR2_FCAP 0x003F0000
2533 #define SRDS_PLLSR2_FCAP_SHIFT 16
2534 #define SRDS_PLLSR2_DCBIAS 0x000F0000
2535 #define SRDS_PLLSR2_DCBIAS_SHIFT 16
2514 u32 pllcr3; 2536 u32 pllcr3;
2515 u32 pllcr4; 2537 u32 pllcr4;
2516 u8 res_18[0x20-0x18]; 2538 u8 res_18[0x20-0x18];
2517 } bank[2]; 2539 } bank[2];
2518 u8 res_40[0x90-0x40]; 2540 u8 res_40[0x90-0x40];
2519 u32 srdstcalcr; /* 0x90 TX Calibration Control */ 2541 u32 srdstcalcr; /* 0x90 TX Calibration Control */
2520 u8 res_94[0xa0-0x94]; 2542 u8 res_94[0xa0-0x94];
2521 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */ 2543 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
2522 u8 res_a4[0xb0-0xa4]; 2544 u8 res_a4[0xb0-0xa4];
2523 u32 srdsgr0; /* 0xb0 General Register 0 */ 2545 u32 srdsgr0; /* 0xb0 General Register 0 */
2524 u8 res_b4[0xe0-0xb4]; 2546 u8 res_b4[0xe0-0xb4];
2525 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */ 2547 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
2526 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */ 2548 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
2527 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */ 2549 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
2528 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */ 2550 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
2529 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */ 2551 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
2530 u8 res_f4[0x100-0xf4]; 2552 u8 res_f4[0x100-0xf4];
2531 struct { 2553 struct {
2532 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */ 2554 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
2533 u8 res_104[0x120-0x104]; 2555 u8 res_104[0x120-0x104];
2534 } srdslnpssr[8]; 2556 } srdslnpssr[8];
2535 u8 res_200[0x800-0x200]; 2557 u8 res_200[0x800-0x200];
2536 struct { 2558 struct {
2537 u32 gcr0; /* 0x800 General Control Register 0 */ 2559 u32 gcr0; /* 0x800 General Control Register 0 */
2538 u32 gcr1; /* 0x804 General Control Register 1 */ 2560 u32 gcr1; /* 0x804 General Control Register 1 */
2539 u32 gcr2; /* 0x808 General Control Register 2 */ 2561 u32 gcr2; /* 0x808 General Control Register 2 */
2540 u32 res_80c; 2562 u32 res_80c;
2541 u32 recr0; /* 0x810 Receive Equalization Control */ 2563 u32 recr0; /* 0x810 Receive Equalization Control */
2542 u32 res_814; 2564 u32 res_814;
2543 u32 tecr0; /* 0x818 Transmit Equalization Control */ 2565 u32 tecr0; /* 0x818 Transmit Equalization Control */
2544 u32 res_81c; 2566 u32 res_81c;
2545 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */ 2567 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
2546 u8 res_824[0x840-0x824]; 2568 u8 res_824[0x840-0x824];
2547 } lane[8]; /* Lane A, B, C, D, E, F, G, H */ 2569 } lane[8]; /* Lane A, B, C, D, E, F, G, H */
2548 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ 2570 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
2549 } serdes_corenet_t; 2571 } serdes_corenet_t;
2550 2572
2551 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 2573 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2552 2574
2553 #define SRDS_MAX_LANES 18 2575 #define SRDS_MAX_LANES 18
2554 #define SRDS_MAX_BANK 3 2576 #define SRDS_MAX_BANK 3
2555 typedef struct serdes_corenet { 2577 typedef struct serdes_corenet {
2556 struct { 2578 struct {
2557 u32 rstctl; /* Reset Control Register */ 2579 u32 rstctl; /* Reset Control Register */
2558 #define SRDS_RSTCTL_RST 0x80000000 2580 #define SRDS_RSTCTL_RST 0x80000000
2559 #define SRDS_RSTCTL_RSTDONE 0x40000000 2581 #define SRDS_RSTCTL_RSTDONE 0x40000000
2560 #define SRDS_RSTCTL_RSTERR 0x20000000 2582 #define SRDS_RSTCTL_RSTERR 0x20000000
2561 #define SRDS_RSTCTL_SDPD 0x00000020 2583 #define SRDS_RSTCTL_SDPD 0x00000020
2562 u32 pllcr0; /* PLL Control Register 0 */ 2584 u32 pllcr0; /* PLL Control Register 0 */
2563 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 2585 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
2564 #define SRDS_PLLCR0_PVCOCNT_EN 0x02000000 2586 #define SRDS_PLLCR0_PVCOCNT_EN 0x02000000
2565 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 2587 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
2566 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 2588 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
2567 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 2589 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
2568 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 2590 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2569 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 2591 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2570 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000 2592 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
2571 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 2593 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2572 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000 2594 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
2573 u32 pllcr1; /* PLL Control Register 1 */ 2595 u32 pllcr1; /* PLL Control Register 1 */
2574 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000 2596 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2575 u32 res[5]; 2597 u32 res[5];
2576 } bank[3]; 2598 } bank[3];
2577 u32 res1[12]; 2599 u32 res1[12];
2578 u32 srdstcalcr; /* TX Calibration Control */ 2600 u32 srdstcalcr; /* TX Calibration Control */
2579 u32 res2[3]; 2601 u32 res2[3];
2580 u32 srdsrcalcr; /* RX Calibration Control */ 2602 u32 srdsrcalcr; /* RX Calibration Control */
2581 u32 res3[3]; 2603 u32 res3[3];
2582 u32 srdsgr0; /* General Register 0 */ 2604 u32 srdsgr0; /* General Register 0 */
2583 u32 res4[11]; 2605 u32 res4[11];
2584 u32 srdspccr0; /* Protocol Converter Config 0 */ 2606 u32 srdspccr0; /* Protocol Converter Config 0 */
2585 u32 srdspccr1; /* Protocol Converter Config 1 */ 2607 u32 srdspccr1; /* Protocol Converter Config 1 */
2586 u32 srdspccr2; /* Protocol Converter Config 2 */ 2608 u32 srdspccr2; /* Protocol Converter Config 2 */
2587 #define SRDS_PCCR2_RST_XGMII1 0x00800000 2609 #define SRDS_PCCR2_RST_XGMII1 0x00800000
2588 #define SRDS_PCCR2_RST_XGMII2 0x00400000 2610 #define SRDS_PCCR2_RST_XGMII2 0x00400000
2589 u32 res5[197]; 2611 u32 res5[197];
2590 struct serdes_lane { 2612 struct serdes_lane {
2591 u32 gcr0; /* General Control Register 0 */ 2613 u32 gcr0; /* General Control Register 0 */
2592 #define SRDS_GCR0_RRST 0x00400000 2614 #define SRDS_GCR0_RRST 0x00400000
2593 #define SRDS_GCR0_1STLANE 0x00010000 2615 #define SRDS_GCR0_1STLANE 0x00010000
2594 #define SRDS_GCR0_UOTHL 0x00100000 2616 #define SRDS_GCR0_UOTHL 0x00100000
2595 u32 gcr1; /* General Control Register 1 */ 2617 u32 gcr1; /* General Control Register 1 */
2596 #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000 2618 #define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000
2597 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000 2619 #define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000
2598 #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000 2620 #define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000
2599 #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000 2621 #define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000
2600 #define SRDS_GCR1_OPAD_CTL 0x04000000 2622 #define SRDS_GCR1_OPAD_CTL 0x04000000
2601 u32 res1[4]; 2623 u32 res1[4];
2602 u32 tecr0; /* TX Equalization Control Reg 0 */ 2624 u32 tecr0; /* TX Equalization Control Reg 0 */
2603 #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000 2625 #define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000
2604 #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000 2626 #define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000
2605 u32 res3; 2627 u32 res3;
2606 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ 2628 u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */
2607 #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000 2629 #define SRDS_TTLCR0_FLT_SEL_MASK 0x3f000000
2608 #define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000 2630 #define SRDS_TTLCR0_FLT_SEL_KFR_26 0x10000000
2609 #define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000 2631 #define SRDS_TTLCR0_FLT_SEL_KPH_28 0x08000000
2610 #define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000 2632 #define SRDS_TTLCR0_FLT_SEL_750PPM 0x03000000
2611 #define SRDS_TTLCR0_PM_DIS 0x00004000 2633 #define SRDS_TTLCR0_PM_DIS 0x00004000
2612 #define SRDS_TTLCR0_FREQOVD_EN 0x00000001 2634 #define SRDS_TTLCR0_FREQOVD_EN 0x00000001
2613 u32 res4[7]; 2635 u32 res4[7];
2614 } lane[24]; 2636 } lane[24];
2615 u32 res6[384]; 2637 u32 res6[384];
2616 } serdes_corenet_t; 2638 } serdes_corenet_t;
2617 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 2639 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
2618 2640
2619 enum { 2641 enum {
2620 FSL_SRDS_B1_LANE_A = 0, 2642 FSL_SRDS_B1_LANE_A = 0,
2621 FSL_SRDS_B1_LANE_B = 1, 2643 FSL_SRDS_B1_LANE_B = 1,
2622 FSL_SRDS_B1_LANE_C = 2, 2644 FSL_SRDS_B1_LANE_C = 2,
2623 FSL_SRDS_B1_LANE_D = 3, 2645 FSL_SRDS_B1_LANE_D = 3,
2624 FSL_SRDS_B1_LANE_E = 4, 2646 FSL_SRDS_B1_LANE_E = 4,
2625 FSL_SRDS_B1_LANE_F = 5, 2647 FSL_SRDS_B1_LANE_F = 5,
2626 FSL_SRDS_B1_LANE_G = 6, 2648 FSL_SRDS_B1_LANE_G = 6,
2627 FSL_SRDS_B1_LANE_H = 7, 2649 FSL_SRDS_B1_LANE_H = 7,
2628 FSL_SRDS_B1_LANE_I = 8, 2650 FSL_SRDS_B1_LANE_I = 8,
2629 FSL_SRDS_B1_LANE_J = 9, 2651 FSL_SRDS_B1_LANE_J = 9,
2630 FSL_SRDS_B2_LANE_A = 16, 2652 FSL_SRDS_B2_LANE_A = 16,
2631 FSL_SRDS_B2_LANE_B = 17, 2653 FSL_SRDS_B2_LANE_B = 17,
2632 FSL_SRDS_B2_LANE_C = 18, 2654 FSL_SRDS_B2_LANE_C = 18,
2633 FSL_SRDS_B2_LANE_D = 19, 2655 FSL_SRDS_B2_LANE_D = 19,
2634 FSL_SRDS_B3_LANE_A = 20, 2656 FSL_SRDS_B3_LANE_A = 20,
2635 FSL_SRDS_B3_LANE_B = 21, 2657 FSL_SRDS_B3_LANE_B = 21,
2636 FSL_SRDS_B3_LANE_C = 22, 2658 FSL_SRDS_B3_LANE_C = 22,
2637 FSL_SRDS_B3_LANE_D = 23, 2659 FSL_SRDS_B3_LANE_D = 23,
2638 }; 2660 };
2639 2661
2640 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ 2662 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
2641 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 2663 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
2642 typedef struct ccsr_sec { 2664 typedef struct ccsr_sec {
2643 u32 res0; 2665 u32 res0;
2644 u32 mcfgr; /* Master CFG Register */ 2666 u32 mcfgr; /* Master CFG Register */
2645 u8 res1[0x8]; 2667 u8 res1[0x8];
2646 struct { 2668 struct {
2647 u32 ms; /* Job Ring LIODN Register, MS */ 2669 u32 ms; /* Job Ring LIODN Register, MS */
2648 u32 ls; /* Job Ring LIODN Register, LS */ 2670 u32 ls; /* Job Ring LIODN Register, LS */
2649 } jrliodnr[4]; 2671 } jrliodnr[4];
2650 u8 res2[0x30]; 2672 u8 res2[0x30];
2651 struct { 2673 struct {
2652 u32 ms; /* RTIC LIODN Register, MS */ 2674 u32 ms; /* RTIC LIODN Register, MS */
2653 u32 ls; /* RTIC LIODN Register, LS */ 2675 u32 ls; /* RTIC LIODN Register, LS */
2654 } rticliodnr[4]; 2676 } rticliodnr[4];
2655 u8 res3[0x1c]; 2677 u8 res3[0x1c];
2656 u32 decorr; /* DECO Request Register */ 2678 u32 decorr; /* DECO Request Register */
2657 struct { 2679 struct {
2658 u32 ms; /* DECO LIODN Register, MS */ 2680 u32 ms; /* DECO LIODN Register, MS */
2659 u32 ls; /* DECO LIODN Register, LS */ 2681 u32 ls; /* DECO LIODN Register, LS */
2660 } decoliodnr[8]; 2682 } decoliodnr[8];
2661 u8 res4[0x40]; 2683 u8 res4[0x40];
2662 u32 dar; /* DECO Avail Register */ 2684 u32 dar; /* DECO Avail Register */
2663 u32 drr; /* DECO Reset Register */ 2685 u32 drr; /* DECO Reset Register */
2664 u8 res5[0xe78]; 2686 u8 res5[0xe78];
2665 u32 crnr_ms; /* CHA Revision Number Register, MS */ 2687 u32 crnr_ms; /* CHA Revision Number Register, MS */
2666 u32 crnr_ls; /* CHA Revision Number Register, LS */ 2688 u32 crnr_ls; /* CHA Revision Number Register, LS */
2667 u32 ctpr_ms; /* Compile Time Parameters Register, MS */ 2689 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
2668 u32 ctpr_ls; /* Compile Time Parameters Register, LS */ 2690 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
2669 u8 res6[0x10]; 2691 u8 res6[0x10];
2670 u32 far_ms; /* Fault Address Register, MS */ 2692 u32 far_ms; /* Fault Address Register, MS */
2671 u32 far_ls; /* Fault Address Register, LS */ 2693 u32 far_ls; /* Fault Address Register, LS */
2672 u32 falr; /* Fault Address LIODN Register */ 2694 u32 falr; /* Fault Address LIODN Register */
2673 u32 fadr; /* Fault Address Detail Register */ 2695 u32 fadr; /* Fault Address Detail Register */
2674 u8 res7[0x4]; 2696 u8 res7[0x4];
2675 u32 csta; /* CAAM Status Register */ 2697 u32 csta; /* CAAM Status Register */
2676 u8 res8[0x8]; 2698 u8 res8[0x8];
2677 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ 2699 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
2678 u32 ccbvid; /* CHA Cluster Block Version ID Register */ 2700 u32 ccbvid; /* CHA Cluster Block Version ID Register */
2679 u32 chavid_ms; /* CHA Version ID Register, MS */ 2701 u32 chavid_ms; /* CHA Version ID Register, MS */
2680 u32 chavid_ls; /* CHA Version ID Register, LS */ 2702 u32 chavid_ls; /* CHA Version ID Register, LS */
2681 u32 chanum_ms; /* CHA Number Register, MS */ 2703 u32 chanum_ms; /* CHA Number Register, MS */
2682 u32 chanum_ls; /* CHA Number Register, LS */ 2704 u32 chanum_ls; /* CHA Number Register, LS */
2683 u32 secvid_ms; /* SEC Version ID Register, MS */ 2705 u32 secvid_ms; /* SEC Version ID Register, MS */
2684 u32 secvid_ls; /* SEC Version ID Register, LS */ 2706 u32 secvid_ls; /* SEC Version ID Register, LS */
2685 u8 res9[0x6020]; 2707 u8 res9[0x6020];
2686 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ 2708 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
2687 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ 2709 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
2688 u8 res10[0x8fd8]; 2710 u8 res10[0x8fd8];
2689 } ccsr_sec_t; 2711 } ccsr_sec_t;
2690 2712
2691 #define SEC_CTPR_MS_AXI_LIODN 0x08000000 2713 #define SEC_CTPR_MS_AXI_LIODN 0x08000000
2692 #define SEC_CTPR_MS_QI 0x02000000 2714 #define SEC_CTPR_MS_QI 0x02000000
2693 #define SEC_RVID_MA 0x0f000000 2715 #define SEC_RVID_MA 0x0f000000
2694 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000 2716 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
2695 #define SEC_CHANUM_MS_JRNUM_SHIFT 28 2717 #define SEC_CHANUM_MS_JRNUM_SHIFT 28
2696 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000 2718 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
2697 #define SEC_CHANUM_MS_DECONUM_SHIFT 24 2719 #define SEC_CHANUM_MS_DECONUM_SHIFT 24
2698 #define SEC_SECVID_MS_IPID_MASK 0xffff0000 2720 #define SEC_SECVID_MS_IPID_MASK 0xffff0000
2699 #define SEC_SECVID_MS_IPID_SHIFT 16 2721 #define SEC_SECVID_MS_IPID_SHIFT 16
2700 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00 2722 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
2701 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8 2723 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8
2702 #define SEC_CCBVID_ERA_MASK 0xff000000 2724 #define SEC_CCBVID_ERA_MASK 0xff000000
2703 #define SEC_CCBVID_ERA_SHIFT 24 2725 #define SEC_CCBVID_ERA_SHIFT 24
2704 #endif 2726 #endif
2705 2727
2706 typedef struct ccsr_qman { 2728 typedef struct ccsr_qman {
2707 #ifdef CONFIG_SYS_FSL_QMAN_V3 2729 #ifdef CONFIG_SYS_FSL_QMAN_V3
2708 u8 res0[0x200]; 2730 u8 res0[0x200];
2709 #else 2731 #else
2710 struct { 2732 struct {
2711 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ 2733 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2712 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ 2734 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2713 u32 res; 2735 u32 res;
2714 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */ 2736 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
2715 } qcsp[32]; 2737 } qcsp[32];
2716 #endif 2738 #endif
2717 /* Not actually reserved, but irrelevant to u-boot */ 2739 /* Not actually reserved, but irrelevant to u-boot */
2718 u8 res[0xbf8 - 0x200]; 2740 u8 res[0xbf8 - 0x200];
2719 u32 ip_rev_1; 2741 u32 ip_rev_1;
2720 u32 ip_rev_2; 2742 u32 ip_rev_2;
2721 u32 fqd_bare; /* FQD Extended Base Addr Register */ 2743 u32 fqd_bare; /* FQD Extended Base Addr Register */
2722 u32 fqd_bar; /* FQD Base Addr Register */ 2744 u32 fqd_bar; /* FQD Base Addr Register */
2723 u8 res1[0x8]; 2745 u8 res1[0x8];
2724 u32 fqd_ar; /* FQD Attributes Register */ 2746 u32 fqd_ar; /* FQD Attributes Register */
2725 u8 res2[0xc]; 2747 u8 res2[0xc];
2726 u32 pfdr_bare; /* PFDR Extended Base Addr Register */ 2748 u32 pfdr_bare; /* PFDR Extended Base Addr Register */
2727 u32 pfdr_bar; /* PFDR Base Addr Register */ 2749 u32 pfdr_bar; /* PFDR Base Addr Register */
2728 u8 res3[0x8]; 2750 u8 res3[0x8];
2729 u32 pfdr_ar; /* PFDR Attributes Register */ 2751 u32 pfdr_ar; /* PFDR Attributes Register */
2730 u8 res4[0x4c]; 2752 u8 res4[0x4c];
2731 u32 qcsp_bare; /* QCSP Extended Base Addr Register */ 2753 u32 qcsp_bare; /* QCSP Extended Base Addr Register */
2732 u32 qcsp_bar; /* QCSP Base Addr Register */ 2754 u32 qcsp_bar; /* QCSP Base Addr Register */
2733 u8 res5[0x78]; 2755 u8 res5[0x78];
2734 u32 ci_sched_cfg; /* Initiator Scheduling Configuration */ 2756 u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
2735 u32 srcidr; /* Source ID Register */ 2757 u32 srcidr; /* Source ID Register */
2736 u32 liodnr; /* LIODN Register */ 2758 u32 liodnr; /* LIODN Register */
2737 u8 res6[4]; 2759 u8 res6[4];
2738 u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */ 2760 u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
2739 u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */ 2761 u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
2740 u8 res7[0x2e8]; 2762 u8 res7[0x2e8];
2741 #ifdef CONFIG_SYS_FSL_QMAN_V3 2763 #ifdef CONFIG_SYS_FSL_QMAN_V3
2742 struct { 2764 struct {
2743 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */ 2765 u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2744 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */ 2766 u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2745 u32 res; 2767 u32 res;
2746 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/ 2768 u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
2747 } qcsp[50]; 2769 } qcsp[50];
2748 #endif 2770 #endif
2749 } ccsr_qman_t; 2771 } ccsr_qman_t;
2750 2772
2751 typedef struct ccsr_bman { 2773 typedef struct ccsr_bman {
2752 /* Not actually reserved, but irrelevant to u-boot */ 2774 /* Not actually reserved, but irrelevant to u-boot */
2753 u8 res[0xbf8]; 2775 u8 res[0xbf8];
2754 u32 ip_rev_1; 2776 u32 ip_rev_1;
2755 u32 ip_rev_2; 2777 u32 ip_rev_2;
2756 u32 fbpr_bare; /* FBPR Extended Base Addr Register */ 2778 u32 fbpr_bare; /* FBPR Extended Base Addr Register */
2757 u32 fbpr_bar; /* FBPR Base Addr Register */ 2779 u32 fbpr_bar; /* FBPR Base Addr Register */
2758 u8 res1[0x8]; 2780 u8 res1[0x8];
2759 u32 fbpr_ar; /* FBPR Attributes Register */ 2781 u32 fbpr_ar; /* FBPR Attributes Register */
2760 u8 res2[0xf0]; 2782 u8 res2[0xf0];
2761 u32 srcidr; /* Source ID Register */ 2783 u32 srcidr; /* Source ID Register */
2762 u32 liodnr; /* LIODN Register */ 2784 u32 liodnr; /* LIODN Register */
2763 u8 res7[0x2f4]; 2785 u8 res7[0x2f4];
2764 } ccsr_bman_t; 2786 } ccsr_bman_t;
2765 2787
2766 typedef struct ccsr_pme { 2788 typedef struct ccsr_pme {
2767 u8 res0[0x804]; 2789 u8 res0[0x804];
2768 u32 liodnbr; /* LIODN Base Register */ 2790 u32 liodnbr; /* LIODN Base Register */
2769 u8 res1[0x1f8]; 2791 u8 res1[0x1f8];
2770 u32 srcidr; /* Source ID Register */ 2792 u32 srcidr; /* Source ID Register */
2771 u8 res2[8]; 2793 u8 res2[8];
2772 u32 liodnr; /* LIODN Register */ 2794 u32 liodnr; /* LIODN Register */
2773 u8 res3[0x1e8]; 2795 u8 res3[0x1e8];
2774 u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/ 2796 u32 pm_ip_rev_1; /* PME IP Block Revision Reg 1*/
2775 u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/ 2797 u32 pm_ip_rev_2; /* PME IP Block Revision Reg 1*/
2776 u8 res4[0x400]; 2798 u8 res4[0x400];
2777 } ccsr_pme_t; 2799 } ccsr_pme_t;
2778 2800
2779 #ifdef CONFIG_SYS_FSL_RAID_ENGINE 2801 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
2780 struct ccsr_raide { 2802 struct ccsr_raide {
2781 u8 res0[0x543]; 2803 u8 res0[0x543];
2782 u32 liodnbr; /* LIODN Base Register */ 2804 u32 liodnbr; /* LIODN Base Register */
2783 u8 res1[0xab8]; 2805 u8 res1[0xab8];
2784 struct { 2806 struct {
2785 struct { 2807 struct {
2786 u32 cfg0; /* cfg register 0 */ 2808 u32 cfg0; /* cfg register 0 */
2787 u32 cfg1; /* cfg register 1 */ 2809 u32 cfg1; /* cfg register 1 */
2788 u8 res1[0x3f8]; 2810 u8 res1[0x3f8];
2789 } ring[2]; 2811 } ring[2];
2790 u8 res[0x800]; 2812 u8 res[0x800];
2791 } jq[2]; 2813 } jq[2];
2792 }; 2814 };
2793 #endif 2815 #endif
2794 2816
2795 #ifdef CONFIG_SYS_DPAA_RMAN 2817 #ifdef CONFIG_SYS_DPAA_RMAN
2796 struct ccsr_rman { 2818 struct ccsr_rman {
2797 u8 res0[0xf64]; 2819 u8 res0[0xf64];
2798 u32 mmliodnbr; /* Message Manager LIODN Base Register */ 2820 u32 mmliodnbr; /* Message Manager LIODN Base Register */
2799 u32 mmitar; /* RMAN Inbound Translation Address Register */ 2821 u32 mmitar; /* RMAN Inbound Translation Address Register */
2800 u32 mmitdr; /* RMAN Inbound Translation Data Register */ 2822 u32 mmitdr; /* RMAN Inbound Translation Data Register */
2801 u8 res4[0x1f090]; 2823 u8 res4[0x1f090];
2802 }; 2824 };
2803 #endif 2825 #endif
2804 2826
2805 #ifdef CONFIG_SYS_PMAN 2827 #ifdef CONFIG_SYS_PMAN
2806 struct ccsr_pman { 2828 struct ccsr_pman {
2807 u8 res_00[0x40]; 2829 u8 res_00[0x40];
2808 u32 poes1; /* PMAN Operation Error Status Register 1 */ 2830 u32 poes1; /* PMAN Operation Error Status Register 1 */
2809 u32 poes2; /* PMAN Operation Error Status Register 2 */ 2831 u32 poes2; /* PMAN Operation Error Status Register 2 */
2810 u32 poeah; /* PMAN Operation Error Address High */ 2832 u32 poeah; /* PMAN Operation Error Address High */
2811 u32 poeal; /* PMAN Operation Error Address Low */ 2833 u32 poeal; /* PMAN Operation Error Address Low */
2812 u8 res_50[0x50]; 2834 u8 res_50[0x50];
2813 u32 pr1; /* PMAN Revision Register 1 */ 2835 u32 pr1; /* PMAN Revision Register 1 */
2814 u32 pr2; /* PMAN Revision Register 2 */ 2836 u32 pr2; /* PMAN Revision Register 2 */
2815 u8 res_a8[0x8]; 2837 u8 res_a8[0x8];
2816 u32 pcap; /* PMAN Capabilities Register */ 2838 u32 pcap; /* PMAN Capabilities Register */
2817 u8 res_b4[0xc]; 2839 u8 res_b4[0xc];
2818 u32 pc1; /* PMAN Control Register 1 */ 2840 u32 pc1; /* PMAN Control Register 1 */
2819 u32 pc2; /* PMAN Control Register 2 */ 2841 u32 pc2; /* PMAN Control Register 2 */
2820 u32 pc3; /* PMAN Control Register 3 */ 2842 u32 pc3; /* PMAN Control Register 3 */
2821 u32 pc4; /* PMAN Control Register 4 */ 2843 u32 pc4; /* PMAN Control Register 4 */
2822 u32 pc5; /* PMAN Control Register 5 */ 2844 u32 pc5; /* PMAN Control Register 5 */
2823 u32 pc6; /* PMAN Control Register 6 */ 2845 u32 pc6; /* PMAN Control Register 6 */
2824 u8 res_d8[0x8]; 2846 u8 res_d8[0x8];
2825 u32 ppa1; /* PMAN Prefetch Attributes Register 1 */ 2847 u32 ppa1; /* PMAN Prefetch Attributes Register 1 */
2826 u32 ppa2; /* PMAN Prefetch Attributes Register 2 */ 2848 u32 ppa2; /* PMAN Prefetch Attributes Register 2 */
2827 u8 res_e8[0x8]; 2849 u8 res_e8[0x8];
2828 u32 pics; /* PMAN Interrupt Control and Status */ 2850 u32 pics; /* PMAN Interrupt Control and Status */
2829 u8 res_f4[0xf0c]; 2851 u8 res_f4[0xf0c];
2830 }; 2852 };
2831 #endif 2853 #endif
2832 2854
2833 #ifdef CONFIG_FSL_CORENET 2855 #ifdef CONFIG_FSL_CORENET
2834 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 2856 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
2835 #ifdef CONFIG_SYS_PMAN 2857 #ifdef CONFIG_SYS_PMAN
2836 #define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000 2858 #define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
2837 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000 2859 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
2838 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000 2860 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
2839 #endif 2861 #endif
2840 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000 2862 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000
2841 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000 2863 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
2842 #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000 2864 #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
2843 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 2865 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
2844 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 2866 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
2845 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 2867 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
2846 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 2868 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
2847 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 2869 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
2870 #define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
2848 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 2871 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2849 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 2872 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
2850 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000 2873 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
2851 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET 2874 #define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET
2852 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 2875 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000
2853 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 2876 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000
2854 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 2877 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
2855 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000 2878 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
2856 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 2879 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
2857 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 2880 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
2858 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\ 2881 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
2859 && !defined(CONFIG_PPC_B4420) 2882 && !defined(CONFIG_PPC_B4420)
2860 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 2883 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
2861 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000 2884 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000
2862 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000 2885 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000
2863 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000 2886 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000
2864 #else 2887 #else
2865 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 2888 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000
2866 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000 2889 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000
2867 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000 2890 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000
2868 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000 2891 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000
2869 #endif 2892 #endif
2870 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 2893 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000
2871 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 2894 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000
2872 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 2895 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
2873 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 2896 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
2874 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 2897 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000
2875 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 2898 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
2876 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 2899 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
2877 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 2900 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
2878 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 2901 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
2879 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 2902 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
2880 #define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000 2903 #define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
2881 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 2904 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
2882 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 2905 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
2883 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 2906 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
2884 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000 2907 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
2885 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000 2908 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
2886 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000 2909 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
2887 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000 2910 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
2888 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000 2911 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
2889 #define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000 2912 #define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
2890 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000 2913 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
2891 #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000 2914 #define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
2892 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000 2915 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
2893 #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000 2916 #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
2894 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000 2917 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
2895 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000 2918 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
2896 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000 2919 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
2897 #define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000 2920 #define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
2898 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000 2921 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
2899 #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000 2922 #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
2900 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000 2923 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
2901 #else 2924 #else
2902 #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 2925 #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
2903 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000 2926 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000
2904 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000 2927 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000
2905 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000 2928 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
2906 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000 2929 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000
2907 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000 2930 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000
2908 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000 2931 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000
2909 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000 2932 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000
2910 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 2933 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000
2911 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 2934 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000
2912 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 2935 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000
2913 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) 2936 #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
2914 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 2937 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000
2915 #else 2938 #else
2916 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000 2939 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000
2917 #endif 2940 #endif
2918 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 2941 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
2919 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 2942 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
2920 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 2943 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
2921 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000 2944 #define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
2922 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 2945 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
2923 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 2946 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
2924 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000 2947 #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000
2925 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000 2948 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000
2926 #ifdef CONFIG_TSECV2 2949 #ifdef CONFIG_TSECV2
2927 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 2950 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000
2928 #elif defined(CONFIG_TSECV2_1) 2951 #elif defined(CONFIG_TSECV2_1)
2929 #define CONFIG_SYS_TSEC1_OFFSET 0x10000 2952 #define CONFIG_SYS_TSEC1_OFFSET 0x10000
2930 #else 2953 #else
2931 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 2954 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
2932 #endif 2955 #endif
2933 #define CONFIG_SYS_MDIO1_OFFSET 0x24000 2956 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
2934 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 2957 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
2935 #if defined(CONFIG_PPC_C29X) 2958 #if defined(CONFIG_PPC_C29X)
2936 #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000 2959 #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
2937 #else 2960 #else
2938 #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000 2961 #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
2939 #endif 2962 #endif
2940 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 2963 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
2941 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 2964 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
2942 #define CONFIG_SYS_SNVS_OFFSET 0xE6000 2965 #define CONFIG_SYS_SNVS_OFFSET 0xE6000
2943 #define CONFIG_SYS_SFP_OFFSET 0xE7000 2966 #define CONFIG_SYS_SFP_OFFSET 0xE7000
2944 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 2967 #define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
2945 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000 2968 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
2946 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000 2969 #define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
2947 #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000 2970 #define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
2948 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000 2971 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
2949 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000 2972 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
2950 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000 2973 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
2951 #endif 2974 #endif
2952 2975
2953 #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 2976 #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
2954 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 2977 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
2955 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 2978 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
2956 2979
2957 #if defined(CONFIG_BSC9132) 2980 #if defined(CONFIG_BSC9132)
2958 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000 2981 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET 0x10000
2959 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \ 2982 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
2960 (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET) 2983 (CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
2961 #endif 2984 #endif
2962 2985
2963 #define CONFIG_SYS_FSL_CPC_ADDR \ 2986 #define CONFIG_SYS_FSL_CPC_ADDR \
2964 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) 2987 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
2988 #define CONFIG_SYS_FSL_SCFG_ADDR \
2989 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
2990 #define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
2991 (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
2965 #define CONFIG_SYS_FSL_QMAN_ADDR \ 2992 #define CONFIG_SYS_FSL_QMAN_ADDR \
2966 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) 2993 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
2967 #define CONFIG_SYS_FSL_BMAN_ADDR \ 2994 #define CONFIG_SYS_FSL_BMAN_ADDR \
2968 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET) 2995 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
2969 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \ 2996 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
2970 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) 2997 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
2971 #define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \ 2998 #define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
2972 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) 2999 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
2973 #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \ 3000 #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
2974 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET) 3001 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
2975 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ 3002 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
2976 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) 3003 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
2977 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ 3004 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
2978 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) 3005 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
2979 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \ 3006 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
2980 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) 3007 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
2981 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \ 3008 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
2982 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) 3009 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
2983 #define CONFIG_SYS_MPC85xx_ECM_ADDR \ 3010 #define CONFIG_SYS_MPC85xx_ECM_ADDR \
2984 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) 3011 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
2985 #define CONFIG_SYS_FSL_DDR_ADDR \ 3012 #define CONFIG_SYS_FSL_DDR_ADDR \
2986 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) 3013 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
2987 #define CONFIG_SYS_FSL_DDR2_ADDR \ 3014 #define CONFIG_SYS_FSL_DDR2_ADDR \
2988 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) 3015 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
2989 #define CONFIG_SYS_FSL_DDR3_ADDR \ 3016 #define CONFIG_SYS_FSL_DDR3_ADDR \
2990 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET) 3017 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
2991 #define CONFIG_SYS_LBC_ADDR \ 3018 #define CONFIG_SYS_LBC_ADDR \
2992 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) 3019 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
2993 #define CONFIG_SYS_IFC_ADDR \ 3020 #define CONFIG_SYS_IFC_ADDR \
2994 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET) 3021 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
2995 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \ 3022 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \
2996 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) 3023 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
2997 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \ 3024 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \
2998 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) 3025 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
2999 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \ 3026 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
3000 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) 3027 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
3001 #define CONFIG_SYS_MPC85xx_GPIO_ADDR \ 3028 #define CONFIG_SYS_MPC85xx_GPIO_ADDR \
3002 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) 3029 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
3003 #define CONFIG_SYS_MPC85xx_SATA1_ADDR \ 3030 #define CONFIG_SYS_MPC85xx_SATA1_ADDR \
3004 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) 3031 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
3005 #define CONFIG_SYS_MPC85xx_SATA2_ADDR \ 3032 #define CONFIG_SYS_MPC85xx_SATA2_ADDR \
3006 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) 3033 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
3007 #define CONFIG_SYS_MPC85xx_L2_ADDR \ 3034 #define CONFIG_SYS_MPC85xx_L2_ADDR \
3008 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) 3035 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
3009 #define CONFIG_SYS_MPC85xx_DMA_ADDR \ 3036 #define CONFIG_SYS_MPC85xx_DMA_ADDR \
3010 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) 3037 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
3011 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ 3038 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
3012 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) 3039 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
3013 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \ 3040 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \
3014 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) 3041 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
3015 #define CONFIG_SYS_MPC85xx_CPM_ADDR \ 3042 #define CONFIG_SYS_MPC85xx_CPM_ADDR \
3016 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) 3043 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
3017 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \ 3044 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
3018 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET) 3045 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
3019 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ 3046 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
3020 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) 3047 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
3021 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ 3048 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
3022 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) 3049 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
3023 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \ 3050 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
3024 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET) 3051 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
3025 #define CONFIG_SYS_MPC85xx_USB1_ADDR \ 3052 #define CONFIG_SYS_MPC85xx_USB1_ADDR \
3026 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET) 3053 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
3027 #define CONFIG_SYS_MPC85xx_USB2_ADDR \ 3054 #define CONFIG_SYS_MPC85xx_USB2_ADDR \
3028 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET) 3055 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
3029 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ 3056 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
3030 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET) 3057 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
3031 #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \ 3058 #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
3032 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET) 3059 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
3033 #define CONFIG_SYS_FSL_SEC_ADDR \ 3060 #define CONFIG_SYS_FSL_SEC_ADDR \
3034 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) 3061 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
3035 #define CONFIG_SYS_FSL_FM1_ADDR \ 3062 #define CONFIG_SYS_FSL_FM1_ADDR \
3036 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) 3063 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
3037 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ 3064 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
3038 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) 3065 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
3039 #define CONFIG_SYS_FSL_FM2_ADDR \ 3066 #define CONFIG_SYS_FSL_FM2_ADDR \
3040 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) 3067 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
3041 #define CONFIG_SYS_FSL_SRIO_ADDR \ 3068 #define CONFIG_SYS_FSL_SRIO_ADDR \
3042 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET) 3069 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
3043 3070
3044 #define CONFIG_SYS_PCI1_ADDR \ 3071 #define CONFIG_SYS_PCI1_ADDR \
3045 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) 3072 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
3046 #define CONFIG_SYS_PCI2_ADDR \ 3073 #define CONFIG_SYS_PCI2_ADDR \
3047 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET) 3074 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
3048 #define CONFIG_SYS_PCIE1_ADDR \ 3075 #define CONFIG_SYS_PCIE1_ADDR \
3049 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET) 3076 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
3050 #define CONFIG_SYS_PCIE2_ADDR \ 3077 #define CONFIG_SYS_PCIE2_ADDR \
3051 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET) 3078 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
3052 #define CONFIG_SYS_PCIE3_ADDR \ 3079 #define CONFIG_SYS_PCIE3_ADDR \
3053 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET) 3080 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
3054 #define CONFIG_SYS_PCIE4_ADDR \ 3081 #define CONFIG_SYS_PCIE4_ADDR \
3055 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET) 3082 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
3056 3083
3057 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 3084 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
3058 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) 3085 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
3059 3086
3060 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 3087 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
3061 struct ccsr_cluster_l2 { 3088 struct ccsr_cluster_l2 {
3062 u32 l2csr0; /* 0x000 L2 cache control and status register 0 */ 3089 u32 l2csr0; /* 0x000 L2 cache control and status register 0 */
3063 u32 l2csr1; /* 0x004 L2 cache control and status register 1 */ 3090 u32 l2csr1; /* 0x004 L2 cache control and status register 1 */
3064 u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */ 3091 u32 l2cfg0; /* 0x008 L2 cache configuration register 0 */
3065 u8 res_0c[500];/* 0x00c - 0x1ff */ 3092 u8 res_0c[500];/* 0x00c - 0x1ff */
3066 u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */ 3093 u32 l2pir0; /* 0x200 L2 cache partitioning ID register 0 */
3067 u8 res_204[4]; 3094 u8 res_204[4];
3068 u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */ 3095 u32 l2par0; /* 0x208 L2 cache partitioning allocation register 0 */
3069 u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */ 3096 u32 l2pwr0; /* 0x20c L2 cache partitioning way register 0 */
3070 u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */ 3097 u32 l2pir1; /* 0x210 L2 cache partitioning ID register 1 */
3071 u8 res_214[4]; 3098 u8 res_214[4];
3072 u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */ 3099 u32 l2par1; /* 0x218 L2 cache partitioning allocation register 1 */
3073 u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */ 3100 u32 l2pwr1; /* 0x21c L2 cache partitioning way register 1 */
3074 u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */ 3101 u32 u2pir2; /* 0x220 L2 cache partitioning ID register 2 */
3075 u8 res_224[4]; 3102 u8 res_224[4];
3076 u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */ 3103 u32 l2par2; /* 0x228 L2 cache partitioning allocation register 2 */
3077 u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */ 3104 u32 l2pwr2; /* 0x22c L2 cache partitioning way register 2 */
3078 u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */ 3105 u32 l2pir3; /* 0x230 L2 cache partitioning ID register 3 */
3079 u8 res_234[4]; 3106 u8 res_234[4];
3080 u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */ 3107 u32 l2par3; /* 0x238 L2 cache partitining allocation register 3 */
3081 u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */ 3108 u32 l2pwr3; /* 0x23c L2 cache partitining way register 3 */
3082 u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */ 3109 u32 l2pir4; /* 0x240 L2 cache partitioning ID register 3 */
3083 u8 res244[4]; 3110 u8 res244[4];
3084 u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */ 3111 u32 l2par4; /* 0x248 L2 cache partitioning allocation register 3 */
3085 u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */ 3112 u32 l2pwr4; /* 0x24c L2 cache partitioning way register 3 */
3086 u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */ 3113 u32 l2pir5; /* 0x250 L2 cache partitioning ID register 3 */
3087 u8 res_254[4]; 3114 u8 res_254[4];
3088 u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */ 3115 u32 l2par5; /* 0x258 L2 cache partitioning allocation register 3 */
3089 u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */ 3116 u32 l2pwr5; /* 0x25c L2 cache partitioning way register 3 */
3090 u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */ 3117 u32 l2pir6; /* 0x260 L2 cache partitioning ID register 3 */
3091 u8 res_264[4]; 3118 u8 res_264[4];
3092 u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */ 3119 u32 l2par6; /* 0x268 L2 cache partitioning allocation register 3 */
3093 u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */ 3120 u32 l2pwr6; /* 0x26c L2 cache partitioning way register 3 */
3094 u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */ 3121 u32 l2pir7; /* 0x270 L2 cache partitioning ID register 3 */
3095 u8 res274[4]; 3122 u8 res274[4];
3096 u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */ 3123 u32 l2par7; /* 0x278 L2 cache partitioning allocation register 3 */
3097 u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */ 3124 u32 l2pwr7; /* 0x27c L2 cache partitioning way register 3 */
3098 u8 res_280[0xb80]; /* 0x280 - 0xdff */ 3125 u8 res_280[0xb80]; /* 0x280 - 0xdff */
3099 u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */ 3126 u32 l2errinjhi; /* 0xe00 L2 cache error injection mask high */
3100 u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */ 3127 u32 l2errinjlo; /* 0xe04 L2 cache error injection mask low */
3101 u32 l2errinjctl;/* 0xe08 L2 cache error injection control */ 3128 u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
3102 u8 res_e0c[20]; /* 0xe0c - 0x01f */ 3129 u8 res_e0c[20]; /* 0xe0c - 0x01f */
3103 u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */ 3130 u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
3104 u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */ 3131 u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
3105 u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */ 3132 u32 l2captecc; /* 0xe28 L2 cache error capture ECC syndrome */
3106 u8 res_e2c[20]; /* 0xe2c - 0xe3f */ 3133 u8 res_e2c[20]; /* 0xe2c - 0xe3f */
3107 u32 l2errdet; /* 0xe40 L2 cache error detect */ 3134 u32 l2errdet; /* 0xe40 L2 cache error detect */
3108 u32 l2errdis; /* 0xe44 L2 cache error disable */ 3135 u32 l2errdis; /* 0xe44 L2 cache error disable */
3109 u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */ 3136 u32 l2errinten; /* 0xe48 L2 cache error interrupt enable */
3110 u32 l2errattr; /* 0xe4c L2 cache error attribute */ 3137 u32 l2errattr; /* 0xe4c L2 cache error attribute */
3111 u32 l2erreaddr; /* 0xe50 L2 cache error extended address */ 3138 u32 l2erreaddr; /* 0xe50 L2 cache error extended address */
3112 u32 l2erraddr; /* 0xe54 L2 cache error address */ 3139 u32 l2erraddr; /* 0xe54 L2 cache error address */
3113 u32 l2errctl; /* 0xe58 L2 cache error control */ 3140 u32 l2errctl; /* 0xe58 L2 cache error control */
3114 }; 3141 };
3115 #define CONFIG_SYS_FSL_CLUSTER_1_L2 \ 3142 #define CONFIG_SYS_FSL_CLUSTER_1_L2 \
3116 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET) 3143 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
3117 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ 3144 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
3118 3145
3119 #define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000 3146 #define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000
3120 struct dcsr_dcfg_regs { 3147 struct dcsr_dcfg_regs {
3121 u8 res_0[0x520]; 3148 u8 res_0[0x520];
3122 u32 ecccr1; 3149 u32 ecccr1;
3123 #define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000 3150 #define DCSR_DCFG_ECC_DISABLE_USB1 0x00008000
3124 #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000 3151 #define DCSR_DCFG_ECC_DISABLE_USB2 0x00004000
3125 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */ 3152 u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
3126 }; 3153 };
3127 #endif /*__IMMAP_85xx__*/ 3154 #endif /*__IMMAP_85xx__*/
3128 3155
arch/powerpc/lib/bootm.c
Diff comments   View file @ 247161b
1 /* 1 /*
2 * (C) Copyright 2008 Semihalf 2 * (C) Copyright 2008 Semihalf
3 * 3 *
4 * (C) Copyright 2000-2006 4 * (C) Copyright 2000-2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 10
11 #include <common.h> 11 #include <common.h>
12 #include <watchdog.h> 12 #include <watchdog.h>
13 #include <command.h> 13 #include <command.h>
14 #include <image.h> 14 #include <image.h>
15 #include <malloc.h> 15 #include <malloc.h>
16 #include <u-boot/zlib.h> 16 #include <u-boot/zlib.h>
17 #include <bzlib.h> 17 #include <bzlib.h>
18 #include <environment.h> 18 #include <environment.h>
19 #include <asm/byteorder.h> 19 #include <asm/byteorder.h>
20 #include <asm/mp.h> 20 #include <asm/mp.h>
21 21
22 #if defined(CONFIG_OF_LIBFDT) 22 #if defined(CONFIG_OF_LIBFDT)
23 #include <libfdt.h> 23 #include <libfdt.h>
24 #include <fdt_support.h> 24 #include <fdt_support.h>
25 #endif 25 #endif
26 26
27 #ifdef CONFIG_SYS_INIT_RAM_LOCK 27 #ifdef CONFIG_SYS_INIT_RAM_LOCK
28 #include <asm/cache.h> 28 #include <asm/cache.h>
29 #endif 29 #endif
30 30
31 DECLARE_GLOBAL_DATA_PTR; 31 DECLARE_GLOBAL_DATA_PTR;
32 32
33 static ulong get_sp (void); 33 static ulong get_sp (void);
34 extern void ft_fixup_num_cores(void *blob); 34 extern void ft_fixup_num_cores(void *blob);
35 static void set_clocks_in_mhz (bd_t *kbd); 35 static void set_clocks_in_mhz (bd_t *kbd);
36 36
37 #ifndef CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE 37 #ifndef CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE
38 #define CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE (768*1024*1024) 38 #define CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE (768*1024*1024)
39 #endif 39 #endif
40 40
41 static void boot_jump_linux(bootm_headers_t *images) 41 static void boot_jump_linux(bootm_headers_t *images)
42 { 42 {
43 void (*kernel)(bd_t *, ulong r4, ulong r5, ulong r6, 43 void (*kernel)(bd_t *, ulong r4, ulong r5, ulong r6,
44 ulong r7, ulong r8, ulong r9); 44 ulong r7, ulong r8, ulong r9);
45 #ifdef CONFIG_OF_LIBFDT 45 #ifdef CONFIG_OF_LIBFDT
46 char *of_flat_tree = images->ft_addr; 46 char *of_flat_tree = images->ft_addr;
47 #endif 47 #endif
48 48
49 kernel = (void (*)(bd_t *, ulong, ulong, ulong, 49 kernel = (void (*)(bd_t *, ulong, ulong, ulong,
50 ulong, ulong, ulong))images->ep; 50 ulong, ulong, ulong))images->ep;
51 debug ("## Transferring control to Linux (at address %08lx) ...\n", 51 debug ("## Transferring control to Linux (at address %08lx) ...\n",
52 (ulong)kernel); 52 (ulong)kernel);
53 53
54 bootstage_mark(BOOTSTAGE_ID_RUN_OS); 54 bootstage_mark(BOOTSTAGE_ID_RUN_OS);
55 55
56 #ifdef CONFIG_BOOTSTAGE_FDT
57 bootstage_fdt_add_report();
58 #endif
59 #ifdef CONFIG_BOOTSTAGE_REPORT
60 bootstage_report();
61 #endif
62
56 #if defined(CONFIG_SYS_INIT_RAM_LOCK) && !defined(CONFIG_E500) 63 #if defined(CONFIG_SYS_INIT_RAM_LOCK) && !defined(CONFIG_E500)
57 unlock_ram_in_cache(); 64 unlock_ram_in_cache();
58 #endif 65 #endif
59 66
60 #if defined(CONFIG_OF_LIBFDT) 67 #if defined(CONFIG_OF_LIBFDT)
61 if (of_flat_tree) { /* device tree; boot new style */ 68 if (of_flat_tree) { /* device tree; boot new style */
62 /* 69 /*
63 * Linux Kernel Parameters (passing device tree): 70 * Linux Kernel Parameters (passing device tree):
64 * r3: pointer to the fdt 71 * r3: pointer to the fdt
65 * r4: 0 72 * r4: 0
66 * r5: 0 73 * r5: 0
67 * r6: epapr magic 74 * r6: epapr magic
68 * r7: size of IMA in bytes 75 * r7: size of IMA in bytes
69 * r8: 0 76 * r8: 0
70 * r9: 0 77 * r9: 0
71 */ 78 */
72 debug (" Booting using OF flat tree...\n"); 79 debug (" Booting using OF flat tree...\n");
73 WATCHDOG_RESET (); 80 WATCHDOG_RESET ();
74 (*kernel) ((bd_t *)of_flat_tree, 0, 0, EPAPR_MAGIC, 81 (*kernel) ((bd_t *)of_flat_tree, 0, 0, EPAPR_MAGIC,
75 getenv_bootm_mapsize(), 0, 0); 82 getenv_bootm_mapsize(), 0, 0);
76 /* does not return */ 83 /* does not return */
77 } else 84 } else
78 #endif 85 #endif
79 { 86 {
80 /* 87 /*
81 * Linux Kernel Parameters (passing board info data): 88 * Linux Kernel Parameters (passing board info data):
82 * r3: ptr to board info data 89 * r3: ptr to board info data
83 * r4: initrd_start or 0 if no initrd 90 * r4: initrd_start or 0 if no initrd
84 * r5: initrd_end - unused if r4 is 0 91 * r5: initrd_end - unused if r4 is 0
85 * r6: Start of command line string 92 * r6: Start of command line string
86 * r7: End of command line string 93 * r7: End of command line string
87 * r8: 0 94 * r8: 0
88 * r9: 0 95 * r9: 0
89 */ 96 */
90 ulong cmd_start = images->cmdline_start; 97 ulong cmd_start = images->cmdline_start;
91 ulong cmd_end = images->cmdline_end; 98 ulong cmd_end = images->cmdline_end;
92 ulong initrd_start = images->initrd_start; 99 ulong initrd_start = images->initrd_start;
93 ulong initrd_end = images->initrd_end; 100 ulong initrd_end = images->initrd_end;
94 bd_t *kbd = images->kbd; 101 bd_t *kbd = images->kbd;
95 102
96 debug (" Booting using board info...\n"); 103 debug (" Booting using board info...\n");
97 WATCHDOG_RESET (); 104 WATCHDOG_RESET ();
98 (*kernel) (kbd, initrd_start, initrd_end, 105 (*kernel) (kbd, initrd_start, initrd_end,
99 cmd_start, cmd_end, 0, 0); 106 cmd_start, cmd_end, 0, 0);
100 /* does not return */ 107 /* does not return */
101 } 108 }
102 return ; 109 return ;
103 } 110 }
104 111
105 void arch_lmb_reserve(struct lmb *lmb) 112 void arch_lmb_reserve(struct lmb *lmb)
106 { 113 {
107 phys_size_t bootm_size; 114 phys_size_t bootm_size;
108 ulong size, sp, bootmap_base; 115 ulong size, sp, bootmap_base;
109 116
110 bootmap_base = getenv_bootm_low(); 117 bootmap_base = getenv_bootm_low();
111 bootm_size = getenv_bootm_size(); 118 bootm_size = getenv_bootm_size();
112 119
113 #ifdef DEBUG 120 #ifdef DEBUG
114 if (((u64)bootmap_base + bootm_size) > 121 if (((u64)bootmap_base + bootm_size) >
115 (CONFIG_SYS_SDRAM_BASE + (u64)gd->ram_size)) 122 (CONFIG_SYS_SDRAM_BASE + (u64)gd->ram_size))
116 puts("WARNING: bootm_low + bootm_size exceed total memory\n"); 123 puts("WARNING: bootm_low + bootm_size exceed total memory\n");
117 if ((bootmap_base + bootm_size) > get_effective_memsize()) 124 if ((bootmap_base + bootm_size) > get_effective_memsize())
118 puts("WARNING: bootm_low + bootm_size exceed eff. memory\n"); 125 puts("WARNING: bootm_low + bootm_size exceed eff. memory\n");
119 #endif 126 #endif
120 127
121 size = min(bootm_size, get_effective_memsize()); 128 size = min(bootm_size, get_effective_memsize());
122 size = min(size, CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE); 129 size = min(size, CONFIG_SYS_LINUX_LOWMEM_MAX_SIZE);
123 130
124 if (size < bootm_size) { 131 if (size < bootm_size) {
125 ulong base = bootmap_base + size; 132 ulong base = bootmap_base + size;
126 printf("WARNING: adjusting available memory to %lx\n", size); 133 printf("WARNING: adjusting available memory to %lx\n", size);
127 lmb_reserve(lmb, base, bootm_size - size); 134 lmb_reserve(lmb, base, bootm_size - size);
128 } 135 }
129 136
130 /* 137 /*
131 * Booting a (Linux) kernel image 138 * Booting a (Linux) kernel image
132 * 139 *
133 * Allocate space for command line and board info - the 140 * Allocate space for command line and board info - the
134 * address should be as high as possible within the reach of 141 * address should be as high as possible within the reach of
135 * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused 142 * the kernel (see CONFIG_SYS_BOOTMAPSZ settings), but in unused
136 * memory, which means far enough below the current stack 143 * memory, which means far enough below the current stack
137 * pointer. 144 * pointer.
138 */ 145 */
139 sp = get_sp(); 146 sp = get_sp();
140 debug ("## Current stack ends at 0x%08lx\n", sp); 147 debug ("## Current stack ends at 0x%08lx\n", sp);
141 148
142 /* adjust sp by 4K to be safe */ 149 /* adjust sp by 4K to be safe */
143 sp -= 4096; 150 sp -= 4096;
144 lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - sp)); 151 lmb_reserve(lmb, sp, (CONFIG_SYS_SDRAM_BASE + get_effective_memsize() - sp));
145 152
146 #ifdef CONFIG_MP 153 #ifdef CONFIG_MP
147 cpu_mp_lmb_reserve(lmb); 154 cpu_mp_lmb_reserve(lmb);
148 #endif 155 #endif
149 156
150 return ; 157 return ;
151 } 158 }
152 159
153 static void boot_prep_linux(bootm_headers_t *images) 160 static void boot_prep_linux(bootm_headers_t *images)
154 { 161 {
155 #ifdef CONFIG_MP 162 #ifdef CONFIG_MP
156 /* 163 /*
157 * if we are MP make sure to flush the device tree so any changes are 164 * if we are MP make sure to flush the device tree so any changes are
158 * made visibile to all other cores. In AMP boot scenarios the cores 165 * made visibile to all other cores. In AMP boot scenarios the cores
159 * might not be HW cache coherent with each other. 166 * might not be HW cache coherent with each other.
160 */ 167 */
161 flush_cache((unsigned long)images->ft_addr, images->ft_len); 168 flush_cache((unsigned long)images->ft_addr, images->ft_len);
162 #endif 169 #endif
163 } 170 }
164 171
165 static int boot_cmdline_linux(bootm_headers_t *images) 172 static int boot_cmdline_linux(bootm_headers_t *images)
166 { 173 {
167 ulong of_size = images->ft_len; 174 ulong of_size = images->ft_len;
168 struct lmb *lmb = &images->lmb; 175 struct lmb *lmb = &images->lmb;
169 ulong *cmd_start = &images->cmdline_start; 176 ulong *cmd_start = &images->cmdline_start;
170 ulong *cmd_end = &images->cmdline_end; 177 ulong *cmd_end = &images->cmdline_end;
171 178
172 int ret = 0; 179 int ret = 0;
173 180
174 if (!of_size) { 181 if (!of_size) {
175 /* allocate space and init command line */ 182 /* allocate space and init command line */
176 ret = boot_get_cmdline (lmb, cmd_start, cmd_end); 183 ret = boot_get_cmdline (lmb, cmd_start, cmd_end);
177 if (ret) { 184 if (ret) {
178 puts("ERROR with allocation of cmdline\n"); 185 puts("ERROR with allocation of cmdline\n");
179 return ret; 186 return ret;
180 } 187 }
181 } 188 }
182 189
183 return ret; 190 return ret;
184 } 191 }
185 192
186 static int boot_bd_t_linux(bootm_headers_t *images) 193 static int boot_bd_t_linux(bootm_headers_t *images)
187 { 194 {
188 ulong of_size = images->ft_len; 195 ulong of_size = images->ft_len;
189 struct lmb *lmb = &images->lmb; 196 struct lmb *lmb = &images->lmb;
190 bd_t **kbd = &images->kbd; 197 bd_t **kbd = &images->kbd;
191 198
192 int ret = 0; 199 int ret = 0;
193 200
194 if (!of_size) { 201 if (!of_size) {
195 /* allocate space for kernel copy of board info */ 202 /* allocate space for kernel copy of board info */
196 ret = boot_get_kbd (lmb, kbd); 203 ret = boot_get_kbd (lmb, kbd);
197 if (ret) { 204 if (ret) {
198 puts("ERROR with allocation of kernel bd\n"); 205 puts("ERROR with allocation of kernel bd\n");
199 return ret; 206 return ret;
200 } 207 }
201 set_clocks_in_mhz(*kbd); 208 set_clocks_in_mhz(*kbd);
202 } 209 }
203 210
204 return ret; 211 return ret;
205 } 212 }
206 213
207 static int boot_body_linux(bootm_headers_t *images) 214 static int boot_body_linux(bootm_headers_t *images)
208 { 215 {
209 int ret; 216 int ret;
210 217
211 /* allocate space for kernel copy of board info */ 218 /* allocate space for kernel copy of board info */
212 ret = boot_bd_t_linux(images); 219 ret = boot_bd_t_linux(images);
213 if (ret) 220 if (ret)
214 return ret; 221 return ret;
215 222
216 ret = image_setup_linux(images); 223 ret = image_setup_linux(images);
217 if (ret) 224 if (ret)
218 return ret; 225 return ret;
219 226
220 return 0; 227 return 0;
221 } 228 }
222 229
223 noinline 230 noinline
224 int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images) 231 int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
225 { 232 {
226 int ret; 233 int ret;
227 234
228 if (flag & BOOTM_STATE_OS_CMDLINE) { 235 if (flag & BOOTM_STATE_OS_CMDLINE) {
229 boot_cmdline_linux(images); 236 boot_cmdline_linux(images);
230 return 0; 237 return 0;
231 } 238 }
232 239
233 if (flag & BOOTM_STATE_OS_BD_T) { 240 if (flag & BOOTM_STATE_OS_BD_T) {
234 boot_bd_t_linux(images); 241 boot_bd_t_linux(images);
235 return 0; 242 return 0;
236 } 243 }
237 244
238 if (flag & BOOTM_STATE_OS_PREP) { 245 if (flag & BOOTM_STATE_OS_PREP) {
239 boot_prep_linux(images); 246 boot_prep_linux(images);
240 return 0; 247 return 0;
241 } 248 }
242 249
243 boot_prep_linux(images); 250 boot_prep_linux(images);
244 ret = boot_body_linux(images); 251 ret = boot_body_linux(images);
245 if (ret) 252 if (ret)
246 return ret; 253 return ret;
247 boot_jump_linux(images); 254 boot_jump_linux(images);
248 255
249 return 0; 256 return 0;
250 } 257 }
251 258
252 static ulong get_sp (void) 259 static ulong get_sp (void)
253 { 260 {
254 ulong sp; 261 ulong sp;
255 262
256 asm( "mr %0,1": "=r"(sp) : ); 263 asm( "mr %0,1": "=r"(sp) : );
257 return sp; 264 return sp;
258 } 265 }
259 266
260 static void set_clocks_in_mhz (bd_t *kbd) 267 static void set_clocks_in_mhz (bd_t *kbd)
261 { 268 {
262 char *s; 269 char *s;
263 270
264 if ((s = getenv ("clocks_in_mhz")) != NULL) { 271 if ((s = getenv ("clocks_in_mhz")) != NULL) {
265 /* convert all clock information to MHz */ 272 /* convert all clock information to MHz */
266 kbd->bi_intfreq /= 1000000L; 273 kbd->bi_intfreq /= 1000000L;
267 kbd->bi_busfreq /= 1000000L; 274 kbd->bi_busfreq /= 1000000L;
268 #if defined(CONFIG_CPM2) 275 #if defined(CONFIG_CPM2)
269 kbd->bi_cpmfreq /= 1000000L; 276 kbd->bi_cpmfreq /= 1000000L;
270 kbd->bi_brgfreq /= 1000000L; 277 kbd->bi_brgfreq /= 1000000L;
271 kbd->bi_sccfreq /= 1000000L; 278 kbd->bi_sccfreq /= 1000000L;
272 kbd->bi_vco /= 1000000L; 279 kbd->bi_vco /= 1000000L;
273 #endif 280 #endif
274 #if defined(CONFIG_MPC5xxx) 281 #if defined(CONFIG_MPC5xxx)
275 kbd->bi_ipbfreq /= 1000000L; 282 kbd->bi_ipbfreq /= 1000000L;
276 kbd->bi_pcifreq /= 1000000L; 283 kbd->bi_pcifreq /= 1000000L;
277 #endif /* CONFIG_MPC5xxx */ 284 #endif /* CONFIG_MPC5xxx */
278 } 285 }
279 } 286 }
280 287
281 #if defined(CONFIG_BOOTM_VXWORKS) 288 #if defined(CONFIG_BOOTM_VXWORKS)
282 void boot_prep_vxworks(bootm_headers_t *images) 289 void boot_prep_vxworks(bootm_headers_t *images)
283 { 290 {
284 #if defined(CONFIG_OF_LIBFDT) 291 #if defined(CONFIG_OF_LIBFDT)
285 int off; 292 int off;
286 u64 base, size; 293 u64 base, size;
287 294
288 if (!images->ft_addr) 295 if (!images->ft_addr)
289 return; 296 return;
290 297
291 base = (u64)gd->bd->bi_memstart; 298 base = (u64)gd->bd->bi_memstart;
292 size = (u64)gd->bd->bi_memsize; 299 size = (u64)gd->bd->bi_memsize;
293 300
294 off = fdt_path_offset(images->ft_addr, "/memory"); 301 off = fdt_path_offset(images->ft_addr, "/memory");
295 if (off < 0) 302 if (off < 0)
296 fdt_fixup_memory(images->ft_addr, base, size); 303 fdt_fixup_memory(images->ft_addr, base, size);
297 304
298 #if defined(CONFIG_MP) 305 #if defined(CONFIG_MP)
299 #if defined(CONFIG_MPC85xx) 306 #if defined(CONFIG_MPC85xx)
300 ft_fixup_cpu(images->ft_addr, base + size); 307 ft_fixup_cpu(images->ft_addr, base + size);
301 ft_fixup_num_cores(images->ft_addr); 308 ft_fixup_num_cores(images->ft_addr);
302 #elif defined(CONFIG_MPC86xx) 309 #elif defined(CONFIG_MPC86xx)
303 off = fdt_add_mem_rsv(images->ft_addr, 310 off = fdt_add_mem_rsv(images->ft_addr,
304 determine_mp_bootpg(NULL), (u64)4096); 311 determine_mp_bootpg(NULL), (u64)4096);
305 if (off < 0) 312 if (off < 0)
306 printf("## WARNING %s: %s\n", __func__, fdt_strerror(off)); 313 printf("## WARNING %s: %s\n", __func__, fdt_strerror(off));
307 ft_fixup_num_cores(images->ft_addr); 314 ft_fixup_num_cores(images->ft_addr);
308 #endif 315 #endif
309 flush_cache((unsigned long)images->ft_addr, images->ft_len); 316 flush_cache((unsigned long)images->ft_addr, images->ft_len);
310 #endif 317 #endif
311 #endif 318 #endif
312 } 319 }
313 320
314 void boot_jump_vxworks(bootm_headers_t *images) 321 void boot_jump_vxworks(bootm_headers_t *images)
315 { 322 {
316 /* PowerPC VxWorks boot interface conforms to the ePAPR standard 323 /* PowerPC VxWorks boot interface conforms to the ePAPR standard
317 * general purpuse registers: 324 * general purpuse registers:
318 * 325 *
319 * r3: Effective address of the device tree image 326 * r3: Effective address of the device tree image
320 * r4: 0 327 * r4: 0
321 * r5: 0 328 * r5: 0
322 * r6: ePAPR magic value 329 * r6: ePAPR magic value
323 * r7: shall be the size of the boot IMA in bytes 330 * r7: shall be the size of the boot IMA in bytes
324 * r8: 0 331 * r8: 0
325 * r9: 0 332 * r9: 0
326 * TCR: WRC = 0, no watchdog timer reset will occur 333 * TCR: WRC = 0, no watchdog timer reset will occur
327 */ 334 */
328 WATCHDOG_RESET(); 335 WATCHDOG_RESET();
329 336
330 ((void (*)(void *, ulong, ulong, ulong, 337 ((void (*)(void *, ulong, ulong, ulong,
331 ulong, ulong, ulong))images->ep)(images->ft_addr, 338 ulong, ulong, ulong))images->ep)(images->ft_addr,
332 0, 0, EPAPR_MAGIC, getenv_bootm_mapsize(), 0, 0); 339 0, 0, EPAPR_MAGIC, getenv_bootm_mapsize(), 0, 0);
333 } 340 }
334 #endif 341 #endif
335 342
board/freescale/b4860qds/b4860qds.c
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <command.h> 8 #include <command.h>
9 #include <i2c.h> 9 #include <i2c.h>
10 #include <netdev.h> 10 #include <netdev.h>
11 #include <linux/compiler.h> 11 #include <linux/compiler.h>
12 #include <asm/mmu.h> 12 #include <asm/mmu.h>
13 #include <asm/processor.h> 13 #include <asm/processor.h>
14 #include <asm/errno.h>
14 #include <asm/cache.h> 15 #include <asm/cache.h>
15 #include <asm/immap_85xx.h> 16 #include <asm/immap_85xx.h>
16 #include <asm/fsl_law.h> 17 #include <asm/fsl_law.h>
17 #include <asm/fsl_serdes.h> 18 #include <asm/fsl_serdes.h>
18 #include <asm/fsl_portals.h> 19 #include <asm/fsl_portals.h>
19 #include <asm/fsl_liodn.h> 20 #include <asm/fsl_liodn.h>
20 #include <fm_eth.h> 21 #include <fm_eth.h>
21 22
22 #include "../common/qixis.h" 23 #include "../common/qixis.h"
23 #include "../common/vsc3316_3308.h" 24 #include "../common/vsc3316_3308.h"
24 #include "../common/idt8t49n222a_serdes_clk.h" 25 #include "../common/idt8t49n222a_serdes_clk.h"
25 #include "b4860qds.h" 26 #include "b4860qds.h"
26 #include "b4860qds_qixis.h" 27 #include "b4860qds_qixis.h"
27 #include "b4860qds_crossbar_con.h" 28 #include "b4860qds_crossbar_con.h"
28 29
29 #define CLK_MUX_SEL_MASK 0x4 30 #define CLK_MUX_SEL_MASK 0x4
30 #define ETH_PHY_CLK_OUT 0x4 31 #define ETH_PHY_CLK_OUT 0x4
31 #define PLL_NUM 2
32 32
33 DECLARE_GLOBAL_DATA_PTR; 33 DECLARE_GLOBAL_DATA_PTR;
34 34
35 int checkboard(void) 35 int checkboard(void)
36 { 36 {
37 char buf[64]; 37 char buf[64];
38 u8 sw; 38 u8 sw;
39 struct cpu_type *cpu = gd->arch.cpu; 39 struct cpu_type *cpu = gd->arch.cpu;
40 static const char *const freq[] = {"100", "125", "156.25", "161.13", 40 static const char *const freq[] = {"100", "125", "156.25", "161.13",
41 "122.88", "122.88", "122.88"}; 41 "122.88", "122.88", "122.88"};
42 int clock; 42 int clock;
43 43
44 printf("Board: %sQDS, ", cpu->name); 44 printf("Board: %sQDS, ", cpu->name);
45 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", 45 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
46 QIXIS_READ(id), QIXIS_READ(arch)); 46 QIXIS_READ(id), QIXIS_READ(arch));
47 47
48 sw = QIXIS_READ(brdcfg[0]); 48 sw = QIXIS_READ(brdcfg[0]);
49 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; 49 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
50 50
51 if (sw < 0x8) 51 if (sw < 0x8)
52 printf("vBank: %d\n", sw); 52 printf("vBank: %d\n", sw);
53 else if (sw >= 0x8 && sw <= 0xE) 53 else if (sw >= 0x8 && sw <= 0xE)
54 puts("NAND\n"); 54 puts("NAND\n");
55 else 55 else
56 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); 56 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
57 57
58 printf("FPGA: v%d (%s), build %d", 58 printf("FPGA: v%d (%s), build %d",
59 (int)QIXIS_READ(scver), qixis_read_tag(buf), 59 (int)QIXIS_READ(scver), qixis_read_tag(buf),
60 (int)qixis_read_minor()); 60 (int)qixis_read_minor());
61 /* the timestamp string contains "\n" at the end */ 61 /* the timestamp string contains "\n" at the end */
62 printf(" on %s", qixis_read_time(buf)); 62 printf(" on %s", qixis_read_time(buf));
63 63
64 /* 64 /*
65 * Display the actual SERDES reference clocks as configured by the 65 * Display the actual SERDES reference clocks as configured by the
66 * dip switches on the board. Note that the SWx registers could 66 * dip switches on the board. Note that the SWx registers could
67 * technically be set to force the reference clocks to match the 67 * technically be set to force the reference clocks to match the
68 * values that the SERDES expects (or vice versa). For now, however, 68 * values that the SERDES expects (or vice versa). For now, however,
69 * we just display both values and hope the user notices when they 69 * we just display both values and hope the user notices when they
70 * don't match. 70 * don't match.
71 */ 71 */
72 puts("SERDES Reference Clocks: "); 72 puts("SERDES Reference Clocks: ");
73 sw = QIXIS_READ(brdcfg[2]); 73 sw = QIXIS_READ(brdcfg[2]);
74 clock = (sw >> 5) & 7; 74 clock = (sw >> 5) & 7;
75 printf("Bank1=%sMHz ", freq[clock]); 75 printf("Bank1=%sMHz ", freq[clock]);
76 sw = QIXIS_READ(brdcfg[4]); 76 sw = QIXIS_READ(brdcfg[4]);
77 clock = (sw >> 6) & 3; 77 clock = (sw >> 6) & 3;
78 printf("Bank2=%sMHz\n", freq[clock]); 78 printf("Bank2=%sMHz\n", freq[clock]);
79 79
80 return 0; 80 return 0;
81 } 81 }
82 82
83 int select_i2c_ch_pca(u8 ch) 83 int select_i2c_ch_pca(u8 ch)
84 { 84 {
85 int ret; 85 int ret;
86 86
87 /* Selecting proper channel via PCA*/ 87 /* Selecting proper channel via PCA*/
88 ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1); 88 ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
89 if (ret) { 89 if (ret) {
90 printf("PCA: failed to select proper channel.\n"); 90 printf("PCA: failed to select proper channel.\n");
91 return ret; 91 return ret;
92 } 92 }
93 93
94 return 0; 94 return 0;
95 } 95 }
96 96
97 int configure_vsc3316_3308(void) 97 int configure_vsc3316_3308(void)
98 { 98 {
99 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 99 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
100 unsigned int num_vsc16_con, num_vsc08_con; 100 unsigned int num_vsc16_con, num_vsc08_con;
101 u32 serdes1_prtcl, serdes2_prtcl; 101 u32 serdes1_prtcl, serdes2_prtcl;
102 int ret; 102 int ret;
103 103
104 serdes1_prtcl = in_be32(&gur->rcwsr[4]) & 104 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
105 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 105 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
106 if (!serdes1_prtcl) { 106 if (!serdes1_prtcl) {
107 printf("SERDES1 is not enabled\n"); 107 printf("SERDES1 is not enabled\n");
108 return 0; 108 return 0;
109 } 109 }
110 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 110 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
111 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); 111 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
112 112
113 serdes2_prtcl = in_be32(&gur->rcwsr[4]) & 113 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
114 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 114 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
115 if (!serdes2_prtcl) { 115 if (!serdes2_prtcl) {
116 printf("SERDES2 is not enabled\n"); 116 printf("SERDES2 is not enabled\n");
117 return 0; 117 return 0;
118 } 118 }
119 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 119 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
120 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); 120 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
121 121
122 switch (serdes1_prtcl) { 122 switch (serdes1_prtcl) {
123 case 0x29:
123 case 0x2a: 124 case 0x2a:
124 case 0x2C: 125 case 0x2C:
125 case 0x2D: 126 case 0x2D:
126 case 0x2E: 127 case 0x2E:
127 /* 128 /*
128 * Configuration: 129 * Configuration:
129 * SERDES: 1 130 * SERDES: 1
130 * Lanes: A,B: SGMII 131 * Lanes: A,B: SGMII
131 * Lanes: C,D,E,F,G,H: CPRI 132 * Lanes: C,D,E,F,G,H: CPRI
132 */ 133 */
133 debug("Configuring crossbar to use onboard SGMII PHYs:" 134 debug("Configuring crossbar to use onboard SGMII PHYs:"
134 "srds_prctl:%x\n", serdes1_prtcl); 135 "srds_prctl:%x\n", serdes1_prtcl);
135 num_vsc16_con = NUM_CON_VSC3316; 136 num_vsc16_con = NUM_CON_VSC3316;
136 /* Configure VSC3316 crossbar switch */ 137 /* Configure VSC3316 crossbar switch */
137 ret = select_i2c_ch_pca(I2C_CH_VSC3316); 138 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
138 if (!ret) { 139 if (!ret) {
139 ret = vsc3316_config(VSC3316_TX_ADDRESS, 140 ret = vsc3316_config(VSC3316_TX_ADDRESS,
140 vsc16_tx_4sfp_sgmii_12_56, 141 vsc16_tx_4sfp_sgmii_12_56,
141 num_vsc16_con); 142 num_vsc16_con);
142 if (ret) 143 if (ret)
143 return ret; 144 return ret;
144 ret = vsc3316_config(VSC3316_RX_ADDRESS, 145 ret = vsc3316_config(VSC3316_RX_ADDRESS,
145 vsc16_rx_4sfp_sgmii_12_56, 146 vsc16_rx_4sfp_sgmii_12_56,
146 num_vsc16_con); 147 num_vsc16_con);
147 if (ret) 148 if (ret)
148 return ret; 149 return ret;
149 } else { 150 } else {
150 return ret; 151 return ret;
151 } 152 }
152 break; 153 break;
153 154
155 case 0x02:
156 case 0x04:
157 case 0x05:
158 case 0x06:
159 case 0x08:
160 case 0x09:
161 case 0x0A:
162 case 0x0B:
163 case 0x0C:
164 case 0x30:
165 case 0x32:
166 case 0x33:
167 case 0x34:
168 case 0x39:
169 case 0x3A:
170 case 0x3C:
171 case 0x3D:
172 case 0x5C:
173 case 0x5D:
174 /*
175 * Configuration:
176 * SERDES: 1
177 * Lanes: A,B: AURORA
178 * Lanes: C,d: SGMII
179 * Lanes: E,F,G,H: CPRI
180 */
181 debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
182 " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
183 num_vsc16_con = NUM_CON_VSC3316;
184 /* Configure VSC3316 crossbar switch */
185 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
186 if (!ret) {
187 ret = vsc3316_config(VSC3316_TX_ADDRESS,
188 vsc16_tx_sfp_sgmii_aurora,
189 num_vsc16_con);
190 if (ret)
191 return ret;
192 ret = vsc3316_config(VSC3316_RX_ADDRESS,
193 vsc16_rx_sfp_sgmii_aurora,
194 num_vsc16_con);
195 if (ret)
196 return ret;
197 } else {
198 return ret;
199 }
200 break;
201
154 #ifdef CONFIG_PPC_B4420 202 #ifdef CONFIG_PPC_B4420
203 case 0x17:
155 case 0x18: 204 case 0x18:
156 /* 205 /*
157 * Configuration: 206 * Configuration:
158 * SERDES: 1 207 * SERDES: 1
159 * Lanes: A,B,C,D: SGMII 208 * Lanes: A,B,C,D: SGMII
160 * Lanes: E,F,G,H: CPRI 209 * Lanes: E,F,G,H: CPRI
161 */ 210 */
162 debug("Configuring crossbar to use onboard SGMII PHYs:" 211 debug("Configuring crossbar to use onboard SGMII PHYs:"
163 "srds_prctl:%x\n", serdes1_prtcl); 212 "srds_prctl:%x\n", serdes1_prtcl);
164 num_vsc16_con = NUM_CON_VSC3316; 213 num_vsc16_con = NUM_CON_VSC3316;
165 /* Configure VSC3316 crossbar switch */ 214 /* Configure VSC3316 crossbar switch */
166 ret = select_i2c_ch_pca(I2C_CH_VSC3316); 215 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
167 if (!ret) { 216 if (!ret) {
168 ret = vsc3316_config(VSC3316_TX_ADDRESS, 217 ret = vsc3316_config(VSC3316_TX_ADDRESS,
169 vsc16_tx_sgmii_lane_cd, num_vsc16_con); 218 vsc16_tx_sgmii_lane_cd, num_vsc16_con);
170 if (ret) 219 if (ret)
171 return ret; 220 return ret;
172 ret = vsc3316_config(VSC3316_RX_ADDRESS, 221 ret = vsc3316_config(VSC3316_RX_ADDRESS,
173 vsc16_rx_sgmii_lane_cd, num_vsc16_con); 222 vsc16_rx_sgmii_lane_cd, num_vsc16_con);
174 if (ret) 223 if (ret)
175 return ret; 224 return ret;
176 } else { 225 } else {
177 return ret; 226 return ret;
178 } 227 }
179 break; 228 break;
180 #endif 229 #endif
181 230
182 case 0x3E: 231 case 0x3E:
183 case 0x0D: 232 case 0x0D:
184 case 0x0E: 233 case 0x0E:
185 case 0x12: 234 case 0x12:
186 num_vsc16_con = NUM_CON_VSC3316; 235 num_vsc16_con = NUM_CON_VSC3316;
187 /* Configure VSC3316 crossbar switch */ 236 /* Configure VSC3316 crossbar switch */
188 ret = select_i2c_ch_pca(I2C_CH_VSC3316); 237 ret = select_i2c_ch_pca(I2C_CH_VSC3316);
189 if (!ret) { 238 if (!ret) {
190 ret = vsc3316_config(VSC3316_TX_ADDRESS, 239 ret = vsc3316_config(VSC3316_TX_ADDRESS,
191 vsc16_tx_sfp, num_vsc16_con); 240 vsc16_tx_sfp, num_vsc16_con);
192 if (ret) 241 if (ret)
193 return ret; 242 return ret;
194 ret = vsc3316_config(VSC3316_RX_ADDRESS, 243 ret = vsc3316_config(VSC3316_RX_ADDRESS,
195 vsc16_rx_sfp, num_vsc16_con); 244 vsc16_rx_sfp, num_vsc16_con);
196 if (ret) 245 if (ret)
197 return ret; 246 return ret;
198 } else { 247 } else {
199 return ret; 248 return ret;
200 } 249 }
201 break; 250 break;
202 default: 251 default:
203 printf("WARNING:VSC crossbars programming not supported for:%x" 252 printf("WARNING:VSC crossbars programming not supported for:%x"
204 " SerDes1 Protocol.\n", serdes1_prtcl); 253 " SerDes1 Protocol.\n", serdes1_prtcl);
205 return -1; 254 return -1;
206 } 255 }
207 256
208 switch (serdes2_prtcl) { 257 switch (serdes2_prtcl) {
209 case 0x9E: 258 case 0x9E:
210 case 0x9A: 259 case 0x9A:
211 case 0x98: 260 case 0x98:
212 case 0xb2: 261 case 0xb2:
213 case 0x49: 262 case 0x49:
214 case 0x4E: 263 case 0x4E:
215 case 0x8D: 264 case 0x8D:
216 case 0x7A: 265 case 0x7A:
217 num_vsc08_con = NUM_CON_VSC3308; 266 num_vsc08_con = NUM_CON_VSC3308;
218 /* Configure VSC3308 crossbar switch */ 267 /* Configure VSC3308 crossbar switch */
219 ret = select_i2c_ch_pca(I2C_CH_VSC3308); 268 ret = select_i2c_ch_pca(I2C_CH_VSC3308);
220 if (!ret) { 269 if (!ret) {
221 ret = vsc3308_config(VSC3308_TX_ADDRESS, 270 ret = vsc3308_config(VSC3308_TX_ADDRESS,
222 vsc08_tx_amc, num_vsc08_con); 271 vsc08_tx_amc, num_vsc08_con);
223 if (ret) 272 if (ret)
224 return ret; 273 return ret;
225 ret = vsc3308_config(VSC3308_RX_ADDRESS, 274 ret = vsc3308_config(VSC3308_RX_ADDRESS,
226 vsc08_rx_amc, num_vsc08_con); 275 vsc08_rx_amc, num_vsc08_con);
227 if (ret) 276 if (ret)
228 return ret; 277 return ret;
229 } else { 278 } else {
230 return ret; 279 return ret;
231 } 280 }
232 break; 281 break;
233 default: 282 default:
234 printf("WARNING:VSC crossbars programming not supported for: %x" 283 printf("WARNING:VSC crossbars programming not supported for: %x"
235 " SerDes2 Protocol.\n", serdes2_prtcl); 284 " SerDes2 Protocol.\n", serdes2_prtcl);
236 return -1; 285 return -1;
237 } 286 }
238 287
239 return 0; 288 return 0;
240 } 289 }
241 290
291 static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
292 {
293 u32 rst_err;
294
295 /* Steps For SerDes PLLs reset and reconfiguration
296 * or PLL power-up procedure
297 */
298 debug("CALIBRATE PLL:%d\n", pll_num);
299 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
300 SRDS_RSTCTL_SDRST_B);
301 udelay(10);
302 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
303 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
304 udelay(10);
305 setbits_be32(&srds_regs->bank[pll_num].rstctl,
306 SRDS_RSTCTL_RST);
307 setbits_be32(&srds_regs->bank[pll_num].rstctl,
308 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
309 | SRDS_RSTCTL_SDRST_B));
310
311 udelay(20);
312
313 /* Check whether PLL has been locked or not */
314 rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
315 SRDS_RSTCTL_RSTERR;
316 rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
317 debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
318 if (rst_err)
319 return rst_err;
320
321 return rst_err;
322 }
323
324 static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
325 {
326 int ret = 0;
327 u32 fcap, dcbias, bcap, pllcr1, pllcr0;
328
329 if (calibrate_pll(srds_regs, pll_num)) {
330 /* STEP 1 */
331 /* Read fcap, dcbias and bcap value */
332 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
333 SRDS_PLLCR0_DCBIAS_OUT_EN);
334 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
335 SRDS_PLLSR2_FCAP;
336 fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
337 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
338 SRDS_PLLSR2_BCAP_EN;
339 bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
340 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
341 SRDS_PLLCR0_DCBIAS_OUT_EN);
342 dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
343 SRDS_PLLSR2_DCBIAS;
344 dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
345 debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
346 bcap, fcap, dcbias);
347 if (fcap == 0 && bcap == 1) {
348 /* Step 3 */
349 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
350 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
351 | SRDS_RSTCTL_SDRST_B));
352 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
353 SRDS_PLLCR1_BCAP_EN);
354 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
355 SRDS_PLLCR1_BCAP_OVD);
356 if (calibrate_pll(srds_regs, pll_num)) {
357 /*save the fcap, dcbias and bcap values*/
358 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
359 SRDS_PLLCR0_DCBIAS_OUT_EN);
360 fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
361 & SRDS_PLLSR2_FCAP;
362 fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
363 bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
364 & SRDS_PLLSR2_BCAP_EN;
365 bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
366 setbits_be32(&srds_regs->bank[pll_num].pllcr0,
367 SRDS_PLLCR0_DCBIAS_OUT_EN);
368 dcbias = in_be32
369 (&srds_regs->bank[pll_num].pllsr2) &
370 SRDS_PLLSR2_DCBIAS;
371 dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
372
373 /* Step 4*/
374 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
375 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
376 | SRDS_RSTCTL_SDRST_B));
377 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
378 SRDS_PLLCR1_BYP_CAL);
379 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
380 SRDS_PLLCR1_BCAP_EN);
381 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
382 SRDS_PLLCR1_BCAP_OVD);
383 /* change the fcap and dcbias to the saved
384 * values from Step 3 */
385 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
386 SRDS_PLLCR1_PLL_FCAP);
387 pllcr1 = (in_be32
388 (&srds_regs->bank[pll_num].pllcr1)|
389 (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
390 out_be32(&srds_regs->bank[pll_num].pllcr1,
391 pllcr1);
392 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
393 SRDS_PLLCR0_DCBIAS_OVRD);
394 pllcr0 = (in_be32
395 (&srds_regs->bank[pll_num].pllcr0)|
396 (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
397 out_be32(&srds_regs->bank[pll_num].pllcr0,
398 pllcr0);
399 ret = calibrate_pll(srds_regs, pll_num);
400 if (ret)
401 return ret;
402 } else {
403 goto out;
404 }
405 } else { /* Step 5 */
406 clrbits_be32(&srds_regs->bank[pll_num].rstctl,
407 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
408 | SRDS_RSTCTL_SDRST_B));
409 udelay(10);
410 /* Change the fcap, dcbias, and bcap to the
411 * values from Step 1 */
412 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
413 SRDS_PLLCR1_BYP_CAL);
414 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
415 SRDS_PLLCR1_PLL_FCAP);
416 pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
417 (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
418 out_be32(&srds_regs->bank[pll_num].pllcr1,
419 pllcr1);
420 clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
421 SRDS_PLLCR0_DCBIAS_OVRD);
422 pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
423 (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
424 out_be32(&srds_regs->bank[pll_num].pllcr0,
425 pllcr0);
426 clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
427 SRDS_PLLCR1_BCAP_EN);
428 setbits_be32(&srds_regs->bank[pll_num].pllcr1,
429 SRDS_PLLCR1_BCAP_OVD);
430 ret = calibrate_pll(srds_regs, pll_num);
431 if (ret)
432 return ret;
433 }
434 }
435 out:
436 return 0;
437 }
438
439 static int check_serdes_pll_locks(void)
440 {
441 serdes_corenet_t *srds1_regs =
442 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
443 serdes_corenet_t *srds2_regs =
444 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
445 int i, ret1, ret2;
446
447 debug("\nSerDes1 Lock check\n");
448 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
449 ret1 = check_pll_locks(srds1_regs, i);
450 if (ret1) {
451 printf("SerDes1, PLL:%d didnt lock\n", i);
452 return ret1;
453 }
454 }
455 debug("\nSerDes2 Lock check\n");
456 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
457 ret2 = check_pll_locks(srds2_regs, i);
458 if (ret2) {
459 printf("SerDes2, PLL:%d didnt lock\n", i);
460 return ret2;
461 }
462 }
463
464 return 0;
465 }
466
242 int config_serdes1_refclks(void) 467 int config_serdes1_refclks(void)
243 { 468 {
244 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 469 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
245 serdes_corenet_t *srds_regs = 470 serdes_corenet_t *srds_regs =
246 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 471 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
247 u32 serdes1_prtcl, lane; 472 u32 serdes1_prtcl, lane;
248 unsigned int flag_sgmii_prtcl = 0; 473 unsigned int flag_sgmii_aurora_prtcl = 0;
249 int ret, i; 474 int i;
475 int ret = 0;
250 476
251 serdes1_prtcl = in_be32(&gur->rcwsr[4]) & 477 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
252 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 478 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
253 if (!serdes1_prtcl) { 479 if (!serdes1_prtcl) {
254 printf("SERDES1 is not enabled\n"); 480 printf("SERDES1 is not enabled\n");
255 return -1; 481 return -1;
256 } 482 }
257 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 483 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
258 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); 484 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
259 485
260 /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks 486 /* To prevent generation of reset request from SerDes
487 * while changing the refclks, By setting SRDS_RST_MSK bit,
488 * SerDes reset event cannot cause a reset request
261 */ 489 */
262 for (i = 0; i < PLL_NUM; i++) 490 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
263 clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST); 491
264 /* Reconfigure IDT idt8t49n222a device for CPRI to work 492 /* Reconfigure IDT idt8t49n222a device for CPRI to work
265 * For this SerDes1's Refclk1 and refclk2 need to be set 493 * For this SerDes1's Refclk1 and refclk2 need to be set
266 * to 122.88MHz 494 * to 122.88MHz
267 */ 495 */
268 switch (serdes1_prtcl) { 496 switch (serdes1_prtcl) {
269 case 0x2A: 497 case 0x2A:
270 case 0x2C: 498 case 0x2C:
271 case 0x2D: 499 case 0x2D:
272 case 0x2E: 500 case 0x2E:
501 case 0x02:
502 case 0x04:
503 case 0x05:
504 case 0x06:
505 case 0x08:
506 case 0x09:
507 case 0x0A:
508 case 0x0B:
509 case 0x0C:
510 case 0x30:
511 case 0x32:
512 case 0x33:
513 case 0x34:
514 case 0x39:
515 case 0x3A:
516 case 0x3C:
517 case 0x3D:
518 case 0x5C:
519 case 0x5D:
273 debug("Configuring idt8t49n222a for CPRI SerDes clks:" 520 debug("Configuring idt8t49n222a for CPRI SerDes clks:"
274 " for srds_prctl:%x\n", serdes1_prtcl); 521 " for srds_prctl:%x\n", serdes1_prtcl);
275 ret = select_i2c_ch_pca(I2C_CH_IDT); 522 ret = select_i2c_ch_pca(I2C_CH_IDT);
276 if (!ret) { 523 if (!ret) {
277 ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1, 524 ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
278 SERDES_REFCLK_122_88, 525 SERDES_REFCLK_122_88,
279 SERDES_REFCLK_122_88, 0); 526 SERDES_REFCLK_122_88, 0);
280 if (ret) { 527 if (ret) {
281 printf("IDT8T49N222A configuration failed.\n"); 528 printf("IDT8T49N222A configuration failed.\n");
282 return ret; 529 goto out;
283 } else 530 } else
284 printf("IDT8T49N222A configured.\n"); 531 debug("IDT8T49N222A configured.\n");
285 } else { 532 } else {
286 return ret; 533 goto out;
287 } 534 }
288 select_i2c_ch_pca(I2C_CH_DEFAULT); 535 select_i2c_ch_pca(I2C_CH_DEFAULT);
289 536
290 /* Change SerDes1's Refclk1 to 125MHz for on board 537 /* Change SerDes1's Refclk1 to 125MHz for on board
291 * SGMIIs to work 538 * SGMIIs or Aurora to work
292 */ 539 */
293 for (lane = 0; lane < SRDS_MAX_LANES; lane++) { 540 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
294 enum srds_prtcl lane_prtcl = serdes_get_prtcl 541 enum srds_prtcl lane_prtcl = serdes_get_prtcl
295 (0, serdes1_prtcl, lane); 542 (0, serdes1_prtcl, lane);
296 switch (lane_prtcl) { 543 switch (lane_prtcl) {
297 case SGMII_FM1_DTSEC1: 544 case SGMII_FM1_DTSEC1:
298 case SGMII_FM1_DTSEC2: 545 case SGMII_FM1_DTSEC2:
299 case SGMII_FM1_DTSEC3: 546 case SGMII_FM1_DTSEC3:
300 case SGMII_FM1_DTSEC4: 547 case SGMII_FM1_DTSEC4:
301 case SGMII_FM1_DTSEC5: 548 case SGMII_FM1_DTSEC5:
302 case SGMII_FM1_DTSEC6: 549 case SGMII_FM1_DTSEC6:
303 flag_sgmii_prtcl++; 550 case AURORA:
551 flag_sgmii_aurora_prtcl++;
304 break; 552 break;
305 default: 553 default:
306 break; 554 break;
307 } 555 }
308 } 556 }
309 557
310 if (flag_sgmii_prtcl) 558 if (flag_sgmii_aurora_prtcl)
311 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); 559 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
312 560
313 /* Steps For SerDes PLLs reset and reconfiguration after 561 /* Steps For SerDes PLLs reset and reconfiguration after
314 * changing SerDes's refclks 562 * changing SerDes's refclks
315 */ 563 */
316 for (i = 0; i < PLL_NUM; i++) { 564 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
317 debug("For PLL%d reset and reconfiguration after" 565 debug("For PLL%d reset and reconfiguration after"
318 " changing refclks\n", i+1); 566 " changing refclks\n", i+1);
319 clrbits_be32(&srds_regs->bank[i].rstctl, 567 clrbits_be32(&srds_regs->bank[i].rstctl,
320 SRDS_RSTCTL_SDRST_B); 568 SRDS_RSTCTL_SDRST_B);
321 udelay(10); 569 udelay(10);
322 clrbits_be32(&srds_regs->bank[i].rstctl, 570 clrbits_be32(&srds_regs->bank[i].rstctl,
323 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B)); 571 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
324 udelay(10); 572 udelay(10);
325 setbits_be32(&srds_regs->bank[i].rstctl, 573 setbits_be32(&srds_regs->bank[i].rstctl,
326 SRDS_RSTCTL_RST); 574 SRDS_RSTCTL_RST);
327 setbits_be32(&srds_regs->bank[i].rstctl, 575 setbits_be32(&srds_regs->bank[i].rstctl,
328 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B 576 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
329 | SRDS_RSTCTL_SDRST_B)); 577 | SRDS_RSTCTL_SDRST_B));
330 } 578 }
331 break; 579 break;
332 default: 580 default:
333 printf("WARNING:IDT8T49N222A configuration not" 581 printf("WARNING:IDT8T49N222A configuration not"
334 " supported for:%x SerDes1 Protocol.\n", 582 " supported for:%x SerDes1 Protocol.\n",
335 serdes1_prtcl); 583 serdes1_prtcl);
336 return -1;
337 } 584 }
338 585
339 return 0; 586 out:
587 /* Clearing SRDS_RST_MSK bit as now
588 * SerDes reset event can cause a reset request
589 */
590 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
591 return ret;
340 } 592 }
341 593
594 int config_serdes2_refclks(void)
595 {
596 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
597 serdes_corenet_t *srds2_regs =
598 (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
599 u32 serdes2_prtcl;
600 int ret = 0;
601 int i;
602
603 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
604 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
605 if (!serdes2_prtcl) {
606 debug("SERDES2 is not enabled\n");
607 return -ENODEV;
608 }
609 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
610 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
611
612 /* To prevent generation of reset request from SerDes
613 * while changing the refclks, By setting SRDS_RST_MSK bit,
614 * SerDes reset event cannot cause a reset request
615 */
616 setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
617
618 /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
619 * For this SerDes2's Refclk1 need to be set to 100MHz
620 */
621 switch (serdes2_prtcl) {
622 case 0x9E:
623 case 0x9A:
624 case 0xb2:
625 debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
626 serdes2_prtcl);
627 ret = select_i2c_ch_pca(I2C_CH_IDT);
628 if (!ret) {
629 ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
630 SERDES_REFCLK_100,
631 SERDES_REFCLK_156_25, 0);
632 if (ret) {
633 printf("IDT8T49N222A configuration failed.\n");
634 goto out;
635 } else
636 debug("IDT8T49N222A configured.\n");
637 } else {
638 goto out;
639 }
640 select_i2c_ch_pca(I2C_CH_DEFAULT);
641
642 /* Steps For SerDes PLLs reset and reconfiguration after
643 * changing SerDes's refclks
644 */
645 for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
646 clrbits_be32(&srds2_regs->bank[i].rstctl,
647 SRDS_RSTCTL_SDRST_B);
648 udelay(10);
649 clrbits_be32(&srds2_regs->bank[i].rstctl,
650 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
651 udelay(10);
652 setbits_be32(&srds2_regs->bank[i].rstctl,
653 SRDS_RSTCTL_RST);
654 setbits_be32(&srds2_regs->bank[i].rstctl,
655 (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
656 | SRDS_RSTCTL_SDRST_B));
657
658 udelay(10);
659 }
660 break;
661 default:
662 printf("IDT configuration not supported for:%x S2 Protocol.\n",
663 serdes2_prtcl);
664 }
665
666 out:
667 /* Clearing SRDS_RST_MSK bit as now
668 * SerDes reset event can cause a reset request
669 */
670 clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
671 return ret;
672 }
673
342 int board_early_init_r(void) 674 int board_early_init_r(void)
343 { 675 {
344 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; 676 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
345 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); 677 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
678 int ret;
346 679
347 /* 680 /*
348 * Remap Boot flash + PROMJET region to caching-inhibited 681 * Remap Boot flash + PROMJET region to caching-inhibited
349 * so that flash can be erased properly. 682 * so that flash can be erased properly.
350 */ 683 */
351 684
352 /* Flush d-cache and invalidate i-cache of any FLASH data */ 685 /* Flush d-cache and invalidate i-cache of any FLASH data */
353 flush_dcache(); 686 flush_dcache();
354 invalidate_icache(); 687 invalidate_icache();
355 688
356 /* invalidate existing TLB entry for flash + promjet */ 689 /* invalidate existing TLB entry for flash + promjet */
357 disable_tlb(flash_esel); 690 disable_tlb(flash_esel);
358 691
359 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, 692 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
360 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 693 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
361 0, flash_esel, BOOKE_PAGESZ_256M, 1); 694 0, flash_esel, BOOKE_PAGESZ_256M, 1);
362 695
363 set_liodns(); 696 set_liodns();
364 #ifdef CONFIG_SYS_DPAA_QBMAN 697 #ifdef CONFIG_SYS_DPAA_QBMAN
365 setup_portals(); 698 setup_portals();
366 #endif 699 #endif
367 /* SerDes1 refclks need to be set again, as default clks 700 /* SerDes1 refclks need to be set again, as default clks
368 * are not suitable for CPRI and onboard SGMIIs to work 701 * are not suitable for CPRI and onboard SGMIIs to work
369 * simultaneously. 702 * simultaneously.
370 * This function will set SerDes1's Refclk1 and refclk2 703 * This function will set SerDes1's Refclk1 and refclk2
371 * as per SerDes1 protocols 704 * as per SerDes1 protocols
372 */ 705 */
373 if (config_serdes1_refclks()) 706 if (config_serdes1_refclks())
374 printf("SerDes1 Refclks couldn't set properly.\n"); 707 printf("SerDes1 Refclks couldn't set properly.\n");
375 else 708 else
376 printf("SerDes1 Refclks have been set.\n"); 709 printf("SerDes1 Refclks have been set.\n");
710
711 /* SerDes2 refclks need to be set again, as default clks
712 * are not suitable for PCIe SATA to work
713 * This function will set SerDes2's Refclk1 and refclk2
714 * for SerDes2 protocols having PCIe in them
715 * for PCIe SATA to work
716 */
717 ret = config_serdes2_refclks();
718 if (!ret)
719 printf("SerDes2 Refclks have been set.\n");
720 else if (ret == -ENODEV)
721 printf("SerDes disable, Refclks couldn't change.\n");
722 else
723 printf("SerDes2 Refclk reconfiguring failed.\n");
724
725 #if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
726 defined(CONFIG_SYS_FSL_ERRATUM_A006475)
727 /* Rechecking the SerDes locks after all SerDes configurations
728 * are done, As SerDes PLLs may not lock reliably at 5 G VCO
729 * and at cold temperatures.
730 * Following sequence ensure the proper locking of SerDes PLLs.
731 */
732 if (SVR_MAJ(get_svr()) == 1) {
733 if (check_serdes_pll_locks())
734 printf("SerDes plls still not locked properly.\n");
735 else
736 printf("SerDes plls have been locked well.\n");
737 }
738 #endif
377 739
378 /* Configure VSC3316 and VSC3308 crossbar switches */ 740 /* Configure VSC3316 and VSC3308 crossbar switches */
379 if (configure_vsc3316_3308()) 741 if (configure_vsc3316_3308())
380 printf("VSC:failed to configure VSC3316/3308.\n"); 742 printf("VSC:failed to configure VSC3316/3308.\n");
381 else 743 else
382 printf("VSC:VSC3316/3308 successfully configured.\n"); 744 printf("VSC:VSC3316/3308 successfully configured.\n");
383 745
384 select_i2c_ch_pca(I2C_CH_DEFAULT); 746 select_i2c_ch_pca(I2C_CH_DEFAULT);
385 747
386 return 0; 748 return 0;
387 } 749 }
388 750
389 unsigned long get_board_sys_clk(void) 751 unsigned long get_board_sys_clk(void)
390 { 752 {
391 u8 sysclk_conf = QIXIS_READ(brdcfg[1]); 753 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
392 754
393 switch ((sysclk_conf & 0x0C) >> 2) { 755 switch ((sysclk_conf & 0x0C) >> 2) {
394 case QIXIS_CLK_100: 756 case QIXIS_CLK_100:
395 return 100000000; 757 return 100000000;
396 case QIXIS_CLK_125: 758 case QIXIS_CLK_125:
397 return 125000000; 759 return 125000000;
398 case QIXIS_CLK_133: 760 case QIXIS_CLK_133:
399 return 133333333; 761 return 133333333;
400 } 762 }
401 return 66666666; 763 return 66666666;
402 } 764 }
403 765
404 unsigned long get_board_ddr_clk(void) 766 unsigned long get_board_ddr_clk(void)
405 { 767 {
406 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); 768 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
407 769
408 switch (ddrclk_conf & 0x03) { 770 switch (ddrclk_conf & 0x03) {
409 case QIXIS_CLK_100: 771 case QIXIS_CLK_100:
410 return 100000000; 772 return 100000000;
411 case QIXIS_CLK_125: 773 case QIXIS_CLK_125:
412 return 125000000; 774 return 125000000;
413 case QIXIS_CLK_133: 775 case QIXIS_CLK_133:
414 return 133333333; 776 return 133333333;
415 } 777 }
416 return 66666666; 778 return 66666666;
417 } 779 }
418 780
419 static int serdes_refclock(u8 sw, u8 sdclk) 781 static int serdes_refclock(u8 sw, u8 sdclk)
420 { 782 {
421 unsigned int clock; 783 unsigned int clock;
422 int ret = -1; 784 int ret = -1;
423 u8 brdcfg4; 785 u8 brdcfg4;
424 786
425 if (sdclk == 1) { 787 if (sdclk == 1) {
426 brdcfg4 = QIXIS_READ(brdcfg[4]); 788 brdcfg4 = QIXIS_READ(brdcfg[4]);
427 if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT) 789 if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
428 return SRDS_PLLCR0_RFCK_SEL_125; 790 return SRDS_PLLCR0_RFCK_SEL_125;
429 else 791 else
430 clock = (sw >> 5) & 7; 792 clock = (sw >> 5) & 7;
431 } else 793 } else
432 clock = (sw >> 6) & 3; 794 clock = (sw >> 6) & 3;
433 795
434 switch (clock) { 796 switch (clock) {
435 case 0: 797 case 0:
436 ret = SRDS_PLLCR0_RFCK_SEL_100; 798 ret = SRDS_PLLCR0_RFCK_SEL_100;
437 break; 799 break;
438 case 1: 800 case 1:
439 ret = SRDS_PLLCR0_RFCK_SEL_125; 801 ret = SRDS_PLLCR0_RFCK_SEL_125;
440 break; 802 break;
441 case 2: 803 case 2:
442 ret = SRDS_PLLCR0_RFCK_SEL_156_25; 804 ret = SRDS_PLLCR0_RFCK_SEL_156_25;
443 break; 805 break;
444 case 3: 806 case 3:
445 ret = SRDS_PLLCR0_RFCK_SEL_161_13; 807 ret = SRDS_PLLCR0_RFCK_SEL_161_13;
446 break; 808 break;
447 case 4: 809 case 4:
448 case 5: 810 case 5:
449 case 6: 811 case 6:
450 ret = SRDS_PLLCR0_RFCK_SEL_122_88; 812 ret = SRDS_PLLCR0_RFCK_SEL_122_88;
451 break; 813 break;
452 default: 814 default:
453 ret = -1; 815 ret = -1;
454 break; 816 break;
455 } 817 }
456 818
457 return ret; 819 return ret;
458 } 820 }
459 821
460 #define NUM_SRDS_BANKS 2 822 #define NUM_SRDS_BANKS 2
461 823
462 int misc_init_r(void) 824 int misc_init_r(void)
463 { 825 {
464 u8 sw; 826 u8 sw;
465 serdes_corenet_t *srds_regs = 827 serdes_corenet_t *srds_regs =
466 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; 828 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
467 u32 actual[NUM_SRDS_BANKS]; 829 u32 actual[NUM_SRDS_BANKS];
468 unsigned int i; 830 unsigned int i;
469 int clock; 831 int clock;
470 832
471 sw = QIXIS_READ(brdcfg[2]); 833 sw = QIXIS_READ(brdcfg[2]);
472 clock = serdes_refclock(sw, 1); 834 clock = serdes_refclock(sw, 1);
473 if (clock >= 0) 835 if (clock >= 0)
474 actual[0] = clock; 836 actual[0] = clock;
475 else 837 else
476 printf("Warning: SDREFCLK1 switch setting is unsupported\n"); 838 printf("Warning: SDREFCLK1 switch setting is unsupported\n");
477 839
478 sw = QIXIS_READ(brdcfg[4]); 840 sw = QIXIS_READ(brdcfg[4]);
479 clock = serdes_refclock(sw, 2); 841 clock = serdes_refclock(sw, 2);
480 if (clock >= 0) 842 if (clock >= 0)
481 actual[1] = clock; 843 actual[1] = clock;
482 else 844 else
483 printf("Warning: SDREFCLK2 switch setting unsupported\n"); 845 printf("Warning: SDREFCLK2 switch setting unsupported\n");
484 846
485 for (i = 0; i < NUM_SRDS_BANKS; i++) { 847 for (i = 0; i < NUM_SRDS_BANKS; i++) {
486 u32 pllcr0 = srds_regs->bank[i].pllcr0; 848 u32 pllcr0 = srds_regs->bank[i].pllcr0;
487 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; 849 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
488 if (expected != actual[i]) { 850 if (expected != actual[i]) {
489 printf("Warning: SERDES bank %u expects reference clock" 851 printf("Warning: SERDES bank %u expects reference clock"
490 " %sMHz, but actual is %sMHz\n", i + 1, 852 " %sMHz, but actual is %sMHz\n", i + 1,
491 serdes_clock_to_string(expected), 853 serdes_clock_to_string(expected),
492 serdes_clock_to_string(actual[i])); 854 serdes_clock_to_string(actual[i]));
493 } 855 }
494 } 856 }
495 857
496 return 0; 858 return 0;
497 } 859 }
498 860
499 void ft_board_setup(void *blob, bd_t *bd) 861 void ft_board_setup(void *blob, bd_t *bd)
500 { 862 {
501 phys_addr_t base; 863 phys_addr_t base;
502 phys_size_t size; 864 phys_size_t size;
503 865
504 ft_cpu_setup(blob, bd); 866 ft_cpu_setup(blob, bd);
505 867
506 base = getenv_bootm_low(); 868 base = getenv_bootm_low();
507 size = getenv_bootm_size(); 869 size = getenv_bootm_size();
508 870
509 fdt_fixup_memory(blob, (u64)base, (u64)size); 871 fdt_fixup_memory(blob, (u64)base, (u64)size);
510 872
511 #ifdef CONFIG_PCI 873 #ifdef CONFIG_PCI
512 pci_of_setup(blob, bd); 874 pci_of_setup(blob, bd);
513 #endif 875 #endif
514 876
515 fdt_fixup_liodn(blob); 877 fdt_fixup_liodn(blob);
516 878
517 #ifdef CONFIG_HAS_FSL_DR_USB 879 #ifdef CONFIG_HAS_FSL_DR_USB
518 fdt_fixup_dr_usb(blob, bd); 880 fdt_fixup_dr_usb(blob, bd);
519 #endif 881 #endif
520 882
521 #ifdef CONFIG_SYS_DPAA_FMAN 883 #ifdef CONFIG_SYS_DPAA_FMAN
522 fdt_fixup_fman_ethernet(blob); 884 fdt_fixup_fman_ethernet(blob);
523 fdt_fixup_board_enet(blob); 885 fdt_fixup_board_enet(blob);
524 #endif 886 #endif
525 } 887 }
526 888
527 /* 889 /*
528 * Dump board switch settings. 890 * Dump board switch settings.
529 * The bits that cannot be read/sampled via some FPGA or some 891 * The bits that cannot be read/sampled via some FPGA or some
530 * registers, they will be displayed as 892 * registers, they will be displayed as
531 * underscore in binary format. mask[] has those bits. 893 * underscore in binary format. mask[] has those bits.
532 * Some bits are calculated differently than the actual switches 894 * Some bits are calculated differently than the actual switches
533 * if booting with overriding by FPGA. 895 * if booting with overriding by FPGA.
534 */ 896 */
535 void qixis_dump_switch(void) 897 void qixis_dump_switch(void)
536 { 898 {
537 int i; 899 int i;
538 u8 sw[5]; 900 u8 sw[5];
539 901
540 /* 902 /*
541 * Any bit with 1 means that bit cannot be reverse engineered. 903 * Any bit with 1 means that bit cannot be reverse engineered.
542 * It will be displayed as _ in binary format. 904 * It will be displayed as _ in binary format.
543 */ 905 */
544 static const u8 mask[] = {0x07, 0, 0, 0xff, 0}; 906 static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
545 char buf[10]; 907 char buf[10];
546 u8 brdcfg[16], dutcfg[16]; 908 u8 brdcfg[16], dutcfg[16];
547 909
548 for (i = 0; i < 16; i++) { 910 for (i = 0; i < 16; i++) {
549 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i); 911 brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
550 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i); 912 dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
551 } 913 }
552 914
553 sw[0] = ((brdcfg[0] & 0x0f) << 4) | \ 915 sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
554 (brdcfg[9] & 0x08); 916 (brdcfg[9] & 0x08);
555 sw[1] = ((dutcfg[1] & 0x01) << 7) | \ 917 sw[1] = ((dutcfg[1] & 0x01) << 7) | \
556 ((dutcfg[2] & 0x07) << 4) | \ 918 ((dutcfg[2] & 0x07) << 4) | \
557 ((dutcfg[6] & 0x10) >> 1) | \ 919 ((dutcfg[6] & 0x10) >> 1) | \
558 ((dutcfg[6] & 0x80) >> 5) | \ 920 ((dutcfg[6] & 0x80) >> 5) | \
559 ((dutcfg[1] & 0x40) >> 5) | \ 921 ((dutcfg[1] & 0x40) >> 5) | \
560 (dutcfg[6] & 0x01); 922 (dutcfg[6] & 0x01);
561 sw[2] = dutcfg[0]; 923 sw[2] = dutcfg[0];
562 sw[3] = 0; 924 sw[3] = 0;
563 sw[4] = ((brdcfg[1] & 0x30) << 2) | \ 925 sw[4] = ((brdcfg[1] & 0x30) << 2) | \
564 ((brdcfg[1] & 0xc0) >> 2) | \ 926 ((brdcfg[1] & 0xc0) >> 2) | \
565 (brdcfg[1] & 0x0f); 927 (brdcfg[1] & 0x0f);
566 928
567 puts("DIP switch settings:\n"); 929 puts("DIP switch settings:\n");
568 for (i = 0; i < 5; i++) { 930 for (i = 0; i < 5; i++) {
569 printf("SW%d = 0b%s (0x%02x)\n", 931 printf("SW%d = 0b%s (0x%02x)\n",
570 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]); 932 i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
571 } 933 }
board/freescale/b4860qds/b4860qds_crossbar_con.h
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc. 2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __CROSSBAR_CONNECTIONS_H__ 7 #ifndef __CROSSBAR_CONNECTIONS_H__
8 #define __CROSSBAR_CONNECTIONS_H__ 8 #define __CROSSBAR_CONNECTIONS_H__
9 9
10 #define NUM_CON_VSC3316 8 10 #define NUM_CON_VSC3316 8
11 #define NUM_CON_VSC3308 4 11 #define NUM_CON_VSC3308 4
12 12
13 static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10}, 13 static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
14 {5, 11}, {4, 5}, {2, 6}, {12, 9} }; 14 {5, 11}, {4, 5}, {2, 6}, {12, 9} };
15 15
16 static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, 16 static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
17 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 17 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
18 18
19 static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1}, 19 static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
20 {7, 8}, {9, 0}, {2, 14}, {12, 15}, 20 {7, 8}, {9, 0}, {2, 14}, {12, 15},
21 {-1, -1}, {-1, -1} }; 21 {-1, -1}, {-1, -1} };
22 22
23 static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1}, 23 static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
24 {7, 8}, {9, 0}, {5, 14}, {4, 15}, 24 {7, 8}, {9, 0}, {5, 14}, {4, 15},
25 {-1, -1}, {-1, -1} }; 25 {-1, -1}, {-1, -1} };
26 26
27 static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
28 {7, 8}, {9, 0}, {5, 14},
29 {4, 15}, {2, 12}, {12, 13} };
30
27 #ifdef CONFIG_PPC_B4420 31 #ifdef CONFIG_PPC_B4420
28 static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, 32 static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
29 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 33 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
30 #endif 34 #endif
31 35
32 static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1}, 36 static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
33 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 37 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
34 38
35 static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9}, 39 static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
36 {11, 11}, {5, 10}, {6, 3}, {9, 12} }; 40 {11, 11}, {5, 10}, {6, 3}, {9, 12} };
37 41
38 static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, 42 static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
39 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 43 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
40 44
41 static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1}, 45 static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
42 {7, 8}, {1, 9}, {14, 3}, {15, 12}, 46 {7, 8}, {1, 9}, {14, 3}, {15, 12},
43 {-1, -1}, {-1, -1} }; 47 {-1, -1}, {-1, -1} };
44 48
45 static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1}, 49 static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
46 {7, 8}, {1, 9}, {14, 11}, {15, 10}, 50 {7, 8}, {1, 9}, {14, 11}, {15, 10},
47 {-1, -1}, {-1, -1} }; 51 {-1, -1}, {-1, -1} };
52
53 static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
54 {7, 8}, {1, 9}, {14, 11},
55 {15, 10}, {13, 3}, {12, 12} };
48 56
49 #ifdef CONFIG_PPC_B4420 57 #ifdef CONFIG_PPC_B4420
50 static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, 58 static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
51 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 59 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
52 #endif 60 #endif
53 61
54 static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1}, 62 static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1},
55 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 63 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
56 64
57 static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} }; 65 static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
58 66
59 static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} }; 67 static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} };
60 68
61 static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} }; 69 static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
62 70
63 static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} }; 71 static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} };
64 72
65 #endif 73 #endif
66 74
board/freescale/b4860qds/eth_b4860qds.c
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2012 Freescale Semiconductor, Inc. 2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Author: Sandeep Kumar Singh <sandeep@freescale.com> 3 * Author: Sandeep Kumar Singh <sandeep@freescale.com>
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 /* This file is based on board/freescale/corenet_ds/eth_superhydra.c */ 8 /* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
9 9
10 /* 10 /*
11 * This file handles the board muxing between the Fman Ethernet MACs and 11 * This file handles the board muxing between the Fman Ethernet MACs and
12 * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII 12 * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
13 * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board. 13 * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
14 * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only 14 * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
15 * one Fman device on B4860. The SERDES configuration is used to determine 15 * one Fman device on B4860. The SERDES configuration is used to determine
16 * where the SGMII and XAUI cards exist, and also which Fman MACs are routed 16 * where the SGMII and XAUI cards exist, and also which Fman MACs are routed
17 * to which PHYs. So for a given Fman MAC, there is one and only PHY it 17 * to which PHYs. So for a given Fman MAC, there is one and only PHY it
18 * connects to. MACs cannot be routed to PHYs dynamically. This configuration 18 * connects to. MACs cannot be routed to PHYs dynamically. This configuration
19 * is done at boot time by reading SERDES protocol from RCW. 19 * is done at boot time by reading SERDES protocol from RCW.
20 */ 20 */
21 21
22 #include <common.h> 22 #include <common.h>
23 #include <netdev.h> 23 #include <netdev.h>
24 #include <asm/fsl_serdes.h> 24 #include <asm/fsl_serdes.h>
25 #include <fm_eth.h> 25 #include <fm_eth.h>
26 #include <fsl_mdio.h> 26 #include <fsl_mdio.h>
27 #include <malloc.h> 27 #include <malloc.h>
28 #include <fdt_support.h> 28 #include <fdt_support.h>
29 #include <asm/fsl_dtsec.h> 29 #include <asm/fsl_dtsec.h>
30 30
31 #include "../common/ngpixis.h" 31 #include "../common/ngpixis.h"
32 #include "../common/fman.h" 32 #include "../common/fman.h"
33 #include "../common/qixis.h" 33 #include "../common/qixis.h"
34 #include "b4860qds_qixis.h" 34 #include "b4860qds_qixis.h"
35 35
36 #define EMI_NONE 0xFFFFFFFF 36 #define EMI_NONE 0xFFFFFFFF
37 37
38 #ifdef CONFIG_FMAN_ENET 38 #ifdef CONFIG_FMAN_ENET
39 39
40 /* 40 /*
41 * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that 41 * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
42 * lane at index is mapped to slot number n. A value of '0' will mean 42 * lane at index is mapped to slot number n. A value of '0' will mean
43 * that the mapping must be determined dynamically, or that the lane maps to 43 * that the mapping must be determined dynamically, or that the lane maps to
44 * something other than a board slot 44 * something other than a board slot
45 */ 45 */
46 static u8 lane_to_slot[] = { 46 static u8 lane_to_slot[] = {
47 0, 0, 0, 0, 47 0, 0, 0, 0,
48 0, 0, 0, 0, 48 0, 0, 0, 0,
49 1, 1, 1, 1, 49 1, 1, 1, 1,
50 0, 0, 0, 0 50 0, 0, 0, 0
51 }; 51 };
52 52
53 /* 53 /*
54 * This function initializes the lane_to_slot[] array. It reads RCW to check 54 * This function initializes the lane_to_slot[] array. It reads RCW to check
55 * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes 55 * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
56 * lane_to_slot[] accordingly 56 * lane_to_slot[] accordingly
57 */ 57 */
58 static void initialize_lane_to_slot(void) 58 static void initialize_lane_to_slot(void)
59 { 59 {
60 unsigned int serdes2_prtcl; 60 unsigned int serdes2_prtcl;
61 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 61 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
62 serdes2_prtcl = in_be32(&gur->rcwsr[4]) & 62 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
63 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 63 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
64 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 64 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
65 debug("Initializing lane to slot: Serdes2 protocol: %x\n", 65 debug("Initializing lane to slot: Serdes2 protocol: %x\n",
66 serdes2_prtcl); 66 serdes2_prtcl);
67 67
68 switch (serdes2_prtcl) { 68 switch (serdes2_prtcl) {
69 case 0x17:
69 case 0x18: 70 case 0x18:
70 /* 71 /*
71 * Configuration: 72 * Configuration:
72 * SERDES: 2 73 * SERDES: 2
73 * Lanes: A,B,C,D: SGMII 74 * Lanes: A,B,C,D: SGMII
74 * Lanes: E,F: Aur 75 * Lanes: E,F: Aur
75 * Lanes: G,H: SRIO 76 * Lanes: G,H: SRIO
76 */ 77 */
77 case 0x91: 78 case 0x91:
78 /* 79 /*
79 * Configuration: 80 * Configuration:
80 * SERDES: 2 81 * SERDES: 2
81 * Lanes: A,B: SGMII 82 * Lanes: A,B: SGMII
82 * Lanes: C,D: SRIO2 83 * Lanes: C,D: SRIO2
83 * Lanes: E,F,G,H: XAUI2 84 * Lanes: E,F,G,H: XAUI2
84 */ 85 */
85 case 0x93: 86 case 0x93:
86 /* 87 /*
87 * Configuration: 88 * Configuration:
88 * SERDES: 2 89 * SERDES: 2
89 * Lanes: A,B,C,D: SGMII 90 * Lanes: A,B,C,D: SGMII
90 * Lanes: E,F,G,H: XAUI2 91 * Lanes: E,F,G,H: XAUI2
91 */ 92 */
92 case 0x98: 93 case 0x98:
93 /* 94 /*
94 * Configuration: 95 * Configuration:
95 * SERDES: 2 96 * SERDES: 2
96 * Lanes: A,B,C,D: XAUI2 97 * Lanes: A,B,C,D: XAUI2
97 * Lanes: E,F,G,H: XAUI2 98 * Lanes: E,F,G,H: XAUI2
98 */ 99 */
99 case 0x9a: 100 case 0x9a:
100 /* 101 /*
101 * Configuration: 102 * Configuration:
102 * SERDES: 2 103 * SERDES: 2
103 * Lanes: A,B: PCI 104 * Lanes: A,B: PCI
104 * Lanes: C,D: SGMII 105 * Lanes: C,D: SGMII
105 * Lanes: E,F,G,H: XAUI2 106 * Lanes: E,F,G,H: XAUI2
106 */ 107 */
107 case 0x9e: 108 case 0x9e:
108 /* 109 /*
109 * Configuration: 110 * Configuration:
110 * SERDES: 2 111 * SERDES: 2
111 * Lanes: A,B,C,D: PCI 112 * Lanes: A,B,C,D: PCI
112 * Lanes: E,F,G,H: XAUI2 113 * Lanes: E,F,G,H: XAUI2
113 */ 114 */
114 case 0xb2: 115 case 0xb2:
115 /* 116 /*
116 * Configuration: 117 * Configuration:
117 * SERDES: 2 118 * SERDES: 2
118 * Lanes: A,B,C,D: PCI 119 * Lanes: A,B,C,D: PCI
119 * Lanes: E,F: SGMII 3&4 120 * Lanes: E,F: SGMII 3&4
120 * Lanes: G,H: XFI 121 * Lanes: G,H: XFI
121 */ 122 */
122 case 0xc2: 123 case 0xc2:
123 /* 124 /*
124 * Configuration: 125 * Configuration:
125 * SERDES: 2 126 * SERDES: 2
126 * Lanes: A,B: SGMII 127 * Lanes: A,B: SGMII
127 * Lanes: C,D: SRIO2 128 * Lanes: C,D: SRIO2
128 * Lanes: E,F,G,H: XAUI2 129 * Lanes: E,F,G,H: XAUI2
129 */ 130 */
130 lane_to_slot[12] = 2; 131 lane_to_slot[12] = 2;
131 lane_to_slot[13] = lane_to_slot[12]; 132 lane_to_slot[13] = lane_to_slot[12];
132 lane_to_slot[14] = lane_to_slot[12]; 133 lane_to_slot[14] = lane_to_slot[12];
133 lane_to_slot[15] = lane_to_slot[12]; 134 lane_to_slot[15] = lane_to_slot[12];
134 break; 135 break;
135 136
136 default: 137 default:
137 printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", 138 printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
138 serdes2_prtcl); 139 serdes2_prtcl);
139 break; 140 break;
140 } 141 }
141 return; 142 return;
142 } 143 }
143 144
144 #endif /* #ifdef CONFIG_FMAN_ENET */ 145 #endif /* #ifdef CONFIG_FMAN_ENET */
145 146
146 int board_eth_init(bd_t *bis) 147 int board_eth_init(bd_t *bis)
147 { 148 {
148 #ifdef CONFIG_FMAN_ENET 149 #ifdef CONFIG_FMAN_ENET
149 struct memac_mdio_info memac_mdio_info; 150 struct memac_mdio_info memac_mdio_info;
150 struct memac_mdio_info tg_memac_mdio_info; 151 struct memac_mdio_info tg_memac_mdio_info;
151 unsigned int i; 152 unsigned int i;
152 unsigned int serdes1_prtcl, serdes2_prtcl; 153 unsigned int serdes1_prtcl, serdes2_prtcl;
153 int qsgmii; 154 int qsgmii;
154 struct mii_dev *bus; 155 struct mii_dev *bus;
155 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 156 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
156 serdes1_prtcl = in_be32(&gur->rcwsr[4]) & 157 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
157 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 158 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
158 if (!serdes1_prtcl) { 159 if (!serdes1_prtcl) {
159 printf("SERDES1 is not enabled\n"); 160 printf("SERDES1 is not enabled\n");
160 return 0; 161 return 0;
161 } 162 }
162 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 163 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
163 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); 164 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
164 165
165 serdes2_prtcl = in_be32(&gur->rcwsr[4]) & 166 serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
166 FSL_CORENET2_RCWSR4_SRDS2_PRTCL; 167 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
167 if (!serdes2_prtcl) { 168 if (!serdes2_prtcl) {
168 printf("SERDES2 is not enabled\n"); 169 printf("SERDES2 is not enabled\n");
169 return 0; 170 return 0;
170 } 171 }
171 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; 172 serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
172 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); 173 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
173 174
174 printf("Initializing Fman\n"); 175 printf("Initializing Fman\n");
175 176
176 initialize_lane_to_slot(); 177 initialize_lane_to_slot();
177 178
178 memac_mdio_info.regs = 179 memac_mdio_info.regs =
179 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; 180 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
180 memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; 181 memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
181 182
182 /* Register the real 1G MDIO bus */ 183 /* Register the real 1G MDIO bus */
183 fm_memac_mdio_init(bis, &memac_mdio_info); 184 fm_memac_mdio_init(bis, &memac_mdio_info);
184 185
185 tg_memac_mdio_info.regs = 186 tg_memac_mdio_info.regs =
186 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; 187 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
187 tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 188 tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
188 189
189 /* Register the real 10G MDIO bus */ 190 /* Register the real 10G MDIO bus */
190 fm_memac_mdio_init(bis, &tg_memac_mdio_info); 191 fm_memac_mdio_init(bis, &tg_memac_mdio_info);
191 192
192 /* 193 /*
193 * Program the two on board DTSEC PHY addresses assuming that they are 194 * Program the two on board DTSEC PHY addresses assuming that they are
194 * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and 195 * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
195 * 6 to on board SGMII phys 196 * 6 to on board SGMII phys
196 */ 197 */
197 fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); 198 fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
198 fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); 199 fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
199 200
200 switch (serdes1_prtcl) { 201 switch (serdes1_prtcl) {
202 case 0x29:
201 case 0x2a: 203 case 0x2a:
202 /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */ 204 /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
203 debug("Setting phy addresses for FM1_DTSEC5: %x and" 205 debug("Setting phy addresses for FM1_DTSEC5: %x and"
204 "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR, 206 "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
205 CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); 207 CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
206 fm_info_set_phy_address(FM1_DTSEC5, 208 fm_info_set_phy_address(FM1_DTSEC5,
207 CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); 209 CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
208 fm_info_set_phy_address(FM1_DTSEC6, 210 fm_info_set_phy_address(FM1_DTSEC6,
209 CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); 211 CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
210 break; 212 break;
211 #ifdef CONFIG_PPC_B4420 213 #ifdef CONFIG_PPC_B4420
214 case 0x17:
212 case 0x18: 215 case 0x18:
213 /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ 216 /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
214 debug("Setting phy addresses for FM1_DTSEC3: %x and" 217 debug("Setting phy addresses for FM1_DTSEC3: %x and"
215 "FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR, 218 "FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
216 CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); 219 CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
217 /* Fixing Serdes clock by programming FPGA register */ 220 /* Fixing Serdes clock by programming FPGA register */
218 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); 221 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
219 fm_info_set_phy_address(FM1_DTSEC3, 222 fm_info_set_phy_address(FM1_DTSEC3,
220 CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); 223 CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
221 fm_info_set_phy_address(FM1_DTSEC4, 224 fm_info_set_phy_address(FM1_DTSEC4,
222 CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); 225 CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
223 break; 226 break;
224 #endif 227 #endif
225 default: 228 default:
226 printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n", 229 printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n",
227 serdes1_prtcl); 230 serdes1_prtcl);
228 break; 231 break;
229 } 232 }
230 switch (serdes2_prtcl) { 233 switch (serdes2_prtcl) {
234 case 0x17:
231 case 0x18: 235 case 0x18:
232 debug("Setting phy addresses on SGMII Riser card for" 236 debug("Setting phy addresses on SGMII Riser card for"
233 "FM1_DTSEC ports: \n"); 237 "FM1_DTSEC ports: \n");
234 fm_info_set_phy_address(FM1_DTSEC1, 238 fm_info_set_phy_address(FM1_DTSEC1,
235 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); 239 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
236 fm_info_set_phy_address(FM1_DTSEC2, 240 fm_info_set_phy_address(FM1_DTSEC2,
237 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); 241 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
238 fm_info_set_phy_address(FM1_DTSEC3, 242 fm_info_set_phy_address(FM1_DTSEC3,
239 CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); 243 CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
240 fm_info_set_phy_address(FM1_DTSEC4, 244 fm_info_set_phy_address(FM1_DTSEC4,
241 CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR); 245 CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
242 break; 246 break;
247 case 0x48:
243 case 0x49: 248 case 0x49:
244 debug("Setting phy addresses on SGMII Riser card for" 249 debug("Setting phy addresses on SGMII Riser card for"
245 "FM1_DTSEC ports: \n"); 250 "FM1_DTSEC ports: \n");
246 fm_info_set_phy_address(FM1_DTSEC1, 251 fm_info_set_phy_address(FM1_DTSEC1,
247 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); 252 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
248 fm_info_set_phy_address(FM1_DTSEC2, 253 fm_info_set_phy_address(FM1_DTSEC2,
249 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); 254 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
250 fm_info_set_phy_address(FM1_DTSEC3, 255 fm_info_set_phy_address(FM1_DTSEC3,
251 CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); 256 CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
252 break; 257 break;
253 case 0x8d: 258 case 0x8d:
254 case 0xb2: 259 case 0xb2:
255 debug("Setting phy addresses on SGMII Riser card for" 260 debug("Setting phy addresses on SGMII Riser card for"
256 "FM1_DTSEC ports: \n"); 261 "FM1_DTSEC ports: \n");
257 fm_info_set_phy_address(FM1_DTSEC3, 262 fm_info_set_phy_address(FM1_DTSEC3,
258 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); 263 CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
259 fm_info_set_phy_address(FM1_DTSEC4, 264 fm_info_set_phy_address(FM1_DTSEC4,
260 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); 265 CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
261 break; 266 break;
262 case 0x98: 267 case 0x98:
263 /* XAUI in Slot1 and Slot2 */ 268 /* XAUI in Slot1 and Slot2 */
264 debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n", 269 debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n",
265 CONFIG_SYS_FM1_10GEC1_PHY_ADDR); 270 CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
266 fm_info_set_phy_address(FM1_10GEC1, 271 fm_info_set_phy_address(FM1_10GEC1,
267 CONFIG_SYS_FM1_10GEC1_PHY_ADDR); 272 CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
268 debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n", 273 debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
269 CONFIG_SYS_FM1_10GEC2_PHY_ADDR); 274 CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
270 fm_info_set_phy_address(FM1_10GEC2, 275 fm_info_set_phy_address(FM1_10GEC2,
271 CONFIG_SYS_FM1_10GEC2_PHY_ADDR); 276 CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
272 break; 277 break;
273 case 0x9E: 278 case 0x9E:
274 /* XAUI in Slot2 */ 279 /* XAUI in Slot2 */
275 debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n", 280 debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
276 CONFIG_SYS_FM1_10GEC2_PHY_ADDR); 281 CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
277 fm_info_set_phy_address(FM1_10GEC2, 282 fm_info_set_phy_address(FM1_10GEC2,
278 CONFIG_SYS_FM1_10GEC2_PHY_ADDR); 283 CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
279 break; 284 break;
280 default: 285 default:
281 printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", 286 printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
282 serdes2_prtcl); 287 serdes2_prtcl);
283 break; 288 break;
284 } 289 }
285 290
286 /*set PHY address for QSGMII Riser Card on slot2*/ 291 /*set PHY address for QSGMII Riser Card on slot2*/
287 bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); 292 bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
288 qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM); 293 qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
289 294
290 if (qsgmii) { 295 if (qsgmii) {
291 switch (serdes2_prtcl) { 296 switch (serdes2_prtcl) {
292 case 0xb2: 297 case 0xb2:
293 case 0x8d: 298 case 0x8d:
294 fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR); 299 fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
295 fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1); 300 fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
296 break; 301 break;
297 default: 302 default:
298 break; 303 break;
299 } 304 }
300 } 305 }
301 306
302 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 307 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
303 int idx = i - FM1_DTSEC1; 308 int idx = i - FM1_DTSEC1;
304 309
305 switch (fm_info_get_enet_if(i)) { 310 switch (fm_info_get_enet_if(i)) {
306 case PHY_INTERFACE_MODE_SGMII: 311 case PHY_INTERFACE_MODE_SGMII:
307 fm_info_set_mdio(i, 312 fm_info_set_mdio(i,
308 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); 313 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
309 break; 314 break;
310 case PHY_INTERFACE_MODE_NONE: 315 case PHY_INTERFACE_MODE_NONE:
311 fm_info_set_phy_address(i, 0); 316 fm_info_set_phy_address(i, 0);
312 break; 317 break;
313 default: 318 default:
314 printf("Fman1: DTSEC%u set to unknown interface %i\n", 319 printf("Fman1: DTSEC%u set to unknown interface %i\n",
315 idx + 1, fm_info_get_enet_if(i)); 320 idx + 1, fm_info_get_enet_if(i));
316 fm_info_set_phy_address(i, 0); 321 fm_info_set_phy_address(i, 0);
317 break; 322 break;
318 } 323 }
319 } 324 }
320 325
321 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { 326 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
322 int idx = i - FM1_10GEC1; 327 int idx = i - FM1_10GEC1;
323 328
324 switch (fm_info_get_enet_if(i)) { 329 switch (fm_info_get_enet_if(i)) {
325 case PHY_INTERFACE_MODE_XGMII: 330 case PHY_INTERFACE_MODE_XGMII:
326 fm_info_set_mdio(i, 331 fm_info_set_mdio(i,
327 miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME)); 332 miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
328 break; 333 break;
329 default: 334 default:
330 printf("Fman1: 10GSEC%u set to unknown interface %i\n", 335 printf("Fman1: 10GSEC%u set to unknown interface %i\n",
331 idx + 1, fm_info_get_enet_if(i)); 336 idx + 1, fm_info_get_enet_if(i));
332 fm_info_set_phy_address(i, 0); 337 fm_info_set_phy_address(i, 0);
333 break; 338 break;
334 } 339 }
335 } 340 }
336 341
337 342
338 cpu_eth_init(bis); 343 cpu_eth_init(bis);
339 #endif 344 #endif
340 345
341 return pci_eth_init(bis); 346 return pci_eth_init(bis);
342 } 347 }
343 348
344 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, 349 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
345 enum fm_port port, int offset) 350 enum fm_port port, int offset)
346 { 351 {
347 int phy; 352 int phy;
348 char alias[32]; 353 char alias[32];
349 354
350 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { 355 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
351 phy = fm_info_get_phy_address(port); 356 phy = fm_info_get_phy_address(port);
352 357
353 sprintf(alias, "phy_sgmii_%x", phy); 358 sprintf(alias, "phy_sgmii_%x", phy);
354 fdt_set_phy_handle(fdt, compat, addr, alias); 359 fdt_set_phy_handle(fdt, compat, addr, alias);
355 } 360 }
356 } 361 }
357 362
358 void fdt_fixup_board_enet(void *fdt) 363 void fdt_fixup_board_enet(void *fdt)
359 { 364 {
360 int i; 365 int i;
361 char alias[32]; 366 char alias[32];
362 367
363 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 368 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
364 switch (fm_info_get_enet_if(i)) { 369 switch (fm_info_get_enet_if(i)) {
365 case PHY_INTERFACE_MODE_NONE: 370 case PHY_INTERFACE_MODE_NONE:
366 sprintf(alias, "ethernet%u", i); 371 sprintf(alias, "ethernet%u", i);
367 fdt_status_disabled_by_alias(fdt, alias); 372 fdt_status_disabled_by_alias(fdt, alias);
368 break; 373 break;
369 default: 374 default:
370 break; 375 break;
371 } 376 }
372 } 377 }
373 } 378 }
374 379
board/freescale/t1040qds/Makefile
Diff comments   View file @ 247161b
1 # 1 #
2 # Copyright 2013 Freescale Semiconductor, Inc. 2 # Copyright 2013 Freescale Semiconductor, Inc.
3 # 3 #
4 # SPDX-License-Identifier: GPL-2.0+ 4 # SPDX-License-Identifier: GPL-2.0+
5 # 5 #
6 6
7 obj-y += t1040qds.o 7 obj-y += t1040qds.o
8 obj-y += ddr.o 8 obj-y += ddr.o
9 obj-$(CONFIG_PCI) += pci.o 9 obj-$(CONFIG_PCI) += pci.o
10 obj-y += law.o 10 obj-y += law.o
11 obj-y += tlb.o 11 obj-y += tlb.o
12 obj-y += eth.o 12 obj-y += eth.o
13 obj-y += diu.o
13 14
board/freescale/t1040qds/diu.c
Diff comments   View file @ 247161b
File was created 1 /*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <command.h>
10 #include <linux/ctype.h>
11 #include <asm/io.h>
12 #include <stdio_dev.h>
13 #include <video_fb.h>
14 #include <fsl_diu_fb.h>
15 #include "../common/qixis.h"
16 #include "t1040qds.h"
17 #include "t1040qds_qixis.h"
18 #include <i2c.h>
19
20
21 #define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F
22 #define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33
23 #define I2C_DVI_PLL_DIVIDER_REG 0x34
24 #define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35
25 #define I2C_DVI_PLL_FILTER_REG 0x36
26 #define I2C_DVI_TEST_PATTERN_REG 0x48
27 #define I2C_DVI_POWER_MGMT_REG 0x49
28 #define I2C_DVI_LOCK_STATE_REG 0x4D
29 #define I2C_DVI_SYNC_POLARITY_REG 0x56
30
31 /*
32 * Set VSYNC/HSYNC to active high. This is polarity of sync signals
33 * from DIU->DVI. The DIU default is active igh, so DVI is set to
34 * active high.
35 */
36 #define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98
37
38 #define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
39 #define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26
40 #define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0
41 #define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08
42 #define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16
43 #define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60
44
45 /* Clear test pattern */
46 #define I2C_DVI_TEST_PATTERN_VAL 0x18
47 /* Exit Power-down mode */
48 #define I2C_DVI_POWER_MGMT_VAL 0xC0
49
50 /* Monitor polarity is handled via DVI Sync Polarity Register */
51 #define I2C_DVI_SYNC_POLARITY_VAL 0x00
52
53 /*
54 * DIU Area Descriptor
55 *
56 * Note that we need to byte-swap the value before it's written to the AD
57 * register. So even though the registers don't look like they're in the same
58 * bit positions as they are on the MPC8610, the same value is written to the
59 * AD register on the MPC8610 and on the P1022.
60 */
61 #define AD_BYTE_F 0x10000000
62 #define AD_ALPHA_C_SHIFT 25
63 #define AD_BLUE_C_SHIFT 23
64 #define AD_GREEN_C_SHIFT 21
65 #define AD_RED_C_SHIFT 19
66 #define AD_PIXEL_S_SHIFT 16
67 #define AD_COMP_3_SHIFT 12
68 #define AD_COMP_2_SHIFT 8
69 #define AD_COMP_1_SHIFT 4
70 #define AD_COMP_0_SHIFT 0
71
72 /* Programming of HDMI Chrontel CH7301 connector */
73 int diu_set_dvi_encoder(unsigned int pixclock)
74 {
75 int ret;
76 u8 temp;
77 select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
78
79 temp = I2C_DVI_TEST_PATTERN_VAL;
80 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
81 &temp, 1);
82 if (ret) {
83 puts("I2C: failed to select proper dvi test pattern\n");
84 return ret;
85 }
86 temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
87 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
88 1, &temp, 1);
89 if (ret) {
90 puts("I2C: failed to select dvi input data format\n");
91 return ret;
92 }
93
94 /* Set Sync polarity register */
95 temp = I2C_DVI_SYNC_POLARITY_VAL;
96 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
97 &temp, 1);
98 if (ret) {
99 puts("I2C: failed to select dvi syc polarity\n");
100 return ret;
101 }
102
103 /* Set PLL registers based on pixel clock rate*/
104 if (pixclock > 65000000) {
105 temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
106 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
107 I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
108 if (ret) {
109 puts("I2C: failed to select dvi pll charge_cntl\n");
110 return ret;
111 }
112 temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
113 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
114 I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
115 if (ret) {
116 puts("I2C: failed to select dvi pll divider\n");
117 return ret;
118 }
119 temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
120 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
121 I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
122 if (ret) {
123 puts("I2C: failed to select dvi pll filter\n");
124 return ret;
125 }
126 } else {
127 temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
128 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
129 I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
130 if (ret) {
131 puts("I2C: failed to select dvi pll charge_cntl\n");
132 return ret;
133 }
134 temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
135 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
136 I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
137 if (ret) {
138 puts("I2C: failed to select dvi pll divider\n");
139 return ret;
140 }
141 temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
142 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
143 I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
144 if (ret) {
145 puts("I2C: failed to select dvi pll filter\n");
146 return ret;
147 }
148 }
149
150 temp = I2C_DVI_POWER_MGMT_VAL;
151 ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
152 &temp, 1);
153 if (ret) {
154 puts("I2C: failed to select dvi power mgmt\n");
155 return ret;
156 }
157
158 udelay(500);
159
160 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
161 return 0;
162 }
163
164 void diu_set_pixel_clock(unsigned int pixclock)
165 {
166 unsigned long speed_ccb, temp;
167 u32 pixval;
168 int ret = 0;
169 speed_ccb = get_bus_freq(0);
170 temp = 1000000000 / pixclock;
171 temp *= 1000;
172 pixval = speed_ccb / temp;
173
174 /* Program HDMI encoder */
175 ret = diu_set_dvi_encoder(temp);
176 if (ret) {
177 puts("Failed to set DVI encoder\n");
178 return;
179 }
180
181 /* Program pixel clock */
182 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
183 ((pixval << PXCK_BITS_START) & PXCK_MASK));
184 /* enable clock*/
185 out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
186 ((pixval << PXCK_BITS_START) & PXCK_MASK));
187 }
188
189 int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
190 {
191 u32 pixel_format;
192 u8 sw;
193
194 /*Route I2C4 to DIU system as HSYNC/VSYNC*/
195 sw = QIXIS_READ(brdcfg[5]);
196 QIXIS_WRITE(brdcfg[5],
197 ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
198
199 /*Configure Display ouput port as HDMI*/
200 sw = QIXIS_READ(brdcfg[15]);
201 QIXIS_WRITE(brdcfg[15],
202 ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
203 | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
204
205 pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
206 (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
207 (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
208 (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
209 (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
210
211 printf("DIU: Switching to monitor @ %ux%u\n", xres, yres);
212
213
214 return fsl_diu_init(xres, yres, pixel_format, 0);
215 }
216
board/freescale/t1040qds/t1040qds.h
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __T1040_QDS_H__ 7 #ifndef __T1040_QDS_H__
8 #define __T1040_QDS_H__ 8 #define __T1040_QDS_H__
9 9
10 void fdt_fixup_board_enet(void *blob); 10 void fdt_fixup_board_enet(void *blob);
11 void pci_of_setup(void *blob, bd_t *bd); 11 void pci_of_setup(void *blob, bd_t *bd);
12 int select_i2c_ch_pca9547(u8 ch);
12 13
13 #endif 14 #endif
14 15
board/freescale/t1040qds/t1040qds_qixis.h
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __T1040QDS_QIXIS_H__ 7 #ifndef __T1040QDS_QIXIS_H__
8 #define __T1040QDS_QIXIS_H__ 8 #define __T1040QDS_QIXIS_H__
9 9
10 /* Definitions of QIXIS Registers for T1040QDS */ 10 /* Definitions of QIXIS Registers for T1040QDS */
11 11
12 /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ 12 /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
13 #define BRDCFG4_EMISEL_MASK 0xE0 13 #define BRDCFG4_EMISEL_MASK 0xE0
14 #define BRDCFG4_EMISEL_SHIFT 5 14 #define BRDCFG4_EMISEL_SHIFT 5
15 15
16 /* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
17 #define BRDCFG5_IMX_MASK 0xC0
18 #define BRDCFG5_IMX_DIU 0x80
19
20 /* BRDCFG15[3] controls LCD Panel Powerdown*/
21 #define BRDCFG15_LCDPD_MASK 0x10
22 #define BRDCFG15_LCDPD_ENABLED 0x00
23
24 /* BRDCFG15[6:7] controls DIU MUX selction*/
25 #define BRDCFG15_DIUSEL_MASK 0x03
26 #define BRDCFG15_DIUSEL_HDMI 0x00
27
16 /* SYSCLK */ 28 /* SYSCLK */
17 #define QIXIS_SYSCLK_66 0x0 29 #define QIXIS_SYSCLK_66 0x0
18 #define QIXIS_SYSCLK_83 0x1 30 #define QIXIS_SYSCLK_83 0x1
19 #define QIXIS_SYSCLK_100 0x2 31 #define QIXIS_SYSCLK_100 0x2
20 #define QIXIS_SYSCLK_125 0x3 32 #define QIXIS_SYSCLK_125 0x3
21 #define QIXIS_SYSCLK_133 0x4 33 #define QIXIS_SYSCLK_133 0x4
22 #define QIXIS_SYSCLK_150 0x5 34 #define QIXIS_SYSCLK_150 0x5
23 #define QIXIS_SYSCLK_160 0x6 35 #define QIXIS_SYSCLK_160 0x6
24 #define QIXIS_SYSCLK_166 0x7 36 #define QIXIS_SYSCLK_166 0x7
25 #define QIXIS_SYSCLK_64 0x8 37 #define QIXIS_SYSCLK_64 0x8
26 38
27 /* DDRCLK */ 39 /* DDRCLK */
28 #define QIXIS_DDRCLK_66 0x0 40 #define QIXIS_DDRCLK_66 0x0
29 #define QIXIS_DDRCLK_100 0x1 41 #define QIXIS_DDRCLK_100 0x1
30 #define QIXIS_DDRCLK_125 0x2 42 #define QIXIS_DDRCLK_125 0x2
31 #define QIXIS_DDRCLK_133 0x3 43 #define QIXIS_DDRCLK_133 0x3
32 44
33 45
34 #define QIXIS_SRDS1CLK_122 0x5a 46 #define QIXIS_SRDS1CLK_122 0x5a
35 #define QIXIS_SRDS1CLK_125 0x5e 47 #define QIXIS_SRDS1CLK_125 0x5e
36 #endif 48 #endif
37 49
board/freescale/t104xrdb/ddr.c
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <i2c.h> 8 #include <i2c.h>
9 #include <hwconfig.h> 9 #include <hwconfig.h>
10 #include <asm/mmu.h> 10 #include <asm/mmu.h>
11 #include <fsl_ddr_sdram.h> 11 #include <fsl_ddr_sdram.h>
12 #include <fsl_ddr_dimm_params.h> 12 #include <fsl_ddr_dimm_params.h>
13 #include <asm/fsl_law.h> 13 #include <asm/fsl_law.h>
14 #include "ddr.h" 14 #include "ddr.h"
15 15
16 DECLARE_GLOBAL_DATA_PTR; 16 DECLARE_GLOBAL_DATA_PTR;
17 17
18 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, 18 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
19 unsigned int controller_number, 19 unsigned int controller_number,
20 unsigned int dimm_number) 20 unsigned int dimm_number)
21 { 21 {
22 const char dimm_model[] = "RAW timing DDR"; 22 const char dimm_model[] = "RAW timing DDR";
23 23
24 if ((controller_number == 0) && (dimm_number == 0)) { 24 if ((controller_number == 0) && (dimm_number == 0)) {
25 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); 25 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
26 memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); 26 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
27 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); 27 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
28 } 28 }
29 29
30 return 0; 30 return 0;
31 } 31 }
32 32
33 void fsl_ddr_board_options(memctl_options_t *popts, 33 void fsl_ddr_board_options(memctl_options_t *popts,
34 dimm_params_t *pdimm, 34 dimm_params_t *pdimm,
35 unsigned int ctrl_num) 35 unsigned int ctrl_num)
36 { 36 {
37 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; 37 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
38 ulong ddr_freq; 38 ulong ddr_freq;
39 39
40 if (ctrl_num > 1) { 40 if (ctrl_num > 1) {
41 printf("Not supported controller number %d\n", ctrl_num); 41 printf("Not supported controller number %d\n", ctrl_num);
42 return; 42 return;
43 } 43 }
44 if (!pdimm->n_ranks) 44 if (!pdimm->n_ranks)
45 return; 45 return;
46 46
47 pbsp = udimms[0]; 47 pbsp = udimms[0];
48 48
49 /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr 49 /* Get clk_adjust according to the board ddr
50 * freqency and n_banks specified in board_specific_parameters table. 50 * freqency and n_banks specified in board_specific_parameters table.
51 */ 51 */
52 ddr_freq = get_ddr_freq(0) / 1000000; 52 ddr_freq = get_ddr_freq(0) / 1000000;
53 while (pbsp->datarate_mhz_high) { 53 while (pbsp->datarate_mhz_high) {
54 if (pbsp->n_ranks == pdimm->n_ranks && 54 if (pbsp->n_ranks == pdimm->n_ranks &&
55 (pdimm->rank_density >> 30) >= pbsp->rank_gb) { 55 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
56 if (ddr_freq <= pbsp->datarate_mhz_high) { 56 if (ddr_freq <= pbsp->datarate_mhz_high) {
57 popts->cpo_override = pbsp->cpo;
58 popts->write_data_delay =
59 pbsp->write_data_delay;
60 popts->clk_adjust = pbsp->clk_adjust; 57 popts->clk_adjust = pbsp->clk_adjust;
61 popts->wrlvl_start = pbsp->wrlvl_start; 58 popts->wrlvl_start = pbsp->wrlvl_start;
62 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 59 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
63 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 60 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
64 popts->twot_en = pbsp->force_2t;
65 goto found; 61 goto found;
66 } 62 }
67 pbsp_highest = pbsp; 63 pbsp_highest = pbsp;
68 } 64 }
69 pbsp++; 65 pbsp++;
70 } 66 }
71 67
72 if (pbsp_highest) { 68 if (pbsp_highest) {
73 printf("Error: board specific timing not found\n"); 69 printf("Error: board specific timing not found\n");
74 printf("for data rate %lu MT/s\n", ddr_freq); 70 printf("for data rate %lu MT/s\n", ddr_freq);
75 printf("Trying to use the highest speed (%u) parameters\n", 71 printf("Trying to use the highest speed (%u) parameters\n",
76 pbsp_highest->datarate_mhz_high); 72 pbsp_highest->datarate_mhz_high);
77 popts->cpo_override = pbsp_highest->cpo;
78 popts->write_data_delay = pbsp_highest->write_data_delay;
79 popts->clk_adjust = pbsp_highest->clk_adjust; 73 popts->clk_adjust = pbsp_highest->clk_adjust;
80 popts->wrlvl_start = pbsp_highest->wrlvl_start; 74 popts->wrlvl_start = pbsp_highest->wrlvl_start;
81 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; 75 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
82 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; 76 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
83 popts->twot_en = pbsp_highest->force_2t;
84 } else { 77 } else {
85 panic("DIMM is not supported by this board"); 78 panic("DIMM is not supported by this board");
86 } 79 }
87 found: 80 found:
88 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" 81 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
89 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, " 82 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
90 "wrlvl_ctrl_3 0x%x\n", 83 "wrlvl_ctrl_3 0x%x\n",
91 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, 84 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
92 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, 85 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
93 pbsp->wrlvl_ctl_3); 86 pbsp->wrlvl_ctl_3);
94 87
95 /* 88 /*
96 * Factors to consider for half-strength driver enable: 89 * Factors to consider for half-strength driver enable:
97 * - number of DIMMs installed 90 * - number of DIMMs installed
98 */ 91 */
99 popts->half_strength_driver_enable = 0; 92 popts->half_strength_driver_enable = 0;
100 /* 93 /*
101 * Write leveling override 94 * Write leveling override
102 */ 95 */
103 popts->wrlvl_override = 1; 96 popts->wrlvl_override = 1;
104 popts->wrlvl_sample = 0xf; 97 popts->wrlvl_sample = 0xf;
105 98
106 /* 99 /*
107 * rtt and rtt_wr override 100 * rtt and rtt_wr override
108 */ 101 */
109 popts->rtt_override = 0; 102 popts->rtt_override = 0;
110 103
111 /* Enable ZQ calibration */ 104 /* Enable ZQ calibration */
112 popts->zq_en = 1; 105 popts->zq_en = 1;
113 106
114 /* DHC_EN =1, ODT = 75 Ohm */ 107 /* DHC_EN =1, ODT = 75 Ohm */
115 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); 108 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
116 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); 109 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
117 } 110 }
118 111
119 phys_size_t initdram(int board_type) 112 phys_size_t initdram(int board_type)
120 { 113 {
121 phys_size_t dram_size; 114 phys_size_t dram_size;
122 115
123 puts("Initializing....using SPD\n"); 116 puts("Initializing....using SPD\n");
124 117
125 dram_size = fsl_ddr_sdram(); 118 dram_size = fsl_ddr_sdram();
126 119
127 dram_size = setup_ddr_tlbs(dram_size / 0x100000); 120 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
128 dram_size *= 0x100000; 121 dram_size *= 0x100000;
129 122
130 puts(" DDR: "); 123 puts(" DDR: ");
131 return dram_size; 124 return dram_size;
132 } 125 }
133 126
board/freescale/t104xrdb/ddr.h
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #ifndef __DDR_H__ 7 #ifndef __DDR_H__
8 #define __DDR_H__ 8 #define __DDR_H__
9
10 dimm_params_t ddr_raw_timing = { 9 dimm_params_t ddr_raw_timing = {
11 .n_ranks = 2, 10 .n_ranks = 2,
12 .rank_density = 2147483648u, 11 .rank_density = 2147483648u,
13 .capacity = 4294967296u, 12 .capacity = 4294967296u,
14 .primary_sdram_width = 64, 13 .primary_sdram_width = 64,
15 .ec_sdram_width = 8, 14 .ec_sdram_width = 8,
16 .registered_dimm = 0, 15 .registered_dimm = 0,
17 .mirrored_dimm = 1, 16 .mirrored_dimm = 0,
18 .n_row_addr = 15, 17 .n_row_addr = 15,
19 .n_col_addr = 10, 18 .n_col_addr = 10,
20 .n_banks_per_sdram_device = 8, 19 .n_banks_per_sdram_device = 8,
21 .edc_config = 2, /* ECC */ 20 .edc_config = 2, /* ECC */
22 .burst_lengths_bitmask = 0x0c, 21 .burst_lengths_bitmask = 0x0c,
23
24 .tckmin_x_ps = 1071, 22 .tckmin_x_ps = 1071,
25 .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ 23 .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */
26 .taa_ps = 13910, 24 .taa_ps = 13125,
27 .twr_ps = 15000, 25 .twr_ps = 15000,
28 .trcd_ps = 13910, 26 .trcd_ps = 13125,
29 .trrd_ps = 6000, 27 .trrd_ps = 6000,
30 .trp_ps = 13910, 28 .trp_ps = 13125,
31 .tras_ps = 34000, 29 .tras_ps = 34000,
32 .trc_ps = 48910, 30 .trc_ps = 48125,
33 .trfc_ps = 260000, 31 .trfc_ps = 260000,
34 .twtr_ps = 7500, 32 .twtr_ps = 7500,
35 .trtp_ps = 7500, 33 .trtp_ps = 7500,
36 .refresh_rate_ps = 7800000, 34 .refresh_rate_ps = 7800000,
37 .tfaw_ps = 35000, 35 .tfaw_ps = 35000,
38 }; 36 };
39 37
40 struct board_specific_parameters { 38 struct board_specific_parameters {
41 u32 n_ranks; 39 u32 n_ranks;
42 u32 datarate_mhz_high; 40 u32 datarate_mhz_high;
43 u32 rank_gb; 41 u32 rank_gb;
44 u32 clk_adjust; 42 u32 clk_adjust;
45 u32 wrlvl_start; 43 u32 wrlvl_start;
46 u32 wrlvl_ctl_2; 44 u32 wrlvl_ctl_2;
47 u32 wrlvl_ctl_3; 45 u32 wrlvl_ctl_3;
48 u32 cpo;
49 u32 write_data_delay;
50 u32 force_2t;
51 }; 46 };
52 47
53 /* 48 /*
54 * These tables contain all valid speeds we want to override with board 49 * These tables contain all valid speeds we want to override with board
55 * specific parameters. datarate_mhz_high values need to be in ascending order 50 * specific parameters. datarate_mhz_high values need to be in ascending order
56 * for each n_ranks group. 51 * for each n_ranks group.
57 */ 52 */
58 53
59 static const struct board_specific_parameters udimm0[] = { 54 static const struct board_specific_parameters udimm0[] = {
60 /* 55 /*
61 * memory controller 0 56 * memory controller 0
62 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T 57 * num| hi| rank| clk| wrlvl | wrlvl
63 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | 58 * ranks| mhz| GB |adjst| start | ctl2
64 */ 59 */
65 {2, 1066, 4, 8, 4, 0x05070609, 0x08090a08, 0xff, 2, 0}, 60 {2, 833, 4, 4, 6, 0x06060607, 0x08080807},
66 {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, 61 {2, 833, 0, 4, 6, 0x06060607, 0x08080807},
67 {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, 62 {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
68 {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, 63 {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
69 {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, 64 {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
65 {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
66 {1, 833, 4, 4, 6, 0x06060607, 0x08080807},
67 {1, 833, 0, 4, 6, 0x06060607, 0x08080807},
68 {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
69 {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
70 {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
71 {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
70 {} 72 {}
71 }; 73 };
72 74
board/freescale/t208xqds/eth_t208xqds.c
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * Shengzhou Liu <Shengzhou.Liu@freescale.com> 4 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #include <common.h> 9 #include <common.h>
10 #include <command.h> 10 #include <command.h>
11 #include <netdev.h> 11 #include <netdev.h>
12 #include <asm/mmu.h> 12 #include <asm/mmu.h>
13 #include <asm/processor.h> 13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h> 14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h> 15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h> 16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h> 17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h> 18 #include <asm/fsl_liodn.h>
19 #include <malloc.h> 19 #include <malloc.h>
20 #include <fm_eth.h> 20 #include <fm_eth.h>
21 #include <fsl_mdio.h> 21 #include <fsl_mdio.h>
22 #include <miiphy.h> 22 #include <miiphy.h>
23 #include <phy.h> 23 #include <phy.h>
24 #include <asm/fsl_dtsec.h> 24 #include <asm/fsl_dtsec.h>
25 #include <asm/fsl_serdes.h> 25 #include <asm/fsl_serdes.h>
26 #include "../common/qixis.h" 26 #include "../common/qixis.h"
27 #include "../common/fman.h" 27 #include "../common/fman.h"
28 #include "t208xqds_qixis.h" 28 #include "t208xqds_qixis.h"
29 29
30 #define EMI_NONE 0xFFFFFFFF 30 #define EMI_NONE 0xFFFFFFFF
31 #define EMI1_RGMII1 0 31 #define EMI1_RGMII1 0
32 #define EMI1_RGMII2 1 32 #define EMI1_RGMII2 1
33 #define EMI1_SLOT1 2 33 #define EMI1_SLOT1 2
34 #if defined(CONFIG_T2080QDS) 34 #if defined(CONFIG_T2080QDS)
35 #define EMI1_SLOT2 6 35 #define EMI1_SLOT2 6
36 #define EMI1_SLOT3 3 36 #define EMI1_SLOT3 3
37 #define EMI1_SLOT4 4 37 #define EMI1_SLOT4 4
38 #define EMI1_SLOT5 5 38 #define EMI1_SLOT5 5
39 #define EMI2 7
39 #elif defined(CONFIG_T2081QDS) 40 #elif defined(CONFIG_T2081QDS)
40 #define EMI1_SLOT2 3 41 #define EMI1_SLOT2 3
41 #define EMI1_SLOT3 4 42 #define EMI1_SLOT3 4
42 #define EMI1_SLOT5 5 43 #define EMI1_SLOT5 5
43 #define EMI1_SLOT6 6 44 #define EMI1_SLOT6 6
44 #define EMI1_SLOT7 7 45 #define EMI1_SLOT7 7
45 #endif
46 #define EMI2 8 46 #define EMI2 8
47 #endif
47 48
48 static int mdio_mux[NUM_FM_PORTS]; 49 static int mdio_mux[NUM_FM_PORTS];
49 50
50 static const char * const mdio_names[] = { 51 static const char * const mdio_names[] = {
51 #if defined(CONFIG_T2080QDS) 52 #if defined(CONFIG_T2080QDS)
52 "T2080QDS_MDIO_RGMII1", 53 "T2080QDS_MDIO_RGMII1",
53 "T2080QDS_MDIO_RGMII2", 54 "T2080QDS_MDIO_RGMII2",
54 "T2080QDS_MDIO_SLOT1", 55 "T2080QDS_MDIO_SLOT1",
55 "T2080QDS_MDIO_SLOT3", 56 "T2080QDS_MDIO_SLOT3",
56 "T2080QDS_MDIO_SLOT4", 57 "T2080QDS_MDIO_SLOT4",
57 "T2080QDS_MDIO_SLOT5", 58 "T2080QDS_MDIO_SLOT5",
58 "T2080QDS_MDIO_SLOT2", 59 "T2080QDS_MDIO_SLOT2",
59 "T2080QDS_MDIO_10GC", 60 "T2080QDS_MDIO_10GC",
60 #elif defined(CONFIG_T2081QDS) 61 #elif defined(CONFIG_T2081QDS)
61 "T2081QDS_MDIO_RGMII1", 62 "T2081QDS_MDIO_RGMII1",
62 "T2081QDS_MDIO_RGMII2", 63 "T2081QDS_MDIO_RGMII2",
63 "T2081QDS_MDIO_SLOT1", 64 "T2081QDS_MDIO_SLOT1",
64 "T2081QDS_MDIO_SLOT2", 65 "T2081QDS_MDIO_SLOT2",
65 "T2081QDS_MDIO_SLOT3", 66 "T2081QDS_MDIO_SLOT3",
66 "T2081QDS_MDIO_SLOT5", 67 "T2081QDS_MDIO_SLOT5",
67 "T2081QDS_MDIO_SLOT6", 68 "T2081QDS_MDIO_SLOT6",
68 "T2081QDS_MDIO_SLOT7", 69 "T2081QDS_MDIO_SLOT7",
69 "T2081QDS_MDIO_10GC", 70 "T2081QDS_MDIO_10GC",
70 #endif 71 #endif
71 }; 72 };
72 73
73 /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */ 74 /* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
74 #if defined(CONFIG_T2080QDS) 75 #if defined(CONFIG_T2080QDS)
75 static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1}; 76 static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
76 #elif defined(CONFIG_T2081QDS) 77 #elif defined(CONFIG_T2081QDS)
77 static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1}; 78 static u8 lane_to_slot[] = {2, 2, 2, 2, 1, 1, 1, 1};
78 #endif 79 #endif
79 80
80 static const char *t208xqds_mdio_name_for_muxval(u8 muxval) 81 static const char *t208xqds_mdio_name_for_muxval(u8 muxval)
81 { 82 {
82 return mdio_names[muxval]; 83 return mdio_names[muxval];
83 } 84 }
84 85
85 struct mii_dev *mii_dev_for_muxval(u8 muxval) 86 struct mii_dev *mii_dev_for_muxval(u8 muxval)
86 { 87 {
87 struct mii_dev *bus; 88 struct mii_dev *bus;
88 const char *name = t208xqds_mdio_name_for_muxval(muxval); 89 const char *name = t208xqds_mdio_name_for_muxval(muxval);
89 90
90 if (!name) { 91 if (!name) {
91 printf("No bus for muxval %x\n", muxval); 92 printf("No bus for muxval %x\n", muxval);
92 return NULL; 93 return NULL;
93 } 94 }
94 95
95 bus = miiphy_get_dev_by_name(name); 96 bus = miiphy_get_dev_by_name(name);
96 97
97 if (!bus) { 98 if (!bus) {
98 printf("No bus by name %s\n", name); 99 printf("No bus by name %s\n", name);
99 return NULL; 100 return NULL;
100 } 101 }
101 102
102 return bus; 103 return bus;
103 } 104 }
104 105
105 struct t208xqds_mdio { 106 struct t208xqds_mdio {
106 u8 muxval; 107 u8 muxval;
107 struct mii_dev *realbus; 108 struct mii_dev *realbus;
108 }; 109 };
109 110
110 static void t208xqds_mux_mdio(u8 muxval) 111 static void t208xqds_mux_mdio(u8 muxval)
111 { 112 {
112 u8 brdcfg4; 113 u8 brdcfg4;
113 if (muxval < 8) { 114 if (muxval < 8) {
114 brdcfg4 = QIXIS_READ(brdcfg[4]); 115 brdcfg4 = QIXIS_READ(brdcfg[4]);
115 brdcfg4 &= ~BRDCFG4_EMISEL_MASK; 116 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
116 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT); 117 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
117 QIXIS_WRITE(brdcfg[4], brdcfg4); 118 QIXIS_WRITE(brdcfg[4], brdcfg4);
118 } 119 }
119 } 120 }
120 121
121 static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad, 122 static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,
122 int regnum) 123 int regnum)
123 { 124 {
124 struct t208xqds_mdio *priv = bus->priv; 125 struct t208xqds_mdio *priv = bus->priv;
125 126
126 t208xqds_mux_mdio(priv->muxval); 127 t208xqds_mux_mdio(priv->muxval);
127 128
128 return priv->realbus->read(priv->realbus, addr, devad, regnum); 129 return priv->realbus->read(priv->realbus, addr, devad, regnum);
129 } 130 }
130 131
131 static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad, 132 static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,
132 int regnum, u16 value) 133 int regnum, u16 value)
133 { 134 {
134 struct t208xqds_mdio *priv = bus->priv; 135 struct t208xqds_mdio *priv = bus->priv;
135 136
136 t208xqds_mux_mdio(priv->muxval); 137 t208xqds_mux_mdio(priv->muxval);
137 138
138 return priv->realbus->write(priv->realbus, addr, devad, regnum, value); 139 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
139 } 140 }
140 141
141 static int t208xqds_mdio_reset(struct mii_dev *bus) 142 static int t208xqds_mdio_reset(struct mii_dev *bus)
142 { 143 {
143 struct t208xqds_mdio *priv = bus->priv; 144 struct t208xqds_mdio *priv = bus->priv;
144 145
145 return priv->realbus->reset(priv->realbus); 146 return priv->realbus->reset(priv->realbus);
146 } 147 }
147 148
148 static int t208xqds_mdio_init(char *realbusname, u8 muxval) 149 static int t208xqds_mdio_init(char *realbusname, u8 muxval)
149 { 150 {
150 struct t208xqds_mdio *pmdio; 151 struct t208xqds_mdio *pmdio;
151 struct mii_dev *bus = mdio_alloc(); 152 struct mii_dev *bus = mdio_alloc();
152 153
153 if (!bus) { 154 if (!bus) {
154 printf("Failed to allocate t208xqds MDIO bus\n"); 155 printf("Failed to allocate t208xqds MDIO bus\n");
155 return -1; 156 return -1;
156 } 157 }
157 158
158 pmdio = malloc(sizeof(*pmdio)); 159 pmdio = malloc(sizeof(*pmdio));
159 if (!pmdio) { 160 if (!pmdio) {
160 printf("Failed to allocate t208xqds private data\n"); 161 printf("Failed to allocate t208xqds private data\n");
161 free(bus); 162 free(bus);
162 return -1; 163 return -1;
163 } 164 }
164 165
165 bus->read = t208xqds_mdio_read; 166 bus->read = t208xqds_mdio_read;
166 bus->write = t208xqds_mdio_write; 167 bus->write = t208xqds_mdio_write;
167 bus->reset = t208xqds_mdio_reset; 168 bus->reset = t208xqds_mdio_reset;
168 sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval)); 169 sprintf(bus->name, t208xqds_mdio_name_for_muxval(muxval));
169 170
170 pmdio->realbus = miiphy_get_dev_by_name(realbusname); 171 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
171 172
172 if (!pmdio->realbus) { 173 if (!pmdio->realbus) {
173 printf("No bus with name %s\n", realbusname); 174 printf("No bus with name %s\n", realbusname);
174 free(bus); 175 free(bus);
175 free(pmdio); 176 free(pmdio);
176 return -1; 177 return -1;
177 } 178 }
178 179
179 pmdio->muxval = muxval; 180 pmdio->muxval = muxval;
180 bus->priv = pmdio; 181 bus->priv = pmdio;
181 return mdio_register(bus); 182 return mdio_register(bus);
182 } 183 }
183 184
184 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, 185 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
185 enum fm_port port, int offset) 186 enum fm_port port, int offset)
186 { 187 {
187 int phy; 188 int phy;
188 char alias[20]; 189 char alias[20];
189 struct fixed_link f_link; 190 struct fixed_link f_link;
190 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 191 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
191 u32 srds_s1 = in_be32(&gur->rcwsr[4]) & 192 u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
192 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 193 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
193 194
194 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 195 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
195 196
196 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { 197 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
197 phy = fm_info_get_phy_address(port); 198 phy = fm_info_get_phy_address(port);
198 switch (port) { 199 switch (port) {
199 #if defined(CONFIG_T2080QDS) 200 #if defined(CONFIG_T2080QDS)
200 case FM1_DTSEC1: 201 case FM1_DTSEC1:
201 case FM1_DTSEC2: 202 case FM1_DTSEC2:
202 case FM1_DTSEC9: 203 case FM1_DTSEC9:
203 case FM1_DTSEC10: 204 case FM1_DTSEC10:
204 if (mdio_mux[port] == EMI1_SLOT2) { 205 if (mdio_mux[port] == EMI1_SLOT2) {
205 sprintf(alias, "phy_sgmii_s2_%x", phy); 206 sprintf(alias, "phy_sgmii_s2_%x", phy);
206 fdt_set_phy_handle(fdt, compat, addr, alias); 207 fdt_set_phy_handle(fdt, compat, addr, alias);
207 fdt_status_okay_by_alias(fdt, "emi1_slot2"); 208 fdt_status_okay_by_alias(fdt, "emi1_slot2");
208 } else if (mdio_mux[port] == EMI1_SLOT3) { 209 } else if (mdio_mux[port] == EMI1_SLOT3) {
209 sprintf(alias, "phy_sgmii_s3_%x", phy); 210 sprintf(alias, "phy_sgmii_s3_%x", phy);
210 fdt_set_phy_handle(fdt, compat, addr, alias); 211 fdt_set_phy_handle(fdt, compat, addr, alias);
211 fdt_status_okay_by_alias(fdt, "emi1_slot3"); 212 fdt_status_okay_by_alias(fdt, "emi1_slot3");
212 } 213 }
213 break; 214 break;
214 case FM1_DTSEC5: 215 case FM1_DTSEC5:
215 case FM1_DTSEC6: 216 case FM1_DTSEC6:
216 if (mdio_mux[port] == EMI1_SLOT1) { 217 if (mdio_mux[port] == EMI1_SLOT1) {
217 sprintf(alias, "phy_sgmii_s1_%x", phy); 218 sprintf(alias, "phy_sgmii_s1_%x", phy);
218 fdt_set_phy_handle(fdt, compat, addr, alias); 219 fdt_set_phy_handle(fdt, compat, addr, alias);
219 fdt_status_okay_by_alias(fdt, "emi1_slot1"); 220 fdt_status_okay_by_alias(fdt, "emi1_slot1");
220 } else if (mdio_mux[port] == EMI1_SLOT2) { 221 } else if (mdio_mux[port] == EMI1_SLOT2) {
221 sprintf(alias, "phy_sgmii_s2_%x", phy); 222 sprintf(alias, "phy_sgmii_s2_%x", phy);
222 fdt_set_phy_handle(fdt, compat, addr, alias); 223 fdt_set_phy_handle(fdt, compat, addr, alias);
223 fdt_status_okay_by_alias(fdt, "emi1_slot2"); 224 fdt_status_okay_by_alias(fdt, "emi1_slot2");
224 } 225 }
225 break; 226 break;
226 #elif defined(CONFIG_T2081QDS) 227 #elif defined(CONFIG_T2081QDS)
227 case FM1_DTSEC1: 228 case FM1_DTSEC1:
228 case FM1_DTSEC2: 229 case FM1_DTSEC2:
229 case FM1_DTSEC5: 230 case FM1_DTSEC5:
230 case FM1_DTSEC6: 231 case FM1_DTSEC6:
231 case FM1_DTSEC9: 232 case FM1_DTSEC9:
232 case FM1_DTSEC10: 233 case FM1_DTSEC10:
233 if (mdio_mux[port] == EMI1_SLOT2) { 234 if (mdio_mux[port] == EMI1_SLOT2) {
234 sprintf(alias, "phy_sgmii_s2_%x", phy); 235 sprintf(alias, "phy_sgmii_s2_%x", phy);
235 fdt_set_phy_handle(fdt, compat, addr, alias); 236 fdt_set_phy_handle(fdt, compat, addr, alias);
236 fdt_status_okay_by_alias(fdt, "emi1_slot2"); 237 fdt_status_okay_by_alias(fdt, "emi1_slot2");
237 } else if (mdio_mux[port] == EMI1_SLOT3) { 238 } else if (mdio_mux[port] == EMI1_SLOT3) {
238 sprintf(alias, "phy_sgmii_s3_%x", phy); 239 sprintf(alias, "phy_sgmii_s3_%x", phy);
239 fdt_set_phy_handle(fdt, compat, addr, alias); 240 fdt_set_phy_handle(fdt, compat, addr, alias);
240 fdt_status_okay_by_alias(fdt, "emi1_slot3"); 241 fdt_status_okay_by_alias(fdt, "emi1_slot3");
241 } else if (mdio_mux[port] == EMI1_SLOT5) { 242 } else if (mdio_mux[port] == EMI1_SLOT5) {
242 sprintf(alias, "phy_sgmii_s5_%x", phy); 243 sprintf(alias, "phy_sgmii_s5_%x", phy);
243 fdt_set_phy_handle(fdt, compat, addr, alias); 244 fdt_set_phy_handle(fdt, compat, addr, alias);
244 fdt_status_okay_by_alias(fdt, "emi1_slot5"); 245 fdt_status_okay_by_alias(fdt, "emi1_slot5");
245 } else if (mdio_mux[port] == EMI1_SLOT6) { 246 } else if (mdio_mux[port] == EMI1_SLOT6) {
246 sprintf(alias, "phy_sgmii_s6_%x", phy); 247 sprintf(alias, "phy_sgmii_s6_%x", phy);
247 fdt_set_phy_handle(fdt, compat, addr, alias); 248 fdt_set_phy_handle(fdt, compat, addr, alias);
248 fdt_status_okay_by_alias(fdt, "emi1_slot6"); 249 fdt_status_okay_by_alias(fdt, "emi1_slot6");
249 } else if (mdio_mux[port] == EMI1_SLOT7) { 250 } else if (mdio_mux[port] == EMI1_SLOT7) {
250 sprintf(alias, "phy_sgmii_s7_%x", phy); 251 sprintf(alias, "phy_sgmii_s7_%x", phy);
251 fdt_set_phy_handle(fdt, compat, addr, alias); 252 fdt_set_phy_handle(fdt, compat, addr, alias);
252 fdt_status_okay_by_alias(fdt, "emi1_slot7"); 253 fdt_status_okay_by_alias(fdt, "emi1_slot7");
253 } 254 }
254 break; 255 break;
255 #endif 256 #endif
256 default: 257 default:
257 break; 258 break;
258 } 259 }
259 260
260 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { 261 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
261 switch (srds_s1) { 262 switch (srds_s1) {
262 case 0x66: /* XFI interface */ 263 case 0x66: /* XFI interface */
263 case 0x6b: 264 case 0x6b:
264 case 0x6c: 265 case 0x6c:
265 case 0x6d: 266 case 0x6d:
266 case 0x71: 267 case 0x71:
267 f_link.phy_id = port; 268 f_link.phy_id = port;
268 f_link.duplex = 1; 269 f_link.duplex = 1;
269 f_link.link_speed = 10000; 270 f_link.link_speed = 10000;
270 f_link.pause = 0; 271 f_link.pause = 0;
271 f_link.asym_pause = 0; 272 f_link.asym_pause = 0;
272 /* no PHY for XFI */ 273 /* no PHY for XFI */
273 fdt_delprop(fdt, offset, "phy-handle"); 274 fdt_delprop(fdt, offset, "phy-handle");
274 fdt_setprop(fdt, offset, "fixed-link", &f_link, 275 fdt_setprop(fdt, offset, "fixed-link", &f_link,
275 sizeof(f_link)); 276 sizeof(f_link));
276 break; 277 break;
277 default: 278 default:
278 break; 279 break;
279 } 280 }
280 } 281 }
281 } 282 }
282 283
283 void fdt_fixup_board_enet(void *fdt) 284 void fdt_fixup_board_enet(void *fdt)
284 { 285 {
285 return; 286 return;
286 } 287 }
287 288
288 /* 289 /*
289 * This function reads RCW to check if Serdes1{A:H} is configured 290 * This function reads RCW to check if Serdes1{A:H} is configured
290 * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly 291 * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly
291 */ 292 */
292 static void initialize_lane_to_slot(void) 293 static void initialize_lane_to_slot(void)
293 { 294 {
294 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 295 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
295 u32 srds_s1 = in_be32(&gur->rcwsr[4]) & 296 u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
296 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 297 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
297 298
298 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 299 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
299 300
300 switch (srds_s1) { 301 switch (srds_s1) {
301 #if defined(CONFIG_T2080QDS) 302 #if defined(CONFIG_T2080QDS)
302 case 0x51: 303 case 0x51:
303 case 0x5f: 304 case 0x5f:
304 case 0x65: 305 case 0x65:
305 case 0x6b: 306 case 0x6b:
306 case 0x71: 307 case 0x71:
307 lane_to_slot[5] = 2; 308 lane_to_slot[5] = 2;
308 lane_to_slot[6] = 2; 309 lane_to_slot[6] = 2;
309 lane_to_slot[7] = 2; 310 lane_to_slot[7] = 2;
310 break; 311 break;
311 case 0xa6: 312 case 0xa6:
312 case 0x8e: 313 case 0x8e:
313 case 0x8f: 314 case 0x8f:
314 case 0x82: 315 case 0x82:
315 case 0x83: 316 case 0x83:
316 case 0xd3: 317 case 0xd3:
317 case 0xd9: 318 case 0xd9:
318 case 0xcb: 319 case 0xcb:
319 lane_to_slot[6] = 2; 320 lane_to_slot[6] = 2;
320 lane_to_slot[7] = 2; 321 lane_to_slot[7] = 2;
321 break; 322 break;
322 case 0xda: 323 case 0xda:
323 lane_to_slot[4] = 3; 324 lane_to_slot[4] = 3;
324 lane_to_slot[5] = 3; 325 lane_to_slot[5] = 3;
325 lane_to_slot[6] = 3; 326 lane_to_slot[6] = 3;
326 lane_to_slot[7] = 3; 327 lane_to_slot[7] = 3;
327 break; 328 break;
328 #elif defined(CONFIG_T2081QDS) 329 #elif defined(CONFIG_T2081QDS)
329 case 0x6b: 330 case 0x6b:
330 lane_to_slot[4] = 1; 331 lane_to_slot[4] = 1;
331 lane_to_slot[5] = 3; 332 lane_to_slot[5] = 3;
332 lane_to_slot[6] = 3; 333 lane_to_slot[6] = 3;
333 lane_to_slot[7] = 3; 334 lane_to_slot[7] = 3;
334 break; 335 break;
335 case 0xca: 336 case 0xca:
336 case 0xcb: 337 case 0xcb:
337 lane_to_slot[1] = 7; 338 lane_to_slot[1] = 7;
338 lane_to_slot[2] = 6; 339 lane_to_slot[2] = 6;
339 lane_to_slot[3] = 5; 340 lane_to_slot[3] = 5;
340 lane_to_slot[5] = 3; 341 lane_to_slot[5] = 3;
341 lane_to_slot[6] = 3; 342 lane_to_slot[6] = 3;
342 lane_to_slot[7] = 3; 343 lane_to_slot[7] = 3;
343 break; 344 break;
344 case 0xf2: 345 case 0xf2:
345 lane_to_slot[1] = 7; 346 lane_to_slot[1] = 7;
346 lane_to_slot[2] = 7; 347 lane_to_slot[2] = 7;
347 lane_to_slot[3] = 7; 348 lane_to_slot[3] = 7;
348 lane_to_slot[5] = 4; 349 lane_to_slot[5] = 4;
349 lane_to_slot[6] = 3; 350 lane_to_slot[6] = 3;
350 lane_to_slot[7] = 7; 351 lane_to_slot[7] = 7;
351 break; 352 break;
352 #endif 353 #endif
353 default: 354 default:
354 break; 355 break;
355 } 356 }
356 } 357 }
357 358
358 int board_eth_init(bd_t *bis) 359 int board_eth_init(bd_t *bis)
359 { 360 {
360 #if defined(CONFIG_FMAN_ENET) 361 #if defined(CONFIG_FMAN_ENET)
361 int i, idx, lane, slot, interface; 362 int i, idx, lane, slot, interface;
362 struct memac_mdio_info dtsec_mdio_info; 363 struct memac_mdio_info dtsec_mdio_info;
363 struct memac_mdio_info tgec_mdio_info; 364 struct memac_mdio_info tgec_mdio_info;
364 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); 365 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
365 u32 rcwsr13 = in_be32(&gur->rcwsr[13]); 366 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
366 u32 srds_s1; 367 u32 srds_s1;
367 368
368 srds_s1 = in_be32(&gur->rcwsr[4]) & 369 srds_s1 = in_be32(&gur->rcwsr[4]) &
369 FSL_CORENET2_RCWSR4_SRDS1_PRTCL; 370 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
370 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; 371 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
371 372
372 initialize_lane_to_slot(); 373 initialize_lane_to_slot();
373 374
374 /* Initialize the mdio_mux array so we can recognize empty elements */ 375 /* Initialize the mdio_mux array so we can recognize empty elements */
375 for (i = 0; i < NUM_FM_PORTS; i++) 376 for (i = 0; i < NUM_FM_PORTS; i++)
376 mdio_mux[i] = EMI_NONE; 377 mdio_mux[i] = EMI_NONE;
377 378
378 dtsec_mdio_info.regs = 379 dtsec_mdio_info.regs =
379 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; 380 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
380 381
381 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 382 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
382 383
383 /* Register the 1G MDIO bus */ 384 /* Register the 1G MDIO bus */
384 fm_memac_mdio_init(bis, &dtsec_mdio_info); 385 fm_memac_mdio_init(bis, &dtsec_mdio_info);
385 386
386 tgec_mdio_info.regs = 387 tgec_mdio_info.regs =
387 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; 388 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
388 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; 389 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
389 390
390 /* Register the 10G MDIO bus */ 391 /* Register the 10G MDIO bus */
391 fm_memac_mdio_init(bis, &tgec_mdio_info); 392 fm_memac_mdio_init(bis, &tgec_mdio_info);
392 393
393 /* Register the muxing front-ends to the MDIO buses */ 394 /* Register the muxing front-ends to the MDIO buses */
394 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1); 395 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
395 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2); 396 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
396 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1); 397 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
397 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2); 398 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
398 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3); 399 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
399 #if defined(CONFIG_T2080QDS) 400 #if defined(CONFIG_T2080QDS)
400 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4); 401 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
401 #endif 402 #endif
402 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5); 403 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
403 #if defined(CONFIG_T2081QDS) 404 #if defined(CONFIG_T2081QDS)
404 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6); 405 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
405 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7); 406 t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
406 #endif 407 #endif
407 t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2); 408 t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
408 409
409 /* Set the two on-board RGMII PHY address */ 410 /* Set the two on-board RGMII PHY address */
410 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR); 411 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
411 if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 412 if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
412 FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII) 413 FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
413 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR); 414 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
414 else 415 else
415 fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR); 416 fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
416 417
417 switch (srds_s1) { 418 switch (srds_s1) {
418 case 0x1c: 419 case 0x1c:
419 case 0x95: 420 case 0x95:
420 case 0xa2: 421 case 0xa2:
421 case 0x94: 422 case 0x94:
422 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */ 423 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
423 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); 424 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
424 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); 425 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
425 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); 426 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
426 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); 427 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
427 /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */ 428 /* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
428 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); 429 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
429 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); 430 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
430 break; 431 break;
431 case 0x51: 432 case 0x51:
432 case 0x5f: 433 case 0x5f:
433 case 0x65: 434 case 0x65:
434 /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */ 435 /* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
435 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); 436 fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
436 /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ 437 /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
437 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); 438 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
438 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); 439 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
439 break; 440 break;
440 case 0x66: 441 case 0x66:
441 /* 442 /*
442 * XFI does not need a PHY to work, but to avoid U-boot use 443 * XFI does not need a PHY to work, but to avoid U-boot use
443 * default PHY address which is zero to a MAC when it found 444 * default PHY address which is zero to a MAC when it found
444 * a MAC has no PHY address, we give a PHY address to XFI 445 * a MAC has no PHY address, we give a PHY address to XFI
445 * MAC, and should not use a real XAUI PHY address, since 446 * MAC, and should not use a real XAUI PHY address, since
446 * MDIO can access it successfully, and then MDIO thinks 447 * MDIO can access it successfully, and then MDIO thinks
447 * the XAUI card is used for the XFI MAC, which will cause 448 * the XAUI card is used for the XFI MAC, which will cause
448 * error. 449 * error.
449 */ 450 */
450 fm_info_set_phy_address(FM1_10GEC1, 4); 451 fm_info_set_phy_address(FM1_10GEC1, 4);
451 fm_info_set_phy_address(FM1_10GEC2, 5); 452 fm_info_set_phy_address(FM1_10GEC2, 5);
452 fm_info_set_phy_address(FM1_10GEC3, 6); 453 fm_info_set_phy_address(FM1_10GEC3, 6);
453 fm_info_set_phy_address(FM1_10GEC4, 7); 454 fm_info_set_phy_address(FM1_10GEC4, 7);
454 break; 455 break;
455 case 0x6b: 456 case 0x6b:
456 fm_info_set_phy_address(FM1_10GEC1, 4); 457 fm_info_set_phy_address(FM1_10GEC1, 4);
457 fm_info_set_phy_address(FM1_10GEC2, 5); 458 fm_info_set_phy_address(FM1_10GEC2, 5);
458 fm_info_set_phy_address(FM1_10GEC3, 6); 459 fm_info_set_phy_address(FM1_10GEC3, 6);
459 fm_info_set_phy_address(FM1_10GEC4, 7); 460 fm_info_set_phy_address(FM1_10GEC4, 7);
460 /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */ 461 /* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
461 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); 462 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
462 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); 463 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
463 break; 464 break;
464 case 0x6c: 465 case 0x6c:
465 case 0x6d: 466 case 0x6d:
466 fm_info_set_phy_address(FM1_10GEC1, 4); 467 fm_info_set_phy_address(FM1_10GEC1, 4);
467 fm_info_set_phy_address(FM1_10GEC2, 5); 468 fm_info_set_phy_address(FM1_10GEC2, 5);
468 /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */ 469 /* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
469 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); 470 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
470 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); 471 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
471 break; 472 break;
472 case 0x71: 473 case 0x71:
473 /* SGMII in Slot3 */ 474 /* SGMII in Slot3 */
474 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); 475 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
475 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); 476 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
476 /* SGMII in Slot2 */ 477 /* SGMII in Slot2 */
477 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); 478 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
478 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); 479 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
479 break; 480 break;
480 case 0xa6: 481 case 0xa6:
481 case 0x8e: 482 case 0x8e:
482 case 0x8f: 483 case 0x8f:
483 case 0x82: 484 case 0x82:
484 case 0x83: 485 case 0x83:
485 /* SGMII in Slot3 */ 486 /* SGMII in Slot3 */
486 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); 487 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
487 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); 488 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
488 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); 489 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
489 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); 490 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
490 /* SGMII in Slot2 */ 491 /* SGMII in Slot2 */
491 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); 492 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
492 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); 493 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
493 break; 494 break;
494 case 0xa4: 495 case 0xa4:
495 case 0x96: 496 case 0x96:
496 case 0x8a: 497 case 0x8a:
497 /* SGMII in Slot3 */ 498 /* SGMII in Slot3 */
498 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR); 499 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
499 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); 500 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
500 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); 501 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
501 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); 502 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
502 break; 503 break;
503 #if defined(CONFIG_T2080QDS) 504 #if defined(CONFIG_T2080QDS)
504 case 0xd9: 505 case 0xd9:
505 case 0xd3: 506 case 0xd3:
506 case 0xcb: 507 case 0xcb:
507 /* SGMII in Slot3 */ 508 /* SGMII in Slot3 */
508 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR); 509 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
509 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR); 510 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
510 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR); 511 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
511 /* SGMII in Slot2 */ 512 /* SGMII in Slot2 */
512 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR); 513 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
513 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); 514 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
514 break; 515 break;
515 #elif defined(CONFIG_T2081QDS) 516 #elif defined(CONFIG_T2081QDS)
516 case 0xca: 517 case 0xca:
517 case 0xcb: 518 case 0xcb:
518 /* SGMII in Slot3 */ 519 /* SGMII in Slot3 */
519 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR); 520 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
520 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR); 521 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
521 /* SGMII in Slot5 */ 522 /* SGMII in Slot5 */
522 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR); 523 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
523 /* SGMII in Slot6 */ 524 /* SGMII in Slot6 */
524 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); 525 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
525 /* SGMII in Slot7 */ 526 /* SGMII in Slot7 */
526 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); 527 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
527 break; 528 break;
528 #endif 529 #endif
529 case 0xf2: 530 case 0xf2:
530 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */ 531 /* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
531 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR); 532 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
532 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR); 533 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
533 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR); 534 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
534 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR); 535 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
535 break; 536 break;
536 default: 537 default:
537 break; 538 break;
538 } 539 }
539 540
540 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 541 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
541 idx = i - FM1_DTSEC1; 542 idx = i - FM1_DTSEC1;
542 interface = fm_info_get_enet_if(i); 543 interface = fm_info_get_enet_if(i);
543 switch (interface) { 544 switch (interface) {
544 case PHY_INTERFACE_MODE_SGMII: 545 case PHY_INTERFACE_MODE_SGMII:
545 lane = serdes_get_first_lane(FSL_SRDS_1, 546 lane = serdes_get_first_lane(FSL_SRDS_1,
546 SGMII_FM1_DTSEC1 + idx); 547 SGMII_FM1_DTSEC1 + idx);
547 if (lane < 0) 548 if (lane < 0)
548 break; 549 break;
549 slot = lane_to_slot[lane]; 550 slot = lane_to_slot[lane];
550 debug("FM1@DTSEC%u expects SGMII in slot %u\n", 551 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
551 idx + 1, slot); 552 idx + 1, slot);
552 if (QIXIS_READ(present2) & (1 << (slot - 1))) 553 if (QIXIS_READ(present2) & (1 << (slot - 1)))
553 fm_disable_port(i); 554 fm_disable_port(i);
554 555
555 switch (slot) { 556 switch (slot) {
556 case 1: 557 case 1:
557 mdio_mux[i] = EMI1_SLOT1; 558 mdio_mux[i] = EMI1_SLOT1;
558 fm_info_set_mdio(i, mii_dev_for_muxval( 559 fm_info_set_mdio(i, mii_dev_for_muxval(
559 mdio_mux[i])); 560 mdio_mux[i]));
560 break; 561 break;
561 case 2: 562 case 2:
562 mdio_mux[i] = EMI1_SLOT2; 563 mdio_mux[i] = EMI1_SLOT2;
563 fm_info_set_mdio(i, mii_dev_for_muxval( 564 fm_info_set_mdio(i, mii_dev_for_muxval(
564 mdio_mux[i])); 565 mdio_mux[i]));
565 break; 566 break;
566 case 3: 567 case 3:
567 mdio_mux[i] = EMI1_SLOT3; 568 mdio_mux[i] = EMI1_SLOT3;
568 fm_info_set_mdio(i, mii_dev_for_muxval( 569 fm_info_set_mdio(i, mii_dev_for_muxval(
569 mdio_mux[i])); 570 mdio_mux[i]));
570 break; 571 break;
571 #if defined(CONFIG_T2081QDS) 572 #if defined(CONFIG_T2081QDS)
572 case 5: 573 case 5:
573 mdio_mux[i] = EMI1_SLOT5; 574 mdio_mux[i] = EMI1_SLOT5;
574 fm_info_set_mdio(i, mii_dev_for_muxval( 575 fm_info_set_mdio(i, mii_dev_for_muxval(
575 mdio_mux[i])); 576 mdio_mux[i]));
576 break; 577 break;
577 case 6: 578 case 6:
578 mdio_mux[i] = EMI1_SLOT6; 579 mdio_mux[i] = EMI1_SLOT6;
579 fm_info_set_mdio(i, mii_dev_for_muxval( 580 fm_info_set_mdio(i, mii_dev_for_muxval(
580 mdio_mux[i])); 581 mdio_mux[i]));
581 break; 582 break;
582 case 7: 583 case 7:
583 mdio_mux[i] = EMI1_SLOT7; 584 mdio_mux[i] = EMI1_SLOT7;
584 fm_info_set_mdio(i, mii_dev_for_muxval( 585 fm_info_set_mdio(i, mii_dev_for_muxval(
585 mdio_mux[i])); 586 mdio_mux[i]));
586 break; 587 break;
587 #endif 588 #endif
588 } 589 }
589 break; 590 break;
590 case PHY_INTERFACE_MODE_RGMII: 591 case PHY_INTERFACE_MODE_RGMII:
591 if (i == FM1_DTSEC3) 592 if (i == FM1_DTSEC3)
592 mdio_mux[i] = EMI1_RGMII1; 593 mdio_mux[i] = EMI1_RGMII1;
593 else if (i == FM1_DTSEC4 || FM1_DTSEC10) 594 else if (i == FM1_DTSEC4 || FM1_DTSEC10)
594 mdio_mux[i] = EMI1_RGMII2; 595 mdio_mux[i] = EMI1_RGMII2;
595 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); 596 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
596 break; 597 break;
597 default: 598 default:
598 break; 599 break;
599 } 600 }
600 } 601 }
601 602
602 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { 603 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
603 idx = i - FM1_10GEC1; 604 idx = i - FM1_10GEC1;
604 switch (fm_info_get_enet_if(i)) { 605 switch (fm_info_get_enet_if(i)) {
605 case PHY_INTERFACE_MODE_XGMII: 606 case PHY_INTERFACE_MODE_XGMII:
606 if (srds_s1 == 0x51) { 607 if (srds_s1 == 0x51) {
607 lane = serdes_get_first_lane(FSL_SRDS_1, 608 lane = serdes_get_first_lane(FSL_SRDS_1,
608 XAUI_FM1_MAC9 + idx); 609 XAUI_FM1_MAC9 + idx);
609 } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) { 610 } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
610 lane = serdes_get_first_lane(FSL_SRDS_1, 611 lane = serdes_get_first_lane(FSL_SRDS_1,
611 HIGIG_FM1_MAC9 + idx); 612 HIGIG_FM1_MAC9 + idx);
612 } else { 613 } else {
613 if (i == FM1_10GEC1 || i == FM1_10GEC2) 614 if (i == FM1_10GEC1 || i == FM1_10GEC2)
614 lane = serdes_get_first_lane(FSL_SRDS_1, 615 lane = serdes_get_first_lane(FSL_SRDS_1,
615 XFI_FM1_MAC9 + idx); 616 XFI_FM1_MAC9 + idx);
616 else 617 else
617 lane = serdes_get_first_lane(FSL_SRDS_1, 618 lane = serdes_get_first_lane(FSL_SRDS_1,
618 XFI_FM1_MAC1 + idx); 619 XFI_FM1_MAC1 + idx);
619 } 620 }
620 621
621 if (lane < 0) 622 if (lane < 0)
622 break; 623 break;
623 mdio_mux[i] = EMI2; 624 mdio_mux[i] = EMI2;
624 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i])); 625 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
625 626
626 if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) || 627 if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
627 (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || 628 (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
628 (srds_s1 == 0x71)) { 629 (srds_s1 == 0x71)) {
629 /* As XFI is in cage intead of a slot, so 630 /* As XFI is in cage intead of a slot, so
630 * ensure doesn't disable the corresponding port 631 * ensure doesn't disable the corresponding port
631 */ 632 */
632 break; 633 break;
633 } 634 }
634 635
635 slot = lane_to_slot[lane]; 636 slot = lane_to_slot[lane];
636 if (QIXIS_READ(present2) & (1 << (slot - 1))) 637 if (QIXIS_READ(present2) & (1 << (slot - 1)))
637 fm_disable_port(i); 638 fm_disable_port(i);
638 break; 639 break;
639 default: 640 default:
640 break; 641 break;
641 } 642 }
642 } 643 }
643 644
644 cpu_eth_init(bis); 645 cpu_eth_init(bis);
645 #endif /* CONFIG_FMAN_ENET */ 646 #endif /* CONFIG_FMAN_ENET */
646 647
647 return pci_eth_init(bis); 648 return pci_eth_init(bis);
648 } 649 }
board/freescale/t208xrdb/Makefile
Diff comments   View file @ 247161b
File was created 1 #
2 # Copyright 2014 Freescale Semiconductor, Inc.
3 #
4 # SPDX-License-Identifier: GPL-2.0+
5 #
6
7 obj-$(CONFIG_T2080RDB) += t208xrdb.o
8 obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
9 obj-$(CONFIG_T2080RDB) += cpld.o
10 obj-$(CONFIG_PCI) += pci.o
11 obj-y += ddr.o
12 obj-y += law.o
13 obj-y += tlb.o
14
board/freescale/t208xrdb/README
Diff comments   View file @ 247161b
File was created 1 T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
2 It can work in two mode: standalone mode and PCIe endpoint mode.
3
4 T2080 SoC Overview
5 ------------------
6 The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
7 Architecture processor cores with high-performance datapath acceleration
8 logic and network and peripheral bus interfaces required for networking,
9 telecom/datacom, wireless infrastructure, and mil/aerospace applications.
10
11 T2080 includes the following functions and features:
12 - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
13 - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
14 - Hierarchical interconnect fabric
15 - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
16 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
17 - 16 SerDes lanes up to 10.3125 GHz
18 - 8 Ethernet interfaces, supporting combinations of the following:
19 - Up to four 10 Gbps Ethernet MACs
20 - Up to eight 1 Gbps Ethernet MACs
21 - Up to four 2.5 Gbps Ethernet MACs
22 - High-speed peripheral interfaces
23 - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
24 - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
25 - Additional peripheral interfaces
26 - Two serial ATA (SATA 2.0) controllers
27 - Two high-speed USB 2.0 controllers with integrated PHY
28 - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
29 - Enhanced serial peripheral interface (eSPI)
30 - Four I2C controllers
31 - Four 2-pin UARTs or two 4-pin UARTs
32 - Integrated Flash Controller supporting NAND and NOR flash
33 - Three eight-channel DMA engines
34 - Support for hardware virtualization and partitioning enforcement
35 - QorIQ Platform's Trust Architecture 2.0
36
37 Differences between T2080 and T2081
38 -----------------------------------
39 Feature T2080 T2081
40 1G Ethernet numbers: 8 6
41 10G Ethernet numbers: 4 2
42 SerDes lanes: 16 8
43 Serial RapidIO,RMan: 2 no
44 SATA Controller: 2 no
45 Aurora: yes no
46 SoC Package: 896-pins 780-pins
47
48
49 T2080PCIe-RDB board Overview
50 ----------------------------
51 - SERDES Configuration
52 - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
53 - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
54 - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
55 - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
56 - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
57 - SerDes-2 Lane G-H: to SATA1 & SATA2
58 - Ethernet
59 - Two on-board 10M/100M/1G RGMII ethernet ports
60 - Two on-board 10Gbps XFI fiber ports
61 - Two on-board 10Gbps Base-T copper ports
62 - DDR Memory
63 - Supports 72bit 4GB DDR3-LP SODIMM
64 - PCIe
65 - One PCIe x4 gold-finger
66 - One PCIe x4 connector
67 - One PCIe x2 end-point device (C293 Crypto co-processor)
68 - IFC/Local Bus
69 - NOR: 128MB 16-bit NOR Flash
70 - NAND: 512MB 8-bit NAND flash
71 - CPLD: for system controlling with programable header on-board
72 - SATA
73 - Two SATA 2.0 onnectors on-board
74 - USB
75 - Supports two USB 2.0 ports with integrated PHYs
76 - Two type A ports with 5V@1.5A per port.
77 - SDHC
78 - one TF-card connector on-board
79 - SPI
80 - On-board 64MB SPI flash
81 - Other
82 - Two Serial ports
83 - Four I2C ports
84
85
86 System Memory map
87 -----------------
88 Start Address End Address Description Size
89 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
90 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
91 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
92 0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
93 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
94 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
95 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
96 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
97 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
98 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
99 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
100 0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
101 0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
102 0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
103 0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
104 0x0_0000_0000 0x0_ffff_ffff DDR 4GB
105
106
107 128M NOR Flash memory Map
108 -------------------------
109 Start Address End Address Definition Max size
110 0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
111 0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
112 0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
113 0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB
114 0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
115 0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
116 0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
117 0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
118 0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
119 0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
120 0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
121 0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB
122 0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
123 0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
124 0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
125 0xE8000000 0xE801FFFF RCW (current bank) 128KB
126
127
128 T2080PCIe-RDB Ethernet Port Map
129 -------------------------------
130 Label In Uboot In Linux FMan Address Comments PHY
131 ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315)
132 ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315)
133 ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202)
134 ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202)
135 ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E)
136 ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E)
137
138
139 T2080PCIe-RDB Default DIP-Switch setting
140 ----------------------------------------
141 SW1[1:8] = '00010011'
142 SW2[1:8] = '10111111'
143 SW3[1:8] = '11100001'
144
145 Software configurations and board settings
146 ------------------------------------------
147 1. NOR boot:
148 a. build NOR boot image
149 $ make T2080RDB
150 b. program u-boot.bin image to NOR flash
151 => tftp 1000000 u-boot.bin
152 => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
153 set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
154
155 Switching between default bank and alternate bank on NOR flash
156 To change boot source to vbank4:
157 via software: run command 'cpld reset altbank' in u-boot.
158 via DIP-switch: set SW3[5:7] = '011'
159
160 To change boot source to vbank0:
161 via software: run command 'cpld reset' in u-boot.
162 via DIP-Switch: set SW3[5:7] = '111'
163
164 2. NAND Boot:
165 a. build PBL image for NAND boot
166 $ make T2080RDB_NAND_config
167 $ make u-boot.pbl
168 b. program u-boot.pbl to NAND flash
169 => tftp 1000000 u-boot.pbl
170 => nand erase 0 d0000
171 => nand write 1000000 0 $filesize
172 set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
173
174 3. SPI Boot:
175 a. build PBL image for SPI boot
176 $ make T2080RDB_SPIFLASH_config
177 $ make u-boot.pbl
178 b. program u-boot.pbl to SPI flash
179 => tftp 1000000 u-boot.pbl
180 => sf probe 0
181 => sf erase 0 d0000
182 => sf write 1000000 0 $filesize
183 set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
184
185 4. SD Boot:
186 a. build PBL image for SD boot
187 $ make T2080RDB_SDCARD_config
188 $ make u-boot.pbl
189 b. program u-boot.pbl to TF card
190 => tftp 1000000 u-boot.pbl
191 => mmc write 1000000 8 1650
192 set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
193
194
195 How to update the ucode of Cortina CS4315/CS4340 10G PHY
196 --------------------------------------------------------
197 => tftp 1000000 CS4315-CS4340-PHY-ucode.txt
198 => pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize
199
200
201 How to update the ucode of Freescale FMAN
202 -----------------------------------------
203 => tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin
204 => pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
205
206
207 For more details, please refer to T2080PCIe-RDB User Guide and access
208 website www.freescale.com and Freescale QorIQ SDK Infocenter document.
209
board/freescale/t208xrdb/cpld.c
Diff comments   View file @ 247161b
File was created 1 /*
2 * Copyright 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 *
6 * Freescale T2080RDB board-specific CPLD controlling supports.
7 */
8
9 #include <common.h>
10 #include <command.h>
11 #include "cpld.h"
12
13 u8 cpld_read(unsigned int reg)
14 {
15 void *p = (void *)CONFIG_SYS_CPLD_BASE;
16
17 return in_8(p + reg);
18 }
19
20 void cpld_write(unsigned int reg, u8 value)
21 {
22 void *p = (void *)CONFIG_SYS_CPLD_BASE;
23
24 out_8(p + reg, value);
25 }
26
27 /* Set the boot bank to the alternate bank */
28 void cpld_set_altbank(void)
29 {
30 u8 reg = CPLD_READ(flash_csr);
31
32 reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
33 CPLD_WRITE(flash_csr, reg);
34 CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
35 }
36
37 /* Set the boot bank to the default bank */
38 void cpld_set_defbank(void)
39 {
40 u8 reg = CPLD_READ(flash_csr);
41
42 reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
43 CPLD_WRITE(flash_csr, reg);
44 CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
45 }
46
47 int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
48 {
49 int rc = 0;
50
51 if (argc <= 1)
52 return cmd_usage(cmdtp);
53
54 if (strcmp(argv[1], "reset") == 0) {
55 if (strcmp(argv[2], "altbank") == 0)
56 cpld_set_altbank();
57 else
58 cpld_set_defbank();
59 } else {
60 rc = cmd_usage(cmdtp);
61 }
62
63 return rc;
64 }
65
66 U_BOOT_CMD(
67 cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
68 "Reset the board or alternate bank",
69 "reset: reset to default bank\n"
70 "cpld reset altbank: reset to alternate bank\n"
71 );
72
board/freescale/t208xrdb/cpld.h
Diff comments   View file @ 247161b
File was created 1 /*
2 * Copyright 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /*
8 * CPLD register set of T2080RDB board-specific.
9 */
10 struct cpld_data {
11 u8 chip_id1; /* 0x00 - Chip ID1 register */
12 u8 chip_id2; /* 0x01 - Chip ID2 register */
13 u8 hw_ver; /* 0x02 - Hardware Revision Register */
14 u8 sw_ver; /* 0x03 - Software Revision register */
15 u8 res0[12]; /* 0x04 - 0x0F - not used */
16 u8 reset_ctl; /* 0x10 - Reset control Register */
17 u8 flash_csr; /* 0x11 - Flash control and status register */
18 u8 thermal_csr; /* 0x12 - Thermal control and status register */
19 u8 led_csr; /* 0x13 - LED control and status register */
20 u8 sfp_csr; /* 0x14 - SFP+ control and status register */
21 u8 misc_csr; /* 0x15 - Misc control and status register */
22 u8 boot_or; /* 0x16 - Boot config override register */
23 u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */
24 u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */
25 } cpld_data_t;
26
27 u8 cpld_read(unsigned int reg);
28 void cpld_write(unsigned int reg, u8 value);
29
30 #define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
31 #define CPLD_WRITE(reg, value) \
32 cpld_write(offsetof(struct cpld_data, reg), value)
33
34 /* CPLD on IFC */
35 #define CPLD_LBMAP_MASK 0x3F
36 #define CPLD_BANK_SEL_MASK 0x07
37 #define CPLD_BANK_OVERRIDE 0x40
38 #define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */
39 #define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */
40 #define CPLD_LBMAP_RESET 0xFF
41 #define CPLD_LBMAP_SHIFT 0x03
42 #define CPLD_BOOT_SEL 0x80
43
board/freescale/t208xrdb/ddr.c
Diff comments   View file @ 247161b
File was created 1 /*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 or later as published by the Free Software Foundation.
7 */
8
9 #include <common.h>
10 #include <i2c.h>
11 #include <hwconfig.h>
12 #include <asm/mmu.h>
13 #include <fsl_ddr_sdram.h>
14 #include <fsl_ddr_dimm_params.h>
15 #include <asm/fsl_law.h>
16 #include "ddr.h"
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 void fsl_ddr_board_options(memctl_options_t *popts,
21 dimm_params_t *pdimm,
22 unsigned int ctrl_num)
23 {
24 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
25 ulong ddr_freq;
26
27 if (ctrl_num > 1) {
28 printf("Not supported controller number %d\n", ctrl_num);
29 return;
30 }
31 if (!pdimm->n_ranks)
32 return;
33
34 pbsp = udimms[0];
35
36 /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
37 * freqency and n_banks specified in board_specific_parameters table.
38 */
39 ddr_freq = get_ddr_freq(0) / 1000000;
40 while (pbsp->datarate_mhz_high) {
41 if (pbsp->n_ranks == pdimm->n_ranks &&
42 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
43 if (ddr_freq <= pbsp->datarate_mhz_high) {
44 popts->clk_adjust = pbsp->clk_adjust;
45 popts->wrlvl_start = pbsp->wrlvl_start;
46 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
47 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
48 goto found;
49 }
50 pbsp_highest = pbsp;
51 }
52 pbsp++;
53 }
54
55 if (pbsp_highest) {
56 printf("Error: board specific timing not found");
57 printf("for data rate %lu MT/s\n", ddr_freq);
58 printf("Trying to use the highest speed (%u) parameters\n",
59 pbsp_highest->datarate_mhz_high);
60 popts->clk_adjust = pbsp_highest->clk_adjust;
61 popts->wrlvl_start = pbsp_highest->wrlvl_start;
62 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
63 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
64 } else {
65 panic("DIMM is not supported by this board");
66 }
67 found:
68 debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
69 "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
70 "wrlvl_ctrl_3 0x%x\n",
71 pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
72 pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
73 pbsp->wrlvl_ctl_3);
74
75 /*
76 * Factors to consider for half-strength driver enable:
77 * - number of DIMMs installed
78 */
79 popts->half_strength_driver_enable = 0;
80 /*
81 * Write leveling override
82 */
83 popts->wrlvl_override = 1;
84 popts->wrlvl_sample = 0xf;
85
86 /*
87 * Rtt and Rtt_WR override
88 */
89 popts->rtt_override = 0;
90
91 /* Enable ZQ calibration */
92 popts->zq_en = 1;
93
94 /* DHC_EN =1, ODT = 75 Ohm */
95 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
96 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
97 }
98
99 phys_size_t initdram(int board_type)
100 {
101 phys_size_t dram_size;
102
103 puts("Initializing....using SPD\n");
104
105 dram_size = fsl_ddr_sdram();
106
107 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
108 dram_size *= 0x100000;
109
110 puts(" DDR: ");
111 return dram_size;
112 }
113
board/freescale/t208xrdb/ddr.h
Diff comments   View file @ 247161b
File was created 1 /*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #ifndef __DDR_H__
8 #define __DDR_H__
9 struct board_specific_parameters {
10 u32 n_ranks;
11 u32 datarate_mhz_high;
12 u32 rank_gb;
13 u32 clk_adjust;
14 u32 wrlvl_start;
15 u32 wrlvl_ctl_2;
16 u32 wrlvl_ctl_3;
17 };
18
19 /*
20 * These tables contain all valid speeds we want to override with board
21 * specific parameters. datarate_mhz_high values need to be in ascending order
22 * for each n_ranks group.
23 */
24
25 static const struct board_specific_parameters udimm0[] = {
26 /*
27 * memory controller 0
28 * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
29 * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
30 */
31 {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
32 {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
33 {2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
34 {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
35 {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
36 {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
37 {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
38 {1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
39 {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
40 {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
41 {}
42 };
43
44 static const struct board_specific_parameters *udimms[] = {
45 udimm0,
46 };
47 #endif
48
board/freescale/t208xrdb/eth_t208xrdb.c
Diff comments   View file @ 247161b
File was created 1 /*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9 #include <common.h>
10 #include <command.h>
11 #include <netdev.h>
12 #include <asm/mmu.h>
13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
19 #include <malloc.h>
20 #include <fm_eth.h>
21 #include <fsl_mdio.h>
22 #include <miiphy.h>
23 #include <phy.h>
24 #include <asm/fsl_dtsec.h>
25 #include <asm/fsl_serdes.h>
26
27 int board_eth_init(bd_t *bis)
28 {
29 #if defined(CONFIG_FMAN_ENET)
30 int i, interface;
31 struct memac_mdio_info dtsec_mdio_info;
32 struct memac_mdio_info tgec_mdio_info;
33 struct mii_dev *dev;
34 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
35 u32 srds_s1;
36
37 srds_s1 = in_be32(&gur->rcwsr[4]) &
38 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
39 srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
40
41 dtsec_mdio_info.regs =
42 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
43
44 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
45
46 /* Register the 1G MDIO bus */
47 fm_memac_mdio_init(bis, &dtsec_mdio_info);
48
49 tgec_mdio_info.regs =
50 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
51 tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
52
53 /* Register the 10G MDIO bus */
54 fm_memac_mdio_init(bis, &tgec_mdio_info);
55
56 /* Set the two on-board RGMII PHY address */
57 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
58 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
59
60 switch (srds_s1) {
61 case 0x66:
62 case 0x6b:
63 fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
64 fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
65 fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
66 fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
67 break;
68 default:
69 printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
70 srds_s1);
71 break;
72 }
73
74 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
75 interface = fm_info_get_enet_if(i);
76 switch (interface) {
77 case PHY_INTERFACE_MODE_RGMII:
78 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
79 fm_info_set_mdio(i, dev);
80 break;
81 default:
82 break;
83 }
84 }
85
86 for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
87 switch (fm_info_get_enet_if(i)) {
88 case PHY_INTERFACE_MODE_XGMII:
89 dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
90 fm_info_set_mdio(i, dev);
91 break;
92 default:
93 break;
94 }
95 }
96
97 cpu_eth_init(bis);
98 #endif /* CONFIG_FMAN_ENET */
99
100 return pci_eth_init(bis);
101 }
102
103 void fdt_fixup_board_enet(void *fdt)
104 {
105 return;
106 }
107
board/freescale/t208xrdb/law.c
Diff comments   View file @ 247161b
File was created 1 /*
2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <asm/fsl_law.h>
12 #include <asm/mmu.h>
13
14 struct law_entry law_table[] = {
15 SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
16 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
17 SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
18 #endif
19 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
20 SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
21 #endif
22 #ifdef CONFIG_SYS_CPLD_BASE_PHYS
23 SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
24 #endif
25 #ifdef CONFIG_SYS_DCSRBAR_PHYS
26 /* Limit DCSR to 32M to access NPC Trace Buffer */
27 SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
28 #endif
29 #ifdef CONFIG_SYS_NAND_BASE_PHYS
30 SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
31 #endif
32 };
33
34 int num_law_entries = ARRAY_SIZE(law_table);
35
board/freescale/t208xrdb/pci.c
Diff comments   View file @ 247161b
File was created 1 /*
2 * Copyright 2007-2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <pci.h>
10 #include <asm/fsl_pci.h>
11 #include <libfdt.h>
12 #include <fdt_support.h>
13 #include <asm/fsl_serdes.h>
14
15 void pci_init_board(void)
16 {
17 fsl_pcie_init_board(0);
18 }
19
20 void pci_of_setup(void *blob, bd_t *bd)
21 {
22 FT_FSL_PCI_SETUP;
23 }
24
board/freescale/t208xrdb/t2080_pbi.cfg
Diff comments   View file @ 247161b
File was created 1 #
2 # Copyright 2013 Freescale Semiconductor, Inc.
3 #
4 # SPDX-License-Identifier: GPL-2.0+
5 #
6 # Refer doc/README.pblimage for more details about how-to configure
7 # and create PBL boot image
8 #
9
10 #PBI commands
11 #Initialize CPC1
12 09010000 00200400
13 09138000 00000000
14 091380c0 00000100
15 #512KB SRAM
16 09010100 00000000
17 09010104 fff80009
18 09010f00 08000000
19 #enable CPC1
20 09010000 80000000
21 #Configure LAW for CPC1
22 09000d00 00000000
23 09000d04 fff80000
24 09000d08 81000012
25 #Initialize eSPI controller, default configuration is slow for eSPI to
26 #load data, this configuration comes from u-boot eSPI driver.
27 09110000 80000403
28 09110020 2d170008
29 09110024 00100008
30 09110028 00100008
31 0911002c 00100008
32 #Errata for slowing down the MDC clock to make it <= 2.5 MHZ
33 094fc030 00008148
34 094fd030 00008148
35 #Configure alternate space
36 09000010 00000000
37 09000014 ff000000
38 09000018 81000000
39 #Flush PBL data
40 09138000 00000000
41 091380c0 00000000
42
board/freescale/t208xrdb/t2080_rcw.cfg
Diff comments   View file @ 247161b
File was created 1 #PBL preamble and RCW header for T2080RDB
2 aa55aa55 010e0100
3 #SerDes Protocol: 0x66_0x16
4 #Core/DDR: 1533Mhz/1600MT/s
5 120c0017 15000000 00000000 00000000
6 66160002 00008400 ec104000 c1000000
7 00000000 00000000 00000000 000307fc
8 00000000 00000000 00000000 00000004
9
board/freescale/t208xrdb/t208xrdb.c
Diff comments   View file @ 247161b
File was created 1 /*
2 * Copyright 2009-2013 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #include <common.h>
8 #include <command.h>
9 #include <i2c.h>
10 #include <netdev.h>
11 #include <linux/compiler.h>
12 #include <asm/mmu.h>
13 #include <asm/processor.h>
14 #include <asm/immap_85xx.h>
15 #include <asm/fsl_law.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/fsl_portals.h>
18 #include <asm/fsl_liodn.h>
19 #include <fm_eth.h>
20 #include "t208xrdb.h"
21 #include "cpld.h"
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 int checkboard(void)
26 {
27 struct cpu_type *cpu = gd->arch.cpu;
28 static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
29
30 printf("Board: %sRDB, ", cpu->name);
31 printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
32 CPLD_READ(hw_ver), CPLD_READ(sw_ver));
33
34 #ifdef CONFIG_SDCARD
35 puts("SD/MMC\n");
36 #elif CONFIG_SPIFLASH
37 puts("SPI\n");
38 #else
39 u8 reg;
40
41 reg = CPLD_READ(flash_csr);
42
43 if (reg & CPLD_BOOT_SEL) {
44 puts("NAND\n");
45 } else {
46 reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
47 printf("NOR vBank%d\n", ~reg & 0x7);
48 }
49 #endif
50
51 puts("SERDES Reference Clocks:\n");
52 printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
53 printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
54
55 return 0;
56 }
57
58 int board_early_init_r(void)
59 {
60 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
61 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
62 /*
63 * Remap Boot flash + PROMJET region to caching-inhibited
64 * so that flash can be erased properly.
65 */
66
67 /* Flush d-cache and invalidate i-cache of any FLASH data */
68 flush_dcache();
69 invalidate_icache();
70
71 /* invalidate existing TLB entry for flash + promjet */
72 disable_tlb(flash_esel);
73
74 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
75 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
76 0, flash_esel, BOOKE_PAGESZ_256M, 1);
77
78 set_liodns();
79 #ifdef CONFIG_SYS_DPAA_QBMAN
80 setup_portals();
81 #endif
82
83 return 0;
84 }
85
86 unsigned long get_board_sys_clk(void)
87 {
88 return CONFIG_SYS_CLK_FREQ;
89 }
90
91 unsigned long get_board_ddr_clk(void)
92 {
93 return CONFIG_DDR_CLK_FREQ;
94 }
95
96 int misc_init_r(void)
97 {
98 return 0;
99 }
100
101 void ft_board_setup(void *blob, bd_t *bd)
102 {
103 phys_addr_t base;
104 phys_size_t size;
105
106 ft_cpu_setup(blob, bd);
107
108 base = getenv_bootm_low();
109 size = getenv_bootm_size();
110
111 fdt_fixup_memory(blob, (u64)base, (u64)size);
112
113 #ifdef CONFIG_PCI
114 pci_of_setup(blob, bd);
115 #endif
116
117 fdt_fixup_liodn(blob);
118 fdt_fixup_dr_usb(blob, bd);
119
120 #ifdef CONFIG_SYS_DPAA_FMAN
121 fdt_fixup_fman_ethernet(blob);
122 fdt_fixup_board_enet(blob);
123 #endif
124 }
125
board/freescale/t208xrdb/t208xrdb.h
Diff comments   View file @ 247161b
File was created 1 /*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #ifndef __CORENET_DS_H__
8 #define __CORENET_DS_H__
9
10 void fdt_fixup_board_enet(void *blob);
11 void pci_of_setup(void *blob, bd_t *bd);
12
13 #endif
14
board/freescale/t208xrdb/tlb.c
Diff comments   View file @ 247161b
File was created 1 /*
2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10 #include <common.h>
11 #include <asm/mmu.h>
12
13 struct fsl_e_tlb_entry tlb_table[] = {
14 /* TLB 0 - for temp stack in cache */
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
16 CONFIG_SYS_INIT_RAM_ADDR_PHYS,
17 MAS3_SX|MAS3_SW|MAS3_SR, 0,
18 0, 0, BOOKE_PAGESZ_4K, 0),
19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
20 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0),
23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
24 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
25 MAS3_SX|MAS3_SW|MAS3_SR, 0,
26 0, 0, BOOKE_PAGESZ_4K, 0),
27 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
28 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
29 MAS3_SX|MAS3_SW|MAS3_SR, 0,
30 0, 0, BOOKE_PAGESZ_4K, 0),
31
32 /* TLB 1 */
33 /* *I*** - Covers boot page */
34 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
35 /*
36 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
37 * SRAM is at 0xfff00000, it covered the 0xfffff000.
38 */
39 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
40 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
41 0, 0, BOOKE_PAGESZ_1M, 1),
42 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
43 /*
44 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
45 * space is at 0xfff00000, it covered the 0xfffff000.
46 */
47 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
48 CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
49 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
50 0, 0, BOOKE_PAGESZ_1M, 1),
51 #else
52 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
53 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
54 0, 0, BOOKE_PAGESZ_4K, 1),
55 #endif
56
57 /* *I*G* - CCSRBAR */
58 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
59 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
60 0, 1, BOOKE_PAGESZ_16M, 1),
61
62 /* *I*G* - Flash, localbus */
63 /* This will be changed to *I*G* after relocation to RAM. */
64 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
65 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
66 0, 2, BOOKE_PAGESZ_256M, 1),
67
68 /* *I*G* - PCIe 1, 0x80000000 */
69 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
70 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
71 0, 3, BOOKE_PAGESZ_512M, 1),
72
73 /* *I*G* - PCIe 2, 0xa0000000 */
74 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
75 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
76 0, 4, BOOKE_PAGESZ_256M, 1),
77
78 /* *I*G* - PCIe 3, 0xb0000000 */
79 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
80 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
81 0, 5, BOOKE_PAGESZ_256M, 1),
82
83
84 /* *I*G* - PCIe 4, 0xc0000000 */
85 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
86 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
87 0, 6, BOOKE_PAGESZ_256M, 1),
88
89 /* *I*G* - PCI I/O */
90 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
91 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
92 0, 7, BOOKE_PAGESZ_256K, 1),
93
94 /* Bman/Qman */
95 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
96 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
97 MAS3_SX|MAS3_SW|MAS3_SR, 0,
98 0, 9, BOOKE_PAGESZ_16M, 1),
99 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
100 CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
101 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
102 0, 10, BOOKE_PAGESZ_16M, 1),
103 #endif
104 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
105 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
106 MAS3_SX|MAS3_SW|MAS3_SR, 0,
107 0, 11, BOOKE_PAGESZ_16M, 1),
108 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
109 CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
110 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
111 0, 12, BOOKE_PAGESZ_16M, 1),
112 #endif
113 #ifdef CONFIG_SYS_DCSRBAR_PHYS
114 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
115 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
116 0, 13, BOOKE_PAGESZ_32M, 1),
117 #endif
118 #ifdef CONFIG_SYS_NAND_BASE
119 /*
120 * *I*G - NAND
121 * entry 14 and 15 has been used hard coded, they will be disabled
122 * in cpu_init_f, so we use entry 16 for nand.
123 */
124 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
125 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
126 0, 16, BOOKE_PAGESZ_64K, 1),
127 #endif
128 #ifdef CONFIG_SYS_CPLD_BASE
129 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
130 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
131 0, 17, BOOKE_PAGESZ_4K, 1),
132 #endif
133 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
134 /*
135 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
136 * fetching ucode and ENV from master
137 */
138 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
139 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
140 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
141 0, 18, BOOKE_PAGESZ_1M, 1),
142 #endif
143 #if defined(CONFIG_SYS_RAMBOOT)
144 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
145 MAS3_SX|MAS3_SW|MAS3_SR, 0,
146 0, 19, BOOKE_PAGESZ_2G, 1)
147 #endif
148
149 };
150
151 int num_tlb_entries = ARRAY_SIZE(tlb_table);
152
1 # 1 #
2 # List of boards 2 # List of boards
3 # 3 #
4 # Syntax: 4 # Syntax:
5 # white-space separated list of entries; 5 # white-space separated list of entries;
6 # each entry has the fields documented below. 6 # each entry has the fields documented below.
7 # 7 #
8 # Unused fields can be specified as "-", or omitted if they 8 # Unused fields can be specified as "-", or omitted if they
9 # are the last field on the line. 9 # are the last field on the line.
10 # 10 #
11 # Lines starting with '#' are comments. 11 # Lines starting with '#' are comments.
12 # Blank lines are ignored. 12 # Blank lines are ignored.
13 # 13 #
14 # The CPU field takes the form: 14 # The CPU field takes the form:
15 # cpu[:spl_cpu] 15 # cpu[:spl_cpu]
16 # If spl_cpu is specified the make variable CPU will be set to this 16 # If spl_cpu is specified the make variable CPU will be set to this
17 # during the SPL build. 17 # during the SPL build.
18 # 18 #
19 # The options field takes the form: 19 # The options field takes the form:
20 # <board config name>[:comma separated config options] 20 # <board config name>[:comma separated config options]
21 # Each config option has the form (value defaults to "1"): 21 # Each config option has the form (value defaults to "1"):
22 # option[=value] 22 # option[=value]
23 # So if you have: 23 # So if you have:
24 # FOO:HAS_BAR,BAZ=64 24 # FOO:HAS_BAR,BAZ=64
25 # The file include/configs/FOO.h will be used, and these defines created: 25 # The file include/configs/FOO.h will be used, and these defines created:
26 # #define CONFIG_HAS_BAR 1 26 # #define CONFIG_HAS_BAR 1
27 # #define CONFIG_BAZ 64 27 # #define CONFIG_BAZ 64
28 # 28 #
29 # The maintainers field lists the e-mail addresses of the board's 29 # The maintainers field lists the e-mail addresses of the board's
30 # maintainers, separated by colons. NOTE: there are spaces in this field! 30 # maintainers, separated by colons. NOTE: there are spaces in this field!
31 # For any board without permanent maintainer, please contact 31 # For any board without permanent maintainer, please contact
32 # Wolfgang Denk <wd@denx.de> 32 # Wolfgang Denk <wd@denx.de>
33 # And Cc: the <u-boot@lists.denx.de> mailing list. 33 # And Cc: the <u-boot@lists.denx.de> mailing list.
34 34
35 # The list should be ordered according to the C locale. 35 # The list should be ordered according to the C locale.
36 # 36 #
37 # To keep the list formatted and sorted, script tools/reformat.py is available. 37 # To keep the list formatted and sorted, script tools/reformat.py is available.
38 # It can be used from a shell: 38 # It can be used from a shell:
39 # tools/reformat.py -i -d '-' -s 8 <boards.cfg >boards0.cfg && mv boards0.cfg boards.cfg 39 # tools/reformat.py -i -d '-' -s 8 <boards.cfg >boards0.cfg && mv boards0.cfg boards.cfg
40 # It can directly be invoked from vim: 40 # It can directly be invoked from vim:
41 # :%!tools/reformat.py -i -d '-' -s 8 41 # :%!tools/reformat.py -i -d '-' -s 8
42 # 42 #
43 # Status, Arch, CPU:SPLCPU, SoC, Vendor, Board name, Target, Options, Maintainers 43 # Status, Arch, CPU:SPLCPU, SoC, Vendor, Board name, Target, Options, Maintainers
44 ########################################################################################################### 44 ###########################################################################################################
45 45
46 Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng <fenghua@phytium.com.cn> 46 Active aarch64 armv8 - armltd vexpress64 vexpress_aemv8a vexpress_aemv8a:ARM64 David Feng <fenghua@phytium.com.cn>
47 Active arc arc700 - synopsys <none> arcangel4 - Alexey Brodkin <abrodkin@synopsys.com> 47 Active arc arc700 - synopsys <none> arcangel4 - Alexey Brodkin <abrodkin@synopsys.com>
48 Active arc arc700 - synopsys - axs101 - Alexey Brodkin <abrodkin@synopsys.com> 48 Active arc arc700 - synopsys - axs101 - Alexey Brodkin <abrodkin@synopsys.com>
49 Active arc arc700 - synopsys <none> arcangel4-be - Alexey Brodkin <abrodkin@synopsys.com> 49 Active arc arc700 - synopsys <none> arcangel4-be - Alexey Brodkin <abrodkin@synopsys.com>
50 Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij <linus.walleij@linaro.org> 50 Active arm arm1136 - armltd integrator integratorcp_cm1136 integratorcp:CM1136 Linus Walleij <linus.walleij@linaro.org>
51 Active arm arm1136 mx31 - - imx31_phycore - - 51 Active arm arm1136 mx31 - - imx31_phycore - -
52 Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk <wd@denx.de> 52 Active arm arm1136 mx31 davedenx - qong - Wolfgang Denk <wd@denx.de>
53 Active arm arm1136 mx31 freescale - mx31pdk - Fabio Estevam <fabio.estevam@freescale.com> 53 Active arm arm1136 mx31 freescale - mx31pdk - Fabio Estevam <fabio.estevam@freescale.com>
54 Active arm arm1136 mx31 hale - tt01 - Helmut Raiger <helmut.raiger@hale.at> 54 Active arm arm1136 mx31 hale - tt01 - Helmut Raiger <helmut.raiger@hale.at>
55 Active arm arm1136 mx31 logicpd - imx31_litekit - - 55 Active arm arm1136 mx31 logicpd - imx31_litekit - -
56 Active arm arm1136 mx35 - - woodburn - Stefano Babic <sbabic@denx.de> 56 Active arm arm1136 mx35 - - woodburn - Stefano Babic <sbabic@denx.de>
57 Active arm arm1136 mx35 - woodburn woodburn_sd woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg - 57 Active arm arm1136 mx35 - woodburn woodburn_sd woodburn_sd:IMX_CONFIG=board/woodburn/imximage.cfg -
58 Active arm arm1136 mx35 CarMediaLab - flea3 - Stefano Babic <sbabic@denx.de> 58 Active arm arm1136 mx35 CarMediaLab - flea3 - Stefano Babic <sbabic@denx.de>
59 Active arm arm1136 mx35 freescale - mx35pdk - Stefano Babic <sbabic@denx.de> 59 Active arm arm1136 mx35 freescale - mx35pdk - Stefano Babic <sbabic@denx.de>
60 Active arm arm1176 bcm2835 raspberrypi rpi_b rpi_b - Stephen Warren <swarren@wwwdotorg.org> 60 Active arm arm1176 bcm2835 raspberrypi rpi_b rpi_b - Stephen Warren <swarren@wwwdotorg.org>
61 Active arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park <c-park@ti.com> 61 Active arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park <c-park@ti.com>
62 Active arm arm720t - armltd integrator integratorap_cm720t integratorap:CM720T Linus Walleij <linus.walleij@linaro.org> 62 Active arm arm720t - armltd integrator integratorap_cm720t integratorap:CM720T Linus Walleij <linus.walleij@linaro.org>
63 Active arm arm920t - armltd integrator integratorap_cm920t integratorap:CM920T Linus Walleij <linus.walleij@linaro.org> 63 Active arm arm920t - armltd integrator integratorap_cm920t integratorap:CM920T Linus Walleij <linus.walleij@linaro.org>
64 Active arm arm920t - armltd integrator integratorcp_cm920t integratorcp:CM920T Linus Walleij <linus.walleij@linaro.org> 64 Active arm arm920t - armltd integrator integratorcp_cm920t integratorcp:CM920T Linus Walleij <linus.walleij@linaro.org>
65 Active arm arm920t a320 faraday - a320evb - Po-Yu Chuang <ratbert@faraday-tech.com> 65 Active arm arm920t a320 faraday - a320evb - Po-Yu Chuang <ratbert@faraday-tech.com>
66 Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek - Andreas Bießmann <andreas.devel@gmail.com> 66 Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek - Andreas Bießmann <andreas.devel@gmail.com>
67 Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek_ram at91rm9200ek:RAMBOOT Andreas Bießmann <andreas.devel@gmail.com> 67 Active arm arm920t at91 atmel at91rm9200ek at91rm9200ek_ram at91rm9200ek:RAMBOOT Andreas Bießmann <andreas.devel@gmail.com>
68 Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2 - Jens Scharsig <esw@bus-elektronik.de> 68 Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2 - Jens Scharsig <esw@bus-elektronik.de>
69 Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig <esw@bus-elektronik.de> 69 Active arm arm920t at91 BuS eb_cpux9k2 eb_cpux9k2_ram eb_cpux9k2:RAMBOOT Jens Scharsig <esw@bus-elektronik.de>
70 Active arm arm920t at91 eukrea cpuat91 cpuat91 - Eric Benard <eric@eukrea.com> 70 Active arm arm920t at91 eukrea cpuat91 cpuat91 - Eric Benard <eric@eukrea.com>
71 Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard <eric@eukrea.com> 71 Active arm arm920t at91 eukrea cpuat91 cpuat91_ram cpuat91:RAMBOOT Eric Benard <eric@eukrea.com>
72 Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de> 72 Active arm arm920t imx - - scb9328 - Torsten Koschorrek <koschorrek@synertronixx.de>
73 Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer@opengear.com> 73 Active arm arm920t ks8695 - - cm4008 - Greg Ungerer <greg.ungerer@opengear.com>
74 Active arm arm920t ks8695 - - cm41xx - - 74 Active arm arm920t ks8695 - - cm41xx - -
75 Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Müller <d.mueller@elsoft.ch> 75 Active arm arm920t s3c24x0 mpl vcma9 VCMA9 - David Müller <d.mueller@elsoft.ch>
76 Active arm arm920t s3c24x0 samsung - smdk2410 - David Müller <d.mueller@elsoft.ch> 76 Active arm arm920t s3c24x0 samsung - smdk2410 - David Müller <d.mueller@elsoft.ch>
77 Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij <linus.walleij@linaro.org> 77 Active arm arm926ejs - armltd integrator integratorap_cm926ejs integratorap:CM926EJ_S Linus Walleij <linus.walleij@linaro.org>
78 Active arm arm926ejs - armltd integrator integratorcp_cm926ejs integratorcp:CM924EJ_S Linus Walleij <linus.walleij@linaro.org> 78 Active arm arm926ejs - armltd integrator integratorcp_cm926ejs integratorcp:CM924EJ_S Linus Walleij <linus.walleij@linaro.org>
79 Active arm arm926ejs armada100 Marvell - aspenite - Prafulla Wadaskar <prafulla@marvell.com> 79 Active arm arm926ejs armada100 Marvell - aspenite - Prafulla Wadaskar <prafulla@marvell.com>
80 Active arm arm926ejs armada100 Marvell - gplugd - Ajay Bhargav <ajay.bhargav@einfochips.com> 80 Active arm arm926ejs armada100 Marvell - gplugd - Ajay Bhargav <ajay.bhargav@einfochips.com>
81 Active arm arm926ejs at91 - - afeb9260 - Sergey Lapin <slapin@ossfans.org> 81 Active arm arm926ejs at91 - - afeb9260 - Sergey Lapin <slapin@ossfans.org>
82 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs0 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net> 82 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs0 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
83 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs1 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net> 83 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_dataflash_cs1 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
84 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_nandflash at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 84 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9260ek_nandflash at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
85 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_2mmc_nandflash at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 85 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_2mmc_nandflash at91sam9260ek:AT91SAM9G20,AT91SAM9G20EK_2MMC,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
86 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs0 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net> 86 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs0 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
87 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs1 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net> 87 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_dataflash_cs1 at91sam9260ek:AT91SAM9G20,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
88 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_mmc at91sam9260ek:AT91SAM9G20,SYS_USE_MMC Stelian Pop <stelian@popies.net> 88 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_mmc at91sam9260ek:AT91SAM9G20,SYS_USE_MMC Stelian Pop <stelian@popies.net>
89 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_nandflash at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 89 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9g20ek_nandflash at91sam9260ek:AT91SAM9G20,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
90 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs0 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net> 90 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs0 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
91 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs1 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net> 91 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_dataflash_cs1 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 Stelian Pop <stelian@popies.net>
92 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_nandflash at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 92 Active arm arm926ejs at91 atmel at91sam9260ek at91sam9xeek_nandflash at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
93 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs0 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net> 93 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs0 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
94 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs3 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3 Stelian Pop <stelian@popies.net> 94 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_dataflash_cs3 at91sam9261ek:AT91SAM9261,SYS_USE_DATAFLASH_CS3 Stelian Pop <stelian@popies.net>
95 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_nandflash at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 95 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9261ek_nandflash at91sam9261ek:AT91SAM9261,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
96 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs0 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net> 96 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs0 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS0 Stelian Pop <stelian@popies.net>
97 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs3 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3 Stelian Pop <stelian@popies.net> 97 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_dataflash_cs3 at91sam9261ek:AT91SAM9G10,SYS_USE_DATAFLASH_CS3 Stelian Pop <stelian@popies.net>
98 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_nandflash at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 98 Active arm arm926ejs at91 atmel at91sam9261ek at91sam9g10ek_nandflash at91sam9261ek:AT91SAM9G10,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
99 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net> 99 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
100 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash_cs0 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net> 100 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_dataflash_cs0 at91sam9263ek:AT91SAM9263,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
101 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_nandflash at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 101 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_nandflash at91sam9263ek:AT91SAM9263,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
102 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH Stelian Pop <stelian@popies.net> 102 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash at91sam9263ek:AT91SAM9263,SYS_USE_NORFLASH Stelian Pop <stelian@popies.net>
103 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash_boot at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH Stelian Pop <stelian@popies.net> 103 Active arm arm926ejs at91 atmel at91sam9263ek at91sam9263ek_norflash_boot at91sam9263ek:AT91SAM9263,SYS_USE_BOOT_NORFLASH Stelian Pop <stelian@popies.net>
104 Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_nandflash at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH Bo Shen<voice.shen@atmel.com> 104 Active arm arm926ejs at91 atmel at91sam9m10g45ek at91sam9m10g45ek_nandflash at91sam9m10g45ek:AT91SAM9M10G45,SYS_USE_NANDFLASH Bo Shen<voice.shen@atmel.com>
105 Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_mmc at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC Josh Wu <josh.wu@atmel.com> 105 Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_mmc at91sam9n12ek:AT91SAM9N12,SYS_USE_MMC Josh Wu <josh.wu@atmel.com>
106 Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_nandflash at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH Josh Wu <josh.wu@atmel.com> 106 Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_nandflash at91sam9n12ek:AT91SAM9N12,SYS_USE_NANDFLASH Josh Wu <josh.wu@atmel.com>
107 Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_spiflash at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH Josh Wu <josh.wu@atmel.com> 107 Active arm arm926ejs at91 atmel at91sam9n12ek at91sam9n12ek_spiflash at91sam9n12ek:AT91SAM9N12,SYS_USE_SPIFLASH Josh Wu <josh.wu@atmel.com>
108 Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_dataflash at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net> 108 Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_dataflash at91sam9rlek:AT91SAM9RL,SYS_USE_DATAFLASH Stelian Pop <stelian@popies.net>
109 Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_nandflash at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net> 109 Active arm arm926ejs at91 atmel at91sam9rlek at91sam9rlek_nandflash at91sam9rlek:AT91SAM9RL,SYS_USE_NANDFLASH Stelian Pop <stelian@popies.net>
110 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_dataflash at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH Bo Shen <voice.shen@atmel.com> 110 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_dataflash at91sam9x5ek:AT91SAM9X5,SYS_USE_DATAFLASH Bo Shen <voice.shen@atmel.com>
111 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_mmc at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC Bo Shen <voice.shen@atmel.com> 111 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_mmc at91sam9x5ek:AT91SAM9X5,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
112 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_nandflash at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com> 112 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_nandflash at91sam9x5ek:AT91SAM9X5,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
113 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_spiflash at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH Bo Shen <voice.shen@atmel.com> 113 Active arm arm926ejs at91 atmel at91sam9x5ek at91sam9x5ek_spiflash at91sam9x5ek:AT91SAM9X5,SYS_USE_SPIFLASH Bo Shen <voice.shen@atmel.com>
114 Active arm arm926ejs at91 bluewater - snapper9260 snapper9260:AT91SAM9260 Ryan Mallon <ryan@bluewatersys.com> 114 Active arm arm926ejs at91 bluewater - snapper9260 snapper9260:AT91SAM9260 Ryan Mallon <ryan@bluewatersys.com>
115 Active arm arm926ejs at91 bluewater snapper9260 snapper9g20 snapper9260:AT91SAM9G20 Ryan Mallon <ryan@bluewatersys.com> 115 Active arm arm926ejs at91 bluewater snapper9260 snapper9g20 snapper9260:AT91SAM9G20 Ryan Mallon <ryan@bluewatersys.com>
116 Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc - Jens Scharsig <esw@bus-elektronik.de> 116 Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc - Jens Scharsig <esw@bus-elektronik.de>
117 Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc_ram vl_ma2sc:RAMLOAD Jens Scharsig <esw@bus-elektronik.de> 117 Active arm arm926ejs at91 BuS vl_ma2sc vl_ma2sc_ram vl_ma2sc:RAMLOAD Jens Scharsig <esw@bus-elektronik.de>
118 Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com> 118 Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
119 Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_nandflash sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com> 119 Active arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_nandflash sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
120 Active arm arm926ejs at91 calao tny_a9260 tny_a9260_eeprom tny_a9260:AT91SAM9260,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com> 120 Active arm arm926ejs at91 calao tny_a9260 tny_a9260_eeprom tny_a9260:AT91SAM9260,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
121 Active arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com> 121 Active arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
122 Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com> 122 Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
123 Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com> 123 Active arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
124 Active arm arm926ejs at91 calao usb_a9263 usb_a9263_dataflash usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH Mateusz Kulikowski <mateusz.kulikowski@gmail.com> 124 Active arm arm926ejs at91 calao usb_a9263 usb_a9263_dataflash usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
125 Active arm arm926ejs at91 egnite ethernut5 ethernut5 ethernut5:AT91SAM9XE egnite GmbH <info@egnite.de> 125 Active arm arm926ejs at91 egnite ethernut5 ethernut5 ethernut5:AT91SAM9XE egnite GmbH <info@egnite.de>
126 Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> 126 Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
127 Active arm arm926ejs at91 emk top9000 top9000su_xe top9000:SU9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> 127 Active arm arm926ejs at91 emk top9000 top9000su_xe top9000:SU9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
128 Active arm arm926ejs at91 esd meesc meesc meesc:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 128 Active arm arm926ejs at91 esd meesc meesc meesc:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
129 Active arm arm926ejs at91 esd meesc meesc_dataflash meesc:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 129 Active arm arm926ejs at91 esd meesc meesc_dataflash meesc:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
130 Active arm arm926ejs at91 esd otc570 otc570 otc570:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 130 Active arm arm926ejs at91 esd otc570 otc570 otc570:AT91SAM9263,SYS_USE_NANDFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
131 Active arm arm926ejs at91 esd otc570 otc570_dataflash otc570:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu> 131 Active arm arm926ejs at91 esd otc570 otc570_dataflash otc570:AT91SAM9263,SYS_USE_DATAFLASH Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
132 Active arm arm926ejs at91 eukrea cpu9260 cpu9260 cpu9260:CPU9260 Eric Benard <eric@eukrea.com> 132 Active arm arm926ejs at91 eukrea cpu9260 cpu9260 cpu9260:CPU9260 Eric Benard <eric@eukrea.com>
133 Active arm arm926ejs at91 eukrea cpu9260 cpu9260_128M cpu9260:CPU9260,CPU9260_128M Eric Benard <eric@eukrea.com> 133 Active arm arm926ejs at91 eukrea cpu9260 cpu9260_128M cpu9260:CPU9260,CPU9260_128M Eric Benard <eric@eukrea.com>
134 Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand cpu9260:CPU9260,NANDBOOT Eric Benard <eric@eukrea.com> 134 Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand cpu9260:CPU9260,NANDBOOT Eric Benard <eric@eukrea.com>
135 Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand_128M cpu9260:CPU9260,CPU9260_128M,NANDBOOT Eric Benard <eric@eukrea.com> 135 Active arm arm926ejs at91 eukrea cpu9260 cpu9260_nand_128M cpu9260:CPU9260,CPU9260_128M,NANDBOOT Eric Benard <eric@eukrea.com>
136 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20 cpu9260:CPU9G20 Eric Benard <eric@eukrea.com> 136 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20 cpu9260:CPU9G20 Eric Benard <eric@eukrea.com>
137 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_128M cpu9260:CPU9G20,CPU9G20_128M Eric Benard <eric@eukrea.com> 137 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_128M cpu9260:CPU9G20,CPU9G20_128M Eric Benard <eric@eukrea.com>
138 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand cpu9260:CPU9G20,NANDBOOT Eric Benard <eric@eukrea.com> 138 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand cpu9260:CPU9G20,NANDBOOT Eric Benard <eric@eukrea.com>
139 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand_128M cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT Eric Benard <eric@eukrea.com> 139 Active arm arm926ejs at91 eukrea cpu9260 cpu9G20_nand_128M cpu9260:CPU9G20,CPU9G20_128M,NANDBOOT Eric Benard <eric@eukrea.com>
140 Active arm arm926ejs at91 ronetix pm9261 pm9261 pm9261:AT91SAM9261 Ilko Iliev <iliev@ronetix.at> 140 Active arm arm926ejs at91 ronetix pm9261 pm9261 pm9261:AT91SAM9261 Ilko Iliev <iliev@ronetix.at>
141 Active arm arm926ejs at91 ronetix pm9263 pm9263 pm9263:AT91SAM9263 Ilko Iliev <iliev@ronetix.at> 141 Active arm arm926ejs at91 ronetix pm9263 pm9263 pm9263:AT91SAM9263 Ilko Iliev <iliev@ronetix.at>
142 Active arm arm926ejs at91 ronetix pm9g45 pm9g45 pm9g45:AT91SAM9G45 Ilko Iliev <iliev@ronetix.at> 142 Active arm arm926ejs at91 ronetix pm9g45 pm9g45 pm9g45:AT91SAM9G45 Ilko Iliev <iliev@ronetix.at>
143 Active arm arm926ejs at91 siemens corvus corvus corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH Heiko Schocher <hs@denx.de> 143 Active arm arm926ejs at91 siemens corvus corvus corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH Heiko Schocher <hs@denx.de>
144 Active arm arm926ejs at91 siemens taurus axm taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM Heiko Schocher <hs@denx.de> 144 Active arm arm926ejs at91 siemens taurus axm taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM Heiko Schocher <hs@denx.de>
145 Active arm arm926ejs at91 siemens taurus taurus taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS Heiko Schocher <hs@denx.de> 145 Active arm arm926ejs at91 siemens taurus taurus taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS Heiko Schocher <hs@denx.de>
146 Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig <mhubig@imko.de> 146 Active arm arm926ejs at91 taskit stamp9g20 portuxg20 stamp9g20:AT91SAM9G20,PORTUXG20 Markus Hubig <mhubig@imko.de>
147 Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig <mhubig@imko.de> 147 Active arm arm926ejs at91 taskit stamp9g20 stamp9g20 stamp9g20:AT91SAM9G20 Markus Hubig <mhubig@imko.de>
148 Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx - Heiko Schocher <hs@denx.de> 148 Active arm arm926ejs davinci ait cam_enc_4xx cam_enc_4xx - Heiko Schocher <hs@denx.de>
149 Active arm arm926ejs davinci Barix ipam390 ipam390 - Heiko Schocher <hs@denx.de> 149 Active arm arm926ejs davinci Barix ipam390 ipam390 - Heiko Schocher <hs@denx.de>
150 Active arm arm926ejs davinci davinci da8xxevm da830evm - Nick Thompson <nick.thompson@gefanuc.com> 150 Active arm arm926ejs davinci davinci da8xxevm da830evm - Nick Thompson <nick.thompson@gefanuc.com>
151 Active arm arm926ejs davinci davinci da8xxevm da850_am18xxevm da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 Sudhakar Rajashekhara <sudhakar.raj@ti.com> 151 Active arm arm926ejs davinci davinci da8xxevm da850_am18xxevm da850evm:DA850_AM18X_EVM,MAC_ADDR_IN_EEPROM,SYS_I2C_EEPROM_ADDR_LEN=2,SYS_I2C_EEPROM_ADDR=0x50 Sudhakar Rajashekhara <sudhakar.raj@ti.com>
152 Active arm arm926ejs davinci davinci da8xxevm da850evm da850evm:MAC_ADDR_IN_SPIFLASH Sudhakar Rajashekhara <sudhakar.raj@ti.com> 152 Active arm arm926ejs davinci davinci da8xxevm da850evm da850evm:MAC_ADDR_IN_SPIFLASH Sudhakar Rajashekhara <sudhakar.raj@ti.com>
153 Active arm arm926ejs davinci davinci da8xxevm da850evm_direct_nor da850evm:MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT Sudhakar Rajashekhara <sudhakar.raj@ti.com> 153 Active arm arm926ejs davinci davinci da8xxevm da850evm_direct_nor da850evm:MAC_ADDR_IN_SPIFLASH,USE_NOR,DIRECT_NOR_BOOT Sudhakar Rajashekhara <sudhakar.raj@ti.com>
154 Active arm arm926ejs davinci davinci da8xxevm hawkboard - Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com> 154 Active arm arm926ejs davinci davinci da8xxevm hawkboard - Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
155 Active arm arm926ejs davinci davinci da8xxevm hawkboard_uart hawkboard:UART_U_BOOT Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com> 155 Active arm arm926ejs davinci davinci da8xxevm hawkboard_uart hawkboard:UART_U_BOOT Syed Mohammed Khasim <sm.khasim@gmail.com>:Sughosh Ganu <urwithsughosh@gmail.com>
156 Active arm arm926ejs davinci davinci dm355evm davinci_dm355evm - Sandeep Paulraj <s-paulraj@ti.com> 156 Active arm arm926ejs davinci davinci dm355evm davinci_dm355evm - Sandeep Paulraj <s-paulraj@ti.com>
157 Active arm arm926ejs davinci davinci dm355leopard davinci_dm355leopard - Sandeep Paulraj <s-paulraj@ti.com> 157 Active arm arm926ejs davinci davinci dm355leopard davinci_dm355leopard - Sandeep Paulraj <s-paulraj@ti.com>
158 Active arm arm926ejs davinci davinci dm365evm davinci_dm365evm - Sandeep Paulraj <s-paulraj@ti.com> 158 Active arm arm926ejs davinci davinci dm365evm davinci_dm365evm - Sandeep Paulraj <s-paulraj@ti.com>
159 Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467evm davinci_dm6467evm:REFCLK_FREQ=27000000 Sandeep Paulraj <s-paulraj@ti.com> 159 Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467evm davinci_dm6467evm:REFCLK_FREQ=27000000 Sandeep Paulraj <s-paulraj@ti.com>
160 Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467Tevm davinci_dm6467evm:DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000 Sandeep Paulraj <s-paulraj@ti.com> 160 Active arm arm926ejs davinci davinci dm6467evm davinci_dm6467Tevm davinci_dm6467evm:DAVINCI_DM6467TEVM,REFCLK_FREQ=33000000 Sandeep Paulraj <s-paulraj@ti.com>
161 Active arm arm926ejs davinci davinci dvevm davinci_dvevm - - 161 Active arm arm926ejs davinci davinci dvevm davinci_dvevm - -
162 Active arm arm926ejs davinci davinci ea20 ea20 - Stefano Babic <sbabic@denx.de> 162 Active arm arm926ejs davinci davinci ea20 ea20 - Stefano Babic <sbabic@denx.de>
163 Active arm arm926ejs davinci davinci schmoogie davinci_schmoogie - - 163 Active arm arm926ejs davinci davinci schmoogie davinci_schmoogie - -
164 Active arm arm926ejs davinci davinci sffsdr davinci_sffsdr - - 164 Active arm arm926ejs davinci davinci sffsdr davinci_sffsdr - -
165 Active arm arm926ejs davinci davinci sonata davinci_sonata - - 165 Active arm arm926ejs davinci davinci sonata davinci_sonata - -
166 Active arm arm926ejs davinci enbw enbw_cmc enbw_cmc - Heiko Schocher <hs@denx.de> 166 Active arm arm926ejs davinci enbw enbw_cmc enbw_cmc - Heiko Schocher <hs@denx.de>
167 Active arm arm926ejs davinci omicron calimain calimain - Manfred Rudigier <manfred.rudigier@omicron.at>:Christian Riesch <christian.riesch@omicron.at> 167 Active arm arm926ejs davinci omicron calimain calimain - Manfred Rudigier <manfred.rudigier@omicron.at>:Christian Riesch <christian.riesch@omicron.at>
168 Active arm arm926ejs kirkwood buffalo lsxl lschlv2 lsxl:LSCHLV2 Michael Walle <michael@walle.cc> 168 Active arm arm926ejs kirkwood buffalo lsxl lschlv2 lsxl:LSCHLV2 Michael Walle <michael@walle.cc>
169 Active arm arm926ejs kirkwood buffalo lsxl lsxhl lsxl:LSXHL Michael Walle <michael@walle.cc> 169 Active arm arm926ejs kirkwood buffalo lsxl lsxhl lsxl:LSXHL Michael Walle <michael@walle.cc>
170 Active arm arm926ejs kirkwood cloudengines - pogo_e02 - Dave Purdy <david.c.purdy@gmail.com> 170 Active arm arm926ejs kirkwood cloudengines - pogo_e02 - Dave Purdy <david.c.purdy@gmail.com>
171 Active arm arm926ejs kirkwood d-link - dns325 - Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net> 171 Active arm arm926ejs kirkwood d-link - dns325 - Stefan Herbrechtsmeier <stefan@code.herbrechtsmeier.net>
172 Active arm arm926ejs kirkwood iomega - iconnect - Luka Perkov <luka@openwrt.org> 172 Active arm arm926ejs kirkwood iomega - iconnect - Luka Perkov <luka@openwrt.org>
173 Active arm arm926ejs kirkwood karo tk71 tk71 - - 173 Active arm arm926ejs kirkwood karo tk71 tk71 - -
174 Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp <valentin.longchamp@keymile.com> 174 Active arm arm926ejs kirkwood keymile km_arm km_kirkwood km_kirkwood:KM_KIRKWOOD Valentin Longchamp <valentin.longchamp@keymile.com>
175 Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_128m16 km_kirkwood:KM_KIRKWOOD_128M16 Valentin Longchamp <valentin.longchamp@keymile.com> 175 Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_128m16 km_kirkwood:KM_KIRKWOOD_128M16 Valentin Longchamp <valentin.longchamp@keymile.com>
176 Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp <valentin.longchamp@keymile.com> 176 Active arm arm926ejs kirkwood keymile km_arm km_kirkwood_pci km_kirkwood:KM_KIRKWOOD_PCI Valentin Longchamp <valentin.longchamp@keymile.com>
177 Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp <valentin.longchamp@keymile.com> 177 Active arm arm926ejs kirkwood keymile km_arm kmcoge5un km_kirkwood:KM_COGE5UN Valentin Longchamp <valentin.longchamp@keymile.com>
178 Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp <valentin.longchamp@keymile.com> 178 Active arm arm926ejs kirkwood keymile km_arm kmnusa km_kirkwood:KM_NUSA Valentin Longchamp <valentin.longchamp@keymile.com>
179 Active arm arm926ejs kirkwood keymile km_arm kmsugp1 km_kirkwood:KM_SUGP1 Valentin Longchamp <valentin.longchamp@keymile.com> 179 Active arm arm926ejs kirkwood keymile km_arm kmsugp1 km_kirkwood:KM_SUGP1 Valentin Longchamp <valentin.longchamp@keymile.com>
180 Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp <valentin.longchamp@keymile.com> 180 Active arm arm926ejs kirkwood keymile km_arm kmsuv31 km_kirkwood:KM_SUV31 Valentin Longchamp <valentin.longchamp@keymile.com>
181 Active arm arm926ejs kirkwood keymile km_arm mgcoge3un km_kirkwood:KM_MGCOGE3UN Valentin Longchamp <valentin.longchamp@keymile.com> 181 Active arm arm926ejs kirkwood keymile km_arm mgcoge3un km_kirkwood:KM_MGCOGE3UN Valentin Longchamp <valentin.longchamp@keymile.com>
182 Active arm arm926ejs kirkwood keymile km_arm portl2 km_kirkwood:KM_PORTL2 Valentin Longchamp <valentin.longchamp@keymile.com> 182 Active arm arm926ejs kirkwood keymile km_arm portl2 km_kirkwood:KM_PORTL2 Valentin Longchamp <valentin.longchamp@keymile.com>
183 Active arm arm926ejs kirkwood LaCie net2big_v2 d2net_v2 lacie_kw:D2NET_V2 - 183 Active arm arm926ejs kirkwood LaCie net2big_v2 d2net_v2 lacie_kw:D2NET_V2 -
184 Active arm arm926ejs kirkwood LaCie net2big_v2 net2big_v2 lacie_kw:NET2BIG_V2 Simon Guinot <simon.guinot@sequanux.org> 184 Active arm arm926ejs kirkwood LaCie net2big_v2 net2big_v2 lacie_kw:NET2BIG_V2 Simon Guinot <simon.guinot@sequanux.org>
185 Active arm arm926ejs kirkwood LaCie netspace_v2 inetspace_v2 lacie_kw:INETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org> 185 Active arm arm926ejs kirkwood LaCie netspace_v2 inetspace_v2 lacie_kw:INETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org>
186 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_lite_v2 lacie_kw:NETSPACE_LITE_V2 - 186 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_lite_v2 lacie_kw:NETSPACE_LITE_V2 -
187 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_max_v2 lacie_kw:NETSPACE_MAX_V2 Simon Guinot <simon.guinot@sequanux.org> 187 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_max_v2 lacie_kw:NETSPACE_MAX_V2 Simon Guinot <simon.guinot@sequanux.org>
188 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_mini_v2 lacie_kw:NETSPACE_MINI_V2 - 188 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_mini_v2 lacie_kw:NETSPACE_MINI_V2 -
189 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_v2 lacie_kw:NETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org> 189 Active arm arm926ejs kirkwood LaCie netspace_v2 netspace_v2 lacie_kw:NETSPACE_V2 Simon Guinot <simon.guinot@sequanux.org>
190 Active arm arm926ejs kirkwood LaCie wireless_space wireless_space - - 190 Active arm arm926ejs kirkwood LaCie wireless_space wireless_space - -
191 Active arm arm926ejs kirkwood Marvell - dreamplug - Jason Cooper <u-boot@lakedaemon.net> 191 Active arm arm926ejs kirkwood Marvell - dreamplug - Jason Cooper <u-boot@lakedaemon.net>
192 Active arm arm926ejs kirkwood Marvell - guruplug - Siddarth Gore <gores@marvell.com> 192 Active arm arm926ejs kirkwood Marvell - guruplug - Siddarth Gore <gores@marvell.com>
193 Active arm arm926ejs kirkwood Marvell - mv88f6281gtw_ge - Prafulla Wadaskar <prafulla@marvell.com> 193 Active arm arm926ejs kirkwood Marvell - mv88f6281gtw_ge - Prafulla Wadaskar <prafulla@marvell.com>
194 Active arm arm926ejs kirkwood Marvell - rd6281a - Prafulla Wadaskar <prafulla@marvell.com> 194 Active arm arm926ejs kirkwood Marvell - rd6281a - Prafulla Wadaskar <prafulla@marvell.com>
195 Active arm arm926ejs kirkwood Marvell - sheevaplug - Prafulla Wadaskar <prafulla@marvell.com> 195 Active arm arm926ejs kirkwood Marvell - sheevaplug - Prafulla Wadaskar <prafulla@marvell.com>
196 Active arm arm926ejs kirkwood Marvell openrd openrd_base openrd:BOARD_IS_OPENRD_BASE Prafulla Wadaskar <prafulla@marvell.com> 196 Active arm arm926ejs kirkwood Marvell openrd openrd_base openrd:BOARD_IS_OPENRD_BASE Prafulla Wadaskar <prafulla@marvell.com>
197 Active arm arm926ejs kirkwood Marvell openrd openrd_client openrd:BOARD_IS_OPENRD_CLIENT - 197 Active arm arm926ejs kirkwood Marvell openrd openrd_client openrd:BOARD_IS_OPENRD_CLIENT -
198 Active arm arm926ejs kirkwood Marvell openrd openrd_ultimate openrd:BOARD_IS_OPENRD_ULTIMATE - 198 Active arm arm926ejs kirkwood Marvell openrd openrd_ultimate openrd:BOARD_IS_OPENRD_ULTIMATE -
199 Active arm arm926ejs kirkwood raidsonic ib62x0 ib62x0 - Luka Perkov <luka@openwrt.org> 199 Active arm arm926ejs kirkwood raidsonic ib62x0 ib62x0 - Luka Perkov <luka@openwrt.org>
200 Active arm arm926ejs kirkwood Seagate - dockstar - Eric Cooper <ecc@cmu.edu> 200 Active arm arm926ejs kirkwood Seagate - dockstar - Eric Cooper <ecc@cmu.edu>
201 Active arm arm926ejs kirkwood Seagate - goflexhome - Suriyan Ramasami <suriyan.r@gmail.com> 201 Active arm arm926ejs kirkwood Seagate - goflexhome - Suriyan Ramasami <suriyan.r@gmail.com>
202 Active arm arm926ejs lpc32xx timll devkit3250 devkit3250 - Vladimir Zapolskiy <vz@mleia.com> 202 Active arm arm926ejs lpc32xx timll devkit3250 devkit3250 - Vladimir Zapolskiy <vz@mleia.com>
203 Active arm arm926ejs mb86r0x syteco jadecpu jadecpu - Matthias Weisser <weisserm@arcor.de> 203 Active arm arm926ejs mb86r0x syteco jadecpu jadecpu - Matthias Weisser <weisserm@arcor.de>
204 Active arm arm926ejs mx25 freescale mx25pdk mx25pdk mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com> 204 Active arm arm926ejs mx25 freescale mx25pdk mx25pdk mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com>
205 Active arm arm926ejs mx25 karo tx25 tx25 - John Rigby <jcrigby@gmail.com> 205 Active arm arm926ejs mx25 karo tx25 tx25 - John Rigby <jcrigby@gmail.com>
206 Active arm arm926ejs mx25 syteco zmx25 zmx25 - Matthias Weisser <weisserm@arcor.de> 206 Active arm arm926ejs mx25 syteco zmx25 zmx25 - Matthias Weisser <weisserm@arcor.de>
207 Active arm arm926ejs mx27 armadeus apf27 apf27 - Philippe Reynes <tremyfr@yahoo.fr>:Eric Jarrige <eric.jarrige@armadeus.org> 207 Active arm arm926ejs mx27 armadeus apf27 apf27 - Philippe Reynes <tremyfr@yahoo.fr>:Eric Jarrige <eric.jarrige@armadeus.org>
208 Active arm arm926ejs mx27 logicpd imx27lite imx27lite - Wolfgang Denk <wd@denx.de> 208 Active arm arm926ejs mx27 logicpd imx27lite imx27lite - Wolfgang Denk <wd@denx.de>
209 Active arm arm926ejs mx27 logicpd imx27lite magnesium - Heiko Schocher <hs@denx.de> 209 Active arm arm926ejs mx27 logicpd imx27lite magnesium - Heiko Schocher <hs@denx.de>
210 Active arm arm926ejs mxs bluegiga apx4devkit apx4devkit - Lauri Hintsala <lauri.hintsala@bluegiga.com> 210 Active arm arm926ejs mxs bluegiga apx4devkit apx4devkit - Lauri Hintsala <lauri.hintsala@bluegiga.com>
211 Active arm arm926ejs mxs creative xfi3 xfi3 - Marek Vasut <marek.vasut@gmail.com> 211 Active arm arm926ejs mxs creative xfi3 xfi3 - Marek Vasut <marek.vasut@gmail.com>
212 Active arm arm926ejs mxs denx m28evk m28evk - Marek Vasut <marek.vasut@gmail.com> 212 Active arm arm926ejs mxs denx m28evk m28evk - Marek Vasut <marek.vasut@gmail.com>
213 Active arm arm926ejs mxs freescale mx23evk mx23evk - Otavio Salvador <otavio@ossystems.com.br> 213 Active arm arm926ejs mxs freescale mx23evk mx23evk - Otavio Salvador <otavio@ossystems.com.br>
214 Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com> 214 Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
215 Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com> 215 Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
216 Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com> 216 Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com>
217 Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino - Marek Vasut <marek.vasut@gmail.com> 217 Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino - Marek Vasut <marek.vasut@gmail.com>
218 Active arm arm926ejs mxs ppcag bg0900 bg0900 - Marek Vasut <marex@denx.de> 218 Active arm arm926ejs mxs ppcag bg0900 bg0900 - Marek Vasut <marex@denx.de>
219 Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com> 219 Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com>
220 Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut <marek.vasut@gmail.com> 220 Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut <marek.vasut@gmail.com>
221 Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it> 221 Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
222 Active arm arm926ejs nomadik st nhk8815 nhk8815_onenand nhk8815:BOOT_ONENAND Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it> 222 Active arm arm926ejs nomadik st nhk8815 nhk8815_onenand nhk8815:BOOT_ONENAND Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
223 Active arm arm926ejs omap ti - omap5912osk - Rishi Bhattacharya <rishi@ti.com> 223 Active arm arm926ejs omap ti - omap5912osk - Rishi Bhattacharya <rishi@ti.com>
224 Active arm arm926ejs orion5x LaCie - edminiv2 - Albert ARIBAUD <albert.u.boot@aribaud.net> 224 Active arm arm926ejs orion5x LaCie - edminiv2 - Albert ARIBAUD <albert.u.boot@aribaud.net>
225 Active arm arm926ejs pantheon Marvell - dkb - Lei Wen <leiwen@marvell.com> 225 Active arm arm926ejs pantheon Marvell - dkb - Lei Wen <leiwen@marvell.com>
226 Active arm arm926ejs spear spear - x600 - Stefan Roese <sr@denx.de> 226 Active arm arm926ejs spear spear - x600 - Stefan Roese <sr@denx.de>
227 Active arm arm926ejs spear spear spear300 spear300 spear3xx_evb:spear300 Vipin Kumar <vipin.kumar@st.com> 227 Active arm arm926ejs spear spear spear300 spear300 spear3xx_evb:spear300 Vipin Kumar <vipin.kumar@st.com>
228 Active arm arm926ejs spear spear spear300 spear300_nand spear3xx_evb:spear300,nand - 228 Active arm arm926ejs spear spear spear300 spear300_nand spear3xx_evb:spear300,nand -
229 Active arm arm926ejs spear spear spear300 spear300_usbtty spear3xx_evb:spear300,usbtty - 229 Active arm arm926ejs spear spear spear300 spear300_usbtty spear3xx_evb:spear300,usbtty -
230 Active arm arm926ejs spear spear spear300 spear300_usbtty_nand spear3xx_evb:spear300,usbtty,nand - 230 Active arm arm926ejs spear spear spear300 spear300_usbtty_nand spear3xx_evb:spear300,usbtty,nand -
231 Active arm arm926ejs spear spear spear310 spear310 spear3xx_evb:spear310 Vipin Kumar <vipin.kumar@st.com> 231 Active arm arm926ejs spear spear spear310 spear310 spear3xx_evb:spear310 Vipin Kumar <vipin.kumar@st.com>
232 Active arm arm926ejs spear spear spear310 spear310_nand spear3xx_evb:spear310,nand - 232 Active arm arm926ejs spear spear spear310 spear310_nand spear3xx_evb:spear310,nand -
233 Active arm arm926ejs spear spear spear310 spear310_pnor spear3xx_evb:spear310,FLASH_PNOR - 233 Active arm arm926ejs spear spear spear310 spear310_pnor spear3xx_evb:spear310,FLASH_PNOR -
234 Active arm arm926ejs spear spear spear310 spear310_usbtty spear3xx_evb:spear310,usbtty - 234 Active arm arm926ejs spear spear spear310 spear310_usbtty spear3xx_evb:spear310,usbtty -
235 Active arm arm926ejs spear spear spear310 spear310_usbtty_nand spear3xx_evb:spear310,usbtty,nand - 235 Active arm arm926ejs spear spear spear310 spear310_usbtty_nand spear3xx_evb:spear310,usbtty,nand -
236 Active arm arm926ejs spear spear spear310 spear310_usbtty_pnor spear3xx_evb:spear310,usbtty,FLASH_PNOR - 236 Active arm arm926ejs spear spear spear310 spear310_usbtty_pnor spear3xx_evb:spear310,usbtty,FLASH_PNOR -
237 Active arm arm926ejs spear spear spear320 spear320 spear3xx_evb:spear320 Vipin Kumar <vipin.kumar@st.com> 237 Active arm arm926ejs spear spear spear320 spear320 spear3xx_evb:spear320 Vipin Kumar <vipin.kumar@st.com>
238 Active arm arm926ejs spear spear spear320 spear320_nand spear3xx_evb:spear320,nand - 238 Active arm arm926ejs spear spear spear320 spear320_nand spear3xx_evb:spear320,nand -
239 Active arm arm926ejs spear spear spear320 spear320_pnor spear3xx_evb:spear320,FLASH_PNOR - 239 Active arm arm926ejs spear spear spear320 spear320_pnor spear3xx_evb:spear320,FLASH_PNOR -
240 Active arm arm926ejs spear spear spear320 spear320_usbtty spear3xx_evb:spear320,usbtty - 240 Active arm arm926ejs spear spear spear320 spear320_usbtty spear3xx_evb:spear320,usbtty -
241 Active arm arm926ejs spear spear spear320 spear320_usbtty_nand spear3xx_evb:spear320,usbtty,nand - 241 Active arm arm926ejs spear spear spear320 spear320_usbtty_nand spear3xx_evb:spear320,usbtty,nand -
242 Active arm arm926ejs spear spear spear320 spear320_usbtty_pnor spear3xx_evb:spear320,usbtty,FLASH_PNOR - 242 Active arm arm926ejs spear spear spear320 spear320_usbtty_pnor spear3xx_evb:spear320,usbtty,FLASH_PNOR -
243 Active arm arm926ejs spear spear spear600 spear600 spear6xx_evb:spear600 Vipin Kumar <vipin.kumar@st.com> 243 Active arm arm926ejs spear spear spear600 spear600 spear6xx_evb:spear600 Vipin Kumar <vipin.kumar@st.com>
244 Active arm arm926ejs spear spear spear600 spear600_nand spear6xx_evb:spear600,nand - 244 Active arm arm926ejs spear spear spear600 spear600_nand spear6xx_evb:spear600,nand -
245 Active arm arm926ejs spear spear spear600 spear600_usbtty spear6xx_evb:spear600,usbtty - 245 Active arm arm926ejs spear spear spear600 spear600_usbtty spear6xx_evb:spear600,usbtty -
246 Active arm arm926ejs spear spear spear600 spear600_usbtty_nand spear6xx_evb:spear600,usbtty,nand - 246 Active arm arm926ejs spear spear spear600 spear600_usbtty_nand spear6xx_evb:spear600,usbtty,nand -
247 Active arm arm926ejs versatile armltd versatile versatileab versatile:ARCH_VERSATILE_AB - 247 Active arm arm926ejs versatile armltd versatile versatileab versatile:ARCH_VERSATILE_AB -
248 Active arm arm926ejs versatile armltd versatile versatilepb versatile:ARCH_VERSATILE_PB - 248 Active arm arm926ejs versatile armltd versatile versatilepb versatile:ARCH_VERSATILE_PB -
249 Active arm arm926ejs versatile armltd versatile versatileqemu versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB - 249 Active arm arm926ejs versatile armltd versatile versatileqemu versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB -
250 Active arm arm946es - armltd integrator integratorap_cm946es integratorap:CM946ES Linus Walleij <linus.walleij@linaro.org> 250 Active arm arm946es - armltd integrator integratorap_cm946es integratorap:CM946ES Linus Walleij <linus.walleij@linaro.org>
251 Active arm arm946es - armltd integrator integratorcp_cm946es integratorcp:CM946ES Linus Walleij <linus.walleij@linaro.org> 251 Active arm arm946es - armltd integrator integratorcp_cm946es integratorcp:CM946ES Linus Walleij <linus.walleij@linaro.org>
252 Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - - 252 Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - -
253 Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel@linaro.org> 253 Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel@linaro.org>
254 Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel@linaro.org> 254 Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel@linaro.org>
255 Active arm armv7 am33xx compulab cm_t335 cm_t335 - Igor Grinberg <grinberg@compulab.co.il> 255 Active arm armv7 am33xx compulab cm_t335 cm_t335 - Igor Grinberg <grinberg@compulab.co.il>
256 Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com> 256 Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com>
257 Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de> 257 Active arm armv7 am33xx phytec pcm051 pcm051_rev1 pcm051:REV1 Lars Poeschel <poeschel@lemonage.de>
258 Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel@lemonage.de> 258 Active arm armv7 am33xx phytec pcm051 pcm051_rev3 pcm051:REV3 Lars Poeschel <poeschel@lemonage.de>
259 Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com> 259 Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com>
260 Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com> 260 Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com>
261 Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com> 261 Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>
262 Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten <lothar.felten@gmail.com> 262 Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten <lothar.felten@gmail.com>
263 Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier <hannes.petermaier@br-automation.com> 263 Active arm armv7 am33xx BuR tseries tseries_nand tseries:SERIAL1,CONS_INDEX=1,NAND Hannes Petermaier <hannes.petermaier@br-automation.com>
264 Active arm armv7 am33xx BuR tseries tseries_mmc tseries:SERIAL1,CONS_INDEX=1,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com> 264 Active arm armv7 am33xx BuR tseries tseries_mmc tseries:SERIAL1,CONS_INDEX=1,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
265 Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com> 265 Active arm armv7 am33xx BuR tseries tseries_spi tseries:SERIAL1,CONS_INDEX=1,SPI_BOOT,EMMC_BOOT Hannes Petermaier <hannes.petermaier@br-automation.com>
266 Active arm armv7 am33xx BuR kwb kwb kwb:SERIAL1,CONS_INDEX=1 Hannes Petermaier <hannes.petermaier@br-automation.com> 266 Active arm armv7 am33xx BuR kwb kwb kwb:SERIAL1,CONS_INDEX=1 Hannes Petermaier <hannes.petermaier@br-automation.com>
267 Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini <trini@ti.com> 267 Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini <trini@ti.com>
268 Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini <trini@ti.com> 268 Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
269 Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini@ti.com> 269 Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini@ti.com>
270 Active arm armv7 am33xx ti am335x am335x_evm_norboot am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT Tom Rini <trini@ti.com> 270 Active arm armv7 am33xx ti am335x am335x_evm_norboot am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT Tom Rini <trini@ti.com>
271 Active arm armv7 am33xx ti am335x am335x_evm_spiboot am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT Tom Rini <trini@ti.com> 271 Active arm armv7 am33xx ti am335x am335x_evm_spiboot am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT Tom Rini <trini@ti.com>
272 Active arm armv7 am33xx ti am335x am335x_evm_uart1 am335x_evm:SERIAL2,CONS_INDEX=2,NAND Tom Rini <trini@ti.com> 272 Active arm armv7 am33xx ti am335x am335x_evm_uart1 am335x_evm:SERIAL2,CONS_INDEX=2,NAND Tom Rini <trini@ti.com>
273 Active arm armv7 am33xx ti am335x am335x_evm_uart2 am335x_evm:SERIAL3,CONS_INDEX=3,NAND Tom Rini <trini@ti.com> 273 Active arm armv7 am33xx ti am335x am335x_evm_uart2 am335x_evm:SERIAL3,CONS_INDEX=3,NAND Tom Rini <trini@ti.com>
274 Active arm armv7 am33xx ti am335x am335x_evm_uart3 am335x_evm:SERIAL4,CONS_INDEX=4,NAND Tom Rini <trini@ti.com> 274 Active arm armv7 am33xx ti am335x am335x_evm_uart3 am335x_evm:SERIAL4,CONS_INDEX=4,NAND Tom Rini <trini@ti.com>
275 Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=5,NAND Tom Rini <trini@ti.com> 275 Active arm armv7 am33xx ti am335x am335x_evm_uart4 am335x_evm:SERIAL5,CONS_INDEX=5,NAND Tom Rini <trini@ti.com>
276 Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND Tom Rini <trini@ti.com> 276 Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND Tom Rini <trini@ti.com>
277 Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini <trini@ti.com> 277 Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini <trini@ti.com>
278 Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com> 278 Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
279 Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <matt.porter@linaro.org> 279 Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <matt.porter@linaro.org>
280 Active arm armv7 am33xx ti ti816x ti816x_evm - - 280 Active arm armv7 am33xx ti ti816x ti816x_evm - -
281 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com> 281 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_mmc sama5d3xek:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
282 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com> 282 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_nandflash sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH Bo Shen <voice.shen@atmel.com>
283 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_spiflash sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH Bo Shen <voice.shen@atmel.com> 283 Active arm armv7 at91 atmel sama5d3xek sama5d3xek_spiflash sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH Bo Shen <voice.shen@atmel.com>
284 Active arm armv7 bcm281xx broadcom bcm28155_ap bcm28155_ap bcm28155_ap Tim Kryger <tim.kryger@linaro.org> 284 Active arm armv7 bcm281xx broadcom bcm28155_ap bcm28155_ap bcm28155_ap Tim Kryger <tim.kryger@linaro.org>
285 Active arm armv7 exynos samsung arndale arndale - Inderpal Singh <inderpal.singh@linaro.org> 285 Active arm armv7 exynos samsung arndale arndale - Inderpal Singh <inderpal.singh@linaro.org>
286 Active arm armv7 exynos samsung origen origen - Chander Kashyap <k.chander@samsung.com> 286 Active arm armv7 exynos samsung origen origen - Chander Kashyap <k.chander@samsung.com>
287 Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap <k.chander@samsung.com> 287 Active arm armv7 exynos samsung smdk5250 smdk5250 - Chander Kashyap <k.chander@samsung.com>
288 Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde <rajeshwari.s@samsung.com> 288 Active arm armv7 exynos samsung smdk5250 snow - Rajeshwari Shinde <rajeshwari.s@samsung.com>
289 Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde <rajeshwari.s@samsung.com> 289 Active arm armv7 exynos samsung smdk5420 smdk5420 - Rajeshwari Shinde <rajeshwari.s@samsung.com>
290 Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap <k.chander@samsung.com> 290 Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap <k.chander@samsung.com>
291 Active arm armv7 exynos samsung trats trats - Lukasz Majewski <l.majewski@samsung.com> 291 Active arm armv7 exynos samsung trats trats - Lukasz Majewski <l.majewski@samsung.com>
292 Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com> 292 Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek <p.wilczek@samsung.com>
293 Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak <p.marczak@samsung.com> 293 Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak <p.marczak@samsung.com>
294 Active arm armv7 highbank - highbank highbank - Rob Herring <rob.herring@calxeda.com> 294 Active arm armv7 highbank - highbank highbank - Rob Herring <rob.herring@calxeda.com>
295 Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com> 295 Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut <marek.vasut@gmail.com>
296 Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - 296 Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg -
297 Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sbabic@denx.de> 297 Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic <sbabic@denx.de>
298 Active arm armv7 mx5 freescale mx53ard mx53ard mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg Fabio Estevam <fabio.estevam@freescale.com> 298 Active arm armv7 mx5 freescale mx53ard mx53ard mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg Fabio Estevam <fabio.estevam@freescale.com>
299 Active arm armv7 mx5 freescale mx53evk mx53evk mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg Jason Liu <r64343@freescale.com> 299 Active arm armv7 mx5 freescale mx53evk mx53evk mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg Jason Liu <r64343@freescale.com>
300 Active arm armv7 mx5 freescale mx53loco mx53loco mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg Jason Liu <r64343@freescale.com> 300 Active arm armv7 mx5 freescale mx53loco mx53loco mx53loco:IMX_CONFIG=board/freescale/mx53loco/imximage.cfg Jason Liu <r64343@freescale.com>
301 Active arm armv7 mx5 freescale mx53smd mx53smd mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com> 301 Active arm armv7 mx5 freescale mx53smd mx53smd mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg Fabio Estevam <fabio.estevam@freescale.com>
302 Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - 302 Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg -
303 Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - 303 Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg -
304 Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic@denx.de> 304 Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic@denx.de>
305 Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com> 305 Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/udoo/udoo.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
306 Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com> 306 Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com>
307 Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com> 307 Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com>
308 Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam@freescale.com> 308 Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam@freescale.com>
309 Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr@denx.de> 309 Active arm armv7 mx6 barco titanium titanium titanium:IMX_CONFIG=board/barco/titanium/imximage.cfg Stefan Roese <sr@denx.de>
310 Active arm armv7 mx6 boundary nitrogen6x mx6qsabrelite nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE Eric Nelson <eric.nelson@boundarydevices.com> 310 Active arm armv7 mx6 boundary nitrogen6x mx6qsabrelite nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE Eric Nelson <eric.nelson@boundarydevices.com>
311 Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com> 311 Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
312 Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com> 312 Active arm armv7 mx6 boundary nitrogen6x nitrogen6dl2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl2g.cfg,MX6DL,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com>
313 Active arm armv7 mx6 boundary nitrogen6x nitrogen6q nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com> 313 Active arm armv7 mx6 boundary nitrogen6x nitrogen6q nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
314 Active arm armv7 mx6 boundary nitrogen6x nitrogen6q2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com> 314 Active arm armv7 mx6 boundary nitrogen6x nitrogen6q2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com>
315 Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson <eric.nelson@boundarydevices.com> 315 Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson <eric.nelson@boundarydevices.com>
316 Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com> 316 Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
317 Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com> 317 Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com>
318 Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343@freescale.com> 318 Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343@freescale.com>
319 Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com> 319 Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
320 Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com> 320 Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
321 Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com> 321 Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
322 Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com> 322 Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
323 Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com> 323 Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com>
324 Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com> 324 Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
325 Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com> 325 Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
326 Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph@8d.com> 326 Active arm armv7 omap3 8dtech eco5pk eco5pk - Raphael Assenat <raph@8d.com>
327 Active arm armv7 omap3 comelit dig297 dig297 - Luca Ceresoli <luca.ceresoli@comelit.it> 327 Active arm armv7 omap3 comelit dig297 dig297 - Luca Ceresoli <luca.ceresoli@comelit.it>
328 Active arm armv7 omap3 compulab cm_t35 cm_t35 - Igor Grinberg <grinberg@compulab.co.il> 328 Active arm armv7 omap3 compulab cm_t35 cm_t35 - Igor Grinberg <grinberg@compulab.co.il>
329 Active arm armv7 omap3 corscience tricorder tricorder - Thomas Weber <weber@corscience.de> 329 Active arm armv7 omap3 corscience tricorder tricorder - Thomas Weber <weber@corscience.de>
330 Active arm armv7 omap3 corscience tricorder tricorder_flash tricorder:FLASHCARD Thomas Weber <weber@corscience.de> 330 Active arm armv7 omap3 corscience tricorder tricorder_flash tricorder:FLASHCARD Thomas Weber <weber@corscience.de>
331 Active arm armv7 omap3 htkw mcx mcx - Ilya Yanok <yanok@emcraft.com> 331 Active arm armv7 omap3 htkw mcx mcx - Ilya Yanok <yanok@emcraft.com>
332 Active arm armv7 omap3 isee igep00x0 igep0020 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com> 332 Active arm armv7 omap3 isee igep00x0 igep0020 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
333 Active arm armv7 omap3 isee igep00x0 igep0020_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND - 333 Active arm armv7 omap3 isee igep00x0 igep0020_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND -
334 Active arm armv7 omap3 isee igep00x0 igep0030 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com> 334 Active arm armv7 omap3 isee igep00x0 igep0030 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
335 Active arm armv7 omap3 isee igep00x0 igep0030_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND - 335 Active arm armv7 omap3 isee igep00x0 igep0030_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND -
336 Active arm armv7 omap3 isee igep00x0 igep0032 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com> 336 Active arm armv7 omap3 isee igep00x0 igep0032 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com>
337 Active arm armv7 omap3 logicpd am3517evm am3517_evm - Vaibhav Hiremath <hvaibhav@ti.com> 337 Active arm armv7 omap3 logicpd am3517evm am3517_evm - Vaibhav Hiremath <hvaibhav@ti.com>
338 Active arm armv7 omap3 logicpd omap3som omap3_logic - Peter Barada <peter.barada@logicpd.com> 338 Active arm armv7 omap3 logicpd omap3som omap3_logic - Peter Barada <peter.barada@logicpd.com>
339 Active arm armv7 omap3 logicpd zoom1 omap3_zoom1 - Nishanth Menon <nm@ti.com> 339 Active arm armv7 omap3 logicpd zoom1 omap3_zoom1 - Nishanth Menon <nm@ti.com>
340 Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones <michael.jones@matrix-vision.de> 340 Active arm armv7 omap3 matrix_vision mvblx omap3_mvblx - Michael Jones <michael.jones@matrix-vision.de>
341 Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohár <pali.rohar@gmail.com> 341 Active arm armv7 omap3 nokia rx51 nokia_rx51 - Pali Rohár <pali.rohar@gmail.com>
342 Active arm armv7 omap3 technexion tao3530 omap3_ha tao3530:SYS_BOARD_OMAP3_HA Stefan Roese <sr@denx.de> 342 Active arm armv7 omap3 technexion tao3530 omap3_ha tao3530:SYS_BOARD_OMAP3_HA Stefan Roese <sr@denx.de>
343 Active arm armv7 omap3 technexion tao3530 tao3530 - Tapani Utriainen <linuxfae@technexion.com> 343 Active arm armv7 omap3 technexion tao3530 tao3530 - Tapani Utriainen <linuxfae@technexion.com>
344 Active arm armv7 omap3 technexion twister twister - Stefano Babic <sbabic@denx.de> 344 Active arm armv7 omap3 technexion twister twister - Stefano Babic <sbabic@denx.de>
345 Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic <sbabic@denx.de> 345 Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic <sbabic@denx.de>
346 Active arm armv7 omap3 ti am3517crane am3517_crane - Nagendra T S <nagendra@mistralsolutions.com> 346 Active arm armv7 omap3 ti am3517crane am3517_crane - Nagendra T S <nagendra@mistralsolutions.com>
347 Active arm armv7 omap3 ti beagle omap3_beagle - Tom Rini <trini@ti.com> 347 Active arm armv7 omap3 ti beagle omap3_beagle - Tom Rini <trini@ti.com>
348 Active arm armv7 omap3 ti evm omap3_evm - Tom Rini <trini@ti.com> 348 Active arm armv7 omap3 ti evm omap3_evm - Tom Rini <trini@ti.com>
349 Active arm armv7 omap3 ti evm omap3_evm_quick_mmc - - 349 Active arm armv7 omap3 ti evm omap3_evm_quick_mmc - -
350 Active arm armv7 omap3 ti evm omap3_evm_quick_nand - - 350 Active arm armv7 omap3 ti evm omap3_evm_quick_nand - -
351 Active arm armv7 omap3 ti sdp3430 omap3_sdp3430 - Nishanth Menon <nm@ti.com> 351 Active arm armv7 omap3 ti sdp3430 omap3_sdp3430 - Nishanth Menon <nm@ti.com>
352 Active arm armv7 omap3 timll devkit8000 devkit8000 - Thomas Weber <weber@corscience.de> 352 Active arm armv7 omap3 timll devkit8000 devkit8000 - Thomas Weber <weber@corscience.de>
353 Active arm armv7 omap4 ti panda omap4_panda - Sricharan R <r.sricharan@ti.com> 353 Active arm armv7 omap4 ti panda omap4_panda - Sricharan R <r.sricharan@ti.com>
354 Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R <r.sricharan@ti.com> 354 Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R <r.sricharan@ti.com>
355 Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com> 355 Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
356 Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla <lokeshvutla@ti.com> 356 Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla <lokeshvutla@ti.com>
357 Active arm armv7 omap5 ti omap5_uevm omap5_uevm - - 357 Active arm armv7 omap5 ti omap5_uevm omap5_uevm - -
358 Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 358 Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
359 Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp> 359 Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
360 Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 360 Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
361 Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 361 Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
362 Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 362 Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
363 Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 363 Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
364 Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega <m.zalega@samsung.com> 364 Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega <m.zalega@samsung.com>
365 Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com> 365 Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
366 Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - 366 Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
367 Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org> 367 Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier <mathieu.poirier@linaro.org>
368 Active arm armv7 u8500 st-ericsson u8500 u8500_href - - 368 Active arm armv7 u8500 st-ericsson u8500 u8500_href - -
369 Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com> 369 Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang <b18965@freescale.com>
370 Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 370 Active arm armv7 zynq xilinx zynq zynq_microzed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
371 Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 371 Active arm armv7 zynq xilinx zynq zynq_zc70x - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
372 Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 372 Active arm armv7 zynq xilinx zynq zynq_zc770_xm010 zynq_zc770:ZC770_XM010 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
373 Active arm armv7 zynq xilinx zynq zynq_zc770_xm012 zynq_zc770:ZC770_XM012 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 373 Active arm armv7 zynq xilinx zynq zynq_zc770_xm012 zynq_zc770:ZC770_XM012 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
374 Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 374 Active arm armv7 zynq xilinx zynq zynq_zc770_xm013 zynq_zc770:ZC770_XM013 Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
375 Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com> 375 Active arm armv7 zynq xilinx zynq zynq_zed - Michal Simek <monstr@monstr.eu>:Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
376 Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com> 376 Active arm armv7:arm720t tegra114 nvidia dalmore dalmore - Tom Warren <twarren@nvidia.com>
377 Active arm armv7:arm720t tegra124 nvidia venice2 venice2 - Tom Warren <twarren@nvidia.com> 377 Active arm armv7:arm720t tegra124 nvidia venice2 venice2 - Tom Warren <twarren@nvidia.com>
378 Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel <alban.bedel@avionic-design.de> 378 Active arm armv7:arm720t tegra20 avionic-design medcom-wide medcom-wide - Alban Bedel <alban.bedel@avionic-design.de>
379 Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel <alban.bedel@avionic-design.de> 379 Active arm armv7:arm720t tegra20 avionic-design plutux plutux - Alban Bedel <alban.bedel@avionic-design.de>
380 Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel <alban.bedel@avionic-design.de> 380 Active arm armv7:arm720t tegra20 avionic-design tec tec - Alban Bedel <alban.bedel@avionic-design.de>
381 Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com> 381 Active arm armv7:arm720t tegra20 compal paz00 paz00 - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
382 Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com> 382 Active arm armv7:arm720t tegra20 compulab trimslice trimslice - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
383 Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren <twarren@nvidia.com> 383 Active arm armv7:arm720t tegra20 nvidia harmony harmony - Tom Warren <twarren@nvidia.com>
384 Active arm armv7:arm720t tegra20 nvidia seaboard seaboard - Tom Warren <twarren@nvidia.com> 384 Active arm armv7:arm720t tegra20 nvidia seaboard seaboard - Tom Warren <twarren@nvidia.com>
385 Active arm armv7:arm720t tegra20 nvidia ventana ventana - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com> 385 Active arm armv7:arm720t tegra20 nvidia ventana ventana - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
386 Active arm armv7:arm720t tegra20 nvidia whistler whistler - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com> 386 Active arm armv7:arm720t tegra20 nvidia whistler whistler - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
387 Active arm armv7:arm720t tegra20 toradex colibri_t20_iris colibri_t20_iris - Lucas Stach <dev@lynxeye.de> 387 Active arm armv7:arm720t tegra20 toradex colibri_t20_iris colibri_t20_iris - Lucas Stach <dev@lynxeye.de>
388 Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel <alban.bedel@avionic-design.de> 388 Active arm armv7:arm720t tegra30 avionic-design tec-ng tec-ng - Alban Bedel <alban.bedel@avionic-design.de>
389 Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com> 389 Active arm armv7:arm720t tegra30 nvidia beaver beaver - Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
390 Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren <twarren@nvidia.com> 390 Active arm armv7:arm720t tegra30 nvidia cardhu cardhu - Tom Warren <twarren@nvidia.com>
391 Active arm pxa - - - balloon3 - Marek Vasut <marek.vasut@gmail.com> 391 Active arm pxa - - - balloon3 - Marek Vasut <marek.vasut@gmail.com>
392 Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com> 392 Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com>
393 Active arm pxa - - - palmld - Marek Vasut <marek.vasut@gmail.com> 393 Active arm pxa - - - palmld - Marek Vasut <marek.vasut@gmail.com>
394 Active arm pxa - - - palmtc - Marek Vasut <marek.vasut@gmail.com> 394 Active arm pxa - - - palmtc - Marek Vasut <marek.vasut@gmail.com>
395 Active arm pxa - - - palmtreo680 - Mike Dunn <mikedunn@newsguy.com> 395 Active arm pxa - - - palmtreo680 - Mike Dunn <mikedunn@newsguy.com>
396 Active arm pxa - - - pxa255_idp - Cliff Brake <cliff.brake@gmail.com> 396 Active arm pxa - - - pxa255_idp - Cliff Brake <cliff.brake@gmail.com>
397 Active arm pxa - - - trizepsiv - Stefano Babic <sbabic@denx.de> 397 Active arm pxa - - - trizepsiv - Stefano Babic <sbabic@denx.de>
398 Active arm pxa - - - xaeniax - - 398 Active arm pxa - - - xaeniax - -
399 Active arm pxa - - - zipitz2 - Marek Vasut <marek.vasut@gmail.com> 399 Active arm pxa - - - zipitz2 - Marek Vasut <marek.vasut@gmail.com>
400 Active arm pxa - - trizepsiv polaris trizepsiv:POLARIS Stefano Babic <sbabic@denx.de> 400 Active arm pxa - - trizepsiv polaris trizepsiv:POLARIS Stefano Babic <sbabic@denx.de>
401 Active arm pxa - - vpac270 vpac270_nor_128 vpac270:NOR,RAM_128M Marek Vasut <marek.vasut@gmail.com> 401 Active arm pxa - - vpac270 vpac270_nor_128 vpac270:NOR,RAM_128M Marek Vasut <marek.vasut@gmail.com>
402 Active arm pxa - - vpac270 vpac270_nor_256 vpac270:NOR,RAM_256M Marek Vasut <marek.vasut@gmail.com> 402 Active arm pxa - - vpac270 vpac270_nor_256 vpac270:NOR,RAM_256M Marek Vasut <marek.vasut@gmail.com>
403 Active arm pxa - - vpac270 vpac270_ond_256 vpac270:ONENAND,RAM_256M Marek Vasut <marek.vasut@gmail.com> 403 Active arm pxa - - vpac270 vpac270_ond_256 vpac270:ONENAND,RAM_256M Marek Vasut <marek.vasut@gmail.com>
404 Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich@gmail.com> 404 Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich@gmail.com>
405 Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut@gmail.com> 405 Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut@gmail.com>
406 Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson@gmail.com> 406 Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson@gmail.com>
407 Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com> 407 Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
408 Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann <andreas.devel@googlemail.com> 408 Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann <andreas.devel@googlemail.com>
409 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com> 409 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
410 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com> 410 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
411 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com> 411 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
412 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com> 412 Active avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
413 Active avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> 413 Active avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
414 Active avr32 at32ap at32ap700x in-circuit - grasshopper - Andreas Bießmann <andreas.devel@googlemail.com> 414 Active avr32 at32ap at32ap700x in-circuit - grasshopper - Andreas Bießmann <andreas.devel@googlemail.com>
415 Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson <mpfj@mimc.co.uk> 415 Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson <mpfj@mimc.co.uk>
416 Active avr32 at32ap at32ap700x miromico - hammerhead - Julien May <julien.may@miromico.ch>:Alex Raimondi <alex.raimondi@miromico.ch> 416 Active avr32 at32ap at32ap700x miromico - hammerhead - Julien May <julien.may@miromico.ch>:Alex Raimondi <alex.raimondi@miromico.ch>
417 Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald <devel@bct-electronic.com> 417 Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald <devel@bct-electronic.com>
418 Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 418 Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
419 Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 419 Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
420 Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang <hzhang@ucrobotics.com>:Chong Huang <chuang@ucrobotics.com> 420 Active blackfin blackfin - - - bf525-ucr2 - Haitao Zhang <hzhang@ucrobotics.com>:Chong Huang <chuang@ucrobotics.com>
421 Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 421 Active blackfin blackfin - - - bf526-ezbrd - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
422 Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 422 Active blackfin blackfin - - - bf527-ad7160-eval - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
423 Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 423 Active blackfin blackfin - - - bf527-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
424 Active blackfin blackfin - - - bf527-sdp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 424 Active blackfin blackfin - - - bf527-sdp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
425 Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 425 Active blackfin blackfin - - - bf533-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
426 Active blackfin blackfin - - - bf533-stamp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 426 Active blackfin blackfin - - - bf533-stamp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
427 Active blackfin blackfin - - - bf537-minotaur - Martin Strubel <strubel@section5.ch> 427 Active blackfin blackfin - - - bf537-minotaur - Martin Strubel <strubel@section5.ch>
428 Active blackfin blackfin - - - bf537-pnav - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 428 Active blackfin blackfin - - - bf537-pnav - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
429 Active blackfin blackfin - - - bf537-srv1 - Martin Strubel <strubel@section5.ch> 429 Active blackfin blackfin - - - bf537-srv1 - Martin Strubel <strubel@section5.ch>
430 Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 430 Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
431 Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 431 Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
432 Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 432 Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
433 Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin <shurpin.aa@niistt.ru>:Valentin Yakovenkov <yakovenkov@niistt.ru> 433 Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin <shurpin.aa@niistt.ru>:Valentin Yakovenkov <yakovenkov@niistt.ru>
434 Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 434 Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
435 Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 435 Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
436 Active blackfin blackfin - - - blackstamp - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com> 436 Active blackfin blackfin - - - blackstamp - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
437 Active blackfin blackfin - - - blackvme - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com> 437 Active blackfin blackfin - - - blackvme - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
438 Active blackfin blackfin - - - br4 - Dimitar Penev <dpn@switchfin.org> 438 Active blackfin blackfin - - - br4 - Dimitar Penev <dpn@switchfin.org>
439 Active blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 439 Active blackfin blackfin - - - cm-bf527 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
440 Active blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 440 Active blackfin blackfin - - - cm-bf533 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
441 Active blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 441 Active blackfin blackfin - - - cm-bf537e - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
442 Active blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 442 Active blackfin blackfin - - - cm-bf537u - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
443 Active blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 443 Active blackfin blackfin - - - cm-bf548 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
444 Active blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 444 Active blackfin blackfin - - - cm-bf561 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
445 Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) <info@ssv-embedded.de> 445 Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) <info@ssv-embedded.de>
446 Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule <support@i-syst.com> 446 Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule <support@i-syst.com>
447 Active blackfin blackfin - - - ip04 - Brent Kandetzki <brentk@teleco.com> 447 Active blackfin blackfin - - - ip04 - Brent Kandetzki <brentk@teleco.com>
448 Active blackfin blackfin - - - pr1 - Dimitar Penev <dpn@switchfin.org> 448 Active blackfin blackfin - - - pr1 - Dimitar Penev <dpn@switchfin.org>
449 Active blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 449 Active blackfin blackfin - - - tcm-bf518 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
450 Active blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org> 450 Active blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
451 Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org> 451 Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi@gmail.com>:Blackfin Team <u-boot-devel@blackfin.uclinux.org>
452 Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 452 Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
453 Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 453 Active m68k mcf5227x - freescale m52277evb M52277EVB_stmicro M52277EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x43E00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
454 Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 454 Active m68k mcf523x - freescale m5235evb M5235EVB M5235EVB:SYS_TEXT_BASE=0xFFE00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
455 Active m68k mcf523x - freescale m5235evb M5235EVB_Flash32 M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 455 Active m68k mcf523x - freescale m5235evb M5235EVB_Flash32 M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
456 Active m68k mcf52x2 - - - idmr - - 456 Active m68k mcf52x2 - - - idmr - -
457 Active m68k mcf52x2 - - cobra5272 cobra5272 - - 457 Active m68k mcf52x2 - - cobra5272 cobra5272 - -
458 Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282 eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 Jens Scharsig <esw@bus-elektronik.de> 458 Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282 eb_cpu5282:SYS_TEXT_BASE=0xFF000000,SYS_MONITOR_BASE=0xFF000400 Jens Scharsig <esw@bus-elektronik.de>
459 Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282_internal eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 Jens Scharsig <esw@bus-elektronik.de> 459 Active m68k mcf52x2 - BuS eb_cpu5282 eb_cpu5282_internal eb_cpu5282:SYS_TEXT_BASE=0xF0000000,SYS_MONITOR_BASE=0xF0000418 Jens Scharsig <esw@bus-elektronik.de>
460 Active m68k mcf52x2 - esd tasreg TASREG - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 460 Active m68k mcf52x2 - esd tasreg TASREG - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
461 Active m68k mcf52x2 - freescale m5208evbe M5208EVBE - - 461 Active m68k mcf52x2 - freescale m5208evbe M5208EVBE - -
462 Active m68k mcf52x2 - freescale m5249evb M5249EVB - - 462 Active m68k mcf52x2 - freescale m5249evb M5249EVB - -
463 Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew <Tsi-Chung.Liew@freescale.com> 463 Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
464 Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com> 464 Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com>
465 Active m68k mcf52x2 - freescale m5271evb M5271EVB - - 465 Active m68k mcf52x2 - freescale m5271evb M5271EVB - -
466 Active m68k mcf52x2 - freescale m5272c3 M5272C3 - - 466 Active m68k mcf52x2 - freescale m5272c3 M5272C3 - -
467 Active m68k mcf52x2 - freescale m5275evb M5275EVB - - 467 Active m68k mcf52x2 - freescale m5275evb M5275EVB - -
468 Active m68k mcf52x2 - freescale m5282evb M5282EVB - - 468 Active m68k mcf52x2 - freescale m5282evb M5282EVB - -
469 Active m68k mcf532x - astro mcf5373l astro_mcf5373l - Wolfgang Wegner <w.wegner@astro-kom.de> 469 Active m68k mcf532x - astro mcf5373l astro_mcf5373l - Wolfgang Wegner <w.wegner@astro-kom.de>
470 Active m68k mcf532x - freescale m53017evb M53017EVB - TsiChung Liew <Tsi-Chung.Liew@freescale.com> 470 Active m68k mcf532x - freescale m53017evb M53017EVB - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
471 Active m68k mcf532x - freescale m5329evb M5329AFEE M5329EVB:NANDFLASH_SIZE=0 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 471 Active m68k mcf532x - freescale m5329evb M5329AFEE M5329EVB:NANDFLASH_SIZE=0 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
472 Active m68k mcf532x - freescale m5329evb M5329BFEE M5329EVB:NANDFLASH_SIZE=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 472 Active m68k mcf532x - freescale m5329evb M5329BFEE M5329EVB:NANDFLASH_SIZE=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
473 Active m68k mcf532x - freescale m5373evb M5373EVB M5373EVB:NANDFLASH_SIZE=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 473 Active m68k mcf532x - freescale m5373evb M5373EVB M5373EVB:NANDFLASH_SIZE=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
474 Active m68k mcf5445x - freescale m54418twr M54418TWR M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - 474 Active m68k mcf5445x - freescale m54418twr M54418TWR M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
475 Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_mii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 - 475 Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_mii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 -
476 Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - 476 Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii M54418TWR:SYS_NAND_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
477 Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii_lowfreq M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - 477 Active m68k mcf5445x - freescale m54418twr M54418TWR_nand_rmii_lowfreq M54418TWR:SYS_NAND_BOOT,LOW_MCFCLK,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
478 Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_mii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 - 478 Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_mii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=25000000 -
479 Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_rmii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 - 479 Active m68k mcf5445x - freescale m54418twr M54418TWR_serial_rmii M54418TWR:CF_SBF,SYS_SERIAL_BOOT,SYS_TEXT_BASE=0x47E00000,SYS_INPUT_CLKSRC=50000000 -
480 Active m68k mcf5445x - freescale m54451evb M54451EVB M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000 - 480 Active m68k mcf5445x - freescale m54451evb M54451EVB M54451EVB:SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=24000000 -
481 Active m68k mcf5445x - freescale m54451evb M54451EVB_stmicro M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000 - 481 Active m68k mcf5445x - freescale m54451evb M54451EVB_stmicro M54451EVB:CF_SBF,SYS_STMICRO_BOOT,SYS_TEXT_BASE=0x47e00000,SYS_INPUT_CLKSRC=24000000 -
482 Active m68k mcf5445x - freescale m54455evb M54455EVB M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 482 Active m68k mcf5445x - freescale m54455evb M54455EVB M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
483 Active m68k mcf5445x - freescale m54455evb M54455EVB_a66 M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 483 Active m68k mcf5445x - freescale m54455evb M54455EVB_a66 M54455EVB:SYS_ATMEL_BOOT,SYS_TEXT_BASE=0x04000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
484 Active m68k mcf5445x - freescale m54455evb M54455EVB_i66 M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 484 Active m68k mcf5445x - freescale m54455evb M54455EVB_i66 M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=66666666 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
485 Active m68k mcf5445x - freescale m54455evb M54455EVB_intel M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 485 Active m68k mcf5445x - freescale m54455evb M54455EVB_intel M54455EVB:SYS_INTEL_BOOT,SYS_TEXT_BASE=0x00000000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
486 Active m68k mcf5445x - freescale m54455evb M54455EVB_stm33 M54455EVB:SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 486 Active m68k mcf5445x - freescale m54455evb M54455EVB_stm33 M54455EVB:SYS_STMICRO_BOOT,CF_SBF,SYS_TEXT_BASE=0x4FE00000,SYS_INPUT_CLKSRC=33333333 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
487 Active m68k mcf547x_8x - freescale m547xevb M5475AFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 487 Active m68k mcf547x_8x - freescale m547xevb M5475AFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
488 Active m68k mcf547x_8x - freescale m547xevb M5475BFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 488 Active m68k mcf547x_8x - freescale m547xevb M5475BFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
489 Active m68k mcf547x_8x - freescale m547xevb M5475CFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com> 489 Active m68k mcf547x_8x - freescale m547xevb M5475CFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
490 Active m68k mcf547x_8x - freescale m547xevb M5475DFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com> 490 Active m68k mcf547x_8x - freescale m547xevb M5475DFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
491 Active m68k mcf547x_8x - freescale m547xevb M5475EFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com> 491 Active m68k mcf547x_8x - freescale m547xevb M5475EFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
492 Active m68k mcf547x_8x - freescale m547xevb M5475FFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 492 Active m68k mcf547x_8x - freescale m547xevb M5475FFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
493 Active m68k mcf547x_8x - freescale m547xevb M5475GFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 493 Active m68k mcf547x_8x - freescale m547xevb M5475GFE M5475EVB:SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
494 Active m68k mcf547x_8x - freescale m548xevb M5485AFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 494 Active m68k mcf547x_8x - freescale m548xevb M5485AFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
495 Active m68k mcf547x_8x - freescale m548xevb M5485BFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 495 Active m68k mcf547x_8x - freescale m548xevb M5485BFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
496 Active m68k mcf547x_8x - freescale m548xevb M5485CFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com> 496 Active m68k mcf547x_8x - freescale m548xevb M5485CFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
497 Active m68k mcf547x_8x - freescale m548xevb M5485DFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com> 497 Active m68k mcf547x_8x - freescale m548xevb M5485DFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
498 Active m68k mcf547x_8x - freescale m548xevb M5485EFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com> 498 Active m68k mcf547x_8x - freescale m548xevb M5485EFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL TsiChung Liew <Tsi-Chung.Liew@freescale.com>
499 Active m68k mcf547x_8x - freescale m548xevb M5485FFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 499 Active m68k mcf547x_8x - freescale m548xevb M5485FFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
500 Active m68k mcf547x_8x - freescale m548xevb M5485GFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com> 500 Active m68k mcf547x_8x - freescale m548xevb M5485GFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
501 Active m68k mcf547x_8x - freescale m548xevb M5485HFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO TsiChung Liew <Tsi-Chung.Liew@freescale.com> 501 Active m68k mcf547x_8x - freescale m548xevb M5485HFE M5485EVB:SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO TsiChung Liew <Tsi-Chung.Liew@freescale.com>
502 Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek <monstr@monstr.eu> 502 Active microblaze microblaze - xilinx microblaze-generic microblaze-generic - Michal Simek <monstr@monstr.eu>
503 Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu <vlad.lungu@windriver.com> 503 Active mips mips32 - - qemu-mips qemu_mips qemu-mips:SYS_BIG_ENDIAN Vlad Lungu <vlad.lungu@windriver.com>
504 Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN - 504 Active mips mips32 - - qemu-mips qemu_mipsel qemu-mips:SYS_LITTLE_ENDIAN -
505 Active mips mips32 - imgtec malta malta malta:SYS_BIG_ENDIAN Paul Burton <paul.burton@imgtec.com> 505 Active mips mips32 - imgtec malta malta malta:SYS_BIG_ENDIAN Paul Burton <paul.burton@imgtec.com>
506 Active mips mips32 - imgtec malta maltael malta:SYS_LITTLE_ENDIAN Paul Burton <paul.burton@imgtec.com> 506 Active mips mips32 - imgtec malta maltael malta:SYS_LITTLE_ENDIAN Paul Burton <paul.burton@imgtec.com>
507 Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM - 507 Active mips mips32 - micronas vct vct_platinum vct:VCT_PLATINUM -
508 Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND - 508 Active mips mips32 - micronas vct vct_platinum_onenand vct:VCT_PLATINUM,VCT_ONENAND -
509 Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE - 509 Active mips mips32 - micronas vct vct_platinum_onenand_small vct:VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE -
510 Active mips mips32 - micronas vct vct_platinum_small vct:VCT_PLATINUM,VCT_SMALL_IMAGE - 510 Active mips mips32 - micronas vct vct_platinum_small vct:VCT_PLATINUM,VCT_SMALL_IMAGE -
511 Active mips mips32 - micronas vct vct_platinumavc vct:VCT_PLATINUMAVC - 511 Active mips mips32 - micronas vct vct_platinumavc vct:VCT_PLATINUMAVC -
512 Active mips mips32 - micronas vct vct_platinumavc_onenand vct:VCT_PLATINUMAVC,VCT_ONENAND - 512 Active mips mips32 - micronas vct vct_platinumavc_onenand vct:VCT_PLATINUMAVC,VCT_ONENAND -
513 Active mips mips32 - micronas vct vct_platinumavc_onenand_small vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE - 513 Active mips mips32 - micronas vct vct_platinumavc_onenand_small vct:VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE -
514 Active mips mips32 - micronas vct vct_platinumavc_small vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE - 514 Active mips mips32 - micronas vct vct_platinumavc_small vct:VCT_PLATINUMAVC,VCT_SMALL_IMAGE -
515 Active mips mips32 - micronas vct vct_premium vct:VCT_PREMIUM - 515 Active mips mips32 - micronas vct vct_premium vct:VCT_PREMIUM -
516 Active mips mips32 - micronas vct vct_premium_onenand vct:VCT_PREMIUM,VCT_ONENAND - 516 Active mips mips32 - micronas vct vct_premium_onenand vct:VCT_PREMIUM,VCT_ONENAND -
517 Active mips mips32 - micronas vct vct_premium_onenand_small vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE - 517 Active mips mips32 - micronas vct vct_premium_onenand_small vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE -
518 Active mips mips32 - micronas vct vct_premium_small vct:VCT_PREMIUM,VCT_SMALL_IMAGE - 518 Active mips mips32 - micronas vct vct_premium_small vct:VCT_PREMIUM,VCT_SMALL_IMAGE -
519 Active mips mips32 au1x00 - dbau1x00 dbau1000 dbau1x00:DBAU1000 Thomas Lange <thomas@corelatus.se> 519 Active mips mips32 au1x00 - dbau1x00 dbau1000 dbau1x00:DBAU1000 Thomas Lange <thomas@corelatus.se>
520 Active mips mips32 au1x00 - dbau1x00 dbau1100 dbau1x00:DBAU1100 Thomas Lange <thomas@corelatus.se> 520 Active mips mips32 au1x00 - dbau1x00 dbau1100 dbau1x00:DBAU1100 Thomas Lange <thomas@corelatus.se>
521 Active mips mips32 au1x00 - dbau1x00 dbau1500 dbau1x00:DBAU1500 Thomas Lange <thomas@corelatus.se> 521 Active mips mips32 au1x00 - dbau1x00 dbau1500 dbau1x00:DBAU1500 Thomas Lange <thomas@corelatus.se>
522 Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se> 522 Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se>
523 Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se> 523 Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se>
524 Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 - 524 Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 -
525 Active mips mips32 incaip - incaip incaip - Wolfgang Denk <wd@denx.de> 525 Active mips mips32 incaip - incaip incaip - Wolfgang Denk <wd@denx.de>
526 Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de> 526 Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
527 Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de> 527 Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
528 Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de> 528 Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
529 Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN - 529 Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
530 Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN - 530 Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
531 Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com> 531 Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
532 Active nds32 n1213 ag101 AndesTech adp-ag101p adp-ag101p - Andes <uboot@andestech.com> 532 Active nds32 n1213 ag101 AndesTech adp-ag101p adp-ag101p - Andes <uboot@andestech.com>
533 Active nds32 n1213 ag102 AndesTech adp-ag102 adp-ag102 - Andes <uboot@andestech.com> 533 Active nds32 n1213 ag102 AndesTech adp-ag102 adp-ag102 - Andes <uboot@andestech.com>
534 Active nios2 nios2 - altera nios2-generic nios2-generic - Scott McNutt <smcnutt@psyent.com> 534 Active nios2 nios2 - altera nios2-generic nios2-generic - Scott McNutt <smcnutt@psyent.com>
535 Active nios2 nios2 - psyent pci5441 PCI5441 - Scott McNutt <smcnutt@psyent.com> 535 Active nios2 nios2 - psyent pci5441 PCI5441 - Scott McNutt <smcnutt@psyent.com>
536 Active nios2 nios2 - psyent pk1c20 PK1C20 - Scott McNutt <smcnutt@psyent.com> 536 Active nios2 nios2 - psyent pk1c20 PK1C20 - Scott McNutt <smcnutt@psyent.com>
537 Active openrisc or1200 - openrisc openrisc-generic openrisc-generic - Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> 537 Active openrisc or1200 - openrisc openrisc-generic openrisc-generic - Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
538 Active powerpc 74xx_7xx - - - ppmc7xx - - 538 Active powerpc 74xx_7xx - - - ppmc7xx - -
539 Active powerpc 74xx_7xx - - evb64260 P3G4 - Wolfgang Denk <wd@denx.de> 539 Active powerpc 74xx_7xx - - evb64260 P3G4 - Wolfgang Denk <wd@denx.de>
540 Active powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu <nyet@zumanetworks.com> 540 Active powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu <nyet@zumanetworks.com>
541 Active powerpc 74xx_7xx - eltec elppc ELPPC - - 541 Active powerpc 74xx_7xx - eltec elppc ELPPC - -
542 Active powerpc 74xx_7xx - esd cpci750 CPCI750 - Reinhard Arlt <reinhard.arlt@esd-electronics.com> 542 Active powerpc 74xx_7xx - esd cpci750 CPCI750 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
543 Active powerpc 74xx_7xx - freescale mpc7448hpc2 mpc7448hpc2 - Roy Zang <tie-fei.zang@freescale.com> 543 Active powerpc 74xx_7xx - freescale mpc7448hpc2 mpc7448hpc2 - Roy Zang <tie-fei.zang@freescale.com>
544 Active powerpc 74xx_7xx - Marvell db64360 DB64360 - - 544 Active powerpc 74xx_7xx - Marvell db64360 DB64360 - -
545 Active powerpc 74xx_7xx - Marvell db64460 DB64460 - - 545 Active powerpc 74xx_7xx - Marvell db64460 DB64460 - -
546 Active powerpc 74xx_7xx - prodrive p3mx p3m7448 p3mx:P3M7448 Stefan Roese <sr@denx.de> 546 Active powerpc 74xx_7xx - prodrive p3mx p3m7448 p3mx:P3M7448 Stefan Roese <sr@denx.de>
547 Active powerpc 74xx_7xx - prodrive p3mx p3m750 p3mx:P3M750 Stefan Roese <sr@denx.de> 547 Active powerpc 74xx_7xx - prodrive p3mx p3m750 p3mx:P3M750 Stefan Roese <sr@denx.de>
548 Active powerpc mpc512x - - - pdm360ng - Michael Weiss <michael.weiss@ifm.com> 548 Active powerpc mpc512x - - - pdm360ng - Michael Weiss <michael.weiss@ifm.com>
549 Active powerpc mpc512x - davedenx - aria - Wolfgang Denk <wd@denx.de> 549 Active powerpc mpc512x - davedenx - aria - Wolfgang Denk <wd@denx.de>
550 Active powerpc mpc512x - esd - mecp5123 - Reinhard Arlt <reinhard.arlt@esd-electronics.com> 550 Active powerpc mpc512x - esd - mecp5123 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
551 Active powerpc mpc512x - freescale mpc5121ads mpc5121ads - - 551 Active powerpc mpc512x - freescale mpc5121ads mpc5121ads - -
552 Active powerpc mpc512x - freescale mpc5121ads mpc5121ads_rev2 mpc5121ads:MPC5121ADS_REV2 - 552 Active powerpc mpc512x - freescale mpc5121ads mpc5121ads_rev2 mpc5121ads:MPC5121ADS_REV2 -
553 Active powerpc mpc512x - ifm ac14xx ac14xx - Anatolij Gustschin <agust@denx.de> 553 Active powerpc mpc512x - ifm ac14xx ac14xx - Anatolij Gustschin <agust@denx.de>
554 Active powerpc mpc5xx - - cmi cmi_mpc5xx - - 554 Active powerpc mpc5xx - - cmi cmi_mpc5xx - -
555 Active powerpc mpc5xx - mpl pati PATI - - 555 Active powerpc mpc5xx - mpl pati PATI - -
556 Active powerpc mpc5xxx - - - canmb - - 556 Active powerpc mpc5xxx - - - canmb - -
557 Active powerpc mpc5xxx - - - cm5200 - - 557 Active powerpc mpc5xxx - - - cm5200 - -
558 Active powerpc mpc5xxx - - - inka4x0 - Detlev Zundel <dzu@denx.de> 558 Active powerpc mpc5xxx - - - inka4x0 - Detlev Zundel <dzu@denx.de>
559 Active powerpc mpc5xxx - - - ipek01 - Wolfgang Grandegger <wg@denx.de> 559 Active powerpc mpc5xxx - - - ipek01 - Wolfgang Grandegger <wg@denx.de>
560 Active powerpc mpc5xxx - - - jupiter - Heiko Schocher <hs@denx.de> 560 Active powerpc mpc5xxx - - - jupiter - Heiko Schocher <hs@denx.de>
561 Active powerpc mpc5xxx - - - motionpro - - 561 Active powerpc mpc5xxx - - - motionpro - -
562 Active powerpc mpc5xxx - - - munices - - 562 Active powerpc mpc5xxx - - - munices - -
563 Active powerpc mpc5xxx - - - v38b - - 563 Active powerpc mpc5xxx - - - v38b - -
564 Active powerpc mpc5xxx - - a3m071 a3m071 - Stefan Roese <sr@denx.de> 564 Active powerpc mpc5xxx - - a3m071 a3m071 - Stefan Roese <sr@denx.de>
565 Active powerpc mpc5xxx - - a3m071 a4m2k a3m071:A4M2K Stefan Roese <sr@denx.de> 565 Active powerpc mpc5xxx - - a3m071 a4m2k a3m071:A4M2K Stefan Roese <sr@denx.de>
566 Active powerpc mpc5xxx - - a4m072 a4m072 - Sergei Poselenov <sposelenov@emcraft.com> 566 Active powerpc mpc5xxx - - a4m072 a4m072 - Sergei Poselenov <sposelenov@emcraft.com>
567 Active powerpc mpc5xxx - - bc3450 BC3450 - - 567 Active powerpc mpc5xxx - - bc3450 BC3450 - -
568 Active powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt <emillbrandt@dekaresearch.com> 568 Active powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt <emillbrandt@dekaresearch.com>
569 Active powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt <emillbrandt@dekaresearch.com> 569 Active powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt <emillbrandt@dekaresearch.com>
570 Active powerpc mpc5xxx - - icecube icecube_5200 IceCube Wolfgang Denk <wd@denx.de> 570 Active powerpc mpc5xxx - - icecube icecube_5200 IceCube Wolfgang Denk <wd@denx.de>
571 Active powerpc mpc5xxx - - icecube icecube_5200_DDR IceCube:MPC5200_DDR - 571 Active powerpc mpc5xxx - - icecube icecube_5200_DDR IceCube:MPC5200_DDR -
572 Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR - 572 Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -
573 Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR - 573 Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -
574 Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 - 574 Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 -
575 Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 - 575 Active powerpc mpc5xxx - - icecube icecube_5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 -
576 Active powerpc mpc5xxx - - icecube Lite5200 IceCube - 576 Active powerpc mpc5xxx - - icecube Lite5200 IceCube -
577 Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 - 577 Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF000000 -
578 Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 - 578 Active powerpc mpc5xxx - - icecube Lite5200_LOWBOOT08 IceCube:SYS_TEXT_BASE=0xFF800000 -
579 Active powerpc mpc5xxx - - icecube lite5200b IceCube:MPC5200_DDR,LITE5200B - 579 Active powerpc mpc5xxx - - icecube lite5200b IceCube:MPC5200_DDR,LITE5200B -
580 Active powerpc mpc5xxx - - icecube lite5200b_LOWBOOT IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000 - 580 Active powerpc mpc5xxx - - icecube lite5200b_LOWBOOT IceCube:MPC5200_DDR,LITE5200B,SYS_TEXT_BASE=0xFF000000 -
581 Active powerpc mpc5xxx - - icecube lite5200b_PM IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM - 581 Active powerpc mpc5xxx - - icecube lite5200b_PM IceCube:MPC5200_DDR,LITE5200B,LITE5200B_PM -
582 Active powerpc mpc5xxx - - mcc200 mcc200 - - 582 Active powerpc mpc5xxx - - mcc200 mcc200 - -
583 Active powerpc mpc5xxx - - mcc200 mcc200_COM12 mcc200:CONSOLE_COM12 - 583 Active powerpc mpc5xxx - - mcc200 mcc200_COM12 mcc200:CONSOLE_COM12 -
584 Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000 - 584 Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000 -
585 Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot_SDRAM mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM - 585 Active powerpc mpc5xxx - - mcc200 mcc200_COM12_highboot_SDRAM mcc200:CONSOLE_COM12,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
586 Active powerpc mpc5xxx - - mcc200 mcc200_COM12_SDRAM mcc200:CONSOLE_COM12,MCC200_SDRAM - 586 Active powerpc mpc5xxx - - mcc200 mcc200_COM12_SDRAM mcc200:CONSOLE_COM12,MCC200_SDRAM -
587 Active powerpc mpc5xxx - - mcc200 mcc200_highboot mcc200:SYS_TEXT_BASE=0xFFF00000 - 587 Active powerpc mpc5xxx - - mcc200 mcc200_highboot mcc200:SYS_TEXT_BASE=0xFFF00000 -
588 Active powerpc mpc5xxx - - mcc200 mcc200_highboot_SDRAM mcc200:SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM - 588 Active powerpc mpc5xxx - - mcc200 mcc200_highboot_SDRAM mcc200:SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
589 Active powerpc mpc5xxx - - mcc200 mcc200_SDRAM mcc200:MCC200_SDRAM - 589 Active powerpc mpc5xxx - - mcc200 mcc200_SDRAM mcc200:MCC200_SDRAM -
590 Active powerpc mpc5xxx - - mcc200 prs200 mcc200:PRS200,MCC200_SDRAM - 590 Active powerpc mpc5xxx - - mcc200 prs200 mcc200:PRS200,MCC200_SDRAM -
591 Active powerpc mpc5xxx - - mcc200 prs200_DDR mcc200:PRS200 - 591 Active powerpc mpc5xxx - - mcc200 prs200_DDR mcc200:PRS200 -
592 Active powerpc mpc5xxx - - mcc200 prs200_highboot mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM - 592 Active powerpc mpc5xxx - - mcc200 prs200_highboot mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000,MCC200_SDRAM -
593 Active powerpc mpc5xxx - - mcc200 prs200_highboot_DDR mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000 - 593 Active powerpc mpc5xxx - - mcc200 prs200_highboot_DDR mcc200:PRS200,SYS_TEXT_BASE=0xFFF00000 -
594 Active powerpc mpc5xxx - - pm520 PM520 - Josef Wagner <Wagner@Microsys.de> 594 Active powerpc mpc5xxx - - pm520 PM520 - Josef Wagner <Wagner@Microsys.de>
595 Active powerpc mpc5xxx - - pm520 PM520_DDR PM520:MPC5200_DDR Josef Wagner <Wagner@Microsys.de> 595 Active powerpc mpc5xxx - - pm520 PM520_DDR PM520:MPC5200_DDR Josef Wagner <Wagner@Microsys.de>
596 Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT PM520:BOOT_ROM Josef Wagner <Wagner@Microsys.de> 596 Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT PM520:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
597 Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT_DDR PM520:MPC5200_DDR,BOOT_ROM Josef Wagner <Wagner@Microsys.de> 597 Active powerpc mpc5xxx - - pm520 PM520_ROMBOOT_DDR PM520:MPC5200_DDR,BOOT_ROM Josef Wagner <Wagner@Microsys.de>
598 Active powerpc mpc5xxx - - total5200 Total5200 Total5200:TOTAL5200_REV=1 - 598 Active powerpc mpc5xxx - - total5200 Total5200 Total5200:TOTAL5200_REV=1 -
599 Active powerpc mpc5xxx - - total5200 Total5200_lowboot Total5200:TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000 - 599 Active powerpc mpc5xxx - - total5200 Total5200_lowboot Total5200:TOTAL5200_REV=1,SYS_TEXT_BASE=0xFE000000 -
600 Active powerpc mpc5xxx - - total5200 Total5200_Rev2 Total5200:TOTAL5200_REV=2 - 600 Active powerpc mpc5xxx - - total5200 Total5200_Rev2 Total5200:TOTAL5200_REV=2 -
601 Active powerpc mpc5xxx - - total5200 Total5200_Rev2_lowboot Total5200:TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000 - 601 Active powerpc mpc5xxx - - total5200 Total5200_Rev2_lowboot Total5200:TOTAL5200_REV=2,SYS_TEXT_BASE=0xFE000000 -
602 Active powerpc mpc5xxx - emk top5200 EVAL5200 TOP5200:EVAL5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> 602 Active powerpc mpc5xxx - emk top5200 EVAL5200 TOP5200:EVAL5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
603 Active powerpc mpc5xxx - emk top5200 MINI5200 TOP5200:MINI5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> 603 Active powerpc mpc5xxx - emk top5200 MINI5200 TOP5200:MINI5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
604 Active powerpc mpc5xxx - emk top5200 TOP5200 TOP5200:TOP5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de> 604 Active powerpc mpc5xxx - emk top5200 TOP5200 TOP5200:TOP5200 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
605 Active powerpc mpc5xxx - esd - cpci5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com> 605 Active powerpc mpc5xxx - esd - cpci5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
606 Active powerpc mpc5xxx - esd - mecp5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com> 606 Active powerpc mpc5xxx - esd - mecp5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
607 Active powerpc mpc5xxx - esd - pf5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com> 607 Active powerpc mpc5xxx - esd - pf5200 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
608 Active powerpc mpc5xxx - ifm o2dnt2 O2D o2d Anatolij Gustschin <agust@denx.de> 608 Active powerpc mpc5xxx - ifm o2dnt2 O2D o2d Anatolij Gustschin <agust@denx.de>
609 Active powerpc mpc5xxx - ifm o2dnt2 O2D300 o2d300 Anatolij Gustschin <agust@denx.de> 609 Active powerpc mpc5xxx - ifm o2dnt2 O2D300 o2d300 Anatolij Gustschin <agust@denx.de>
610 Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2 o2dnt2 Anatolij Gustschin <agust@denx.de> 610 Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2 o2dnt2 Anatolij Gustschin <agust@denx.de>
611 Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2_RAMBOOT o2dnt2:SYS_TEXT_BASE=0x00100000 Anatolij Gustschin <agust@denx.de> 611 Active powerpc mpc5xxx - ifm o2dnt2 O2DNT2_RAMBOOT o2dnt2:SYS_TEXT_BASE=0x00100000 Anatolij Gustschin <agust@denx.de>
612 Active powerpc mpc5xxx - ifm o2dnt2 O2I o2i Anatolij Gustschin <agust@denx.de> 612 Active powerpc mpc5xxx - ifm o2dnt2 O2I o2i Anatolij Gustschin <agust@denx.de>
613 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT o2mnt Anatolij Gustschin <agust@denx.de> 613 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT o2mnt Anatolij Gustschin <agust@denx.de>
614 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M110 o2mnt:IFM_SENSOR_TYPE="O2M110" Anatolij Gustschin <agust@denx.de> 614 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M110 o2mnt:IFM_SENSOR_TYPE="O2M110" Anatolij Gustschin <agust@denx.de>
615 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M112 o2mnt:IFM_SENSOR_TYPE="O2M112" Anatolij Gustschin <agust@denx.de> 615 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M112 o2mnt:IFM_SENSOR_TYPE="O2M112" Anatolij Gustschin <agust@denx.de>
616 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M113 o2mnt:IFM_SENSOR_TYPE="O2M113" Anatolij Gustschin <agust@denx.de> 616 Active powerpc mpc5xxx - ifm o2dnt2 O2MNT_O2M113 o2mnt:IFM_SENSOR_TYPE="O2M113" Anatolij Gustschin <agust@denx.de>
617 Active powerpc mpc5xxx - ifm o2dnt2 O3DNT o3dnt Anatolij Gustschin <agust@denx.de> 617 Active powerpc mpc5xxx - ifm o2dnt2 O3DNT o3dnt Anatolij Gustschin <agust@denx.de>
618 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc - Werner Pfister <Pfister_Werner@intercontrol.de> 618 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc - Werner Pfister <Pfister_Werner@intercontrol.de>
619 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000 Werner Pfister <Pfister_Werner@intercontrol.de> 619 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000 Werner Pfister <Pfister_Werner@intercontrol.de>
620 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5 digsy_mtc:DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de> 620 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5 digsy_mtc:DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de>
621 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de> 621 Active powerpc mpc5xxx - intercontrol digsy_mtc digsy_mtc_rev5_RAMBOOT digsy_mtc:SYS_TEXT_BASE=0x00100000,DIGSY_REV5 Werner Pfister <Pfister_Werner@intercontrol.de>
622 Active powerpc mpc5xxx - manroland - hmi1001 - - 622 Active powerpc mpc5xxx - manroland - hmi1001 - -
623 Active powerpc mpc5xxx - manroland - mucmc52 - Heiko Schocher <hs@denx.de> 623 Active powerpc mpc5xxx - manroland - mucmc52 - Heiko Schocher <hs@denx.de>
624 Active powerpc mpc5xxx - manroland - uc101 - Heiko Schocher <hs@denx.de> 624 Active powerpc mpc5xxx - manroland - uc101 - Heiko Schocher <hs@denx.de>
625 Active powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz@matrix-vision.de> 625 Active powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz@matrix-vision.de>
626 Active powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz@matrix-vision.de> 626 Active powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz@matrix-vision.de>
627 Active powerpc mpc5xxx - phytec pcm030 pcm030 - Jon Smirl <jonsmirl@gmail.com> 627 Active powerpc mpc5xxx - phytec pcm030 pcm030 - Jon Smirl <jonsmirl@gmail.com>
628 Active powerpc mpc5xxx - phytec pcm030 pcm030_LOWBOOT pcm030:SYS_TEXT_BASE=0xFF000000 Jon Smirl <jonsmirl@gmail.com> 628 Active powerpc mpc5xxx - phytec pcm030 pcm030_LOWBOOT pcm030:SYS_TEXT_BASE=0xFF000000 Jon Smirl <jonsmirl@gmail.com>
629 Active powerpc mpc5xxx - tqc tqm5200 aev - - 629 Active powerpc mpc5xxx - tqc tqm5200 aev - -
630 Active powerpc mpc5xxx - tqc tqm5200 cam5200 TQM5200:CAM5200,TQM5200S,TQM5200_B - 630 Active powerpc mpc5xxx - tqc tqm5200 cam5200 TQM5200:CAM5200,TQM5200S,TQM5200_B -
631 Active powerpc mpc5xxx - tqc tqm5200 cam5200_niosflash TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH - 631 Active powerpc mpc5xxx - tqc tqm5200 cam5200_niosflash TQM5200:CAM5200,TQM5200S,TQM5200_B,CAM5200_NIOSFLASH -
632 Active powerpc mpc5xxx - tqc tqm5200 charon - Heiko Schocher <hs@denx.de> 632 Active powerpc mpc5xxx - tqc tqm5200 charon - Heiko Schocher <hs@denx.de>
633 Active powerpc mpc5xxx - tqc tqm5200 fo300 TQM5200:FO300 - 633 Active powerpc mpc5xxx - tqc tqm5200 fo300 TQM5200:FO300 -
634 Active powerpc mpc5xxx - tqc tqm5200 MiniFAP TQM5200:MINIFAP - 634 Active powerpc mpc5xxx - tqc tqm5200 MiniFAP TQM5200:MINIFAP -
635 Active powerpc mpc5xxx - tqc tqm5200 TB5200 - - 635 Active powerpc mpc5xxx - tqc tqm5200 TB5200 - -
636 Active powerpc mpc5xxx - tqc tqm5200 TB5200_B TB5200:TQM5200_B - 636 Active powerpc mpc5xxx - tqc tqm5200 TB5200_B TB5200:TQM5200_B -
637 Active powerpc mpc5xxx - tqc tqm5200 TQM5200 - - 637 Active powerpc mpc5xxx - tqc tqm5200 TQM5200 - -
638 Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B TQM5200:TQM5200_B - 638 Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B TQM5200:TQM5200_B -
639 Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B_HIGHBOOT TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000 - 639 Active powerpc mpc5xxx - tqc tqm5200 TQM5200_B_HIGHBOOT TQM5200:TQM5200_B,SYS_TEXT_BASE=0xFFF00000 -
640 Active powerpc mpc5xxx - tqc tqm5200 TQM5200_STK100 TQM5200:STK52XX_REV100 - 640 Active powerpc mpc5xxx - tqc tqm5200 TQM5200_STK100 TQM5200:STK52XX_REV100 -
641 Active powerpc mpc5xxx - tqc tqm5200 TQM5200S TQM5200:TQM5200_B,TQM5200S - 641 Active powerpc mpc5xxx - tqc tqm5200 TQM5200S TQM5200:TQM5200_B,TQM5200S -
642 Active powerpc mpc5xxx - tqc tqm5200 TQM5200S_HIGHBOOT TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000 - 642 Active powerpc mpc5xxx - tqc tqm5200 TQM5200S_HIGHBOOT TQM5200:TQM5200_B,TQM5200S,SYS_TEXT_BASE=0xFFF00000 -
643 Active powerpc mpc824x - - - utx8245 - Greg Allen <gallen@arlut.utexas.edu> 643 Active powerpc mpc824x - - - utx8245 - Greg Allen <gallen@arlut.utexas.edu>
644 Active powerpc mpc824x - - a3000 A3000 - - 644 Active powerpc mpc824x - - a3000 A3000 - -
645 Active powerpc mpc824x - - cpc45 CPC45 - Josef Wagner <Wagner@Microsys.de> 645 Active powerpc mpc824x - - cpc45 CPC45 - Josef Wagner <Wagner@Microsys.de>
646 Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner <Wagner@Microsys.de> 646 Active powerpc mpc824x - - cpc45 CPC45_ROMBOOT CPC45:BOOT_ROM Josef Wagner <Wagner@Microsys.de>
647 Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk <wd@denx.de> 647 Active powerpc mpc824x - - cu824 CU824 - Wolfgang Denk <wd@denx.de>
648 Active powerpc mpc824x - - eXalion eXalion - Torsten Demke <torsten.demke@fci.com> 648 Active powerpc mpc824x - - eXalion eXalion - Torsten Demke <torsten.demke@fci.com>
649 Active powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso@adaptec.com> 649 Active powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso@adaptec.com>
650 Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com> 650 Active powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
651 Active powerpc mpc824x - - mvblue MVBLUE - - 651 Active powerpc mpc824x - - mvblue MVBLUE - -
652 Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de> 652 Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de>
653 Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com> 653 Active powerpc mpc824x - - sandpoint Sandpoint8245 - Jim Thompson <jim@musenki.com>
654 Active powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com> 654 Active powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
655 Active powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil@etinsys.com> 655 Active powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil@etinsys.com>
656 Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd@denx.de> 656 Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd@denx.de>
657 Active powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno@delphintech.com> 657 Active powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno@delphintech.com>
658 Active powerpc mpc8260 - - - ep82xxm - - 658 Active powerpc mpc8260 - - - ep82xxm - -
659 Active powerpc mpc8260 - - - gw8260 - Oliver Brown <obrown@adventnetworks.com> 659 Active powerpc mpc8260 - - - gw8260 - Oliver Brown <obrown@adventnetworks.com>
660 Active powerpc mpc8260 - - - hymod - Murray Jensen <Murray.Jensen@csiro.au> 660 Active powerpc mpc8260 - - - hymod - Murray Jensen <Murray.Jensen@csiro.au>
661 Active powerpc mpc8260 - - - ppmc8260 - Brad Kemp <Brad.Kemp@seranoa.com> 661 Active powerpc mpc8260 - - - ppmc8260 - Brad Kemp <Brad.Kemp@seranoa.com>
662 Active powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com> 662 Active powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
663 Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen <Murray.Jensen@csiro.au> 663 Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen <Murray.Jensen@csiro.au>
664 Active powerpc mpc8260 - - cpu86 CPU86 - Wolfgang Denk <wd@denx.de> 664 Active powerpc mpc8260 - - cpu86 CPU86 - Wolfgang Denk <wd@denx.de>
665 Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de> 665 Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de>
666 Active powerpc mpc8260 - - cpu87 CPU87 - - 666 Active powerpc mpc8260 - - cpu87 CPU87 - -
667 Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM - 667 Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM -
668 Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com> 668 Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
669 Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher <hs@denx.de> 669 Active powerpc mpc8260 - - ids8247 IDS8247 - Heiko Schocher <hs@denx.de>
670 Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de> 670 Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de>
671 Active powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli@arabellasw.com> 671 Active powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli@arabellasw.com>
672 Active powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <yuli@arabellasw.com> 672 Active powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <yuli@arabellasw.com>
673 Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de> 673 Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de>
674 Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de> 674 Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de>
675 Active powerpc mpc8260 - - pm826 PM825 PM826:PCI,SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de> 675 Active powerpc mpc8260 - - pm826 PM825 PM826:PCI,SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de>
676 Active powerpc mpc8260 - - pm826 PM825_BIGFLASH PM826:PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de> 676 Active powerpc mpc8260 - - pm826 PM825_BIGFLASH PM826:PCI,FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de>
677 Active powerpc mpc8260 - - pm826 PM825_ROMBOOT PM826:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de> 677 Active powerpc mpc8260 - - pm826 PM825_ROMBOOT PM826:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
678 Active powerpc mpc8260 - - pm826 PM825_ROMBOOT_BIGFLASH PM826:PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de> 678 Active powerpc mpc8260 - - pm826 PM825_ROMBOOT_BIGFLASH PM826:PCI,BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
679 Active powerpc mpc8260 - - pm826 PM826 PM826:SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de> 679 Active powerpc mpc8260 - - pm826 PM826 PM826:SYS_TEXT_BASE=0xFF000000 Wolfgang Denk <wd@denx.de>
680 Active powerpc mpc8260 - - pm826 PM826_BIGFLASH PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de> 680 Active powerpc mpc8260 - - pm826 PM826_BIGFLASH PM826:FLASH_32MB,SYS_TEXT_BASE=0x40000000 Wolfgang Denk <wd@denx.de>
681 Active powerpc mpc8260 - - pm826 PM826_ROMBOOT PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de> 681 Active powerpc mpc8260 - - pm826 PM826_ROMBOOT PM826:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
682 Active powerpc mpc8260 - - pm826 PM826_ROMBOOT_BIGFLASH PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de> 682 Active powerpc mpc8260 - - pm826 PM826_ROMBOOT_BIGFLASH PM826:BOOT_ROM,FLASH_32MB,SYS_TEXT_BASE=0xFF800000 Wolfgang Denk <wd@denx.de>
683 Active powerpc mpc8260 - - pm828 PM828 - - 683 Active powerpc mpc8260 - - pm828 PM828 - -
684 Active powerpc mpc8260 - - pm828 PM828_PCI PM828:PCI - 684 Active powerpc mpc8260 - - pm828 PM828_PCI PM828:PCI -
685 Active powerpc mpc8260 - - pm828 PM828_ROMBOOT PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - 685 Active powerpc mpc8260 - - pm828 PM828_ROMBOOT PM828:BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -
686 Active powerpc mpc8260 - - pm828 PM828_ROMBOOT_PCI PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 - 686 Active powerpc mpc8260 - - pm828 PM828_ROMBOOT_PCI PM828:PCI,BOOT_ROM,SYS_TEXT_BASE=0xFF800000 -
687 Active powerpc mpc8260 - - rattler Rattler - Yuli Barcohen <yuli@arabellasw.com> 687 Active powerpc mpc8260 - - rattler Rattler - Yuli Barcohen <yuli@arabellasw.com>
688 Active powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli@arabellasw.com> 688 Active powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli@arabellasw.com>
689 Active powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli@arabellasw.com> 689 Active powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli@arabellasw.com>
690 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli@arabellasw.com> 690 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli@arabellasw.com>
691 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <yuli@arabellasw.com> 691 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <yuli@arabellasw.com>
692 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 692 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
693 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <yuli@arabellasw.com> 693 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <yuli@arabellasw.com>
694 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 694 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
695 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 695 Active powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
696 Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <yuli@arabellasw.com> 696 Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <yuli@arabellasw.com>
697 Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 697 Active powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
698 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com> 698 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
699 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com> 699 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
700 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 700 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
701 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com> 701 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
702 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com> 702 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
703 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 703 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
704 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 704 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
705 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com> 705 Active powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
706 Active powerpc mpc8260 - freescale mpc8266ads MPC8266ADS - Rune Torgersen <runet@innovsys.com> 706 Active powerpc mpc8260 - freescale mpc8266ads MPC8266ADS - Rune Torgersen <runet@innovsys.com>
707 Active powerpc mpc8260 - funkwerk vovpn-gw VoVPN-GW_66MHz VoVPN-GW:CLKIN_66MHz - 707 Active powerpc mpc8260 - funkwerk vovpn-gw VoVPN-GW_66MHz VoVPN-GW:CLKIN_66MHz -
708 Active powerpc mpc8260 - keymile km82xx mgcoge km82xx:MGCOGE Holger Brunck <holger.brunck@keymile.com> 708 Active powerpc mpc8260 - keymile km82xx mgcoge km82xx:MGCOGE Holger Brunck <holger.brunck@keymile.com>
709 Active powerpc mpc8260 - keymile km82xx mgcoge3ne km82xx:MGCOGE3NE Holger Brunck <holger.brunck@keymile.com> 709 Active powerpc mpc8260 - keymile km82xx mgcoge3ne km82xx:MGCOGE3NE Holger Brunck <holger.brunck@keymile.com>
710 Active powerpc mpc8260 - tqc tqm8260 TQM8255_AA TQM8260:MPC8255,300MHz Wolfgang Denk <wd@denx.de> 710 Active powerpc mpc8260 - tqc tqm8260 TQM8255_AA TQM8260:MPC8255,300MHz Wolfgang Denk <wd@denx.de>
711 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AA TQM8260:MPC8260,200MHz Wolfgang Denk <wd@denx.de> 711 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AA TQM8260:MPC8260,200MHz Wolfgang Denk <wd@denx.de>
712 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AB TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de> 712 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AB TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
713 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AC TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de> 713 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AC TQM8260:MPC8260,200MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
714 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AD TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de> 714 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AD TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
715 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AE TQM8260:MPC8260,266MHz Wolfgang Denk <wd@denx.de> 715 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AE TQM8260:MPC8260,266MHz Wolfgang Denk <wd@denx.de>
716 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AF TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de> 716 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AF TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
717 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AG TQM8260:MPC8260,300MHz Wolfgang Denk <wd@denx.de> 717 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AG TQM8260:MPC8260,300MHz Wolfgang Denk <wd@denx.de>
718 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AH TQM8260:MPC8260,300MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de> 718 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AH TQM8260:MPC8260,300MHz,L2_CACHE,BUSMODE_60x Wolfgang Denk <wd@denx.de>
719 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AI TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de> 719 Active powerpc mpc8260 - tqc tqm8260 TQM8260_AI TQM8260:MPC8260,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
720 Active powerpc mpc8260 - tqc tqm8260 TQM8265_AA TQM8260:MPC8265,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de> 720 Active powerpc mpc8260 - tqc tqm8260 TQM8265_AA TQM8260:MPC8265,300MHz,BUSMODE_60x Wolfgang Denk <wd@denx.de>
721 Active powerpc mpc8260 - tqc tqm8272 TQM8272 - - 721 Active powerpc mpc8260 - tqc tqm8272 TQM8272 - -
722 Active powerpc mpc83xx - - - mpc8308_p1m - Ilya Yanok <yanok@emcraft.com> 722 Active powerpc mpc83xx - - - mpc8308_p1m - Ilya Yanok <yanok@emcraft.com>
723 Active powerpc mpc83xx - - sbc8349 sbc8349 - Paul Gortmaker <paul.gortmaker@windriver.com> 723 Active powerpc mpc83xx - - sbc8349 sbc8349 - Paul Gortmaker <paul.gortmaker@windriver.com>
724 Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_33 sbc8349:PCI,PCI_33M Paul Gortmaker <paul.gortmaker@windriver.com> 724 Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_33 sbc8349:PCI,PCI_33M Paul Gortmaker <paul.gortmaker@windriver.com>
725 Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_66 sbc8349:PCI,PCI_66M Paul Gortmaker <paul.gortmaker@windriver.com> 725 Active powerpc mpc83xx - - sbc8349 sbc8349_PCI_66 sbc8349:PCI,PCI_66M Paul Gortmaker <paul.gortmaker@windriver.com>
726 Active powerpc mpc83xx - - ve8313 ve8313 - Heiko Schocher <hs@denx.de> 726 Active powerpc mpc83xx - - ve8313 ve8313 - Heiko Schocher <hs@denx.de>
727 Active powerpc mpc83xx - esd vme8349 caddy2 vme8349:CADDY2 Reinhard Arlt <reinhard.arlt@esd-electronics.com> 727 Active powerpc mpc83xx - esd vme8349 caddy2 vme8349:CADDY2 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
728 Active powerpc mpc83xx - esd vme8349 vme8349 - Reinhard Arlt <reinhard.arlt@esd-electronics.com> 728 Active powerpc mpc83xx - esd vme8349 vme8349 - Reinhard Arlt <reinhard.arlt@esd-electronics.com>
729 Active powerpc mpc83xx - freescale mpc8308rdb MPC8308RDB - Ilya Yanok <yanok@emcraft.com> 729 Active powerpc mpc83xx - freescale mpc8308rdb MPC8308RDB - Ilya Yanok <yanok@emcraft.com>
730 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_33 MPC8313ERDB:SYS_33MHZ - 730 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_33 MPC8313ERDB:SYS_33MHZ -
731 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_66 MPC8313ERDB:SYS_66MHZ - 731 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_66 MPC8313ERDB:SYS_66MHZ -
732 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_33 MPC8313ERDB:SYS_33MHZ,NAND - 732 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_33 MPC8313ERDB:SYS_33MHZ,NAND -
733 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_66 MPC8313ERDB:SYS_66MHZ,NAND - 733 Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_66 MPC8313ERDB:SYS_66MHZ,NAND -
734 Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB - Dave Liu <daveliu@freescale.com> 734 Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB - Dave Liu <daveliu@freescale.com>
735 Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB_NAND MPC8315ERDB:NAND_U_BOOT Dave Liu <daveliu@freescale.com> 735 Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB_NAND MPC8315ERDB:NAND_U_BOOT Dave Liu <daveliu@freescale.com>
736 Active powerpc mpc83xx - freescale mpc8323erdb MPC8323ERDB - Michael Barkowski <michael.barkowski@freescale.com> 736 Active powerpc mpc83xx - freescale mpc8323erdb MPC8323ERDB - Michael Barkowski <michael.barkowski@freescale.com>
737 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS - Dave Liu <daveliu@freescale.com> 737 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS - Dave Liu <daveliu@freescale.com>
738 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_ATM MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com> 738 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_ATM MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
739 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_33 MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com> 739 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_33 MPC832XEMDS:PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
740 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_66 MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com> 740 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_HOST_66 MPC832XEMDS:PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
741 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_SLAVE MPC832XEMDS:PCI,PCISLAVE Dave Liu <daveliu@freescale.com> 741 Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_SLAVE MPC832XEMDS:PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
742 Active powerpc mpc83xx - freescale mpc8349emds MPC8349EMDS - Kim Phillips <kim.phillips@freescale.com> 742 Active powerpc mpc83xx - freescale mpc8349emds MPC8349EMDS - Kim Phillips <kim.phillips@freescale.com>
743 Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX MPC8349ITX:MPC8349ITX - 743 Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX MPC8349ITX:MPC8349ITX -
744 Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX_LOWBOOT MPC8349ITX:MPC8349ITX,SYS_TEXT_BASE=0xFE000000 - 744 Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITX_LOWBOOT MPC8349ITX:MPC8349ITX,SYS_TEXT_BASE=0xFE000000 -
745 Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITXGP MPC8349ITX:MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000 - 745 Active powerpc mpc83xx - freescale mpc8349itx MPC8349ITXGP MPC8349ITX:MPC8349ITXGP,SYS_TEXT_BASE=0xFE000000 -
746 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33 MPC8360EMDS:CLKIN_33MHZ Dave Liu <daveliu@freescale.com> 746 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33 MPC8360EMDS:CLKIN_33MHZ Dave Liu <daveliu@freescale.com>
747 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_ATM MPC8360EMDS:CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com> 747 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_ATM MPC8360EMDS:CLKIN_33MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
748 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_33 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com> 748 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_33 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
749 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_66 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com> 749 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_HOST_66 MPC8360EMDS:CLKIN_33MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
750 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_SLAVE MPC8360EMDS:CLKIN_33MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com> 750 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_33_SLAVE MPC8360EMDS:CLKIN_33MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
751 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66 MPC8360EMDS:CLKIN_66MHZ Dave Liu <daveliu@freescale.com> 751 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66 MPC8360EMDS:CLKIN_66MHZ Dave Liu <daveliu@freescale.com>
752 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_ATM MPC8360EMDS:CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com> 752 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_ATM MPC8360EMDS:CLKIN_66MHZ,PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
753 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_33 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com> 753 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_33 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_33M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
754 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_66 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com> 754 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_HOST_66 MPC8360EMDS:CLKIN_66MHZ,PCI,PCI_66M,PQ_MDS_PIB=1 Dave Liu <daveliu@freescale.com>
755 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com> 755 Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
756 Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <avorontsov@ru.mvista.com> 756 Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <avorontsov@ru.mvista.com>
757 Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com> 757 Active powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com>
758 Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu <daveliu@freescale.com> 758 Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu <daveliu@freescale.com>
759 Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu@freescale.com> 759 Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu@freescale.com>
760 Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com> 760 Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
761 Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck <holger.brunck@keymile.com> 761 Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck <holger.brunck@keymile.com>
762 Active powerpc mpc83xx - keymile km83xx kmeter1 km8360:KMETER1 Holger Brunck <holger.brunck@keymile.com> 762 Active powerpc mpc83xx - keymile km83xx kmeter1 km8360:KMETER1 Holger Brunck <holger.brunck@keymile.com>
763 Active powerpc mpc83xx - keymile km83xx kmopti2 tuxx1:KMOPTI2 Holger Brunck <holger.brunck@keymile.com> 763 Active powerpc mpc83xx - keymile km83xx kmopti2 tuxx1:KMOPTI2 Holger Brunck <holger.brunck@keymile.com>
764 Active powerpc mpc83xx - keymile km83xx kmsupx5 tuxx1:KMSUPX5 Heiko Schocher <hs@denx.de> 764 Active powerpc mpc83xx - keymile km83xx kmsupx5 tuxx1:KMSUPX5 Heiko Schocher <hs@denx.de>
765 Active powerpc mpc83xx - keymile km83xx kmvect1 suvd3:KMVECT1 Holger Brunck <holger.brunck@keymile.com> 765 Active powerpc mpc83xx - keymile km83xx kmvect1 suvd3:KMVECT1 Holger Brunck <holger.brunck@keymile.com>
766 Active powerpc mpc83xx - keymile km83xx suvd3 suvd3:SUVD3 Holger Brunck <holger.brunck@keymile.com> 766 Active powerpc mpc83xx - keymile km83xx suvd3 suvd3:SUVD3 Holger Brunck <holger.brunck@keymile.com>
767 Active powerpc mpc83xx - keymile km83xx tuge1 tuxx1:TUGE1 Holger Brunck <holger.brunck@keymile.com> 767 Active powerpc mpc83xx - keymile km83xx tuge1 tuxx1:TUGE1 Holger Brunck <holger.brunck@keymile.com>
768 Active powerpc mpc83xx - keymile km83xx tuxx1 tuxx1:TUXX1 Holger Brunck <holger.brunck@keymile.com> 768 Active powerpc mpc83xx - keymile km83xx tuxx1 tuxx1:TUXX1 Holger Brunck <holger.brunck@keymile.com>
769 Active powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz@matrix-vision.de> 769 Active powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz@matrix-vision.de>
770 Active powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz <andre.schwarz@matrix-vision.de> 770 Active powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz <andre.schwarz@matrix-vision.de>
771 Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid <info@sheldoninst.com> 771 Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid <info@sheldoninst.com>
772 Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid <info@sheldoninst.com> 772 Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid <info@sheldoninst.com>
773 Active powerpc mpc83xx - tqc tqm834x TQM834x - - 773 Active powerpc mpc83xx - tqc tqm834x TQM834x - -
774 Active powerpc mpc85xx - - sbc8548 sbc8548 - Paul Gortmaker <paul.gortmaker@windriver.com> 774 Active powerpc mpc85xx - - sbc8548 sbc8548 - Paul Gortmaker <paul.gortmaker@windriver.com>
775 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33 sbc8548:PCI,33 Paul Gortmaker <paul.gortmaker@windriver.com> 775 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33 sbc8548:PCI,33 Paul Gortmaker <paul.gortmaker@windriver.com>
776 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33_PCIE sbc8548:PCI,33,PCIE Paul Gortmaker <paul.gortmaker@windriver.com> 776 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33_PCIE sbc8548:PCI,33,PCIE Paul Gortmaker <paul.gortmaker@windriver.com>
777 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66 sbc8548:PCI,66 Paul Gortmaker <paul.gortmaker@windriver.com> 777 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66 sbc8548:PCI,66 Paul Gortmaker <paul.gortmaker@windriver.com>
778 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66_PCIE sbc8548:PCI,66,PCIE Paul Gortmaker <paul.gortmaker@windriver.com> 778 Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66_PCIE sbc8548:PCI,66,PCIE Paul Gortmaker <paul.gortmaker@windriver.com>
779 Active powerpc mpc85xx - - socrates socrates - - 779 Active powerpc mpc85xx - - socrates socrates - -
780 Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com> 780 Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
781 Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 - 781 Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 -
782 Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - 782 Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
783 Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - 783 Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
784 Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 - 784 Active powerpc mpc85xx - freescale b4860qds B4860QDS B4860QDS:PPC_B4860 -
785 Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - 785 Active powerpc mpc85xx - freescale b4860qds B4860QDS_NAND B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
786 Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - 786 Active powerpc mpc85xx - freescale b4860qds B4860QDS_SPIFLASH B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
787 Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - 787 Active powerpc mpc85xx - freescale b4860qds B4860QDS_SRIO_PCIE_BOOT B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
788 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal <poonam.aggrwal@freescale.com> 788 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND BSC9131RDB:BSC9131RDB,NAND Poonam Aggrwal <poonam.aggrwal@freescale.com>
789 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND_SYSCLK100 BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com> 789 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_NAND_SYSCLK100 BSC9131RDB:BSC9131RDB,NAND,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com>
790 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH BSC9131RDB:BSC9131RDB,SPIFLASH Poonam Aggrwal <poonam.aggrwal@freescale.com> 790 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH BSC9131RDB:BSC9131RDB,SPIFLASH Poonam Aggrwal <poonam.aggrwal@freescale.com>
791 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH_SYSCLK100 BSC9131RDB:BSC9131RDB,SPIFLASH,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com> 791 Active powerpc mpc85xx - freescale bsc9131rdb BSC9131RDB_SPIFLASH_SYSCLK100 BSC9131RDB:BSC9131RDB,SPIFLASH,SYS_CLK_100 Poonam Aggrwal <poonam.aggrwal@freescale.com>
792 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK100 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com> 792 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK100 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
793 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK133 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com> 793 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NAND_DDRCLK133 BSC9132QDS:BSC9132QDS,NAND,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
794 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK100 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com> 794 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK100 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
795 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK133 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com> 795 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_NOR_DDRCLK133 BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
796 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK100 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com> 796 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK100 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
797 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com> 797 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SDCARD_DDRCLK133 BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
798 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com> 798 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK100 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 Naveen Burmi <NaveenBurmi@freescale.com>
799 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com> 799 Active powerpc mpc85xx - freescale bsc9132qds BSC9132QDS_SPIFLASH_DDRCLK133 BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 Naveen Burmi <NaveenBurmi@freescale.com>
800 Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com> 800 Active powerpc mpc85xx - freescale c29xpcie C29XPCIE C29XPCIE:C29XPCIE,36BIT Po Liu <po.liu@freescale.com>
801 Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu@freescale.com> 801 Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_NAND C29XPCIE:C29XPCIE,36BIT,NAND Po Liu <po.liu@freescale.com>
802 Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com> 802 Active powerpc mpc85xx - freescale c29xpcie C29XPCIE_SPIFLASH C29XPCIE:C29XPCIE,36BIT,SPIFLASH Po Liu <po.liu@freescale.com>
803 Active powerpc mpc85xx - freescale corenet_ds P3041DS - - 803 Active powerpc mpc85xx - freescale corenet_ds P3041DS - -
804 Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - 804 Active powerpc mpc85xx - freescale corenet_ds P3041DS_NAND P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
805 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - 805 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SDCARD P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
806 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SECURE_BOOT P3041DS:SECURE_BOOT - 806 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SECURE_BOOT P3041DS:SECURE_BOOT -
807 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - 807 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SPIFLASH P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
808 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - 808 Active powerpc mpc85xx - freescale corenet_ds P3041DS_SRIO_PCIE_BOOT P3041DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
809 Active powerpc mpc85xx - freescale corenet_ds P4080DS - - 809 Active powerpc mpc85xx - freescale corenet_ds P4080DS - -
810 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - 810 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SDCARD P4080DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
811 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SECURE_BOOT P4080DS:SECURE_BOOT - 811 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SECURE_BOOT P4080DS:SECURE_BOOT -
812 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - 812 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SPIFLASH P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
813 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - 813 Active powerpc mpc85xx - freescale corenet_ds P4080DS_SRIO_PCIE_BOOT P4080DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
814 Active powerpc mpc85xx - freescale corenet_ds P5020DS - - 814 Active powerpc mpc85xx - freescale corenet_ds P5020DS - -
815 Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - 815 Active powerpc mpc85xx - freescale corenet_ds P5020DS_NAND P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
816 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - 816 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SDCARD P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
817 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SECURE_BOOT P5020DS:SECURE_BOOT - 817 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SECURE_BOOT P5020DS:SECURE_BOOT -
818 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - 818 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SPIFLASH P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
819 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - 819 Active powerpc mpc85xx - freescale corenet_ds P5020DS_SRIO_PCIE_BOOT P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
820 Active powerpc mpc85xx - freescale corenet_ds P5040DS - - 820 Active powerpc mpc85xx - freescale corenet_ds P5040DS - -
821 Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - 821 Active powerpc mpc85xx - freescale corenet_ds P5040DS_NAND P5040DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
822 Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - 822 Active powerpc mpc85xx - freescale corenet_ds P5040DS_SDCARD P5040DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
823 Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - 823 Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
824 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS - - 824 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS - -
825 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT - 825 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT -
826 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND - 826 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND -
827 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SDCARD MPC8536DS:SDCARD - 827 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SDCARD MPC8536DS:SDCARD -
828 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SPIFLASH MPC8536DS:SPIFLASH - 828 Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SPIFLASH MPC8536DS:SPIFLASH -
829 Active powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala@freescale.com> 829 Active powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala@freescale.com>
830 Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS - Kumar Gala <kumar.gala@freescale.com> 830 Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS - Kumar Gala <kumar.gala@freescale.com>
831 Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala <kumar.gala@freescale.com> 831 Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
832 Active powerpc mpc85xx - freescale mpc8544ds MPC8544DS - - 832 Active powerpc mpc85xx - freescale mpc8544ds MPC8544DS - -
833 Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS - - 833 Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS - -
834 Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_36BIT MPC8548CDS:36BIT - 834 Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_36BIT MPC8548CDS:36BIT -
835 Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_legacy MPC8548CDS:LEGACY - 835 Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_legacy MPC8548CDS:LEGACY -
836 Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS - Kumar Gala <kumar.gala@freescale.com> 836 Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS - Kumar Gala <kumar.gala@freescale.com>
837 Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala <kumar.gala@freescale.com> 837 Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
838 Active powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala <kumar.gala@freescale.com> 838 Active powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala <kumar.gala@freescale.com>
839 Active powerpc mpc85xx - freescale mpc8568mds MPC8568MDS - - 839 Active powerpc mpc85xx - freescale mpc8568mds MPC8568MDS - -
840 Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS - - 840 Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS - -
841 Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM - 841 Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM -
842 Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND - 842 Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND -
843 Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - - 843 Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - -
844 Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT - 844 Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT -
845 Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND - 845 Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND -
846 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND - 846 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND -
847 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT - 847 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT -
848 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR P1010RDB:P1010RDB_PA,36BIT - 848 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR P1010RDB:P1010RDB_PA,36BIT -
849 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR_SECBOOT P1010RDB:P1010RDB_PA,36BIT,SECURE_BOOT - 849 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR_SECBOOT P1010RDB:P1010RDB_PA,36BIT,SECURE_BOOT -
850 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SDCARD P1010RDB:P1010RDB_PA,36BIT,SDCARD - 850 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SDCARD P1010RDB:P1010RDB_PA,36BIT,SDCARD -
851 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SPIFLASH P1010RDB:P1010RDB_PA,36BIT,SPIFLASH - 851 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SPIFLASH P1010RDB:P1010RDB_PA,36BIT,SPIFLASH -
852 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT - 852 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PA,36BIT,SPIFLASH,SECURE_BOOT -
853 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NAND P1010RDB:P1010RDB_PA,NAND - 853 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NAND P1010RDB:P1010RDB_PA,NAND -
854 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NAND_SECBOOT P1010RDB:P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT - 854 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NAND_SECBOOT P1010RDB:P1010RDB_PA,NAND_SECBOOT,SECURE_BOOT -
855 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NOR P1010RDB:P1010RDB_PA - 855 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NOR P1010RDB:P1010RDB_PA -
856 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NOR_SECBOOT P1010RDB:P1010RDB_PA,SECURE_BOOT - 856 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_NOR_SECBOOT P1010RDB:P1010RDB_PA,SECURE_BOOT -
857 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SDCARD P1010RDB:P1010RDB_PA,SDCARD - 857 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SDCARD P1010RDB:P1010RDB_PA,SDCARD -
858 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SPIFLASH P1010RDB:P1010RDB_PA,SPIFLASH - 858 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SPIFLASH P1010RDB:P1010RDB_PA,SPIFLASH -
859 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PA,SPIFLASH,SECURE_BOOT - 859 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PA,SPIFLASH,SECURE_BOOT -
860 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NAND P1010RDB:P1010RDB_PB,36BIT,NAND - 860 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NAND P1010RDB:P1010RDB_PB,36BIT,NAND -
861 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT - 861 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PB,36BIT,NAND_SECBOOT,SECURE_BOOT -
862 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NOR P1010RDB:P1010RDB_PB,36BIT - 862 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NOR P1010RDB:P1010RDB_PB,36BIT -
863 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB:P1010RDB_PB,36BIT,SECURE_BOOT - 863 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_NOR_SECBOOT P1010RDB:P1010RDB_PB,36BIT,SECURE_BOOT -
864 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SDCARD P1010RDB:P1010RDB_PB,36BIT,SDCARD - 864 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SDCARD P1010RDB:P1010RDB_PB,36BIT,SDCARD -
865 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SPIFLASH P1010RDB:P1010RDB_PB,36BIT,SPIFLASH - 865 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SPIFLASH P1010RDB:P1010RDB_PB,36BIT,SPIFLASH -
866 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT - 866 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PB,36BIT,SPIFLASH,SECURE_BOOT -
867 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NAND P1010RDB:P1010RDB_PB,NAND - 867 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NAND P1010RDB:P1010RDB_PB,NAND -
868 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NAND_SECBOOT P1010RDB:P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT - 868 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NAND_SECBOOT P1010RDB:P1010RDB_PB,NAND_SECBOOT,SECURE_BOOT -
869 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NOR P1010RDB:P1010RDB_PB - 869 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NOR P1010RDB:P1010RDB_PB -
870 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NOR_SECBOOT P1010RDB:P1010RDB_PB,SECURE_BOOT - 870 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_NOR_SECBOOT P1010RDB:P1010RDB_PB,SECURE_BOOT -
871 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SDCARD P1010RDB:P1010RDB_PB,SDCARD - 871 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SDCARD P1010RDB:P1010RDB_PB,SDCARD -
872 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SPIFLASH P1010RDB:P1010RDB_PB,SPIFLASH - 872 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SPIFLASH P1010RDB:P1010RDB_PB,SPIFLASH -
873 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PB,SPIFLASH,SECURE_BOOT - 873 Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PB_SPIFLASH_SECBOOT P1010RDB:P1010RDB_PB,SPIFLASH,SECURE_BOOT -
874 Active powerpc mpc85xx - freescale p1022ds P1022DS - Timur Tabi <timur@freescale.com> 874 Active powerpc mpc85xx - freescale p1022ds P1022DS - Timur Tabi <timur@freescale.com>
875 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT P1022DS:36BIT Timur Tabi <timur@freescale.com> 875 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT P1022DS:36BIT Timur Tabi <timur@freescale.com>
876 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_NAND P1022DS:36BIT,NAND Timur Tabi <timur@freescale.com> 876 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_NAND P1022DS:36BIT,NAND Timur Tabi <timur@freescale.com>
877 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SDCARD P1022DS:36BIT,SDCARD Timur Tabi <timur@freescale.com> 877 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SDCARD P1022DS:36BIT,SDCARD Timur Tabi <timur@freescale.com>
878 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SPIFLASH P1022DS:36BIT,SPIFLASH Timur Tabi <timur@freescale.com> 878 Active powerpc mpc85xx - freescale p1022ds P1022DS_36BIT_SPIFLASH P1022DS:36BIT,SPIFLASH Timur Tabi <timur@freescale.com>
879 Active powerpc mpc85xx - freescale p1022ds P1022DS_NAND P1022DS:NAND Timur Tabi <timur@freescale.com> 879 Active powerpc mpc85xx - freescale p1022ds P1022DS_NAND P1022DS:NAND Timur Tabi <timur@freescale.com>
880 Active powerpc mpc85xx - freescale p1022ds P1022DS_SDCARD P1022DS:SDCARD Timur Tabi <timur@freescale.com> 880 Active powerpc mpc85xx - freescale p1022ds P1022DS_SDCARD P1022DS:SDCARD Timur Tabi <timur@freescale.com>
881 Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi <timur@freescale.com> 881 Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi <timur@freescale.com>
882 Active powerpc mpc85xx - freescale p1023rdb P1023RDB - - 882 Active powerpc mpc85xx - freescale p1023rdb P1023RDB - -
883 Active powerpc mpc85xx - freescale p1023rds P1023RDS - Roy Zang <tie-fei.zang@freescale.com> 883 Active powerpc mpc85xx - freescale p1023rds P1023RDS - Roy Zang <tie-fei.zang@freescale.com>
884 Active powerpc mpc85xx - freescale p1023rds P1023RDS_NAND P1023RDS:NAND Roy Zang <tie-fei.zang@freescale.com> 884 Active powerpc mpc85xx - freescale p1023rds P1023RDS_NAND P1023RDS:NAND Roy Zang <tie-fei.zang@freescale.com>
885 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB - 885 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB -
886 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT - 886 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT -
887 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SDCARD P1_P2_RDB:P1011RDB,36BIT,SDCARD - 887 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SDCARD P1_P2_RDB:P1011RDB,36BIT,SDCARD -
888 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SPIFLASH P1_P2_RDB:P1011RDB,36BIT,SPIFLASH - 888 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SPIFLASH P1_P2_RDB:P1011RDB,36BIT,SPIFLASH -
889 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_NAND P1_P2_RDB:P1011RDB,NAND - 889 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_NAND P1_P2_RDB:P1011RDB,NAND -
890 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SDCARD P1_P2_RDB:P1011RDB,SDCARD - 890 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SDCARD P1_P2_RDB:P1011RDB,SDCARD -
891 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SPIFLASH P1_P2_RDB:P1011RDB,SPIFLASH - 891 Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_SPIFLASH P1_P2_RDB:P1011RDB,SPIFLASH -
892 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB P1_P2_RDB:P1020RDB - 892 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB P1_P2_RDB:P1020RDB -
893 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT P1_P2_RDB:P1020RDB,36BIT - 893 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT P1_P2_RDB:P1020RDB,36BIT -
894 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SDCARD P1_P2_RDB:P1020RDB,36BIT,SDCARD - 894 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SDCARD P1_P2_RDB:P1020RDB,36BIT,SDCARD -
895 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SPIFLASH P1_P2_RDB:P1020RDB,36BIT,SPIFLASH - 895 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_36BIT_SPIFLASH P1_P2_RDB:P1020RDB,36BIT,SPIFLASH -
896 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_NAND P1_P2_RDB:P1020RDB,NAND - 896 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_NAND P1_P2_RDB:P1020RDB,NAND -
897 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SDCARD P1_P2_RDB:P1020RDB,SDCARD - 897 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SDCARD P1_P2_RDB:P1020RDB,SDCARD -
898 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SPIFLASH P1_P2_RDB:P1020RDB,SPIFLASH - 898 Active powerpc mpc85xx - freescale p1_p2_rdb P1020RDB_SPIFLASH P1_P2_RDB:P1020RDB,SPIFLASH -
899 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB P1_P2_RDB:P2010RDB - 899 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB P1_P2_RDB:P2010RDB -
900 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT P1_P2_RDB:P2010RDB,36BIT - 900 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT P1_P2_RDB:P2010RDB,36BIT -
901 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SDCARD P1_P2_RDB:P2010RDB,36BIT,SDCARD - 901 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SDCARD P1_P2_RDB:P2010RDB,36BIT,SDCARD -
902 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SPIFLASH P1_P2_RDB:P2010RDB,36BIT,SPIFLASH - 902 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_36BIT_SPIFLASH P1_P2_RDB:P2010RDB,36BIT,SPIFLASH -
903 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_NAND P1_P2_RDB:P2010RDB,NAND - 903 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_NAND P1_P2_RDB:P2010RDB,NAND -
904 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SDCARD P1_P2_RDB:P2010RDB,SDCARD - 904 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SDCARD P1_P2_RDB:P2010RDB,SDCARD -
905 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SPIFLASH P1_P2_RDB:P2010RDB,SPIFLASH - 905 Active powerpc mpc85xx - freescale p1_p2_rdb P2010RDB_SPIFLASH P1_P2_RDB:P2010RDB,SPIFLASH -
906 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB P1_P2_RDB:P2020RDB Poonam Aggrwal <poonam.aggrwal@freescale.com> 906 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB P1_P2_RDB:P2020RDB Poonam Aggrwal <poonam.aggrwal@freescale.com>
907 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT P1_P2_RDB:P2020RDB,36BIT - 907 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT P1_P2_RDB:P2020RDB,36BIT -
908 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SDCARD P1_P2_RDB:P2020RDB,36BIT,SDCARD - 908 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SDCARD P1_P2_RDB:P2020RDB,36BIT,SDCARD -
909 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SPIFLASH P1_P2_RDB:P2020RDB,36BIT,SPIFLASH - 909 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_36BIT_SPIFLASH P1_P2_RDB:P2020RDB,36BIT,SPIFLASH -
910 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_NAND P1_P2_RDB:P2020RDB,NAND - 910 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_NAND P1_P2_RDB:P2020RDB,NAND -
911 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SDCARD P1_P2_RDB:P2020RDB,SDCARD - 911 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SDCARD P1_P2_RDB:P2020RDB,SDCARD -
912 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SPIFLASH P1_P2_RDB:P2020RDB,SPIFLASH - 912 Active powerpc mpc85xx - freescale p1_p2_rdb P2020RDB_SPIFLASH P1_P2_RDB:P2020RDB,SPIFLASH -
913 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC p1_p2_rdb_pc:P1020MBG - 913 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC p1_p2_rdb_pc:P1020MBG -
914 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT p1_p2_rdb_pc:P1020MBG,36BIT - 914 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT p1_p2_rdb_pc:P1020MBG,36BIT -
915 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD,36BIT - 915 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD,36BIT -
916 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD - 916 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020MBG-PC_SDCARD p1_p2_rdb_pc:P1020MBG,SDCARD -
917 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC p1_p2_rdb_pc:P1020RDB_PC - 917 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC p1_p2_rdb_pc:P1020RDB_PC -
918 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT p1_p2_rdb_pc:P1020RDB_PC,36BIT - 918 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT p1_p2_rdb_pc:P1020RDB_PC,36BIT -
919 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1020RDB_PC,36BIT,NAND - 919 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1020RDB_PC,36BIT,NAND -
920 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020RDB_PC,36BIT,SDCARD - 920 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020RDB_PC,36BIT,SDCARD -
921 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,36BIT,SPIFLASH - 921 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,36BIT,SPIFLASH -
922 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_NAND p1_p2_rdb_pc:P1020RDB_PC,NAND - 922 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_NAND p1_p2_rdb_pc:P1020RDB_PC,NAND -
923 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SDCARD p1_p2_rdb_pc:P1020RDB_PC,SDCARD - 923 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SDCARD p1_p2_rdb_pc:P1020RDB_PC,SDCARD -
924 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,SPIFLASH - 924 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PC_SPIFLASH p1_p2_rdb_pc:P1020RDB_PC,SPIFLASH -
925 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD p1_p2_rdb_pc:P1020RDB_PD - 925 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD p1_p2_rdb_pc:P1020RDB_PD -
926 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_NAND p1_p2_rdb_pc:P1020RDB_PD,NAND - 926 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_NAND p1_p2_rdb_pc:P1020RDB_PD,NAND -
927 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SDCARD p1_p2_rdb_pc:P1020RDB_PD,SDCARD - 927 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SDCARD p1_p2_rdb_pc:P1020RDB_PD,SDCARD -
928 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SPIFLASH p1_p2_rdb_pc:P1020RDB_PD,SPIFLASH - 928 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020RDB-PD_SPIFLASH p1_p2_rdb_pc:P1020RDB_PD,SPIFLASH -
929 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC p1_p2_rdb_pc:P1020UTM - 929 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC p1_p2_rdb_pc:P1020UTM -
930 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT p1_p2_rdb_pc:P1020UTM,36BIT - 930 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT p1_p2_rdb_pc:P1020UTM,36BIT -
931 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD - 931 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_36BIT_SDCARD p1_p2_rdb_pc:P1020UTM,36BIT,SDCARD -
932 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_SDCARD p1_p2_rdb_pc:P1020UTM,SDCARD - 932 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1020UTM-PC_SDCARD p1_p2_rdb_pc:P1020UTM,SDCARD -
933 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC p1_p2_rdb_pc:P1021RDB - 933 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC p1_p2_rdb_pc:P1021RDB -
934 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT p1_p2_rdb_pc:P1021RDB,36BIT - 934 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT p1_p2_rdb_pc:P1021RDB,36BIT -
935 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1021RDB,36BIT,NAND - 935 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_NAND p1_p2_rdb_pc:P1021RDB,36BIT,NAND -
936 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1021RDB,36BIT,SDCARD - 936 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P1021RDB,36BIT,SDCARD -
937 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1021RDB,36BIT,SPIFLASH - 937 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P1021RDB,36BIT,SPIFLASH -
938 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_NAND p1_p2_rdb_pc:P1021RDB,NAND - 938 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_NAND p1_p2_rdb_pc:P1021RDB,NAND -
939 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SDCARD p1_p2_rdb_pc:P1021RDB,SDCARD - 939 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SDCARD p1_p2_rdb_pc:P1021RDB,SDCARD -
940 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SPIFLASH p1_p2_rdb_pc:P1021RDB,SPIFLASH - 940 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1021RDB-PC_SPIFLASH p1_p2_rdb_pc:P1021RDB,SPIFLASH -
941 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB p1_p2_rdb_pc:P1024RDB - 941 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB p1_p2_rdb_pc:P1024RDB -
942 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_36BIT p1_p2_rdb_pc:P1024RDB,36BIT - 942 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_36BIT p1_p2_rdb_pc:P1024RDB,36BIT -
943 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_NAND p1_p2_rdb_pc:P1024RDB,NAND - 943 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_NAND p1_p2_rdb_pc:P1024RDB,NAND -
944 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SDCARD p1_p2_rdb_pc:P1024RDB,SDCARD - 944 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SDCARD p1_p2_rdb_pc:P1024RDB,SDCARD -
945 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SPIFLASH p1_p2_rdb_pc:P1024RDB,SPIFLASH - 945 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1024RDB_SPIFLASH p1_p2_rdb_pc:P1024RDB,SPIFLASH -
946 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB p1_p2_rdb_pc:P1025RDB - 946 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB p1_p2_rdb_pc:P1025RDB -
947 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_36BIT p1_p2_rdb_pc:P1025RDB,36BIT - 947 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_36BIT p1_p2_rdb_pc:P1025RDB,36BIT -
948 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_NAND p1_p2_rdb_pc:P1025RDB,NAND - 948 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_NAND p1_p2_rdb_pc:P1025RDB,NAND -
949 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SDCARD p1_p2_rdb_pc:P1025RDB,SDCARD - 949 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SDCARD p1_p2_rdb_pc:P1025RDB,SDCARD -
950 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SPIFLASH p1_p2_rdb_pc:P1025RDB,SPIFLASH - 950 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P1025RDB_SPIFLASH p1_p2_rdb_pc:P1025RDB,SPIFLASH -
951 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC p1_p2_rdb_pc:P2020RDB - 951 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC p1_p2_rdb_pc:P2020RDB -
952 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT p1_p2_rdb_pc:P2020RDB,36BIT - 952 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT p1_p2_rdb_pc:P2020RDB,36BIT -
953 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P2020RDB,36BIT,NAND - 953 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_NAND p1_p2_rdb_pc:P2020RDB,36BIT,NAND -
954 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD - 954 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SDCARD p1_p2_rdb_pc:P2020RDB,36BIT,SDCARD -
955 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH - 955 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_36BIT_SPIFLASH p1_p2_rdb_pc:P2020RDB,36BIT,SPIFLASH -
956 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_NAND p1_p2_rdb_pc:P2020RDB,NAND - 956 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_NAND p1_p2_rdb_pc:P2020RDB,NAND -
957 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SDCARD p1_p2_rdb_pc:P2020RDB,SDCARD - 957 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SDCARD p1_p2_rdb_pc:P2020RDB,SDCARD -
958 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SPIFLASH p1_p2_rdb_pc:P2020RDB,SPIFLASH - 958 Active powerpc mpc85xx - freescale p1_p2_rdb_pc P2020RDB-PC_SPIFLASH p1_p2_rdb_pc:P2020RDB,SPIFLASH -
959 Active powerpc mpc85xx - freescale p1_twr TWR-P1025 p1_twr:TWR_P1025 - 959 Active powerpc mpc85xx - freescale p1_twr TWR-P1025 p1_twr:TWR_P1025 -
960 Active powerpc mpc85xx - freescale p2020come P2020COME_SDCARD P2020COME:SDCARD Ira W. Snyder <iws@ovro.caltech.edu> 960 Active powerpc mpc85xx - freescale p2020come P2020COME_SDCARD P2020COME:SDCARD Ira W. Snyder <iws@ovro.caltech.edu>
961 Active powerpc mpc85xx - freescale p2020come P2020COME_SPIFLASH P2020COME:SPIFLASH Ira W. Snyder <iws@ovro.caltech.edu> 961 Active powerpc mpc85xx - freescale p2020come P2020COME_SPIFLASH P2020COME:SPIFLASH Ira W. Snyder <iws@ovro.caltech.edu>
962 Active powerpc mpc85xx - freescale p2020ds P2020DS - - 962 Active powerpc mpc85xx - freescale p2020ds P2020DS - -
963 Active powerpc mpc85xx - freescale p2020ds P2020DS_36BIT P2020DS:36BIT - 963 Active powerpc mpc85xx - freescale p2020ds P2020DS_36BIT P2020DS:36BIT -
964 Active powerpc mpc85xx - freescale p2020ds P2020DS_DDR2 P2020DS:DDR2 - 964 Active powerpc mpc85xx - freescale p2020ds P2020DS_DDR2 P2020DS:DDR2 -
965 Active powerpc mpc85xx - freescale p2020ds P2020DS_SDCARD P2020DS:SDCARD - 965 Active powerpc mpc85xx - freescale p2020ds P2020DS_SDCARD P2020DS:SDCARD -
966 Active powerpc mpc85xx - freescale p2020ds P2020DS_SPIFLASH P2020DS:SPIFLASH - 966 Active powerpc mpc85xx - freescale p2020ds P2020DS_SPIFLASH P2020DS:SPIFLASH -
967 Active powerpc mpc85xx - freescale p2041rdb P2041RDB - - 967 Active powerpc mpc85xx - freescale p2041rdb P2041RDB - -
968 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - 968 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_NAND P2041RDB:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
969 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - 969 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SDCARD P2041RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
970 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SECURE_BOOT P2041RDB:SECURE_BOOT - 970 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SECURE_BOOT P2041RDB:SECURE_BOOT -
971 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - 971 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SPIFLASH P2041RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
972 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - 972 Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
973 Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com> 973 Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
974 Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com> 974 Active powerpc mpc85xx - freescale t104xrdb T1040RDB T1040RDB:PPC_T1040 Poonam Aggrwal <poonam.aggrwal@freescale.com>
975 Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com> 975 Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T1042RDB_PI:PPC_T1042 Poonam Aggrwal <poonam.aggrwal@freescale.com>
976 Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 976 Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080
977 Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 977 Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
978 Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 978 Active powerpc mpc85xx - freescale t208xqds T2080QDS_SPIFLASH T208xQDS:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
979 Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 979 Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
980 Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 980 Active powerpc mpc85xx - freescale t208xqds T2080QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
981 Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081 981 Active powerpc mpc85xx - freescale t208xqds T2081QDS T208xQDS:PPC_T2081
982 Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 982 Active powerpc mpc85xx - freescale t208xqds T2081QDS_SDCARD T208xQDS:PPC_T2081,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
983 Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 983 Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
984 Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 984 Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
985 Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 985 Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
986 Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080
987 Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
988 Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
989 Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
990 Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
986 Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 - 991 Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
987 Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - 992 Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
988 Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - 993 Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
989 Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun@freescale.com> 994 Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun@freescale.com>
990 Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 - 995 Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 -
991 Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - 996 Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
992 Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 - 997 Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
993 Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - 998 Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
994 Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - 999 Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
995 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de> 1000 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach <eibach@gdsys.de>
996 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de> 1001 Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach <eibach@gdsys.de>
997 Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de> 1002 Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach <eibach@gdsys.de>
998 Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach <eibach@gdsys.de> 1003 Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach <eibach@gdsys.de>
999 Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp <valentin.longchamp@keymile.com> 1004 Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp <valentin.longchamp@keymile.com>
1000 Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp <valentin.longchamp@keymile.com> 1005 Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp <valentin.longchamp@keymile.com>
1001 Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan@embeddedalley.com> 1006 Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan@embeddedalley.com>
1002 Active powerpc mpc85xx - stx stxssa stxssa - Dan Malek <dan@embeddedalley.com> 1007 Active powerpc mpc85xx - stx stxssa stxssa - Dan Malek <dan@embeddedalley.com>
1003 Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan@embeddedalley.com> 1008 Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan@embeddedalley.com>
1004 Active powerpc mpc85xx - xes - xpedite520x - - 1009 Active powerpc mpc85xx - xes - xpedite520x - -
1005 Active powerpc mpc85xx - xes - xpedite537x - - 1010 Active powerpc mpc85xx - xes - xpedite537x - -
1006 Active powerpc mpc85xx - xes - xpedite550x - - 1011 Active powerpc mpc85xx - xes - xpedite550x - -
1007 Active powerpc mpc86xx - - - sbc8641d - Paul Gortmaker <paul.gortmaker@windriver.com> 1012 Active powerpc mpc86xx - - - sbc8641d - Paul Gortmaker <paul.gortmaker@windriver.com>
1008 Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - - 1013 Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - -
1009 Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala <kumar.gala@freescale.com> 1014 Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala <kumar.gala@freescale.com>
1010 Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala@freescale.com> 1015 Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala@freescale.com>
1011 Active powerpc mpc86xx - xes - xpedite517x - - 1016 Active powerpc mpc86xx - xes - xpedite517x - -
1012 Active powerpc mpc8xx - - - hermes - Wolfgang Denk <wd@denx.de> 1017 Active powerpc mpc8xx - - - hermes - Wolfgang Denk <wd@denx.de>
1013 Active powerpc mpc8xx - - - lwmon - Wolfgang Denk <wd@denx.de> 1018 Active powerpc mpc8xx - - - lwmon - Wolfgang Denk <wd@denx.de>
1014 Active powerpc mpc8xx - - - quantum - - 1019 Active powerpc mpc8xx - - - quantum - -
1015 Active powerpc mpc8xx - - - RRvision - Wolfgang Denk <wd@denx.de> 1020 Active powerpc mpc8xx - - - RRvision - Wolfgang Denk <wd@denx.de>
1016 Active powerpc mpc8xx - - - spc1920 - - 1021 Active powerpc mpc8xx - - - spc1920 - -
1017 Active powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz@sinovee.com> 1022 Active powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz@sinovee.com>
1018 Active powerpc mpc8xx - - - v37 - - 1023 Active powerpc mpc8xx - - - v37 - -
1019 Active powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli@arabellasw.com> 1024 Active powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli@arabellasw.com>
1020 Active powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli@arabellasw.com> 1025 Active powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli@arabellasw.com>
1021 Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au> 1026 Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au>
1022 Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com> 1027 Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com>
1023 Active powerpc mpc8xx - - fads MPC86xADS - - 1028 Active powerpc mpc8xx - - fads MPC86xADS - -
1024 Active powerpc mpc8xx - - fads MPC885ADS - - 1029 Active powerpc mpc8xx - - fads MPC885ADS - -
1025 Active powerpc mpc8xx - - flagadm FLAGADM - Kári Davíðsson <kd@flaga.is> 1030 Active powerpc mpc8xx - - flagadm FLAGADM - Kári Davíðsson <kd@flaga.is>
1026 Active powerpc mpc8xx - - gen860t GEN860T - Keith Outwater <Keith_Outwater@mvis.com> 1031 Active powerpc mpc8xx - - gen860t GEN860T - Keith Outwater <Keith_Outwater@mvis.com>
1027 Active powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater <Keith_Outwater@mvis.com> 1032 Active powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater <Keith_Outwater@mvis.com>
1028 Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk <wd@denx.de> 1033 Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk <wd@denx.de>
1029 Active powerpc mpc8xx - - icu862 ICU862_100MHz ICU862:100MHz Wolfgang Denk <wd@denx.de> 1034 Active powerpc mpc8xx - - icu862 ICU862_100MHz ICU862:100MHz Wolfgang Denk <wd@denx.de>
1030 Active powerpc mpc8xx - - ip860 IP860 - Wolfgang Denk <wd@denx.de> 1035 Active powerpc mpc8xx - - ip860 IP860 - Wolfgang Denk <wd@denx.de>
1031 Active powerpc mpc8xx - - ivm IVML24 IVML24:IVML24_16M Wolfgang Denk <wd@denx.de> 1036 Active powerpc mpc8xx - - ivm IVML24 IVML24:IVML24_16M Wolfgang Denk <wd@denx.de>
1032 Active powerpc mpc8xx - - ivm IVML24_128 IVML24:IVML24_32M Wolfgang Denk <wd@denx.de> 1037 Active powerpc mpc8xx - - ivm IVML24_128 IVML24:IVML24_32M Wolfgang Denk <wd@denx.de>
1033 Active powerpc mpc8xx - - ivm IVML24_256 IVML24:IVML24_64M Wolfgang Denk <wd@denx.de> 1038 Active powerpc mpc8xx - - ivm IVML24_256 IVML24:IVML24_64M Wolfgang Denk <wd@denx.de>
1034 Active powerpc mpc8xx - - ivm IVMS8 IVMS8:IVMS8_16M Wolfgang Denk <wd@denx.de> 1039 Active powerpc mpc8xx - - ivm IVMS8 IVMS8:IVMS8_16M Wolfgang Denk <wd@denx.de>
1035 Active powerpc mpc8xx - - ivm IVMS8_128 IVMS8:IVMS8_32M Wolfgang Denk <wd@denx.de> 1040 Active powerpc mpc8xx - - ivm IVMS8_128 IVMS8:IVMS8_32M Wolfgang Denk <wd@denx.de>
1036 Active powerpc mpc8xx - - ivm IVMS8_256 IVMS8:IVMS8_64M Wolfgang Denk <wd@denx.de> 1041 Active powerpc mpc8xx - - ivm IVMS8_256 IVMS8:IVMS8_64M Wolfgang Denk <wd@denx.de>
1037 Active powerpc mpc8xx - - netphone NETPHONE NETPHONE:NETPHONE_VERSION=1 - 1042 Active powerpc mpc8xx - - netphone NETPHONE NETPHONE:NETPHONE_VERSION=1 -
1038 Active powerpc mpc8xx - - netphone NETPHONE_V2 NETPHONE:NETPHONE_VERSION=2 - 1043 Active powerpc mpc8xx - - netphone NETPHONE_V2 NETPHONE:NETPHONE_VERSION=2 -
1039 Active powerpc mpc8xx - - netta NETTA - - 1044 Active powerpc mpc8xx - - netta NETTA - -
1040 Active powerpc mpc8xx - - netta NETTA_6412 NETTA:NETTA_6412=1 - 1045 Active powerpc mpc8xx - - netta NETTA_6412 NETTA:NETTA_6412=1 -
1041 Active powerpc mpc8xx - - netta NETTA_6412_SWAPHOOK NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1 - 1046 Active powerpc mpc8xx - - netta NETTA_6412_SWAPHOOK NETTA:NETTA_6412=1,NETTA_SWAPHOOK=1 -
1042 Active powerpc mpc8xx - - netta NETTA_ISDN NETTA:NETTA_ISDN=1 - 1047 Active powerpc mpc8xx - - netta NETTA_ISDN NETTA:NETTA_ISDN=1 -
1043 Active powerpc mpc8xx - - netta NETTA_ISDN_6412 NETTA:NETTA_ISDN=1,NETTA_6412=1 - 1048 Active powerpc mpc8xx - - netta NETTA_ISDN_6412 NETTA:NETTA_ISDN=1,NETTA_6412=1 -
1044 Active powerpc mpc8xx - - netta NETTA_ISDN_6412_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1 - 1049 Active powerpc mpc8xx - - netta NETTA_ISDN_6412_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_6412=1,NETTA_SWAPHOOK=1 -
1045 Active powerpc mpc8xx - - netta NETTA_ISDN_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1 - 1050 Active powerpc mpc8xx - - netta NETTA_ISDN_SWAPHOOK NETTA:NETTA_ISDN=1,NETTA_SWAPHOOK=1 -
1046 Active powerpc mpc8xx - - netta NETTA_SWAPHOOK NETTA:NETTA_SWAPHOOK=1 - 1051 Active powerpc mpc8xx - - netta NETTA_SWAPHOOK NETTA:NETTA_SWAPHOOK=1 -
1047 Active powerpc mpc8xx - - netta2 NETTA2 NETTA2:NETTA2_VERSION=1 - 1052 Active powerpc mpc8xx - - netta2 NETTA2 NETTA2:NETTA2_VERSION=1 -
1048 Active powerpc mpc8xx - - netta2 NETTA2_V2 NETTA2:NETTA2_VERSION=2 - 1053 Active powerpc mpc8xx - - netta2 NETTA2_V2 NETTA2:NETTA2_VERSION=2 -
1049 Active powerpc mpc8xx - - netvia NETVIA NETVIA:NETVIA_VERSION=1 Pantelis Antoniou <panto@intracom.gr> 1054 Active powerpc mpc8xx - - netvia NETVIA NETVIA:NETVIA_VERSION=1 Pantelis Antoniou <panto@intracom.gr>
1050 Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou <panto@intracom.gr> 1055 Active powerpc mpc8xx - - netvia NETVIA_V2 NETVIA:NETVIA_VERSION=2 Pantelis Antoniou <panto@intracom.gr>
1051 Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk <wd@denx.de> 1056 Active powerpc mpc8xx - - r360mpi R360MPI - Wolfgang Denk <wd@denx.de>
1052 Active powerpc mpc8xx - - rbc823 RBC823 - - 1057 Active powerpc mpc8xx - - rbc823 RBC823 - -
1053 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW - - 1058 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW - -
1054 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64 RPXlite_DW:RPXlite_64MHz - 1059 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64 RPXlite_DW:RPXlite_64MHz -
1055 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 - 1060 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20 -
1056 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_LCD RPXlite_DW:LCD,NEC_NL6448BC20 - 1061 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_LCD RPXlite_DW:LCD,NEC_NL6448BC20 -
1057 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM RPXlite_DW:ENV_IS_IN_NVRAM - 1062 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM RPXlite_DW:ENV_IS_IN_NVRAM -
1058 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64 RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM - 1063 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64 RPXlite_DW:RPXlite_64MHz,ENV_IS_IN_NVRAM -
1059 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM - 1064 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
1060 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_LCD RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM - 1065 Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_LCD RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
1061 Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de> 1066 Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
1062 Active powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis <DGE@sixnetio.com> 1067 Active powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis <DGE@sixnetio.com>
1063 Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk <wd@denx.de> 1068 Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk <wd@denx.de>
1064 Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling <fgottschling@eltec.de> 1069 Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling <fgottschling@eltec.de>
1065 Active powerpc mpc8xx - emk top860 TOP860 - Reinhard Meyer <reinhard.meyer@emk-elektronik.de> 1070 Active powerpc mpc8xx - emk top860 TOP860 - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
1066 Active powerpc mpc8xx - kup kup4k KUP4K - Klaus Heydeck <heydeck@kieback-peter.de> 1071 Active powerpc mpc8xx - kup kup4k KUP4K - Klaus Heydeck <heydeck@kieback-peter.de>
1067 Active powerpc mpc8xx - kup kup4x KUP4X - Klaus Heydeck <heydeck@kieback-peter.de> 1072 Active powerpc mpc8xx - kup kup4x KUP4X - Klaus Heydeck <heydeck@kieback-peter.de>
1068 Active powerpc mpc8xx - LEOX elpt860 ELPT860 - The LEOX team <team@leox.org> 1073 Active powerpc mpc8xx - LEOX elpt860 ELPT860 - The LEOX team <team@leox.org>
1069 Active powerpc mpc8xx - manroland - uc100 - Stefan Roese <sr@denx.de> 1074 Active powerpc mpc8xx - manroland - uc100 - Stefan Roese <sr@denx.de>
1070 Active powerpc mpc8xx - snmc qs850 QS823 - - 1075 Active powerpc mpc8xx - snmc qs850 QS823 - -
1071 Active powerpc mpc8xx - snmc qs850 QS850 - - 1076 Active powerpc mpc8xx - snmc qs850 QS850 - -
1072 Active powerpc mpc8xx - snmc qs860t QS860T - - 1077 Active powerpc mpc8xx - snmc qs860t QS860T - -
1073 Active powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek <dan@embeddedalley.com> 1078 Active powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek <dan@embeddedalley.com>
1074 Active powerpc mpc8xx - tqc tqm8xx FPS850L - Wolfgang Denk <wd@denx.de> 1079 Active powerpc mpc8xx - tqc tqm8xx FPS850L - Wolfgang Denk <wd@denx.de>
1075 Active powerpc mpc8xx - tqc tqm8xx FPS860L - Wolfgang Denk <wd@denx.de> 1080 Active powerpc mpc8xx - tqc tqm8xx FPS860L - Wolfgang Denk <wd@denx.de>
1076 Active powerpc mpc8xx - tqc tqm8xx NSCU - - 1081 Active powerpc mpc8xx - tqc tqm8xx NSCU - -
1077 Active powerpc mpc8xx - tqc tqm8xx SM850 - Wolfgang Denk <wd@denx.de> 1082 Active powerpc mpc8xx - tqc tqm8xx SM850 - Wolfgang Denk <wd@denx.de>
1078 Active powerpc mpc8xx - tqc tqm8xx TK885D - - 1083 Active powerpc mpc8xx - tqc tqm8xx TK885D - -
1079 Active powerpc mpc8xx - tqc tqm8xx TQM823L - Wolfgang Denk <wd@denx.de> 1084 Active powerpc mpc8xx - tqc tqm8xx TQM823L - Wolfgang Denk <wd@denx.de>
1080 Active powerpc mpc8xx - tqc tqm8xx TQM823L_LCD TQM823L:LCD,NEC_NL6448BC20 Wolfgang Denk <wd@denx.de> 1085 Active powerpc mpc8xx - tqc tqm8xx TQM823L_LCD TQM823L:LCD,NEC_NL6448BC20 Wolfgang Denk <wd@denx.de>
1081 Active powerpc mpc8xx - tqc tqm8xx TQM823M - - 1086 Active powerpc mpc8xx - tqc tqm8xx TQM823M - -
1082 Active powerpc mpc8xx - tqc tqm8xx TQM850L - Wolfgang Denk <wd@denx.de> 1087 Active powerpc mpc8xx - tqc tqm8xx TQM850L - Wolfgang Denk <wd@denx.de>
1083 Active powerpc mpc8xx - tqc tqm8xx TQM850M - - 1088 Active powerpc mpc8xx - tqc tqm8xx TQM850M - -
1084 Active powerpc mpc8xx - tqc tqm8xx TQM855L - Wolfgang Denk <wd@denx.de> 1089 Active powerpc mpc8xx - tqc tqm8xx TQM855L - Wolfgang Denk <wd@denx.de>
1085 Active powerpc mpc8xx - tqc tqm8xx TQM855M - - 1090 Active powerpc mpc8xx - tqc tqm8xx TQM855M - -
1086 Active powerpc mpc8xx - tqc tqm8xx TQM860L - Wolfgang Denk <wd@denx.de> 1091 Active powerpc mpc8xx - tqc tqm8xx TQM860L - Wolfgang Denk <wd@denx.de>
1087 Active powerpc mpc8xx - tqc tqm8xx TQM860M - - 1092 Active powerpc mpc8xx - tqc tqm8xx TQM860M - -
1088 Active powerpc mpc8xx - tqc tqm8xx TQM862L - - 1093 Active powerpc mpc8xx - tqc tqm8xx TQM862L - -
1089 Active powerpc mpc8xx - tqc tqm8xx TQM862M - - 1094 Active powerpc mpc8xx - tqc tqm8xx TQM862M - -
1090 Active powerpc mpc8xx - tqc tqm8xx TQM866M - - 1095 Active powerpc mpc8xx - tqc tqm8xx TQM866M - -
1091 Active powerpc mpc8xx - tqc tqm8xx TQM885D - - 1096 Active powerpc mpc8xx - tqc tqm8xx TQM885D - -
1092 Active powerpc mpc8xx - tqc tqm8xx TTTech TQM823L:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de> 1097 Active powerpc mpc8xx - tqc tqm8xx TTTech TQM823L:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
1093 Active powerpc mpc8xx - tqc tqm8xx virtlab2 - - 1098 Active powerpc mpc8xx - tqc tqm8xx virtlab2 - -
1094 Active powerpc mpc8xx - tqc tqm8xx wtk TQM823L:LCD,SHARP_LQ065T9DR51U Wolfgang Denk <wd@denx.de> 1099 Active powerpc mpc8xx - tqc tqm8xx wtk TQM823L:LCD,SHARP_LQ065T9DR51U Wolfgang Denk <wd@denx.de>
1095 Active powerpc ppc4xx - - - csb272 - Tolunay Orkun <torkun@nextio.com> 1100 Active powerpc ppc4xx - - - csb272 - Tolunay Orkun <torkun@nextio.com>
1096 Active powerpc ppc4xx - - - csb472 - Tolunay Orkun <torkun@nextio.com> 1101 Active powerpc ppc4xx - - - csb472 - Tolunay Orkun <torkun@nextio.com>
1097 Active powerpc ppc4xx - - - korat - Larry Johnson <lrj@acm.org> 1102 Active powerpc ppc4xx - - - korat - Larry Johnson <lrj@acm.org>
1098 Active powerpc ppc4xx - - - lwmon5 - Stefan Roese <sr@denx.de> 1103 Active powerpc ppc4xx - - - lwmon5 - Stefan Roese <sr@denx.de>
1099 Active powerpc ppc4xx - - - pcs440ep - Stefan Roese <sr@denx.de> 1104 Active powerpc ppc4xx - - - pcs440ep - Stefan Roese <sr@denx.de>
1100 Active powerpc ppc4xx - - - quad100hd - Gary Jennejohn <garyj@denx.de> 1105 Active powerpc ppc4xx - - - quad100hd - Gary Jennejohn <garyj@denx.de>
1101 Active powerpc ppc4xx - - - sbc405 - - 1106 Active powerpc ppc4xx - - - sbc405 - -
1102 Active powerpc ppc4xx - - - sc3 - Heiko Schocher <hs@denx.de> 1107 Active powerpc ppc4xx - - - sc3 - Heiko Schocher <hs@denx.de>
1103 Active powerpc ppc4xx - - - t3corp - Stefan Roese <sr@denx.de> 1108 Active powerpc ppc4xx - - - t3corp - Stefan Roese <sr@denx.de>
1104 Active powerpc ppc4xx - - - zeus - Stefan Roese <sr@denx.de> 1109 Active powerpc ppc4xx - - - zeus - Stefan Roese <sr@denx.de>
1105 Active powerpc ppc4xx - - g2000 G2000 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1110 Active powerpc ppc4xx - - g2000 G2000 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1106 Active powerpc ppc4xx - - jse JSE - Stephen Williams <steve@icarus.com> 1111 Active powerpc ppc4xx - - jse JSE - Stephen Williams <steve@icarus.com>
1107 Active powerpc ppc4xx - - korat korat_perm korat:KORAT_PERMANENT Larry Johnson <lrj@acm.org> 1112 Active powerpc ppc4xx - - korat korat_perm korat:KORAT_PERMANENT Larry Johnson <lrj@acm.org>
1108 Active powerpc ppc4xx - - lwmon5 lcd4_lwmon5 lwmon5:LCD4_LWMON5 Stefan Roese <sr@denx.de> 1113 Active powerpc ppc4xx - - lwmon5 lcd4_lwmon5 lwmon5:LCD4_LWMON5 Stefan Roese <sr@denx.de>
1109 Active powerpc ppc4xx - - w7o W7OLMC - Erik Theisen <etheisen@mindspring.com> 1114 Active powerpc ppc4xx - - w7o W7OLMC - Erik Theisen <etheisen@mindspring.com>
1110 Active powerpc ppc4xx - - w7o W7OLMG - Erik Theisen <etheisen@mindspring.com> 1115 Active powerpc ppc4xx - - w7o W7OLMG - Erik Theisen <etheisen@mindspring.com>
1111 Active powerpc ppc4xx - amcc - acadia - Stefan Roese <sr@denx.de> 1116 Active powerpc ppc4xx - amcc - acadia - Stefan Roese <sr@denx.de>
1112 Active powerpc ppc4xx - amcc - bamboo - Stefan Roese <sr@denx.de> 1117 Active powerpc ppc4xx - amcc - bamboo - Stefan Roese <sr@denx.de>
1113 Active powerpc ppc4xx - amcc - bluestone - Tirumala Marri <tmarri@apm.com> 1118 Active powerpc ppc4xx - amcc - bluestone - Tirumala Marri <tmarri@apm.com>
1114 Active powerpc ppc4xx - amcc - bubinga - - 1119 Active powerpc ppc4xx - amcc - bubinga - -
1115 Active powerpc ppc4xx - amcc - ebony - Stefan Roese <sr@denx.de> 1120 Active powerpc ppc4xx - amcc - ebony - Stefan Roese <sr@denx.de>
1116 Active powerpc ppc4xx - amcc - katmai - Stefan Roese <sr@denx.de> 1121 Active powerpc ppc4xx - amcc - katmai - Stefan Roese <sr@denx.de>
1117 Active powerpc ppc4xx - amcc - luan - John Otken <jotken@softadvances.com> 1122 Active powerpc ppc4xx - amcc - luan - John Otken <jotken@softadvances.com>
1118 Active powerpc ppc4xx - amcc - makalu - Stefan Roese <sr@denx.de> 1123 Active powerpc ppc4xx - amcc - makalu - Stefan Roese <sr@denx.de>
1119 Active powerpc ppc4xx - amcc - ocotea - Stefan Roese <sr@denx.de> 1124 Active powerpc ppc4xx - amcc - ocotea - Stefan Roese <sr@denx.de>
1120 Active powerpc ppc4xx - amcc - redwood - Feng Kan <fkan@amcc.com> 1125 Active powerpc ppc4xx - amcc - redwood - Feng Kan <fkan@amcc.com>
1121 Active powerpc ppc4xx - amcc - taihu - John Otken <jotken@softadvances.com> 1126 Active powerpc ppc4xx - amcc - taihu - John Otken <jotken@softadvances.com>
1122 Active powerpc ppc4xx - amcc - taishan - Stefan Roese <sr@denx.de> 1127 Active powerpc ppc4xx - amcc - taishan - Stefan Roese <sr@denx.de>
1123 Active powerpc ppc4xx - amcc - yucca - - 1128 Active powerpc ppc4xx - amcc - yucca - -
1124 Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese <sr@denx.de> 1129 Active powerpc ppc4xx - amcc canyonlands arches canyonlands:ARCHES Stefan Roese <sr@denx.de>
1125 Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese <sr@denx.de> 1130 Active powerpc ppc4xx - amcc canyonlands canyonlands canyonlands:CANYONLANDS Stefan Roese <sr@denx.de>
1126 Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese <sr@denx.de> 1131 Active powerpc ppc4xx - amcc canyonlands glacier canyonlands:GLACIER Stefan Roese <sr@denx.de>
1127 Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese <sr@denx.de> 1132 Active powerpc ppc4xx - amcc kilauea haleakala kilauea:HALEAKALA Stefan Roese <sr@denx.de>
1128 Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese <sr@denx.de> 1133 Active powerpc ppc4xx - amcc kilauea kilauea kilauea:KILAUEA Stefan Roese <sr@denx.de>
1129 Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese <sr@denx.de> 1134 Active powerpc ppc4xx - amcc sequoia rainier sequoia:RAINIER Stefan Roese <sr@denx.de>
1130 Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de> 1135 Active powerpc ppc4xx - amcc sequoia rainier_ramboot sequoia:RAINIER,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
1131 Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese <sr@denx.de> 1136 Active powerpc ppc4xx - amcc sequoia sequoia sequoia:SEQUOIA Stefan Roese <sr@denx.de>
1132 Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de> 1137 Active powerpc ppc4xx - amcc sequoia sequoia_ramboot sequoia:SEQUOIA,SYS_RAMBOOT,SYS_TEXT_BASE=0x01000000,SYS_LDSCRIPT=board/amcc/sequoia/u-boot-ram.lds Stefan Roese <sr@denx.de>
1133 Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese <sr@denx.de> 1138 Active powerpc ppc4xx - amcc walnut sycamore walnut Stefan Roese <sr@denx.de>
1134 Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese <sr@denx.de> 1139 Active powerpc ppc4xx - amcc walnut walnut - Stefan Roese <sr@denx.de>
1135 Active powerpc ppc4xx - amcc yosemite yellowstone yosemite:YELLOWSTONE Stefan Roese <sr@denx.de> 1140 Active powerpc ppc4xx - amcc yosemite yellowstone yosemite:YELLOWSTONE Stefan Roese <sr@denx.de>
1136 Active powerpc ppc4xx - amcc yosemite yosemite yosemite:YOSEMITE Stefan Roese <sr@denx.de> 1141 Active powerpc ppc4xx - amcc yosemite yosemite yosemite:YOSEMITE Stefan Roese <sr@denx.de>
1137 Active powerpc ppc4xx - avnet fx12mm fx12mm fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de> 1142 Active powerpc ppc4xx - avnet fx12mm fx12mm fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de>
1138 Active powerpc ppc4xx - avnet fx12mm fx12mm_flash fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de> 1143 Active powerpc ppc4xx - avnet fx12mm fx12mm_flash fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o Georg Schardt <schardt@team-ctech.de>
1139 Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es> 1144 Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
1140 Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval_flash v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es> 1145 Active powerpc ppc4xx - avnet v5fx30teval v5fx30teval_flash v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
1141 Active powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave@cray.com> 1146 Active powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave@cray.com>
1142 Active powerpc ppc4xx - dave PPChameleonEVB CATcenter CATcenter:PPCHAMELEON_MODULE_MODEL=1 - 1147 Active powerpc ppc4xx - dave PPChameleonEVB CATcenter CATcenter:PPCHAMELEON_MODULE_MODEL=1 -
1143 Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_25 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 - 1148 Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_25 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 -
1144 Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_33 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 - 1149 Active powerpc ppc4xx - dave PPChameleonEVB CATcenter_33 CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 -
1145 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB - Andrea "llandre" Marson <andrea.marson@dave-tech.it> 1150 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB - Andrea "llandre" Marson <andrea.marson@dave-tech.it>
1146 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it> 1151 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
1147 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it> 1152 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_BA_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=0,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
1148 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it> 1153 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
1149 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it> 1154 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_HI_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
1150 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it> 1155 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_25 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
1151 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it> 1156 Active powerpc ppc4xx - dave PPChameleonEVB PPChameleonEVB_ME_33 PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33 Andrea "llandre" Marson <andrea.marson@dave-tech.it>
1152 Active powerpc ppc4xx - esd apc405 APC405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1157 Active powerpc ppc4xx - esd apc405 APC405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1153 Active powerpc ppc4xx - esd ar405 AR405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1158 Active powerpc ppc4xx - esd ar405 AR405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1154 Active powerpc ppc4xx - esd ash405 ASH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1159 Active powerpc ppc4xx - esd ash405 ASH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1155 Active powerpc ppc4xx - esd cms700 CMS700 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1160 Active powerpc ppc4xx - esd cms700 CMS700 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1156 Active powerpc ppc4xx - esd cpci2dp CPCI2DP - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1161 Active powerpc ppc4xx - esd cpci2dp CPCI2DP - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1157 Active powerpc ppc4xx - esd cpci405 CPCI405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1162 Active powerpc ppc4xx - esd cpci405 CPCI405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1158 Active powerpc ppc4xx - esd cpci405 CPCI4052 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1163 Active powerpc ppc4xx - esd cpci405 CPCI4052 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1159 Active powerpc ppc4xx - esd cpci405 CPCI405AB - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1164 Active powerpc ppc4xx - esd cpci405 CPCI405AB - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1160 Active powerpc ppc4xx - esd cpci405 CPCI405DT - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1165 Active powerpc ppc4xx - esd cpci405 CPCI405DT - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1161 Active powerpc ppc4xx - esd cpciiser4 CPCIISER4 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1166 Active powerpc ppc4xx - esd cpciiser4 CPCIISER4 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1162 Active powerpc ppc4xx - esd dp405 DP405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1167 Active powerpc ppc4xx - esd dp405 DP405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1163 Active powerpc ppc4xx - esd du405 DU405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1168 Active powerpc ppc4xx - esd du405 DU405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1164 Active powerpc ppc4xx - esd du440 DU440 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1169 Active powerpc ppc4xx - esd du440 DU440 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1165 Active powerpc ppc4xx - esd hh405 HH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1170 Active powerpc ppc4xx - esd hh405 HH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1166 Active powerpc ppc4xx - esd hub405 HUB405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1171 Active powerpc ppc4xx - esd hub405 HUB405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1167 Active powerpc ppc4xx - esd ocrtc OCRTC - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1172 Active powerpc ppc4xx - esd ocrtc OCRTC - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1168 Active powerpc ppc4xx - esd pci405 PCI405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1173 Active powerpc ppc4xx - esd pci405 PCI405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1169 Active powerpc ppc4xx - esd plu405 PLU405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1174 Active powerpc ppc4xx - esd plu405 PLU405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1170 Active powerpc ppc4xx - esd pmc405 PMC405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1175 Active powerpc ppc4xx - esd pmc405 PMC405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1171 Active powerpc ppc4xx - esd pmc405de PMC405DE - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1176 Active powerpc ppc4xx - esd pmc405de PMC405DE - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1172 Active powerpc ppc4xx - esd pmc440 PMC440 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1177 Active powerpc ppc4xx - esd pmc440 PMC440 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1173 Active powerpc ppc4xx - esd voh405 VOH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1178 Active powerpc ppc4xx - esd voh405 VOH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1174 Active powerpc ppc4xx - esd vom405 VOM405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1179 Active powerpc ppc4xx - esd vom405 VOM405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1175 Active powerpc ppc4xx - esd wuh405 WUH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com> 1180 Active powerpc ppc4xx - esd wuh405 WUH405 - Matthias Fuchs <matthias.fuchs@esd-electronics.com>
1176 Active powerpc ppc4xx - gdsys - dlvision - Dirk Eibach <eibach@gdsys.de> 1181 Active powerpc ppc4xx - gdsys - dlvision - Dirk Eibach <eibach@gdsys.de>
1177 Active powerpc ppc4xx - gdsys - gdppc440etx - Dirk Eibach <eibach@gdsys.de> 1182 Active powerpc ppc4xx - gdsys - gdppc440etx - Dirk Eibach <eibach@gdsys.de>
1178 Active powerpc ppc4xx - gdsys 405ep dlvision-10g - Dirk Eibach <eibach@gdsys.de> 1183 Active powerpc ppc4xx - gdsys 405ep dlvision-10g - Dirk Eibach <eibach@gdsys.de>
1179 Active powerpc ppc4xx - gdsys 405ep io - Dirk Eibach <eibach@gdsys.de> 1184 Active powerpc ppc4xx - gdsys 405ep io - Dirk Eibach <eibach@gdsys.de>
1180 Active powerpc ppc4xx - gdsys 405ep iocon - Dirk Eibach <eibach@gdsys.de> 1185 Active powerpc ppc4xx - gdsys 405ep iocon - Dirk Eibach <eibach@gdsys.de>
1181 Active powerpc ppc4xx - gdsys 405ep neo - Dirk Eibach <eibach@gdsys.de> 1186 Active powerpc ppc4xx - gdsys 405ep neo - Dirk Eibach <eibach@gdsys.de>
1182 Active powerpc ppc4xx - gdsys 405ex io64 - Dirk Eibach <eibach@gdsys.de> 1187 Active powerpc ppc4xx - gdsys 405ex io64 - Dirk Eibach <eibach@gdsys.de>
1183 Active powerpc ppc4xx - gdsys intip devconcenter intip:DEVCONCENTER Dirk Eibach <eibach@gdsys.de> 1188 Active powerpc ppc4xx - gdsys intip devconcenter intip:DEVCONCENTER Dirk Eibach <eibach@gdsys.de>
1184 Active powerpc ppc4xx - gdsys intip intip intip:INTIB Dirk Eibach <eibach@gdsys.de> 1189 Active powerpc ppc4xx - gdsys intip intip intip:INTIB Dirk Eibach <eibach@gdsys.de>
1185 Active powerpc ppc4xx - mosaixtech - icon - Stefan Roese <sr@denx.de> 1190 Active powerpc ppc4xx - mosaixtech - icon - Stefan Roese <sr@denx.de>
1186 Active powerpc ppc4xx - mpl mip405 MIP405 - Denis Peter <d.peter@mpl.ch> 1191 Active powerpc ppc4xx - mpl mip405 MIP405 - Denis Peter <d.peter@mpl.ch>
1187 Active powerpc ppc4xx - mpl mip405 MIP405T MIP405:MIP405T Denis Peter <d.peter@mpl.ch> 1192 Active powerpc ppc4xx - mpl mip405 MIP405T MIP405:MIP405T Denis Peter <d.peter@mpl.ch>
1188 Active powerpc ppc4xx - mpl pip405 PIP405 - Denis Peter <d.peter@mpl.ch> 1193 Active powerpc ppc4xx - mpl pip405 PIP405 - Denis Peter <d.peter@mpl.ch>
1189 Active powerpc ppc4xx - prodrive - alpr - Stefan Roese <sr@denx.de> 1194 Active powerpc ppc4xx - prodrive - alpr - Stefan Roese <sr@denx.de>
1190 Active powerpc ppc4xx - prodrive - p3p440 - Stefan Roese <sr@denx.de> 1195 Active powerpc ppc4xx - prodrive - p3p440 - Stefan Roese <sr@denx.de>
1191 Active powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer (travis.sawyer@sandburst.com> 1196 Active powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer (travis.sawyer@sandburst.com>
1192 Active powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer (travis.sawyer@sandburst.com> 1197 Active powerpc ppc4xx - sandburst metrobox METROBOX - Travis Sawyer (travis.sawyer@sandburst.com>
1193 Active powerpc ppc4xx - xes - xpedite1000 - Peter Tyser <ptyser@xes-inc.com> 1198 Active powerpc ppc4xx - xes - xpedite1000 - Peter Tyser <ptyser@xes-inc.com>
1194 Active powerpc ppc4xx - xilinx ml507 ml507 ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es> 1199 Active powerpc ppc4xx - xilinx ml507 ml507 ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
1195 Active powerpc ppc4xx - xilinx ml507 ml507_flash ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es> 1200 Active powerpc ppc4xx - xilinx ml507 ml507_flash ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o Ricardo Ribalda <ricardo.ribalda@uam.es>
1196 Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000 Ricardo Ribalda <ricardo.ribalda@uam.es> 1201 Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000 Ricardo Ribalda <ricardo.ribalda@uam.es>
1197 Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic_flash xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es> 1202 Active powerpc ppc4xx - xilinx ppc405-generic xilinx-ppc405-generic_flash xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
1198 Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 Ricardo Ribalda <ricardo.ribalda@uam.es> 1203 Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1 Ricardo Ribalda <ricardo.ribalda@uam.es>
1199 Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic_flash xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es> 1204 Active powerpc ppc4xx - xilinx ppc440-generic xilinx-ppc440-generic_flash xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC Ricardo Ribalda <ricardo.ribalda@uam.es>
1200 Active sandbox sandbox - sandbox sandbox sandbox - Simon Glass <sjg@chromium.org> 1205 Active sandbox sandbox - sandbox sandbox sandbox - Simon Glass <sjg@chromium.org>
1201 Active sh sh2 - renesas rsk7203 rsk7203 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1206 Active sh sh2 - renesas rsk7203 rsk7203 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1202 Active sh sh2 - renesas rsk7264 rsk7264 - Phil Edworthy <phil.edworthy@renesas.com> 1207 Active sh sh2 - renesas rsk7264 rsk7264 - Phil Edworthy <phil.edworthy@renesas.com>
1203 Active sh sh2 - renesas rsk7269 rsk7269 - - 1208 Active sh sh2 - renesas rsk7269 rsk7269 - -
1204 Active sh sh3 - - mpr2 mpr2 - Mark Jonas <mark.jonas@de.bosch.com> 1209 Active sh sh3 - - mpr2 mpr2 - Mark Jonas <mark.jonas@de.bosch.com>
1205 Active sh sh3 - - ms7720se ms7720se - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> 1210 Active sh sh3 - - ms7720se ms7720se - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
1206 Active sh sh3 - - shmin shmin - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1211 Active sh sh3 - - shmin shmin - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1207 Active sh sh4 - - espt espt - - 1212 Active sh sh4 - - espt espt - -
1208 Active sh sh4 - - ms7722se ms7722se - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1213 Active sh sh4 - - ms7722se ms7722se - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1209 Active sh sh4 - - ms7750se ms7750se - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1214 Active sh sh4 - - ms7750se ms7750se - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1210 Active sh sh4 - alphaproject ap_sh4a_4a ap_sh4a_4a - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1215 Active sh sh4 - alphaproject ap_sh4a_4a ap_sh4a_4a - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1211 Active sh sh4 - renesas ap325rxa ap325rxa - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1216 Active sh sh4 - renesas ap325rxa ap325rxa - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1212 Active sh sh4 - renesas ecovec ecovec - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1217 Active sh sh4 - renesas ecovec ecovec - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1213 Active sh sh4 - renesas MigoR MigoR - - 1218 Active sh sh4 - renesas MigoR MigoR - -
1214 Active sh sh4 - renesas r0p7734 r0p7734 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1219 Active sh sh4 - renesas r0p7734 r0p7734 - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1215 Active sh sh4 - renesas r2dplus r2dplus - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1220 Active sh sh4 - renesas r2dplus r2dplus - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1216 Active sh sh4 - renesas r7780mp r7780mp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1221 Active sh sh4 - renesas r7780mp r7780mp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1217 Active sh sh4 - renesas sh7752evb sh7752evb - - 1222 Active sh sh4 - renesas sh7752evb sh7752evb - -
1218 Active sh sh4 - renesas sh7753evb sh7753evb - - 1223 Active sh sh4 - renesas sh7753evb sh7753evb - -
1219 Active sh sh4 - renesas sh7757lcr sh7757lcr - - 1224 Active sh sh4 - renesas sh7757lcr sh7757lcr - -
1220 Active sh sh4 - renesas sh7763rdp sh7763rdp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org> 1225 Active sh sh4 - renesas sh7763rdp sh7763rdp - Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>:Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
1221 Active sh sh4 - renesas sh7785lcr sh7785lcr - - 1226 Active sh sh4 - renesas sh7785lcr sh7785lcr - -
1222 Active sh sh4 - renesas sh7785lcr sh7785lcr_32bit sh7785lcr:SH_32BIT=1 - 1227 Active sh sh4 - renesas sh7785lcr sh7785lcr_32bit sh7785lcr:SH_32BIT=1 -
1223 Active sparc leon2 - gaisler - grsim_leon2 - - 1228 Active sparc leon2 - gaisler - grsim_leon2 - -
1224 Active sparc leon3 - gaisler - gr_cpci_ax2000 - - 1229 Active sparc leon3 - gaisler - gr_cpci_ax2000 - -
1225 Active sparc leon3 - gaisler - gr_ep2s60 - - 1230 Active sparc leon3 - gaisler - gr_ep2s60 - -
1226 Active sparc leon3 - gaisler - gr_xc3s_1500 - - 1231 Active sparc leon3 - gaisler - gr_xc3s_1500 - -
1227 Active sparc leon3 - gaisler - grsim - - 1232 Active sparc leon3 - gaisler - grsim - -
1228 Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 - 1233 Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 -
1229 Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de> 1234 Orphan arm arm1136 mx31 - imx31_phycore imx31_phycore_eet imx31_phycore:IMX31_PHYCORE_EET (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
1230 Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de> 1235 Orphan arm arm1136 mx31 freescale - mx31ads - (resigned) Guennadi Liakhovetski <g.liakhovetski@gmx.de>
1231 Orphan arm pxa - - - lubbock - (dead address) Kyle Harris <kharris@nexus-tech.net> 1236 Orphan arm pxa - - - lubbock - (dead address) Kyle Harris <kharris@nexus-tech.net>
1232 Orphan powerpc 74xx_7xx - - evb64260 EVB64260 - - 1237 Orphan powerpc 74xx_7xx - - evb64260 EVB64260 - -
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1246 1251
include/configs/T1040QDS.h
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * See file CREDITS for list of people who contributed to this 4 * See file CREDITS for list of people who contributed to this
5 * project. 5 * project.
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of 9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version. 10 * the License, or (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 * 16 *
17 * You should have received a copy of the GNU General Public License 17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA 20 * MA 02111-1307 USA
21 */ 21 */
22 22
23 #ifndef __CONFIG_H 23 #ifndef __CONFIG_H
24 #define __CONFIG_H 24 #define __CONFIG_H
25 25
26 /* 26 /*
27 * T1040 QDS board configuration file 27 * T1040 QDS board configuration file
28 */ 28 */
29 #define CONFIG_T1040QDS 29 #define CONFIG_T1040QDS
30 #define CONFIG_PHYS_64BIT 30 #define CONFIG_PHYS_64BIT
31 31
32 #ifdef CONFIG_RAMBOOT_PBL 32 #ifdef CONFIG_RAMBOOT_PBL
33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
35 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg 35 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t1040qds/t1040_pbi.cfg
36 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg 36 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t1040qds/t1040_rcw.cfg
37 #endif 37 #endif
38 38
39 /* High Level Configuration Options */ 39 /* High Level Configuration Options */
40 #define CONFIG_BOOKE 40 #define CONFIG_BOOKE
41 #define CONFIG_E500 /* BOOKE e500 family */ 41 #define CONFIG_E500 /* BOOKE e500 family */
42 #define CONFIG_E500MC /* BOOKE e500mc family */ 42 #define CONFIG_E500MC /* BOOKE e500mc family */
43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 43 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
44 #define CONFIG_MP /* support multiple processors */ 44 #define CONFIG_MP /* support multiple processors */
45 45
46 #ifndef CONFIG_SYS_TEXT_BASE 46 #ifndef CONFIG_SYS_TEXT_BASE
47 #define CONFIG_SYS_TEXT_BASE 0xeff40000 47 #define CONFIG_SYS_TEXT_BASE 0xeff40000
48 #endif 48 #endif
49 49
50 #ifndef CONFIG_RESET_VECTOR_ADDRESS 50 #ifndef CONFIG_RESET_VECTOR_ADDRESS
51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 51 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
52 #endif 52 #endif
53 53
54 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 54 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
55 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 55 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
56 #define CONFIG_FSL_IFC /* Enable IFC Support */ 56 #define CONFIG_FSL_IFC /* Enable IFC Support */
57 #define CONFIG_PCI /* Enable PCI/PCIE */ 57 #define CONFIG_PCI /* Enable PCI/PCIE */
58 #define CONFIG_PCI_INDIRECT_BRIDGE 58 #define CONFIG_PCI_INDIRECT_BRIDGE
59 #define CONFIG_PCIE1 /* PCIE controler 1 */ 59 #define CONFIG_PCIE1 /* PCIE controler 1 */
60 #define CONFIG_PCIE2 /* PCIE controler 2 */ 60 #define CONFIG_PCIE2 /* PCIE controler 2 */
61 #define CONFIG_PCIE3 /* PCIE controler 3 */ 61 #define CONFIG_PCIE3 /* PCIE controler 3 */
62 #define CONFIG_PCIE4 /* PCIE controler 4 */ 62 #define CONFIG_PCIE4 /* PCIE controler 4 */
63 63
64 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
65 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
66 66
67 #define CONFIG_FSL_LAW /* Use common FSL init code */ 67 #define CONFIG_FSL_LAW /* Use common FSL init code */
68 68
69 #define CONFIG_ENV_OVERWRITE 69 #define CONFIG_ENV_OVERWRITE
70 70
71 #ifdef CONFIG_SYS_NO_FLASH 71 #ifdef CONFIG_SYS_NO_FLASH
72 #define CONFIG_ENV_IS_NOWHERE 72 #define CONFIG_ENV_IS_NOWHERE
73 #else 73 #else
74 #define CONFIG_FLASH_CFI_DRIVER 74 #define CONFIG_FLASH_CFI_DRIVER
75 #define CONFIG_SYS_FLASH_CFI 75 #define CONFIG_SYS_FLASH_CFI
76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 76 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
77 #endif 77 #endif
78 78
79 #ifndef CONFIG_SYS_NO_FLASH 79 #ifndef CONFIG_SYS_NO_FLASH
80 #if defined(CONFIG_SPIFLASH) 80 #if defined(CONFIG_SPIFLASH)
81 #define CONFIG_SYS_EXTRA_ENV_RELOC 81 #define CONFIG_SYS_EXTRA_ENV_RELOC
82 #define CONFIG_ENV_IS_IN_SPI_FLASH 82 #define CONFIG_ENV_IS_IN_SPI_FLASH
83 #define CONFIG_ENV_SPI_BUS 0 83 #define CONFIG_ENV_SPI_BUS 0
84 #define CONFIG_ENV_SPI_CS 0 84 #define CONFIG_ENV_SPI_CS 0
85 #define CONFIG_ENV_SPI_MAX_HZ 10000000 85 #define CONFIG_ENV_SPI_MAX_HZ 10000000
86 #define CONFIG_ENV_SPI_MODE 0 86 #define CONFIG_ENV_SPI_MODE 0
87 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 87 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
88 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 88 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
89 #define CONFIG_ENV_SECT_SIZE 0x10000 89 #define CONFIG_ENV_SECT_SIZE 0x10000
90 #elif defined(CONFIG_SDCARD) 90 #elif defined(CONFIG_SDCARD)
91 #define CONFIG_SYS_EXTRA_ENV_RELOC 91 #define CONFIG_SYS_EXTRA_ENV_RELOC
92 #define CONFIG_ENV_IS_IN_MMC 92 #define CONFIG_ENV_IS_IN_MMC
93 #define CONFIG_SYS_MMC_ENV_DEV 0 93 #define CONFIG_SYS_MMC_ENV_DEV 0
94 #define CONFIG_ENV_SIZE 0x2000 94 #define CONFIG_ENV_SIZE 0x2000
95 #define CONFIG_ENV_OFFSET (512 * 1658) 95 #define CONFIG_ENV_OFFSET (512 * 1658)
96 #elif defined(CONFIG_NAND) 96 #elif defined(CONFIG_NAND)
97 #define CONFIG_SYS_EXTRA_ENV_RELOC 97 #define CONFIG_SYS_EXTRA_ENV_RELOC
98 #define CONFIG_ENV_IS_IN_NAND 98 #define CONFIG_ENV_IS_IN_NAND
99 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 99 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
100 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 100 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
101 #else 101 #else
102 #define CONFIG_ENV_IS_IN_FLASH 102 #define CONFIG_ENV_IS_IN_FLASH
103 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 103 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
104 #define CONFIG_ENV_SIZE 0x2000 104 #define CONFIG_ENV_SIZE 0x2000
105 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 105 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
106 #endif 106 #endif
107 #else /* CONFIG_SYS_NO_FLASH */ 107 #else /* CONFIG_SYS_NO_FLASH */
108 #define CONFIG_ENV_SIZE 0x2000 108 #define CONFIG_ENV_SIZE 0x2000
109 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 109 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
110 #endif 110 #endif
111 111
112 #ifndef __ASSEMBLY__ 112 #ifndef __ASSEMBLY__
113 unsigned long get_board_sys_clk(void); 113 unsigned long get_board_sys_clk(void);
114 unsigned long get_board_ddr_clk(void); 114 unsigned long get_board_ddr_clk(void);
115 #endif 115 #endif
116 116
117 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 117 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
118 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 118 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
119 119
120 /* 120 /*
121 * These can be toggled for performance analysis, otherwise use default. 121 * These can be toggled for performance analysis, otherwise use default.
122 */ 122 */
123 #define CONFIG_SYS_CACHE_STASHING 123 #define CONFIG_SYS_CACHE_STASHING
124 #define CONFIG_BACKSIDE_L2_CACHE 124 #define CONFIG_BACKSIDE_L2_CACHE
125 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 125 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
126 #define CONFIG_BTB /* toggle branch predition */ 126 #define CONFIG_BTB /* toggle branch predition */
127 #define CONFIG_DDR_ECC 127 #define CONFIG_DDR_ECC
128 #ifdef CONFIG_DDR_ECC 128 #ifdef CONFIG_DDR_ECC
129 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 129 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
130 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 130 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
131 #endif 131 #endif
132 132
133 #define CONFIG_ENABLE_36BIT_PHYS 133 #define CONFIG_ENABLE_36BIT_PHYS
134 134
135 #define CONFIG_ADDR_MAP 135 #define CONFIG_ADDR_MAP
136 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 136 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
137 137
138 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 138 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
139 #define CONFIG_SYS_MEMTEST_END 0x00400000 139 #define CONFIG_SYS_MEMTEST_END 0x00400000
140 #define CONFIG_SYS_ALT_MEMTEST 140 #define CONFIG_SYS_ALT_MEMTEST
141 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 141 #define CONFIG_PANIC_HANG /* do not reset board on panic */
142 142
143 /* 143 /*
144 * Config the L3 Cache as L3 SRAM 144 * Config the L3 Cache as L3 SRAM
145 */ 145 */
146 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 146 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
147 147
148 #define CONFIG_SYS_DCSRBAR 0xf0000000 148 #define CONFIG_SYS_DCSRBAR 0xf0000000
149 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 149 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
150 150
151 /* EEPROM */ 151 /* EEPROM */
152 #define CONFIG_ID_EEPROM 152 #define CONFIG_ID_EEPROM
153 #define CONFIG_SYS_I2C_EEPROM_NXID 153 #define CONFIG_SYS_I2C_EEPROM_NXID
154 #define CONFIG_SYS_EEPROM_BUS_NUM 0 154 #define CONFIG_SYS_EEPROM_BUS_NUM 0
155 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 155 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
157 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 157 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
158 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 158 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
159 159
160 /* 160 /*
161 * DDR Setup 161 * DDR Setup
162 */ 162 */
163 #define CONFIG_VERY_BIG_RAM 163 #define CONFIG_VERY_BIG_RAM
164 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 164 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
165 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 165 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
166 166
167 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 167 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
168 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 168 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
169 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 169 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
170 170
171 #define CONFIG_DDR_SPD 171 #define CONFIG_DDR_SPD
172 #define CONFIG_SYS_FSL_DDR3 172 #define CONFIG_SYS_FSL_DDR3
173 #define CONFIG_FSL_DDR_INTERACTIVE 173 #define CONFIG_FSL_DDR_INTERACTIVE
174 174
175 #define CONFIG_SYS_SPD_BUS_NUM 0 175 #define CONFIG_SYS_SPD_BUS_NUM 0
176 #define SPD_EEPROM_ADDRESS 0x51 176 #define SPD_EEPROM_ADDRESS 0x51
177 177
178 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 178 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
179 179
180 /* 180 /*
181 * IFC Definitions 181 * IFC Definitions
182 */ 182 */
183 #define CONFIG_SYS_FLASH_BASE 0xe0000000 183 #define CONFIG_SYS_FLASH_BASE 0xe0000000
184 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 184 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
185 185
186 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 186 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
187 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 187 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
188 + 0x8000000) | \ 188 + 0x8000000) | \
189 CSPR_PORT_SIZE_16 | \ 189 CSPR_PORT_SIZE_16 | \
190 CSPR_MSEL_NOR | \ 190 CSPR_MSEL_NOR | \
191 CSPR_V) 191 CSPR_V)
192 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 192 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
193 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 193 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
194 CSPR_PORT_SIZE_16 | \ 194 CSPR_PORT_SIZE_16 | \
195 CSPR_MSEL_NOR | \ 195 CSPR_MSEL_NOR | \
196 CSPR_V) 196 CSPR_V)
197 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 197 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
198 /* NOR Flash Timing Params */ 198 /* NOR Flash Timing Params */
199 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 199 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
200 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 200 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
201 FTIM0_NOR_TEADC(0x5) | \ 201 FTIM0_NOR_TEADC(0x5) | \
202 FTIM0_NOR_TEAHC(0x5)) 202 FTIM0_NOR_TEAHC(0x5))
203 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 203 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
204 FTIM1_NOR_TRAD_NOR(0x1A) |\ 204 FTIM1_NOR_TRAD_NOR(0x1A) |\
205 FTIM1_NOR_TSEQRAD_NOR(0x13)) 205 FTIM1_NOR_TSEQRAD_NOR(0x13))
206 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 206 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
207 FTIM2_NOR_TCH(0x4) | \ 207 FTIM2_NOR_TCH(0x4) | \
208 FTIM2_NOR_TWPH(0x0E) | \ 208 FTIM2_NOR_TWPH(0x0E) | \
209 FTIM2_NOR_TWP(0x1c)) 209 FTIM2_NOR_TWP(0x1c))
210 #define CONFIG_SYS_NOR_FTIM3 0x0 210 #define CONFIG_SYS_NOR_FTIM3 0x0
211 211
212 #define CONFIG_SYS_FLASH_QUIET_TEST 212 #define CONFIG_SYS_FLASH_QUIET_TEST
213 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 213 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
214 214
215 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 215 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
216 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 216 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
217 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 217 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
218 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 218 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
219 219
220 #define CONFIG_SYS_FLASH_EMPTY_INFO 220 #define CONFIG_SYS_FLASH_EMPTY_INFO
221 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 221 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
222 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 222 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
223 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 223 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
224 #define QIXIS_BASE 0xffdf0000 224 #define QIXIS_BASE 0xffdf0000
225 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 225 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
226 #define QIXIS_LBMAP_SWITCH 0x06 226 #define QIXIS_LBMAP_SWITCH 0x06
227 #define QIXIS_LBMAP_MASK 0x0f 227 #define QIXIS_LBMAP_MASK 0x0f
228 #define QIXIS_LBMAP_SHIFT 0 228 #define QIXIS_LBMAP_SHIFT 0
229 #define QIXIS_LBMAP_DFLTBANK 0x00 229 #define QIXIS_LBMAP_DFLTBANK 0x00
230 #define QIXIS_LBMAP_ALTBANK 0x04 230 #define QIXIS_LBMAP_ALTBANK 0x04
231 #define QIXIS_RST_CTL_RESET 0x31 231 #define QIXIS_RST_CTL_RESET 0x31
232 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 232 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
233 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 233 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
234 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 234 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
235 #define QIXIS_RST_FORCE_MEM 0x01 235 #define QIXIS_RST_FORCE_MEM 0x01
236 236
237 #define CONFIG_SYS_CSPR3_EXT (0xf) 237 #define CONFIG_SYS_CSPR3_EXT (0xf)
238 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 238 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
239 | CSPR_PORT_SIZE_8 \ 239 | CSPR_PORT_SIZE_8 \
240 | CSPR_MSEL_GPCM \ 240 | CSPR_MSEL_GPCM \
241 | CSPR_V) 241 | CSPR_V)
242 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 242 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
243 #define CONFIG_SYS_CSOR3 0x0 243 #define CONFIG_SYS_CSOR3 0x0
244 /* QIXIS Timing parameters for IFC CS3 */ 244 /* QIXIS Timing parameters for IFC CS3 */
245 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 245 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
246 FTIM0_GPCM_TEADC(0x0e) | \ 246 FTIM0_GPCM_TEADC(0x0e) | \
247 FTIM0_GPCM_TEAHC(0x0e)) 247 FTIM0_GPCM_TEAHC(0x0e))
248 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 248 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
249 FTIM1_GPCM_TRAD(0x3f)) 249 FTIM1_GPCM_TRAD(0x3f))
250 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 250 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
251 FTIM2_GPCM_TCH(0x8) | \ 251 FTIM2_GPCM_TCH(0x8) | \
252 FTIM2_GPCM_TWP(0x1f)) 252 FTIM2_GPCM_TWP(0x1f))
253 #define CONFIG_SYS_CS3_FTIM3 0x0 253 #define CONFIG_SYS_CS3_FTIM3 0x0
254 254
255 #define CONFIG_NAND_FSL_IFC 255 #define CONFIG_NAND_FSL_IFC
256 #define CONFIG_SYS_NAND_BASE 0xff800000 256 #define CONFIG_SYS_NAND_BASE 0xff800000
257 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 257 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
258 258
259 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 259 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
260 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 260 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
261 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 261 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
262 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 262 | CSPR_MSEL_NAND /* MSEL = NAND */ \
263 | CSPR_V) 263 | CSPR_V)
264 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 264 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
265 265
266 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 266 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
267 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 267 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
268 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 268 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
269 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 269 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
270 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 270 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
271 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 271 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
272 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 272 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
273 273
274 #define CONFIG_SYS_NAND_ONFI_DETECTION 274 #define CONFIG_SYS_NAND_ONFI_DETECTION
275 275
276 /* ONFI NAND Flash mode0 Timing Params */ 276 /* ONFI NAND Flash mode0 Timing Params */
277 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 277 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
278 FTIM0_NAND_TWP(0x18) | \ 278 FTIM0_NAND_TWP(0x18) | \
279 FTIM0_NAND_TWCHT(0x07) | \ 279 FTIM0_NAND_TWCHT(0x07) | \
280 FTIM0_NAND_TWH(0x0a)) 280 FTIM0_NAND_TWH(0x0a))
281 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 281 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
282 FTIM1_NAND_TWBE(0x39) | \ 282 FTIM1_NAND_TWBE(0x39) | \
283 FTIM1_NAND_TRR(0x0e) | \ 283 FTIM1_NAND_TRR(0x0e) | \
284 FTIM1_NAND_TRP(0x18)) 284 FTIM1_NAND_TRP(0x18))
285 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 285 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
286 FTIM2_NAND_TREH(0x0a) | \ 286 FTIM2_NAND_TREH(0x0a) | \
287 FTIM2_NAND_TWHRE(0x1e)) 287 FTIM2_NAND_TWHRE(0x1e))
288 #define CONFIG_SYS_NAND_FTIM3 0x0 288 #define CONFIG_SYS_NAND_FTIM3 0x0
289 289
290 #define CONFIG_SYS_NAND_DDR_LAW 11 290 #define CONFIG_SYS_NAND_DDR_LAW 11
291 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 291 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
292 #define CONFIG_SYS_MAX_NAND_DEVICE 1 292 #define CONFIG_SYS_MAX_NAND_DEVICE 1
293 #define CONFIG_MTD_NAND_VERIFY_WRITE 293 #define CONFIG_MTD_NAND_VERIFY_WRITE
294 #define CONFIG_CMD_NAND 294 #define CONFIG_CMD_NAND
295 295
296 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 296 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
297 297
298 #if defined(CONFIG_NAND) 298 #if defined(CONFIG_NAND)
299 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 299 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
300 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 300 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
301 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 301 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
302 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 302 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
303 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 303 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
304 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 304 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
305 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 305 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
306 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 306 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
307 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT 307 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
308 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR 308 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
309 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 309 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
310 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 310 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
311 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 311 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
312 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 312 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
313 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 313 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
314 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 314 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
315 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT 315 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
316 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR 316 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
317 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 317 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
318 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 318 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
319 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 319 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
320 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 320 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
321 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 321 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
322 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 322 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
323 #else 323 #else
324 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 324 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
325 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 325 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
326 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 326 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
327 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 327 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
328 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 328 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
329 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 329 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
330 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 330 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
331 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 331 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
332 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 332 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
333 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 333 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
334 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 334 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
335 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 335 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
336 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 336 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
337 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 337 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
338 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 338 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
339 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 339 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
340 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 340 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
341 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 341 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
342 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 342 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
343 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 343 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
344 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 344 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
345 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 345 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
346 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 346 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
347 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 347 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
348 #endif 348 #endif
349 349
350 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 350 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
351 351
352 #if defined(CONFIG_RAMBOOT_PBL) 352 #if defined(CONFIG_RAMBOOT_PBL)
353 #define CONFIG_SYS_RAMBOOT 353 #define CONFIG_SYS_RAMBOOT
354 #endif 354 #endif
355 355
356 #define CONFIG_BOARD_EARLY_INIT_R 356 #define CONFIG_BOARD_EARLY_INIT_R
357 #define CONFIG_MISC_INIT_R 357 #define CONFIG_MISC_INIT_R
358 358
359 #define CONFIG_HWCONFIG 359 #define CONFIG_HWCONFIG
360 360
361 /* define to use L1 as initial stack */ 361 /* define to use L1 as initial stack */
362 #define CONFIG_L1_INIT_RAM 362 #define CONFIG_L1_INIT_RAM
363 #define CONFIG_SYS_INIT_RAM_LOCK 363 #define CONFIG_SYS_INIT_RAM_LOCK
364 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 364 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
365 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 365 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
366 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 366 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
367 /* The assembler doesn't like typecast */ 367 /* The assembler doesn't like typecast */
368 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 368 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
369 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 369 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
370 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 370 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
371 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 371 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
372 372
373 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 373 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
374 GENERATED_GBL_DATA_SIZE) 374 GENERATED_GBL_DATA_SIZE)
375 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 375 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
376 376
377 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 377 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
378 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 378 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
379 379
380 /* Serial Port - controlled on board with jumper J8 380 /* Serial Port - controlled on board with jumper J8
381 * open - index 2 381 * open - index 2
382 * shorted - index 1 382 * shorted - index 1
383 */ 383 */
384 #define CONFIG_CONS_INDEX 1 384 #define CONFIG_CONS_INDEX 1
385 #define CONFIG_SYS_NS16550 385 #define CONFIG_SYS_NS16550
386 #define CONFIG_SYS_NS16550_SERIAL 386 #define CONFIG_SYS_NS16550_SERIAL
387 #define CONFIG_SYS_NS16550_REG_SIZE 1 387 #define CONFIG_SYS_NS16550_REG_SIZE 1
388 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 388 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
389 389
390 #define CONFIG_SYS_BAUDRATE_TABLE \ 390 #define CONFIG_SYS_BAUDRATE_TABLE \
391 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 391 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
392 392
393 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 393 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
394 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 394 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
395 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 395 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
396 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 396 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
397 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 397 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
398 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 398 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
399 399
400 /* Use the HUSH parser */ 400 /* Use the HUSH parser */
401 #define CONFIG_SYS_HUSH_PARSER 401 #define CONFIG_SYS_HUSH_PARSER
402 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 402 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
403 403
404 /* Video */
405 #define CONFIG_FSL_DIU_FB
406 #ifdef CONFIG_FSL_DIU_FB
407 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
408 #define CONFIG_VIDEO
409 #define CONFIG_CMD_BMP
410 #define CONFIG_CFB_CONSOLE
411 #define CONFIG_VIDEO_SW_CURSOR
412 #define CONFIG_VGA_AS_SINGLE_DEVICE
413 #define CONFIG_VIDEO_LOGO
414 #define CONFIG_VIDEO_BMP_LOGO
415 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
416 /*
417 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
418 * disable empty flash sector detection, which is I/O-intensive.
419 */
420 #undef CONFIG_SYS_FLASH_EMPTY_INFO
421 #endif
422
404 /* pass open firmware flat tree */ 423 /* pass open firmware flat tree */
405 #define CONFIG_OF_LIBFDT 424 #define CONFIG_OF_LIBFDT
406 #define CONFIG_OF_BOARD_SETUP 425 #define CONFIG_OF_BOARD_SETUP
407 #define CONFIG_OF_STDOUT_VIA_ALIAS 426 #define CONFIG_OF_STDOUT_VIA_ALIAS
408 427
409 /* new uImage format support */ 428 /* new uImage format support */
410 #define CONFIG_FIT 429 #define CONFIG_FIT
411 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 430 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
412 431
413 /* I2C */ 432 /* I2C */
414 #define CONFIG_SYS_I2C 433 #define CONFIG_SYS_I2C
415 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 434 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
416 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ 435 #define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
417 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 436 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
418 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ 437 #define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
419 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 438 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
420 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 439 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
421 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 440 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
422 441
423 #define I2C_MUX_PCA_ADDR 0x77 442 #define I2C_MUX_PCA_ADDR 0x77
424 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 443 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
425 444
426 445
427 /* I2C bus multiplexer */ 446 /* I2C bus multiplexer */
428 #define I2C_MUX_CH_DEFAULT 0x8 447 #define I2C_MUX_CH_DEFAULT 0x8
448 #define I2C_MUX_CH_DIU 0xC
429 449
450 /* LDI/DVI Encoder for display */
451 #define CONFIG_SYS_I2C_LDI_ADDR 0x38
452 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
453
430 /* 454 /*
431 * RTC configuration 455 * RTC configuration
432 */ 456 */
433 #define RTC 457 #define RTC
434 #define CONFIG_RTC_DS3231 1 458 #define CONFIG_RTC_DS3231 1
435 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 459 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
436 460
437 /* 461 /*
438 * eSPI - Enhanced SPI 462 * eSPI - Enhanced SPI
439 */ 463 */
440 #define CONFIG_FSL_ESPI 464 #define CONFIG_FSL_ESPI
441 #define CONFIG_SPI_FLASH 465 #define CONFIG_SPI_FLASH
442 #define CONFIG_SPI_FLASH_STMICRO 466 #define CONFIG_SPI_FLASH_STMICRO
443 #define CONFIG_SPI_FLASH_SST 467 #define CONFIG_SPI_FLASH_SST
444 #define CONFIG_SPI_FLASH_EON 468 #define CONFIG_SPI_FLASH_EON
445 #define CONFIG_CMD_SF 469 #define CONFIG_CMD_SF
446 #define CONFIG_SF_DEFAULT_SPEED 10000000 470 #define CONFIG_SF_DEFAULT_SPEED 10000000
447 #define CONFIG_SF_DEFAULT_MODE 0 471 #define CONFIG_SF_DEFAULT_MODE 0
448 472
449 /* 473 /*
450 * General PCI 474 * General PCI
451 * Memory space is mapped 1-1, but I/O space must start from 0. 475 * Memory space is mapped 1-1, but I/O space must start from 0.
452 */ 476 */
453 477
454 #ifdef CONFIG_PCI 478 #ifdef CONFIG_PCI
455 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 479 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
456 #ifdef CONFIG_PCIE1 480 #ifdef CONFIG_PCIE1
457 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 481 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
458 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 482 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
459 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 483 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
460 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 484 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
461 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 485 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
462 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 486 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
463 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 487 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
464 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 488 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
465 #endif 489 #endif
466 490
467 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 491 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
468 #ifdef CONFIG_PCIE2 492 #ifdef CONFIG_PCIE2
469 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 493 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
470 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 494 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
471 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 495 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
472 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 496 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
473 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 497 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
474 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 498 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
475 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 499 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
476 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 500 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
477 #endif 501 #endif
478 502
479 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 503 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
480 #ifdef CONFIG_PCIE3 504 #ifdef CONFIG_PCIE3
481 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 505 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
482 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 506 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
483 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 507 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
484 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 508 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
485 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 509 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
486 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 510 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
487 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 511 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
488 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 512 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
489 #endif 513 #endif
490 514
491 /* controller 4, Base address 203000 */ 515 /* controller 4, Base address 203000 */
492 #ifdef CONFIG_PCIE4 516 #ifdef CONFIG_PCIE4
493 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 517 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
494 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 518 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
495 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 519 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
496 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 520 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
497 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 521 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
498 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 522 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
499 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 523 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
500 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 524 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
501 #endif 525 #endif
502 526
503 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 527 #define CONFIG_PCI_PNP /* do pci plug-and-play */
504 #define CONFIG_E1000 528 #define CONFIG_E1000
505 529
506 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 530 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
507 #define CONFIG_DOS_PARTITION 531 #define CONFIG_DOS_PARTITION
508 #endif /* CONFIG_PCI */ 532 #endif /* CONFIG_PCI */
509 533
510 /* SATA */ 534 /* SATA */
511 #define CONFIG_FSL_SATA_V2 535 #define CONFIG_FSL_SATA_V2
512 #ifdef CONFIG_FSL_SATA_V2 536 #ifdef CONFIG_FSL_SATA_V2
513 #define CONFIG_LIBATA 537 #define CONFIG_LIBATA
514 #define CONFIG_FSL_SATA 538 #define CONFIG_FSL_SATA
515 539
516 #define CONFIG_SYS_SATA_MAX_DEVICE 2 540 #define CONFIG_SYS_SATA_MAX_DEVICE 2
517 #define CONFIG_SATA1 541 #define CONFIG_SATA1
518 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 542 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
519 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 543 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
520 #define CONFIG_SATA2 544 #define CONFIG_SATA2
521 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 545 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
522 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 546 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
523 547
524 #define CONFIG_LBA48 548 #define CONFIG_LBA48
525 #define CONFIG_CMD_SATA 549 #define CONFIG_CMD_SATA
526 #define CONFIG_DOS_PARTITION 550 #define CONFIG_DOS_PARTITION
527 #define CONFIG_CMD_EXT2 551 #define CONFIG_CMD_EXT2
528 #endif 552 #endif
529 553
530 /* 554 /*
531 * USB 555 * USB
532 */ 556 */
533 #define CONFIG_HAS_FSL_DR_USB 557 #define CONFIG_HAS_FSL_DR_USB
534 558
535 #ifdef CONFIG_HAS_FSL_DR_USB 559 #ifdef CONFIG_HAS_FSL_DR_USB
536 #define CONFIG_USB_EHCI 560 #define CONFIG_USB_EHCI
537 561
538 #ifdef CONFIG_USB_EHCI 562 #ifdef CONFIG_USB_EHCI
539 #define CONFIG_CMD_USB 563 #define CONFIG_CMD_USB
540 #define CONFIG_USB_STORAGE 564 #define CONFIG_USB_STORAGE
541 #define CONFIG_USB_EHCI_FSL 565 #define CONFIG_USB_EHCI_FSL
542 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 566 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
543 #define CONFIG_CMD_EXT2 567 #define CONFIG_CMD_EXT2
544 #endif 568 #endif
545 #endif 569 #endif
546 570
547 #define CONFIG_MMC 571 #define CONFIG_MMC
548 572
549 #ifdef CONFIG_MMC 573 #ifdef CONFIG_MMC
550 #define CONFIG_FSL_ESDHC 574 #define CONFIG_FSL_ESDHC
551 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 575 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
552 #define CONFIG_CMD_MMC 576 #define CONFIG_CMD_MMC
553 #define CONFIG_GENERIC_MMC 577 #define CONFIG_GENERIC_MMC
554 #define CONFIG_CMD_EXT2 578 #define CONFIG_CMD_EXT2
555 #define CONFIG_CMD_FAT 579 #define CONFIG_CMD_FAT
556 #define CONFIG_DOS_PARTITION 580 #define CONFIG_DOS_PARTITION
557 #endif 581 #endif
558 582
559 /* Qman/Bman */ 583 /* Qman/Bman */
560 #ifndef CONFIG_NOBQFMAN 584 #ifndef CONFIG_NOBQFMAN
561 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 585 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
562 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 586 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
563 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 587 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
564 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 588 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
565 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 589 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
566 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 590 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
567 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 591 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
568 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 592 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
569 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 593 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
570 594
571 #define CONFIG_SYS_DPAA_FMAN 595 #define CONFIG_SYS_DPAA_FMAN
572 #define CONFIG_SYS_DPAA_PME 596 #define CONFIG_SYS_DPAA_PME
573 597
574 /* Default address of microcode for the Linux Fman driver */ 598 /* Default address of microcode for the Linux Fman driver */
575 #if defined(CONFIG_SPIFLASH) 599 #if defined(CONFIG_SPIFLASH)
576 /* 600 /*
577 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 601 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
578 * env, so we got 0x110000. 602 * env, so we got 0x110000.
579 */ 603 */
580 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 604 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
581 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 605 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
582 #elif defined(CONFIG_SDCARD) 606 #elif defined(CONFIG_SDCARD)
583 /* 607 /*
584 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 608 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
585 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 609 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
586 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 610 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
587 */ 611 */
588 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 612 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
589 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) 613 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
590 #elif defined(CONFIG_NAND) 614 #elif defined(CONFIG_NAND)
591 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 615 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
592 #define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 616 #define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
593 #else 617 #else
594 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 618 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
595 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 619 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
596 #endif 620 #endif
597 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 621 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
598 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 622 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
599 #endif /* CONFIG_NOBQFMAN */ 623 #endif /* CONFIG_NOBQFMAN */
600 624
601 #ifdef CONFIG_SYS_DPAA_FMAN 625 #ifdef CONFIG_SYS_DPAA_FMAN
602 #define CONFIG_FMAN_ENET 626 #define CONFIG_FMAN_ENET
603 #define CONFIG_PHYLIB_10G 627 #define CONFIG_PHYLIB_10G
604 #define CONFIG_PHY_VITESSE 628 #define CONFIG_PHY_VITESSE
605 #define CONFIG_PHY_REALTEK 629 #define CONFIG_PHY_REALTEK
606 #define CONFIG_PHY_TERANETICS 630 #define CONFIG_PHY_TERANETICS
607 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 631 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
608 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 632 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
609 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 633 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
610 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 634 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
611 #endif 635 #endif
612 636
613 #ifdef CONFIG_FMAN_ENET 637 #ifdef CONFIG_FMAN_ENET
614 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 638 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
615 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 639 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
616 640
617 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 641 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
618 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 642 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
619 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 643 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
620 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 644 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
621 645
622 #define CONFIG_MII /* MII PHY management */ 646 #define CONFIG_MII /* MII PHY management */
623 #define CONFIG_ETHPRIME "FM1@DTSEC1" 647 #define CONFIG_ETHPRIME "FM1@DTSEC1"
624 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 648 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
625 #endif 649 #endif
626 650
627 /* 651 /*
628 * Environment 652 * Environment
629 */ 653 */
630 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 654 #define CONFIG_LOADS_ECHO /* echo on for serial download */
631 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 655 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
632 656
633 /* 657 /*
634 * Command line configuration. 658 * Command line configuration.
635 */ 659 */
636 #include <config_cmd_default.h> 660 #include <config_cmd_default.h>
637 661
638 #define CONFIG_CMD_DATE 662 #define CONFIG_CMD_DATE
639 #define CONFIG_CMD_DHCP 663 #define CONFIG_CMD_DHCP
640 #define CONFIG_CMD_EEPROM 664 #define CONFIG_CMD_EEPROM
641 #define CONFIG_CMD_ELF 665 #define CONFIG_CMD_ELF
642 #define CONFIG_CMD_ERRATA 666 #define CONFIG_CMD_ERRATA
643 #define CONFIG_CMD_GREPENV 667 #define CONFIG_CMD_GREPENV
644 #define CONFIG_CMD_IRQ 668 #define CONFIG_CMD_IRQ
645 #define CONFIG_CMD_I2C 669 #define CONFIG_CMD_I2C
646 #define CONFIG_CMD_MII 670 #define CONFIG_CMD_MII
647 #define CONFIG_CMD_PING 671 #define CONFIG_CMD_PING
648 #define CONFIG_CMD_REGINFO 672 #define CONFIG_CMD_REGINFO
649 #define CONFIG_CMD_SETEXPR 673 #define CONFIG_CMD_SETEXPR
650 674
651 #ifdef CONFIG_PCI 675 #ifdef CONFIG_PCI
652 #define CONFIG_CMD_PCI 676 #define CONFIG_CMD_PCI
653 #define CONFIG_CMD_NET 677 #define CONFIG_CMD_NET
654 #endif 678 #endif
655 679
656 /* 680 /*
657 * Miscellaneous configurable options 681 * Miscellaneous configurable options
658 */ 682 */
659 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 683 #define CONFIG_SYS_LONGHELP /* undef to save memory */
660 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 684 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
661 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 685 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
662 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 686 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
663 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 687 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
664 #ifdef CONFIG_CMD_KGDB 688 #ifdef CONFIG_CMD_KGDB
665 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 689 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
666 #else 690 #else
667 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 691 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
668 #endif 692 #endif
669 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 693 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
670 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 694 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
671 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 695 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
672 696
673 /* 697 /*
674 * For booting Linux, the board info and command line data 698 * For booting Linux, the board info and command line data
675 * have to be in the first 64 MB of memory, since this is 699 * have to be in the first 64 MB of memory, since this is
676 * the maximum mapped by the Linux kernel during initialization. 700 * the maximum mapped by the Linux kernel during initialization.
677 */ 701 */
678 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 702 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
679 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 703 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
680 704
681 #ifdef CONFIG_CMD_KGDB 705 #ifdef CONFIG_CMD_KGDB
682 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 706 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
683 #endif 707 #endif
684 708
685 /* 709 /*
686 * Environment Configuration 710 * Environment Configuration
687 */ 711 */
688 #define CONFIG_ROOTPATH "/opt/nfsroot" 712 #define CONFIG_ROOTPATH "/opt/nfsroot"
689 #define CONFIG_BOOTFILE "uImage" 713 #define CONFIG_BOOTFILE "uImage"
690 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 714 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
691 715
692 /* default location for tftp and bootm */ 716 /* default location for tftp and bootm */
693 #define CONFIG_LOADADDR 1000000 717 #define CONFIG_LOADADDR 1000000
694 718
695 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 719 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
696 720
697 #define CONFIG_BAUDRATE 115200 721 #define CONFIG_BAUDRATE 115200
698 722
699 #define __USB_PHY_TYPE utmi 723 #define __USB_PHY_TYPE utmi
700 724
701 #define CONFIG_EXTRA_ENV_SETTINGS \ 725 #define CONFIG_EXTRA_ENV_SETTINGS \
702 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 726 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
703 "bank_intlv=cs0_cs1;" \ 727 "bank_intlv=cs0_cs1;" \
704 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 728 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
705 "netdev=eth0\0" \ 729 "netdev=eth0\0" \
730 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
706 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 731 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
707 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 732 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
708 "tftpflash=tftpboot $loadaddr $uboot && " \ 733 "tftpflash=tftpboot $loadaddr $uboot && " \
709 "protect off $ubootaddr +$filesize && " \ 734 "protect off $ubootaddr +$filesize && " \
710 "erase $ubootaddr +$filesize && " \ 735 "erase $ubootaddr +$filesize && " \
711 "cp.b $loadaddr $ubootaddr $filesize && " \ 736 "cp.b $loadaddr $ubootaddr $filesize && " \
712 "protect on $ubootaddr +$filesize && " \ 737 "protect on $ubootaddr +$filesize && " \
713 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 738 "cmp.b $loadaddr $ubootaddr $filesize\0" \
714 "consoledev=ttyS0\0" \ 739 "consoledev=ttyS0\0" \
715 "ramdiskaddr=2000000\0" \ 740 "ramdiskaddr=2000000\0" \
716 "ramdiskfile=t1040qds/ramdisk.uboot\0" \ 741 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
717 "fdtaddr=c00000\0" \ 742 "fdtaddr=c00000\0" \
718 "fdtfile=t1040qds/t1040qds.dtb\0" \ 743 "fdtfile=t1040qds/t1040qds.dtb\0" \
719 "bdev=sda3\0" \ 744 "bdev=sda3\0" \
720 "c=ffe\0" 745 "c=ffe\0"
721 746
722 #define CONFIG_LINUX \ 747 #define CONFIG_LINUX \
723 "setenv bootargs root=/dev/ram rw " \ 748 "setenv bootargs root=/dev/ram rw " \
724 "console=$consoledev,$baudrate $othbootargs;" \ 749 "console=$consoledev,$baudrate $othbootargs;" \
725 "setenv ramdiskaddr 0x02000000;" \ 750 "setenv ramdiskaddr 0x02000000;" \
726 "setenv fdtaddr 0x00c00000;" \ 751 "setenv fdtaddr 0x00c00000;" \
727 "setenv loadaddr 0x1000000;" \ 752 "setenv loadaddr 0x1000000;" \
728 "bootm $loadaddr $ramdiskaddr $fdtaddr" 753 "bootm $loadaddr $ramdiskaddr $fdtaddr"
729 754
730 #define CONFIG_HDBOOT \ 755 #define CONFIG_HDBOOT \
731 "setenv bootargs root=/dev/$bdev rw " \ 756 "setenv bootargs root=/dev/$bdev rw " \
732 "console=$consoledev,$baudrate $othbootargs;" \ 757 "console=$consoledev,$baudrate $othbootargs;" \
733 "tftp $loadaddr $bootfile;" \ 758 "tftp $loadaddr $bootfile;" \
734 "tftp $fdtaddr $fdtfile;" \ 759 "tftp $fdtaddr $fdtfile;" \
735 "bootm $loadaddr - $fdtaddr" 760 "bootm $loadaddr - $fdtaddr"
736 761
737 #define CONFIG_NFSBOOTCOMMAND \ 762 #define CONFIG_NFSBOOTCOMMAND \
738 "setenv bootargs root=/dev/nfs rw " \ 763 "setenv bootargs root=/dev/nfs rw " \
739 "nfsroot=$serverip:$rootpath " \ 764 "nfsroot=$serverip:$rootpath " \
740 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 765 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
741 "console=$consoledev,$baudrate $othbootargs;" \ 766 "console=$consoledev,$baudrate $othbootargs;" \
742 "tftp $loadaddr $bootfile;" \ 767 "tftp $loadaddr $bootfile;" \
743 "tftp $fdtaddr $fdtfile;" \ 768 "tftp $fdtaddr $fdtfile;" \
744 "bootm $loadaddr - $fdtaddr" 769 "bootm $loadaddr - $fdtaddr"
745 770
746 #define CONFIG_RAMBOOTCOMMAND \ 771 #define CONFIG_RAMBOOTCOMMAND \
747 "setenv bootargs root=/dev/ram rw " \ 772 "setenv bootargs root=/dev/ram rw " \
748 "console=$consoledev,$baudrate $othbootargs;" \ 773 "console=$consoledev,$baudrate $othbootargs;" \
749 "tftp $ramdiskaddr $ramdiskfile;" \ 774 "tftp $ramdiskaddr $ramdiskfile;" \
750 "tftp $loadaddr $bootfile;" \ 775 "tftp $loadaddr $bootfile;" \
751 "tftp $fdtaddr $fdtfile;" \ 776 "tftp $fdtaddr $fdtfile;" \
752 "bootm $loadaddr $ramdiskaddr $fdtaddr" 777 "bootm $loadaddr $ramdiskaddr $fdtaddr"
753 778
754 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 779 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
755 780
756 #ifdef CONFIG_SECURE_BOOT 781 #ifdef CONFIG_SECURE_BOOT
757 #include <asm/fsl_secure_boot.h> 782 #include <asm/fsl_secure_boot.h>
758 #endif 783 #endif
759 784
760 #endif /* __CONFIG_H */ 785 #endif /* __CONFIG_H */
761 786
include/configs/T1040RDB.h
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * See file CREDITS for list of people who contributed to this 4 * See file CREDITS for list of people who contributed to this
5 * project. 5 * project.
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of 9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version. 10 * the License, or (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 * 16 *
17 * You should have received a copy of the GNU General Public License 17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA 20 * MA 02111-1307 USA
21 */ 21 */
22 22
23 #ifndef __CONFIG_H 23 #ifndef __CONFIG_H
24 #define __CONFIG_H 24 #define __CONFIG_H
25 25
26 /* 26 /*
27 * T1040 RDB board configuration file 27 * T1040 RDB board configuration file
28 */ 28 */
29 #define CONFIG_T104xRDB 29 #define CONFIG_T104xRDB
30 #define CONFIG_T1040RDB 30 #define CONFIG_T1040RDB
31 #define CONFIG_PHYS_64BIT 31 #define CONFIG_PHYS_64BIT
32 32
33 #ifdef CONFIG_RAMBOOT_PBL 33 #ifdef CONFIG_RAMBOOT_PBL
34 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 34 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
35 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 35 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
36 #endif 36 #endif
37 37
38 /* High Level Configuration Options */ 38 /* High Level Configuration Options */
39 #define CONFIG_BOOKE 39 #define CONFIG_BOOKE
40 #define CONFIG_E500 /* BOOKE e500 family */ 40 #define CONFIG_E500 /* BOOKE e500 family */
41 #define CONFIG_E500MC /* BOOKE e500mc family */ 41 #define CONFIG_E500MC /* BOOKE e500mc family */
42 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 42 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
43 #define CONFIG_MP /* support multiple processors */ 43 #define CONFIG_MP /* support multiple processors */
44 44
45 #ifndef CONFIG_SYS_TEXT_BASE 45 #ifndef CONFIG_SYS_TEXT_BASE
46 #define CONFIG_SYS_TEXT_BASE 0xeff40000 46 #define CONFIG_SYS_TEXT_BASE 0xeff40000
47 #endif 47 #endif
48 48
49 #ifndef CONFIG_RESET_VECTOR_ADDRESS 49 #ifndef CONFIG_RESET_VECTOR_ADDRESS
50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
51 #endif 51 #endif
52 52
53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
54 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 54 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
55 #define CONFIG_FSL_IFC /* Enable IFC Support */ 55 #define CONFIG_FSL_IFC /* Enable IFC Support */
56 #define CONFIG_PCI /* Enable PCI/PCIE */ 56 #define CONFIG_PCI /* Enable PCI/PCIE */
57 #define CONFIG_PCI_INDIRECT_BRIDGE 57 #define CONFIG_PCI_INDIRECT_BRIDGE
58 #define CONFIG_PCIE1 /* PCIE controler 1 */ 58 #define CONFIG_PCIE1 /* PCIE controler 1 */
59 #define CONFIG_PCIE2 /* PCIE controler 2 */ 59 #define CONFIG_PCIE2 /* PCIE controler 2 */
60 #define CONFIG_PCIE3 /* PCIE controler 3 */ 60 #define CONFIG_PCIE3 /* PCIE controler 3 */
61 #define CONFIG_PCIE4 /* PCIE controler 4 */ 61 #define CONFIG_PCIE4 /* PCIE controler 4 */
62 62
63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
65 65
66 #define CONFIG_FSL_LAW /* Use common FSL init code */ 66 #define CONFIG_FSL_LAW /* Use common FSL init code */
67 67
68 #define CONFIG_ENV_OVERWRITE 68 #define CONFIG_ENV_OVERWRITE
69 69
70 #ifdef CONFIG_SYS_NO_FLASH 70 #ifdef CONFIG_SYS_NO_FLASH
71 #define CONFIG_ENV_IS_NOWHERE 71 #define CONFIG_ENV_IS_NOWHERE
72 #else 72 #else
73 #define CONFIG_FLASH_CFI_DRIVER 73 #define CONFIG_FLASH_CFI_DRIVER
74 #define CONFIG_SYS_FLASH_CFI 74 #define CONFIG_SYS_FLASH_CFI
75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
76 #endif 76 #endif
77 77
78 #ifndef CONFIG_SYS_NO_FLASH 78 #ifndef CONFIG_SYS_NO_FLASH
79 #if defined(CONFIG_SPIFLASH) 79 #if defined(CONFIG_SPIFLASH)
80 #define CONFIG_SYS_EXTRA_ENV_RELOC 80 #define CONFIG_SYS_EXTRA_ENV_RELOC
81 #define CONFIG_ENV_IS_IN_SPI_FLASH 81 #define CONFIG_ENV_IS_IN_SPI_FLASH
82 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 82 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
83 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 83 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
84 #define CONFIG_ENV_SECT_SIZE 0x10000 84 #define CONFIG_ENV_SECT_SIZE 0x10000
85 #elif defined(CONFIG_SDCARD) 85 #elif defined(CONFIG_SDCARD)
86 #define CONFIG_SYS_EXTRA_ENV_RELOC 86 #define CONFIG_SYS_EXTRA_ENV_RELOC
87 #define CONFIG_ENV_IS_IN_MMC 87 #define CONFIG_ENV_IS_IN_MMC
88 #define CONFIG_SYS_MMC_ENV_DEV 0 88 #define CONFIG_SYS_MMC_ENV_DEV 0
89 #define CONFIG_ENV_SIZE 0x2000 89 #define CONFIG_ENV_SIZE 0x2000
90 #define CONFIG_ENV_OFFSET (512 * 1658) 90 #define CONFIG_ENV_OFFSET (512 * 1658)
91 #elif defined(CONFIG_NAND) 91 #elif defined(CONFIG_NAND)
92 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_SYS_EXTRA_ENV_RELOC
93 #define CONFIG_ENV_IS_IN_NAND 93 #define CONFIG_ENV_IS_IN_NAND
94 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 94 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
95 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 95 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
96 #else 96 #else
97 #define CONFIG_ENV_IS_IN_FLASH 97 #define CONFIG_ENV_IS_IN_FLASH
98 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 98 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
99 #define CONFIG_ENV_SIZE 0x2000 99 #define CONFIG_ENV_SIZE 0x2000
100 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 100 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
101 #endif 101 #endif
102 #else /* CONFIG_SYS_NO_FLASH */ 102 #else /* CONFIG_SYS_NO_FLASH */
103 #define CONFIG_ENV_SIZE 0x2000 103 #define CONFIG_ENV_SIZE 0x2000
104 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 104 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
105 #endif 105 #endif
106 106
107 #define CONFIG_SYS_CLK_FREQ 100000000 107 #define CONFIG_SYS_CLK_FREQ 100000000
108 #define CONFIG_DDR_CLK_FREQ 66666666 108 #define CONFIG_DDR_CLK_FREQ 66666666
109 109
110 /* 110 /*
111 * These can be toggled for performance analysis, otherwise use default. 111 * These can be toggled for performance analysis, otherwise use default.
112 */ 112 */
113 #define CONFIG_SYS_CACHE_STASHING 113 #define CONFIG_SYS_CACHE_STASHING
114 #define CONFIG_BACKSIDE_L2_CACHE 114 #define CONFIG_BACKSIDE_L2_CACHE
115 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 115 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
116 #define CONFIG_BTB /* toggle branch predition */ 116 #define CONFIG_BTB /* toggle branch predition */
117 #define CONFIG_DDR_ECC 117 #define CONFIG_DDR_ECC
118 #ifdef CONFIG_DDR_ECC 118 #ifdef CONFIG_DDR_ECC
119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
120 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 120 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
121 #endif 121 #endif
122 122
123 #define CONFIG_ENABLE_36BIT_PHYS 123 #define CONFIG_ENABLE_36BIT_PHYS
124 124
125 #define CONFIG_ADDR_MAP 125 #define CONFIG_ADDR_MAP
126 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 126 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
127 127
128 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 128 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
129 #define CONFIG_SYS_MEMTEST_END 0x00400000 129 #define CONFIG_SYS_MEMTEST_END 0x00400000
130 #define CONFIG_SYS_ALT_MEMTEST 130 #define CONFIG_SYS_ALT_MEMTEST
131 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 131 #define CONFIG_PANIC_HANG /* do not reset board on panic */
132 132
133 /* 133 /*
134 * Config the L3 Cache as L3 SRAM 134 * Config the L3 Cache as L3 SRAM
135 */ 135 */
136 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 136 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
137 137
138 #define CONFIG_SYS_DCSRBAR 0xf0000000 138 #define CONFIG_SYS_DCSRBAR 0xf0000000
139 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 139 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
140 140
141 /* 141 /*
142 * DDR Setup 142 * DDR Setup
143 */ 143 */
144 #define CONFIG_VERY_BIG_RAM 144 #define CONFIG_VERY_BIG_RAM
145 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 145 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
146 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 146 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
147 147
148 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 148 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
150 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 150 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
151 151
152 #define CONFIG_DDR_SPD 152 #define CONFIG_DDR_SPD
153 #define CONFIG_SYS_DDR_RAW_TIMING 153 #define CONFIG_SYS_DDR_RAW_TIMING
154 #define CONFIG_SYS_FSL_DDR3 154 #define CONFIG_SYS_FSL_DDR3
155 155
156 #define CONFIG_SYS_SPD_BUS_NUM 0 156 #define CONFIG_SYS_SPD_BUS_NUM 0
157 #define SPD_EEPROM_ADDRESS 0x51 157 #define SPD_EEPROM_ADDRESS 0x51
158 158
159 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 159 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
160 160
161 /* 161 /*
162 * IFC Definitions 162 * IFC Definitions
163 */ 163 */
164 #define CONFIG_SYS_FLASH_BASE 0xe8000000 164 #define CONFIG_SYS_FLASH_BASE 0xe8000000
165 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 165 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
166 166
167 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 167 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
168 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 168 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
169 CSPR_PORT_SIZE_16 | \ 169 CSPR_PORT_SIZE_16 | \
170 CSPR_MSEL_NOR | \ 170 CSPR_MSEL_NOR | \
171 CSPR_V) 171 CSPR_V)
172 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 172 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
173 /* NOR Flash Timing Params */ 173 /* NOR Flash Timing Params */
174 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 174 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
175 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 175 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
176 FTIM0_NOR_TEADC(0x5) | \ 176 FTIM0_NOR_TEADC(0x5) | \
177 FTIM0_NOR_TEAHC(0x5)) 177 FTIM0_NOR_TEAHC(0x5))
178 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 178 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
179 FTIM1_NOR_TRAD_NOR(0x1A) |\ 179 FTIM1_NOR_TRAD_NOR(0x1A) |\
180 FTIM1_NOR_TSEQRAD_NOR(0x13)) 180 FTIM1_NOR_TSEQRAD_NOR(0x13))
181 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 181 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
182 FTIM2_NOR_TCH(0x4) | \ 182 FTIM2_NOR_TCH(0x4) | \
183 FTIM2_NOR_TWPH(0x0E) | \ 183 FTIM2_NOR_TWPH(0x0E) | \
184 FTIM2_NOR_TWP(0x1c)) 184 FTIM2_NOR_TWP(0x1c))
185 #define CONFIG_SYS_NOR_FTIM3 0x0 185 #define CONFIG_SYS_NOR_FTIM3 0x0
186 186
187 #define CONFIG_SYS_FLASH_QUIET_TEST 187 #define CONFIG_SYS_FLASH_QUIET_TEST
188 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 188 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
189 189
190 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 190 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
191 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 191 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
192 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 192 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
193 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 193 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
194 194
195 #define CONFIG_SYS_FLASH_EMPTY_INFO 195 #define CONFIG_SYS_FLASH_EMPTY_INFO
196 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 196 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
197 197
198 /* CPLD on IFC */ 198 /* CPLD on IFC */
199 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 199 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
200 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 200 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
201 #define CONFIG_SYS_CSPR2_EXT (0xf) 201 #define CONFIG_SYS_CSPR2_EXT (0xf)
202 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 202 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
203 | CSPR_PORT_SIZE_8 \ 203 | CSPR_PORT_SIZE_8 \
204 | CSPR_MSEL_GPCM \ 204 | CSPR_MSEL_GPCM \
205 | CSPR_V) 205 | CSPR_V)
206 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 206 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
207 #define CONFIG_SYS_CSOR2 0x0 207 #define CONFIG_SYS_CSOR2 0x0
208 /* CPLD Timing parameters for IFC CS2 */ 208 /* CPLD Timing parameters for IFC CS2 */
209 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 209 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
210 FTIM0_GPCM_TEADC(0x0e) | \ 210 FTIM0_GPCM_TEADC(0x0e) | \
211 FTIM0_GPCM_TEAHC(0x0e)) 211 FTIM0_GPCM_TEAHC(0x0e))
212 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 212 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
213 FTIM1_GPCM_TRAD(0x1f)) 213 FTIM1_GPCM_TRAD(0x1f))
214 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 214 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
215 FTIM2_GPCM_TCH(0x0) | \ 215 FTIM2_GPCM_TCH(0x0) | \
216 FTIM2_GPCM_TWP(0x1f)) 216 FTIM2_GPCM_TWP(0x1f))
217 #define CONFIG_SYS_CS2_FTIM3 0x0 217 #define CONFIG_SYS_CS2_FTIM3 0x0
218 218
219 /* NAND Flash on IFC */ 219 /* NAND Flash on IFC */
220 #define CONFIG_NAND_FSL_IFC 220 #define CONFIG_NAND_FSL_IFC
221 #define CONFIG_SYS_NAND_BASE 0xff800000 221 #define CONFIG_SYS_NAND_BASE 0xff800000
222 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 222 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
223 223
224 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 224 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
225 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 225 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
226 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 226 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
227 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 227 | CSPR_MSEL_NAND /* MSEL = NAND */ \
228 | CSPR_V) 228 | CSPR_V)
229 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 229 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
230 230
231 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 231 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
232 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 232 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
233 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 233 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
234 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 234 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
235 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 235 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
236 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 236 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
237 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 237 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
238 238
239 #define CONFIG_SYS_NAND_ONFI_DETECTION 239 #define CONFIG_SYS_NAND_ONFI_DETECTION
240 240
241 /* ONFI NAND Flash mode0 Timing Params */ 241 /* ONFI NAND Flash mode0 Timing Params */
242 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 242 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
243 FTIM0_NAND_TWP(0x18) | \ 243 FTIM0_NAND_TWP(0x18) | \
244 FTIM0_NAND_TWCHT(0x07) | \ 244 FTIM0_NAND_TWCHT(0x07) | \
245 FTIM0_NAND_TWH(0x0a)) 245 FTIM0_NAND_TWH(0x0a))
246 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 246 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
247 FTIM1_NAND_TWBE(0x39) | \ 247 FTIM1_NAND_TWBE(0x39) | \
248 FTIM1_NAND_TRR(0x0e) | \ 248 FTIM1_NAND_TRR(0x0e) | \
249 FTIM1_NAND_TRP(0x18)) 249 FTIM1_NAND_TRP(0x18))
250 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 250 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
251 FTIM2_NAND_TREH(0x0a) | \ 251 FTIM2_NAND_TREH(0x0a) | \
252 FTIM2_NAND_TWHRE(0x1e)) 252 FTIM2_NAND_TWHRE(0x1e))
253 #define CONFIG_SYS_NAND_FTIM3 0x0 253 #define CONFIG_SYS_NAND_FTIM3 0x0
254 254
255 #define CONFIG_SYS_NAND_DDR_LAW 11 255 #define CONFIG_SYS_NAND_DDR_LAW 11
256 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 256 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
257 #define CONFIG_SYS_MAX_NAND_DEVICE 1 257 #define CONFIG_SYS_MAX_NAND_DEVICE 1
258 #define CONFIG_MTD_NAND_VERIFY_WRITE 258 #define CONFIG_MTD_NAND_VERIFY_WRITE
259 #define CONFIG_CMD_NAND 259 #define CONFIG_CMD_NAND
260 260
261 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 261 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
262 262
263 #if defined(CONFIG_NAND) 263 #if defined(CONFIG_NAND)
264 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 264 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
265 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 265 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
266 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 266 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
267 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 267 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
268 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 268 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
269 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 269 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
270 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 270 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
271 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 271 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
272 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 272 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
273 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 273 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
274 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 274 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
275 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 275 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
276 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 276 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
277 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 277 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
278 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 278 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
279 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 279 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
280 #else 280 #else
281 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 281 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
282 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 282 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
283 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 283 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
284 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 284 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
285 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 285 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
286 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 286 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
287 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 287 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
288 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 288 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
289 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 289 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
290 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 290 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
291 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 291 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
292 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 292 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
293 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 293 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
294 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 294 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
295 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 295 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
296 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 296 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
297 #endif 297 #endif
298 298
299 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 299 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
300 300
301 #if defined(CONFIG_RAMBOOT_PBL) 301 #if defined(CONFIG_RAMBOOT_PBL)
302 #define CONFIG_SYS_RAMBOOT 302 #define CONFIG_SYS_RAMBOOT
303 #endif 303 #endif
304 304
305 #define CONFIG_BOARD_EARLY_INIT_R 305 #define CONFIG_BOARD_EARLY_INIT_R
306 #define CONFIG_MISC_INIT_R 306 #define CONFIG_MISC_INIT_R
307 307
308 #define CONFIG_HWCONFIG 308 #define CONFIG_HWCONFIG
309 309
310 /* define to use L1 as initial stack */ 310 /* define to use L1 as initial stack */
311 #define CONFIG_L1_INIT_RAM 311 #define CONFIG_L1_INIT_RAM
312 #define CONFIG_SYS_INIT_RAM_LOCK 312 #define CONFIG_SYS_INIT_RAM_LOCK
313 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 313 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
315 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 315 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
316 /* The assembler doesn't like typecast */ 316 /* The assembler doesn't like typecast */
317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
318 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 318 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
319 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 319 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
320 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 320 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
321 321
322 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 322 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
323 GENERATED_GBL_DATA_SIZE) 323 GENERATED_GBL_DATA_SIZE)
324 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 324 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
325 325
326 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 326 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
327 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 327 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
328 328
329 /* Serial Port - controlled on board with jumper J8 329 /* Serial Port - controlled on board with jumper J8
330 * open - index 2 330 * open - index 2
331 * shorted - index 1 331 * shorted - index 1
332 */ 332 */
333 #define CONFIG_CONS_INDEX 1 333 #define CONFIG_CONS_INDEX 1
334 #define CONFIG_SYS_NS16550 334 #define CONFIG_SYS_NS16550
335 #define CONFIG_SYS_NS16550_SERIAL 335 #define CONFIG_SYS_NS16550_SERIAL
336 #define CONFIG_SYS_NS16550_REG_SIZE 1 336 #define CONFIG_SYS_NS16550_REG_SIZE 1
337 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 337 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
338 338
339 #define CONFIG_SYS_BAUDRATE_TABLE \ 339 #define CONFIG_SYS_BAUDRATE_TABLE \
340 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 340 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
341 341
342 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 342 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
343 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 343 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
344 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 344 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
345 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 345 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
346 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 346 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
347 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 347 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
348 348
349 /* Use the HUSH parser */ 349 /* Use the HUSH parser */
350 #define CONFIG_SYS_HUSH_PARSER 350 #define CONFIG_SYS_HUSH_PARSER
351 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 351 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
352 352
353 /* pass open firmware flat tree */ 353 /* pass open firmware flat tree */
354 #define CONFIG_OF_LIBFDT 354 #define CONFIG_OF_LIBFDT
355 #define CONFIG_OF_BOARD_SETUP 355 #define CONFIG_OF_BOARD_SETUP
356 #define CONFIG_OF_STDOUT_VIA_ALIAS 356 #define CONFIG_OF_STDOUT_VIA_ALIAS
357 357
358 /* new uImage format support */ 358 /* new uImage format support */
359 #define CONFIG_FIT 359 #define CONFIG_FIT
360 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 360 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
361 361
362 /* I2C */ 362 /* I2C */
363 #define CONFIG_SYS_I2C 363 #define CONFIG_SYS_I2C
364 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 364 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
365 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 365 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
366 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 366 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
367 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 367 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
368 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 368 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
369 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 369 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
370 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 370 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
371 371
372 /* I2C bus multiplexer */ 372 /* I2C bus multiplexer */
373 #define I2C_MUX_PCA_ADDR 0x70 373 #define I2C_MUX_PCA_ADDR 0x70
374 #define I2C_MUX_CH_DEFAULT 0x8 374 #define I2C_MUX_CH_DEFAULT 0x8
375 375
376 376
377 /* 377 /*
378 * eSPI - Enhanced SPI 378 * eSPI - Enhanced SPI
379 */ 379 */
380 #define CONFIG_FSL_ESPI 380 #define CONFIG_FSL_ESPI
381 #define CONFIG_SPI_FLASH 381 #define CONFIG_SPI_FLASH
382 #define CONFIG_SPI_FLASH_STMICRO 382 #define CONFIG_SPI_FLASH_STMICRO
383 #define CONFIG_CMD_SF 383 #define CONFIG_CMD_SF
384 #define CONFIG_SF_DEFAULT_SPEED 10000000 384 #define CONFIG_SF_DEFAULT_SPEED 10000000
385 #define CONFIG_SF_DEFAULT_MODE 0 385 #define CONFIG_SF_DEFAULT_MODE 0
386 #define CONFIG_ENV_SPI_BUS 0 386 #define CONFIG_ENV_SPI_BUS 0
387 #define CONFIG_ENV_SPI_CS 0 387 #define CONFIG_ENV_SPI_CS 0
388 #define CONFIG_ENV_SPI_MAX_HZ 10000000 388 #define CONFIG_ENV_SPI_MAX_HZ 10000000
389 #define CONFIG_ENV_SPI_MODE 0 389 #define CONFIG_ENV_SPI_MODE 0
390 390
391 /* 391 /*
392 * General PCI 392 * General PCI
393 * Memory space is mapped 1-1, but I/O space must start from 0. 393 * Memory space is mapped 1-1, but I/O space must start from 0.
394 */ 394 */
395 395
396 #ifdef CONFIG_PCI 396 #ifdef CONFIG_PCI
397 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 397 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
398 #ifdef CONFIG_PCIE1 398 #ifdef CONFIG_PCIE1
399 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 399 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
400 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 400 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
401 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 401 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
402 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 402 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
403 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 403 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
404 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 404 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
405 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 405 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
406 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 406 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
407 #endif 407 #endif
408 408
409 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 409 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
410 #ifdef CONFIG_PCIE2 410 #ifdef CONFIG_PCIE2
411 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 411 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
412 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 412 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
413 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 413 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
414 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 414 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
415 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 415 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
416 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 416 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
417 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 417 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
418 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 418 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
419 #endif 419 #endif
420 420
421 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 421 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
422 #ifdef CONFIG_PCIE3 422 #ifdef CONFIG_PCIE3
423 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 423 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
424 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 424 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
425 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 425 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
426 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 426 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
427 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 427 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
428 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 428 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
429 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 429 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
430 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 430 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
431 #endif 431 #endif
432 432
433 /* controller 4, Base address 203000 */ 433 /* controller 4, Base address 203000 */
434 #ifdef CONFIG_PCIE4 434 #ifdef CONFIG_PCIE4
435 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 435 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
436 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 436 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
437 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 437 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
438 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 438 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
439 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 439 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
440 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 440 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
441 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 441 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
442 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 442 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
443 #endif 443 #endif
444 444
445 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 445 #define CONFIG_PCI_PNP /* do pci plug-and-play */
446 #define CONFIG_E1000 446 #define CONFIG_E1000
447 447
448 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 448 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
449 #define CONFIG_DOS_PARTITION 449 #define CONFIG_DOS_PARTITION
450 #endif /* CONFIG_PCI */ 450 #endif /* CONFIG_PCI */
451 451
452 /* SATA */ 452 /* SATA */
453 #define CONFIG_FSL_SATA_V2 453 #define CONFIG_FSL_SATA_V2
454 #ifdef CONFIG_FSL_SATA_V2 454 #ifdef CONFIG_FSL_SATA_V2
455 #define CONFIG_LIBATA 455 #define CONFIG_LIBATA
456 #define CONFIG_FSL_SATA 456 #define CONFIG_FSL_SATA
457 457
458 #define CONFIG_SYS_SATA_MAX_DEVICE 1 458 #define CONFIG_SYS_SATA_MAX_DEVICE 1
459 #define CONFIG_SATA1 459 #define CONFIG_SATA1
460 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 460 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
461 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 461 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
462 462
463 #define CONFIG_LBA48 463 #define CONFIG_LBA48
464 #define CONFIG_CMD_SATA 464 #define CONFIG_CMD_SATA
465 #define CONFIG_DOS_PARTITION 465 #define CONFIG_DOS_PARTITION
466 #define CONFIG_CMD_EXT2 466 #define CONFIG_CMD_EXT2
467 #endif 467 #endif
468 468
469 /* 469 /*
470 * USB 470 * USB
471 */ 471 */
472 #define CONFIG_HAS_FSL_DR_USB 472 #define CONFIG_HAS_FSL_DR_USB
473 473
474 #ifdef CONFIG_HAS_FSL_DR_USB 474 #ifdef CONFIG_HAS_FSL_DR_USB
475 #define CONFIG_USB_EHCI 475 #define CONFIG_USB_EHCI
476 476
477 #ifdef CONFIG_USB_EHCI 477 #ifdef CONFIG_USB_EHCI
478 #define CONFIG_CMD_USB 478 #define CONFIG_CMD_USB
479 #define CONFIG_USB_STORAGE 479 #define CONFIG_USB_STORAGE
480 #define CONFIG_USB_EHCI_FSL 480 #define CONFIG_USB_EHCI_FSL
481 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 481 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
482 #define CONFIG_CMD_EXT2 482 #define CONFIG_CMD_EXT2
483 #endif 483 #endif
484 #endif 484 #endif
485 485
486 #define CONFIG_MMC 486 #define CONFIG_MMC
487 487
488 #ifdef CONFIG_MMC 488 #ifdef CONFIG_MMC
489 #define CONFIG_FSL_ESDHC 489 #define CONFIG_FSL_ESDHC
490 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 490 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
491 #define CONFIG_CMD_MMC 491 #define CONFIG_CMD_MMC
492 #define CONFIG_GENERIC_MMC 492 #define CONFIG_GENERIC_MMC
493 #define CONFIG_CMD_EXT2 493 #define CONFIG_CMD_EXT2
494 #define CONFIG_CMD_FAT 494 #define CONFIG_CMD_FAT
495 #define CONFIG_DOS_PARTITION 495 #define CONFIG_DOS_PARTITION
496 #endif 496 #endif
497 497
498 /* Qman/Bman */ 498 /* Qman/Bman */
499 #ifndef CONFIG_NOBQFMAN 499 #ifndef CONFIG_NOBQFMAN
500 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 500 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
501 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 501 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
502 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 502 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
503 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 503 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
504 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 504 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
505 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 505 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
506 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 506 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
507 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 507 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
508 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 508 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
509 509
510 #define CONFIG_SYS_DPAA_FMAN 510 #define CONFIG_SYS_DPAA_FMAN
511 #define CONFIG_SYS_DPAA_PME 511 #define CONFIG_SYS_DPAA_PME
512 512
513 /* Default address of microcode for the Linux Fman driver */ 513 /* Default address of microcode for the Linux Fman driver */
514 #if defined(CONFIG_SPIFLASH) 514 #if defined(CONFIG_SPIFLASH)
515 /* 515 /*
516 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 516 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
517 * env, so we got 0x110000. 517 * env, so we got 0x110000.
518 */ 518 */
519 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 519 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
520 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 520 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
521 #elif defined(CONFIG_SDCARD) 521 #elif defined(CONFIG_SDCARD)
522 /* 522 /*
523 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 523 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
524 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 524 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
525 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 525 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
526 */ 526 */
527 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 527 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
528 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) 528 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
529 #elif defined(CONFIG_NAND) 529 #elif defined(CONFIG_NAND)
530 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 530 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
531 #define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 531 #define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
532 #else 532 #else
533 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 533 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
534 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 534 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
535 #endif 535 #endif
536 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 536 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
537 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 537 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
538 #endif /* CONFIG_NOBQFMAN */ 538 #endif /* CONFIG_NOBQFMAN */
539 539
540 #ifdef CONFIG_SYS_DPAA_FMAN 540 #ifdef CONFIG_SYS_DPAA_FMAN
541 #define CONFIG_FMAN_ENET 541 #define CONFIG_FMAN_ENET
542 #define CONFIG_PHY_VITESSE 542 #define CONFIG_PHY_VITESSE
543 #define CONFIG_PHY_REALTEK 543 #define CONFIG_PHY_REALTEK
544 #endif 544 #endif
545 545
546 #ifdef CONFIG_FMAN_ENET 546 #ifdef CONFIG_FMAN_ENET
547 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 547 #define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
548 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 548 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
549 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 549 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
550 550
551 #define CONFIG_MII /* MII PHY management */ 551 #define CONFIG_MII /* MII PHY management */
552 #define CONFIG_ETHPRIME "FM1@DTSEC4" 552 #define CONFIG_ETHPRIME "FM1@DTSEC4"
553 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 553 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
554 #endif 554 #endif
555 555
556 /* 556 /*
557 * Environment 557 * Environment
558 */ 558 */
559 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 559 #define CONFIG_LOADS_ECHO /* echo on for serial download */
560 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 560 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
561 561
562 /* 562 /*
563 * Command line configuration. 563 * Command line configuration.
564 */ 564 */
565 #include <config_cmd_default.h> 565 #include <config_cmd_default.h>
566 566
567 #define CONFIG_CMD_DHCP 567 #define CONFIG_CMD_DHCP
568 #define CONFIG_CMD_ELF 568 #define CONFIG_CMD_ELF
569 #define CONFIG_CMD_ERRATA 569 #define CONFIG_CMD_ERRATA
570 #define CONFIG_CMD_GREPENV 570 #define CONFIG_CMD_GREPENV
571 #define CONFIG_CMD_IRQ 571 #define CONFIG_CMD_IRQ
572 #define CONFIG_CMD_I2C 572 #define CONFIG_CMD_I2C
573 #define CONFIG_CMD_MII 573 #define CONFIG_CMD_MII
574 #define CONFIG_CMD_PING 574 #define CONFIG_CMD_PING
575 #define CONFIG_CMD_REGINFO 575 #define CONFIG_CMD_REGINFO
576 #define CONFIG_CMD_SETEXPR 576 #define CONFIG_CMD_SETEXPR
577 577
578 #ifdef CONFIG_PCI 578 #ifdef CONFIG_PCI
579 #define CONFIG_CMD_PCI 579 #define CONFIG_CMD_PCI
580 #define CONFIG_CMD_NET 580 #define CONFIG_CMD_NET
581 #endif 581 #endif
582 582
583 /* 583 /*
584 * Miscellaneous configurable options 584 * Miscellaneous configurable options
585 */ 585 */
586 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 586 #define CONFIG_SYS_LONGHELP /* undef to save memory */
587 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 587 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
588 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 588 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
589 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 589 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
590 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 590 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
591 #ifdef CONFIG_CMD_KGDB 591 #ifdef CONFIG_CMD_KGDB
592 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 592 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
593 #else 593 #else
594 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 594 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
595 #endif 595 #endif
596 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 596 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
597 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 597 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
598 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 598 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
599 599
600 /* 600 /*
601 * For booting Linux, the board info and command line data 601 * For booting Linux, the board info and command line data
602 * have to be in the first 64 MB of memory, since this is 602 * have to be in the first 64 MB of memory, since this is
603 * the maximum mapped by the Linux kernel during initialization. 603 * the maximum mapped by the Linux kernel during initialization.
604 */ 604 */
605 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 605 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
606 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 606 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
607 607
608 #ifdef CONFIG_CMD_KGDB 608 #ifdef CONFIG_CMD_KGDB
609 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 609 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
610 #endif 610 #endif
611 611
612 /* 612 /*
613 * Environment Configuration 613 * Environment Configuration
614 */ 614 */
615 #define CONFIG_ROOTPATH "/opt/nfsroot" 615 #define CONFIG_ROOTPATH "/opt/nfsroot"
616 #define CONFIG_BOOTFILE "uImage" 616 #define CONFIG_BOOTFILE "uImage"
617 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 617 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
618 618
619 /* default location for tftp and bootm */ 619 /* default location for tftp and bootm */
620 #define CONFIG_LOADADDR 1000000 620 #define CONFIG_LOADADDR 1000000
621 621
622 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ 622 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
623 623
624 #define CONFIG_BAUDRATE 115200 624 #define CONFIG_BAUDRATE 115200
625 625
626 #define __USB_PHY_TYPE utmi 626 #define __USB_PHY_TYPE utmi
627 627
628 #define CONFIG_EXTRA_ENV_SETTINGS \ 628 #define CONFIG_EXTRA_ENV_SETTINGS \
629 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 629 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
630 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 630 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
631 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 631 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
632 "netdev=eth0\0" \ 632 "netdev=eth0\0" \
633 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 633 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
634 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 634 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
635 "tftpflash=tftpboot $loadaddr $uboot && " \ 635 "tftpflash=tftpboot $loadaddr $uboot && " \
636 "protect off $ubootaddr +$filesize && " \ 636 "protect off $ubootaddr +$filesize && " \
637 "erase $ubootaddr +$filesize && " \ 637 "erase $ubootaddr +$filesize && " \
638 "cp.b $loadaddr $ubootaddr $filesize && " \ 638 "cp.b $loadaddr $ubootaddr $filesize && " \
639 "protect on $ubootaddr +$filesize && " \ 639 "protect on $ubootaddr +$filesize && " \
640 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 640 "cmp.b $loadaddr $ubootaddr $filesize\0" \
641 "consoledev=ttyS0\0" \ 641 "consoledev=ttyS0\0" \
642 "ramdiskaddr=2000000\0" \ 642 "ramdiskaddr=2000000\0" \
643 "ramdiskfile=t1040rdb/ramdisk.uboot\0" \ 643 "ramdiskfile=t1040rdb/ramdisk.uboot\0" \
644 "fdtaddr=c00000\0" \ 644 "fdtaddr=c00000\0" \
645 "fdtfile=t1040rdb/t1040rdb.dtb\0" \ 645 "fdtfile=t1040rdb/t1040rdb.dtb\0" \
646 "bdev=sda3\0" \ 646 "bdev=sda3\0" \
647 "c=ffe\0" 647 "c=ffe\0"
648 648
649 #define CONFIG_LINUX \ 649 #define CONFIG_LINUX \
650 "setenv bootargs root=/dev/ram rw " \ 650 "setenv bootargs root=/dev/ram rw " \
651 "console=$consoledev,$baudrate $othbootargs;" \ 651 "console=$consoledev,$baudrate $othbootargs;" \
652 "setenv ramdiskaddr 0x02000000;" \ 652 "setenv ramdiskaddr 0x02000000;" \
653 "setenv fdtaddr 0x00c00000;" \ 653 "setenv fdtaddr 0x00c00000;" \
654 "setenv loadaddr 0x1000000;" \ 654 "setenv loadaddr 0x1000000;" \
655 "bootm $loadaddr $ramdiskaddr $fdtaddr" 655 "bootm $loadaddr $ramdiskaddr $fdtaddr"
656 656
657 #define CONFIG_HDBOOT \ 657 #define CONFIG_HDBOOT \
658 "setenv bootargs root=/dev/$bdev rw " \ 658 "setenv bootargs root=/dev/$bdev rw " \
659 "console=$consoledev,$baudrate $othbootargs;" \ 659 "console=$consoledev,$baudrate $othbootargs;" \
660 "tftp $loadaddr $bootfile;" \ 660 "tftp $loadaddr $bootfile;" \
661 "tftp $fdtaddr $fdtfile;" \ 661 "tftp $fdtaddr $fdtfile;" \
662 "bootm $loadaddr - $fdtaddr" 662 "bootm $loadaddr - $fdtaddr"
663 663
664 #define CONFIG_NFSBOOTCOMMAND \ 664 #define CONFIG_NFSBOOTCOMMAND \
665 "setenv bootargs root=/dev/nfs rw " \ 665 "setenv bootargs root=/dev/nfs rw " \
666 "nfsroot=$serverip:$rootpath " \ 666 "nfsroot=$serverip:$rootpath " \
667 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 667 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
668 "console=$consoledev,$baudrate $othbootargs;" \ 668 "console=$consoledev,$baudrate $othbootargs;" \
669 "tftp $loadaddr $bootfile;" \ 669 "tftp $loadaddr $bootfile;" \
670 "tftp $fdtaddr $fdtfile;" \ 670 "tftp $fdtaddr $fdtfile;" \
671 "bootm $loadaddr - $fdtaddr" 671 "bootm $loadaddr - $fdtaddr"
672 672
673 #define CONFIG_RAMBOOTCOMMAND \ 673 #define CONFIG_RAMBOOTCOMMAND \
674 "setenv bootargs root=/dev/ram rw " \ 674 "setenv bootargs root=/dev/ram rw " \
675 "console=$consoledev,$baudrate $othbootargs;" \ 675 "console=$consoledev,$baudrate $othbootargs;" \
676 "tftp $ramdiskaddr $ramdiskfile;" \ 676 "tftp $ramdiskaddr $ramdiskfile;" \
677 "tftp $loadaddr $bootfile;" \ 677 "tftp $loadaddr $bootfile;" \
678 "tftp $fdtaddr $fdtfile;" \ 678 "tftp $fdtaddr $fdtfile;" \
679 "bootm $loadaddr $ramdiskaddr $fdtaddr" 679 "bootm $loadaddr $ramdiskaddr $fdtaddr"
680 680
681 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 681 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
682 682
683 #ifdef CONFIG_SECURE_BOOT 683 #ifdef CONFIG_SECURE_BOOT
684 #include <asm/fsl_secure_boot.h> 684 #include <asm/fsl_secure_boot.h>
685 #endif 685 #endif
686 686
687 #endif /* __CONFIG_H */ 687 #endif /* __CONFIG_H */
688 688
include/configs/T1042RDB_PI.h
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2013 Freescale Semiconductor, Inc. 2 * Copyright 2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * See file CREDITS for list of people who contributed to this 4 * See file CREDITS for list of people who contributed to this
5 * project. 5 * project.
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of 9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version. 10 * the License, or (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 * 16 *
17 * You should have received a copy of the GNU General Public License 17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA 20 * MA 02111-1307 USA
21 */ 21 */
22 22
23 #ifndef __CONFIG_H 23 #ifndef __CONFIG_H
24 #define __CONFIG_H 24 #define __CONFIG_H
25 25
26 /* 26 /*
27 * T1042RDB_PI board configuration file 27 * T1042RDB_PI board configuration file
28 */ 28 */
29 #define CONFIG_T104xRDB 29 #define CONFIG_T104xRDB
30 #define CONFIG_T1042RDB_PI 30 #define CONFIG_T1042RDB_PI
31 #define CONFIG_PHYS_64BIT 31 #define CONFIG_PHYS_64BIT
32 32
33 #ifdef CONFIG_RAMBOOT_PBL 33 #ifdef CONFIG_RAMBOOT_PBL
34 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 34 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
35 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 35 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
36 #endif 36 #endif
37 37
38 /* High Level Configuration Options */ 38 /* High Level Configuration Options */
39 #define CONFIG_BOOKE 39 #define CONFIG_BOOKE
40 #define CONFIG_E500 /* BOOKE e500 family */ 40 #define CONFIG_E500 /* BOOKE e500 family */
41 #define CONFIG_E500MC /* BOOKE e500mc family */ 41 #define CONFIG_E500MC /* BOOKE e500mc family */
42 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 42 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
43 #define CONFIG_MP /* support multiple processors */ 43 #define CONFIG_MP /* support multiple processors */
44 44
45 #ifndef CONFIG_SYS_TEXT_BASE 45 #ifndef CONFIG_SYS_TEXT_BASE
46 #define CONFIG_SYS_TEXT_BASE 0xeff40000 46 #define CONFIG_SYS_TEXT_BASE 0xeff40000
47 #endif 47 #endif
48 48
49 #ifndef CONFIG_RESET_VECTOR_ADDRESS 49 #ifndef CONFIG_RESET_VECTOR_ADDRESS
50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
51 #endif 51 #endif
52 52
53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
54 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 54 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
55 #define CONFIG_FSL_IFC /* Enable IFC Support */ 55 #define CONFIG_FSL_IFC /* Enable IFC Support */
56 #define CONFIG_PCI /* Enable PCI/PCIE */ 56 #define CONFIG_PCI /* Enable PCI/PCIE */
57 #define CONFIG_PCI_INDIRECT_BRIDGE 57 #define CONFIG_PCI_INDIRECT_BRIDGE
58 #define CONFIG_PCIE1 /* PCIE controler 1 */ 58 #define CONFIG_PCIE1 /* PCIE controler 1 */
59 #define CONFIG_PCIE2 /* PCIE controler 2 */ 59 #define CONFIG_PCIE2 /* PCIE controler 2 */
60 #define CONFIG_PCIE3 /* PCIE controler 3 */ 60 #define CONFIG_PCIE3 /* PCIE controler 3 */
61 #define CONFIG_PCIE4 /* PCIE controler 4 */ 61 #define CONFIG_PCIE4 /* PCIE controler 4 */
62 62
63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
65 65
66 #define CONFIG_FSL_LAW /* Use common FSL init code */ 66 #define CONFIG_FSL_LAW /* Use common FSL init code */
67 67
68 #define CONFIG_ENV_OVERWRITE 68 #define CONFIG_ENV_OVERWRITE
69 69
70 #ifdef CONFIG_SYS_NO_FLASH 70 #ifdef CONFIG_SYS_NO_FLASH
71 #define CONFIG_ENV_IS_NOWHERE 71 #define CONFIG_ENV_IS_NOWHERE
72 #else 72 #else
73 #define CONFIG_FLASH_CFI_DRIVER 73 #define CONFIG_FLASH_CFI_DRIVER
74 #define CONFIG_SYS_FLASH_CFI 74 #define CONFIG_SYS_FLASH_CFI
75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
76 #endif 76 #endif
77 77
78 #ifndef CONFIG_SYS_NO_FLASH 78 #ifndef CONFIG_SYS_NO_FLASH
79 #if defined(CONFIG_SPIFLASH) 79 #if defined(CONFIG_SPIFLASH)
80 #define CONFIG_SYS_EXTRA_ENV_RELOC 80 #define CONFIG_SYS_EXTRA_ENV_RELOC
81 #define CONFIG_ENV_IS_IN_SPI_FLASH 81 #define CONFIG_ENV_IS_IN_SPI_FLASH
82 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 82 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
83 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 83 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
84 #define CONFIG_ENV_SECT_SIZE 0x10000 84 #define CONFIG_ENV_SECT_SIZE 0x10000
85 #elif defined(CONFIG_SDCARD) 85 #elif defined(CONFIG_SDCARD)
86 #define CONFIG_SYS_EXTRA_ENV_RELOC 86 #define CONFIG_SYS_EXTRA_ENV_RELOC
87 #define CONFIG_ENV_IS_IN_MMC 87 #define CONFIG_ENV_IS_IN_MMC
88 #define CONFIG_SYS_MMC_ENV_DEV 0 88 #define CONFIG_SYS_MMC_ENV_DEV 0
89 #define CONFIG_ENV_SIZE 0x2000 89 #define CONFIG_ENV_SIZE 0x2000
90 #define CONFIG_ENV_OFFSET (512 * 1658) 90 #define CONFIG_ENV_OFFSET (512 * 1658)
91 #elif defined(CONFIG_NAND) 91 #elif defined(CONFIG_NAND)
92 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_SYS_EXTRA_ENV_RELOC
93 #define CONFIG_ENV_IS_IN_NAND 93 #define CONFIG_ENV_IS_IN_NAND
94 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 94 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
95 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) 95 #define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
96 #else 96 #else
97 #define CONFIG_ENV_IS_IN_FLASH 97 #define CONFIG_ENV_IS_IN_FLASH
98 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 98 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
99 #define CONFIG_ENV_SIZE 0x2000 99 #define CONFIG_ENV_SIZE 0x2000
100 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 100 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
101 #endif 101 #endif
102 #else /* CONFIG_SYS_NO_FLASH */ 102 #else /* CONFIG_SYS_NO_FLASH */
103 #define CONFIG_ENV_SIZE 0x2000 103 #define CONFIG_ENV_SIZE 0x2000
104 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 104 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
105 #endif 105 #endif
106 106
107 #define CONFIG_SYS_CLK_FREQ 100000000 107 #define CONFIG_SYS_CLK_FREQ 100000000
108 #define CONFIG_DDR_CLK_FREQ 66666666 108 #define CONFIG_DDR_CLK_FREQ 66666666
109 109
110 /* 110 /*
111 * These can be toggled for performance analysis, otherwise use default. 111 * These can be toggled for performance analysis, otherwise use default.
112 */ 112 */
113 #define CONFIG_SYS_CACHE_STASHING 113 #define CONFIG_SYS_CACHE_STASHING
114 #define CONFIG_BACKSIDE_L2_CACHE 114 #define CONFIG_BACKSIDE_L2_CACHE
115 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 115 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
116 #define CONFIG_BTB /* toggle branch predition */ 116 #define CONFIG_BTB /* toggle branch predition */
117 #define CONFIG_DDR_ECC 117 #define CONFIG_DDR_ECC
118 #ifdef CONFIG_DDR_ECC 118 #ifdef CONFIG_DDR_ECC
119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 119 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
120 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 120 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
121 #endif 121 #endif
122 122
123 #define CONFIG_ENABLE_36BIT_PHYS 123 #define CONFIG_ENABLE_36BIT_PHYS
124 124
125 #define CONFIG_ADDR_MAP 125 #define CONFIG_ADDR_MAP
126 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 126 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
127 127
128 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 128 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
129 #define CONFIG_SYS_MEMTEST_END 0x00400000 129 #define CONFIG_SYS_MEMTEST_END 0x00400000
130 #define CONFIG_SYS_ALT_MEMTEST 130 #define CONFIG_SYS_ALT_MEMTEST
131 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 131 #define CONFIG_PANIC_HANG /* do not reset board on panic */
132 132
133 /* 133 /*
134 * Config the L3 Cache as L3 SRAM 134 * Config the L3 Cache as L3 SRAM
135 */ 135 */
136 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 136 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
137 137
138 #define CONFIG_SYS_DCSRBAR 0xf0000000 138 #define CONFIG_SYS_DCSRBAR 0xf0000000
139 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 139 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
140 140
141 /* 141 /*
142 * DDR Setup 142 * DDR Setup
143 */ 143 */
144 #define CONFIG_VERY_BIG_RAM 144 #define CONFIG_VERY_BIG_RAM
145 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 145 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
146 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 146 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
147 147
148 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 148 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
150 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 150 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
151 151
152 #define CONFIG_DDR_SPD 152 #define CONFIG_DDR_SPD
153 #define CONFIG_SYS_DDR_RAW_TIMING 153 #define CONFIG_SYS_DDR_RAW_TIMING
154 #define CONFIG_SYS_FSL_DDR3 154 #define CONFIG_SYS_FSL_DDR3
155 155
156 #define CONFIG_SYS_SPD_BUS_NUM 0 156 #define CONFIG_SYS_SPD_BUS_NUM 0
157 #define SPD_EEPROM_ADDRESS 0x51 157 #define SPD_EEPROM_ADDRESS 0x51
158 158
159 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 159 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
160 160
161 /* 161 /*
162 * IFC Definitions 162 * IFC Definitions
163 */ 163 */
164 #define CONFIG_SYS_FLASH_BASE 0xe8000000 164 #define CONFIG_SYS_FLASH_BASE 0xe8000000
165 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 165 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
166 166
167 #define CONFIG_SYS_NOR_CSPR_EXT (0xf) 167 #define CONFIG_SYS_NOR_CSPR_EXT (0xf)
168 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ 168 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
169 CSPR_PORT_SIZE_16 | \ 169 CSPR_PORT_SIZE_16 | \
170 CSPR_MSEL_NOR | \ 170 CSPR_MSEL_NOR | \
171 CSPR_V) 171 CSPR_V)
172 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 172 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
173 /* NOR Flash Timing Params */ 173 /* NOR Flash Timing Params */
174 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 174 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
175 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 175 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
176 FTIM0_NOR_TEADC(0x5) | \ 176 FTIM0_NOR_TEADC(0x5) | \
177 FTIM0_NOR_TEAHC(0x5)) 177 FTIM0_NOR_TEAHC(0x5))
178 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 178 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
179 FTIM1_NOR_TRAD_NOR(0x1A) |\ 179 FTIM1_NOR_TRAD_NOR(0x1A) |\
180 FTIM1_NOR_TSEQRAD_NOR(0x13)) 180 FTIM1_NOR_TSEQRAD_NOR(0x13))
181 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 181 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
182 FTIM2_NOR_TCH(0x4) | \ 182 FTIM2_NOR_TCH(0x4) | \
183 FTIM2_NOR_TWPH(0x0E) | \ 183 FTIM2_NOR_TWPH(0x0E) | \
184 FTIM2_NOR_TWP(0x1c)) 184 FTIM2_NOR_TWP(0x1c))
185 #define CONFIG_SYS_NOR_FTIM3 0x0 185 #define CONFIG_SYS_NOR_FTIM3 0x0
186 186
187 #define CONFIG_SYS_FLASH_QUIET_TEST 187 #define CONFIG_SYS_FLASH_QUIET_TEST
188 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 188 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
189 189
190 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 190 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
191 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 191 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
192 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 192 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
193 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 193 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
194 194
195 #define CONFIG_SYS_FLASH_EMPTY_INFO 195 #define CONFIG_SYS_FLASH_EMPTY_INFO
196 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 196 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
197 197
198 /* CPLD on IFC */ 198 /* CPLD on IFC */
199 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 199 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
200 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) 200 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
201 #define CONFIG_SYS_CSPR2_EXT (0xf) 201 #define CONFIG_SYS_CSPR2_EXT (0xf)
202 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 202 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
203 | CSPR_PORT_SIZE_8 \ 203 | CSPR_PORT_SIZE_8 \
204 | CSPR_MSEL_GPCM \ 204 | CSPR_MSEL_GPCM \
205 | CSPR_V) 205 | CSPR_V)
206 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 206 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
207 #define CONFIG_SYS_CSOR2 0x0 207 #define CONFIG_SYS_CSOR2 0x0
208 /* CPLD Timing parameters for IFC CS2 */ 208 /* CPLD Timing parameters for IFC CS2 */
209 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 209 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
210 FTIM0_GPCM_TEADC(0x0e) | \ 210 FTIM0_GPCM_TEADC(0x0e) | \
211 FTIM0_GPCM_TEAHC(0x0e)) 211 FTIM0_GPCM_TEAHC(0x0e))
212 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 212 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
213 FTIM1_GPCM_TRAD(0x1f)) 213 FTIM1_GPCM_TRAD(0x1f))
214 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 214 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
215 FTIM2_GPCM_TCH(0x0) | \ 215 FTIM2_GPCM_TCH(0x0) | \
216 FTIM2_GPCM_TWP(0x1f)) 216 FTIM2_GPCM_TWP(0x1f))
217 #define CONFIG_SYS_CS2_FTIM3 0x0 217 #define CONFIG_SYS_CS2_FTIM3 0x0
218 218
219 /* NAND Flash on IFC */ 219 /* NAND Flash on IFC */
220 #define CONFIG_NAND_FSL_IFC 220 #define CONFIG_NAND_FSL_IFC
221 #define CONFIG_SYS_NAND_BASE 0xff800000 221 #define CONFIG_SYS_NAND_BASE 0xff800000
222 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 222 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
223 223
224 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 224 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
225 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 225 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
226 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 226 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
227 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 227 | CSPR_MSEL_NAND /* MSEL = NAND */ \
228 | CSPR_V) 228 | CSPR_V)
229 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 229 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
230 230
231 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 231 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
232 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 232 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
233 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 233 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
234 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ 234 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
235 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ 235 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
236 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ 236 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
237 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 237 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
238 238
239 #define CONFIG_SYS_NAND_ONFI_DETECTION 239 #define CONFIG_SYS_NAND_ONFI_DETECTION
240 240
241 /* ONFI NAND Flash mode0 Timing Params */ 241 /* ONFI NAND Flash mode0 Timing Params */
242 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 242 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
243 FTIM0_NAND_TWP(0x18) | \ 243 FTIM0_NAND_TWP(0x18) | \
244 FTIM0_NAND_TWCHT(0x07) | \ 244 FTIM0_NAND_TWCHT(0x07) | \
245 FTIM0_NAND_TWH(0x0a)) 245 FTIM0_NAND_TWH(0x0a))
246 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 246 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
247 FTIM1_NAND_TWBE(0x39) | \ 247 FTIM1_NAND_TWBE(0x39) | \
248 FTIM1_NAND_TRR(0x0e) | \ 248 FTIM1_NAND_TRR(0x0e) | \
249 FTIM1_NAND_TRP(0x18)) 249 FTIM1_NAND_TRP(0x18))
250 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 250 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
251 FTIM2_NAND_TREH(0x0a) | \ 251 FTIM2_NAND_TREH(0x0a) | \
252 FTIM2_NAND_TWHRE(0x1e)) 252 FTIM2_NAND_TWHRE(0x1e))
253 #define CONFIG_SYS_NAND_FTIM3 0x0 253 #define CONFIG_SYS_NAND_FTIM3 0x0
254 254
255 #define CONFIG_SYS_NAND_DDR_LAW 11 255 #define CONFIG_SYS_NAND_DDR_LAW 11
256 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 256 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
257 #define CONFIG_SYS_MAX_NAND_DEVICE 1 257 #define CONFIG_SYS_MAX_NAND_DEVICE 1
258 #define CONFIG_MTD_NAND_VERIFY_WRITE 258 #define CONFIG_MTD_NAND_VERIFY_WRITE
259 #define CONFIG_CMD_NAND 259 #define CONFIG_CMD_NAND
260 260
261 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) 261 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
262 262
263 #if defined(CONFIG_NAND) 263 #if defined(CONFIG_NAND)
264 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 264 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
265 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 265 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
266 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 266 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
267 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 267 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
268 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 268 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
269 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 269 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
270 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 270 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
271 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 271 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
272 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT 272 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
273 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 273 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
274 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 274 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
275 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 275 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
276 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 276 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
277 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 277 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
278 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 278 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
279 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 279 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
280 #else 280 #else
281 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT 281 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
282 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 282 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
283 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 283 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
284 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 284 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
285 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 285 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
286 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 286 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
287 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 287 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
288 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 288 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
289 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT 289 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
290 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 290 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
291 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 291 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
292 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 292 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
293 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 293 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
294 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 294 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
295 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 295 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
296 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 296 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
297 #endif 297 #endif
298 298
299 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 299 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
300 300
301 #if defined(CONFIG_RAMBOOT_PBL) 301 #if defined(CONFIG_RAMBOOT_PBL)
302 #define CONFIG_SYS_RAMBOOT 302 #define CONFIG_SYS_RAMBOOT
303 #endif 303 #endif
304 304
305 #define CONFIG_BOARD_EARLY_INIT_R 305 #define CONFIG_BOARD_EARLY_INIT_R
306 #define CONFIG_MISC_INIT_R 306 #define CONFIG_MISC_INIT_R
307 307
308 #define CONFIG_HWCONFIG 308 #define CONFIG_HWCONFIG
309 309
310 /* define to use L1 as initial stack */ 310 /* define to use L1 as initial stack */
311 #define CONFIG_L1_INIT_RAM 311 #define CONFIG_L1_INIT_RAM
312 #define CONFIG_SYS_INIT_RAM_LOCK 312 #define CONFIG_SYS_INIT_RAM_LOCK
313 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 313 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
315 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 315 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
316 /* The assembler doesn't like typecast */ 316 /* The assembler doesn't like typecast */
317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 317 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
318 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 318 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
319 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 319 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
320 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 320 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
321 321
322 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 322 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
323 GENERATED_GBL_DATA_SIZE) 323 GENERATED_GBL_DATA_SIZE)
324 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 324 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
325 325
326 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 326 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
327 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 327 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
328 328
329 /* Serial Port - controlled on board with jumper J8 329 /* Serial Port - controlled on board with jumper J8
330 * open - index 2 330 * open - index 2
331 * shorted - index 1 331 * shorted - index 1
332 */ 332 */
333 #define CONFIG_CONS_INDEX 1 333 #define CONFIG_CONS_INDEX 1
334 #define CONFIG_SYS_NS16550 334 #define CONFIG_SYS_NS16550
335 #define CONFIG_SYS_NS16550_SERIAL 335 #define CONFIG_SYS_NS16550_SERIAL
336 #define CONFIG_SYS_NS16550_REG_SIZE 1 336 #define CONFIG_SYS_NS16550_REG_SIZE 1
337 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 337 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
338 338
339 #define CONFIG_SYS_BAUDRATE_TABLE \ 339 #define CONFIG_SYS_BAUDRATE_TABLE \
340 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 340 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
341 341
342 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 342 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
343 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 343 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
344 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 344 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
345 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 345 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
346 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 346 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */
347 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 347 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
348 348
349 /* Use the HUSH parser */ 349 /* Use the HUSH parser */
350 #define CONFIG_SYS_HUSH_PARSER 350 #define CONFIG_SYS_HUSH_PARSER
351 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 351 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
352 352
353 /* pass open firmware flat tree */ 353 /* pass open firmware flat tree */
354 #define CONFIG_OF_LIBFDT 354 #define CONFIG_OF_LIBFDT
355 #define CONFIG_OF_BOARD_SETUP 355 #define CONFIG_OF_BOARD_SETUP
356 #define CONFIG_OF_STDOUT_VIA_ALIAS 356 #define CONFIG_OF_STDOUT_VIA_ALIAS
357 357
358 /* new uImage format support */ 358 /* new uImage format support */
359 #define CONFIG_FIT 359 #define CONFIG_FIT
360 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 360 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
361 361
362 /* I2C */ 362 /* I2C */
363 #define CONFIG_SYS_I2C 363 #define CONFIG_SYS_I2C
364 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 364 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
365 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 365 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
366 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 366 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
367 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 367 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */
368 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 368 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
369 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 369 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
370 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 370 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000
371 371
372 /* I2C bus multiplexer */ 372 /* I2C bus multiplexer */
373 #define I2C_MUX_PCA_ADDR 0x70 373 #define I2C_MUX_PCA_ADDR 0x70
374 374
375 /* 375 /*
376 * RTC configuration 376 * RTC configuration
377 */ 377 */
378 #define RTC 378 #define RTC
379 #define CONFIG_RTC_DS1337 1 379 #define CONFIG_RTC_DS1337 1
380 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 380 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
381 381
382 /*DVI encoder*/ 382 /*DVI encoder*/
383 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 383 #define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
384 384
385 /* 385 /*
386 * eSPI - Enhanced SPI 386 * eSPI - Enhanced SPI
387 */ 387 */
388 #define CONFIG_FSL_ESPI 388 #define CONFIG_FSL_ESPI
389 #define CONFIG_SPI_FLASH 389 #define CONFIG_SPI_FLASH
390 #define CONFIG_SPI_FLASH_STMICRO 390 #define CONFIG_SPI_FLASH_STMICRO
391 #define CONFIG_CMD_SF 391 #define CONFIG_CMD_SF
392 #define CONFIG_SF_DEFAULT_SPEED 10000000 392 #define CONFIG_SF_DEFAULT_SPEED 10000000
393 #define CONFIG_SF_DEFAULT_MODE 0 393 #define CONFIG_SF_DEFAULT_MODE 0
394 #define CONFIG_ENV_SPI_BUS 0 394 #define CONFIG_ENV_SPI_BUS 0
395 #define CONFIG_ENV_SPI_CS 0 395 #define CONFIG_ENV_SPI_CS 0
396 #define CONFIG_ENV_SPI_MAX_HZ 10000000 396 #define CONFIG_ENV_SPI_MAX_HZ 10000000
397 #define CONFIG_ENV_SPI_MODE 0 397 #define CONFIG_ENV_SPI_MODE 0
398 398
399 /* 399 /*
400 * General PCI 400 * General PCI
401 * Memory space is mapped 1-1, but I/O space must start from 0. 401 * Memory space is mapped 1-1, but I/O space must start from 0.
402 */ 402 */
403 403
404 #ifdef CONFIG_PCI 404 #ifdef CONFIG_PCI
405 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 405 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
406 #ifdef CONFIG_PCIE1 406 #ifdef CONFIG_PCIE1
407 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 407 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
408 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 408 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
409 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 409 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
410 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 410 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
411 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 411 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
412 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 412 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
413 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 413 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
414 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 414 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
415 #endif 415 #endif
416 416
417 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 417 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
418 #ifdef CONFIG_PCIE2 418 #ifdef CONFIG_PCIE2
419 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 419 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
420 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 420 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
421 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull 421 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
422 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 422 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
423 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 423 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
424 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 424 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
425 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 425 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
426 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 426 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
427 #endif 427 #endif
428 428
429 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 429 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
430 #ifdef CONFIG_PCIE3 430 #ifdef CONFIG_PCIE3
431 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 431 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
432 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 432 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
433 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull 433 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
434 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 434 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
435 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 435 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
436 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 436 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
437 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 437 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
438 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 438 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
439 #endif 439 #endif
440 440
441 /* controller 4, Base address 203000 */ 441 /* controller 4, Base address 203000 */
442 #ifdef CONFIG_PCIE4 442 #ifdef CONFIG_PCIE4
443 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 443 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
444 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 444 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
445 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull 445 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
446 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 446 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
447 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 447 #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
448 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 448 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
449 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 449 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
450 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 450 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
451 #endif 451 #endif
452 452
453 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 453 #define CONFIG_PCI_PNP /* do pci plug-and-play */
454 #define CONFIG_E1000 454 #define CONFIG_E1000
455 455
456 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 456 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
457 #define CONFIG_DOS_PARTITION 457 #define CONFIG_DOS_PARTITION
458 #endif /* CONFIG_PCI */ 458 #endif /* CONFIG_PCI */
459 459
460 /* SATA */ 460 /* SATA */
461 #define CONFIG_FSL_SATA_V2 461 #define CONFIG_FSL_SATA_V2
462 #ifdef CONFIG_FSL_SATA_V2 462 #ifdef CONFIG_FSL_SATA_V2
463 #define CONFIG_LIBATA 463 #define CONFIG_LIBATA
464 #define CONFIG_FSL_SATA 464 #define CONFIG_FSL_SATA
465 465
466 #define CONFIG_SYS_SATA_MAX_DEVICE 1 466 #define CONFIG_SYS_SATA_MAX_DEVICE 1
467 #define CONFIG_SATA1 467 #define CONFIG_SATA1
468 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 468 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
469 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 469 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
470 470
471 #define CONFIG_LBA48 471 #define CONFIG_LBA48
472 #define CONFIG_CMD_SATA 472 #define CONFIG_CMD_SATA
473 #define CONFIG_DOS_PARTITION 473 #define CONFIG_DOS_PARTITION
474 #define CONFIG_CMD_EXT2 474 #define CONFIG_CMD_EXT2
475 #endif 475 #endif
476 476
477 /* 477 /*
478 * USB 478 * USB
479 */ 479 */
480 #define CONFIG_HAS_FSL_DR_USB 480 #define CONFIG_HAS_FSL_DR_USB
481 481
482 #ifdef CONFIG_HAS_FSL_DR_USB 482 #ifdef CONFIG_HAS_FSL_DR_USB
483 #define CONFIG_USB_EHCI 483 #define CONFIG_USB_EHCI
484 484
485 #ifdef CONFIG_USB_EHCI 485 #ifdef CONFIG_USB_EHCI
486 #define CONFIG_CMD_USB 486 #define CONFIG_CMD_USB
487 #define CONFIG_USB_STORAGE 487 #define CONFIG_USB_STORAGE
488 #define CONFIG_USB_EHCI_FSL 488 #define CONFIG_USB_EHCI_FSL
489 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 489 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
490 #define CONFIG_CMD_EXT2 490 #define CONFIG_CMD_EXT2
491 #endif 491 #endif
492 #endif 492 #endif
493 493
494 #define CONFIG_MMC 494 #define CONFIG_MMC
495 495
496 #ifdef CONFIG_MMC 496 #ifdef CONFIG_MMC
497 #define CONFIG_FSL_ESDHC 497 #define CONFIG_FSL_ESDHC
498 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 498 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
499 #define CONFIG_CMD_MMC 499 #define CONFIG_CMD_MMC
500 #define CONFIG_GENERIC_MMC 500 #define CONFIG_GENERIC_MMC
501 #define CONFIG_CMD_EXT2 501 #define CONFIG_CMD_EXT2
502 #define CONFIG_CMD_FAT 502 #define CONFIG_CMD_FAT
503 #define CONFIG_DOS_PARTITION 503 #define CONFIG_DOS_PARTITION
504 #endif 504 #endif
505 505
506 /* Qman/Bman */ 506 /* Qman/Bman */
507 #ifndef CONFIG_NOBQFMAN 507 #ifndef CONFIG_NOBQFMAN
508 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 508 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
509 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 509 #define CONFIG_SYS_BMAN_NUM_PORTALS 25
510 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 510 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
511 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 511 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
512 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 512 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
513 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 513 #define CONFIG_SYS_QMAN_NUM_PORTALS 25
514 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 514 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
515 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 515 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
516 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 516 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
517 517
518 #define CONFIG_SYS_DPAA_FMAN 518 #define CONFIG_SYS_DPAA_FMAN
519 #define CONFIG_SYS_DPAA_PME 519 #define CONFIG_SYS_DPAA_PME
520 520
521 /* Default address of microcode for the Linux Fman driver */ 521 /* Default address of microcode for the Linux Fman driver */
522 #if defined(CONFIG_SPIFLASH) 522 #if defined(CONFIG_SPIFLASH)
523 /* 523 /*
524 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 524 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
525 * env, so we got 0x110000. 525 * env, so we got 0x110000.
526 */ 526 */
527 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 527 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
528 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 528 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
529 #elif defined(CONFIG_SDCARD) 529 #elif defined(CONFIG_SDCARD)
530 /* 530 /*
531 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 531 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
532 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 532 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
533 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 533 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
534 */ 534 */
535 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 535 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
536 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) 536 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
537 #elif defined(CONFIG_NAND) 537 #elif defined(CONFIG_NAND)
538 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 538 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
539 #define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) 539 #define CONFIG_SYS_QE_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
540 #else 540 #else
541 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 541 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
542 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 542 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
543 #endif 543 #endif
544 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 544 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
545 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 545 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
546 #endif /* CONFIG_NOBQFMAN */ 546 #endif /* CONFIG_NOBQFMAN */
547 547
548 #ifdef CONFIG_SYS_DPAA_FMAN 548 #ifdef CONFIG_SYS_DPAA_FMAN
549 #define CONFIG_FMAN_ENET 549 #define CONFIG_FMAN_ENET
550 #define CONFIG_PHY_VITESSE 550 #define CONFIG_PHY_VITESSE
551 #define CONFIG_PHY_REALTEK 551 #define CONFIG_PHY_REALTEK
552 #endif 552 #endif
553 553
554 #ifdef CONFIG_FMAN_ENET 554 #ifdef CONFIG_FMAN_ENET
555 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 555 #define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
556 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 556 #define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
557 557
558 #define CONFIG_MII /* MII PHY management */ 558 #define CONFIG_MII /* MII PHY management */
559 #define CONFIG_ETHPRIME "FM1@DTSEC4" 559 #define CONFIG_ETHPRIME "FM1@DTSEC4"
560 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 560 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
561 #endif 561 #endif
562 562
563 /* 563 /*
564 * Environment 564 * Environment
565 */ 565 */
566 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 566 #define CONFIG_LOADS_ECHO /* echo on for serial download */
567 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 567 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
568 568
569 /* 569 /*
570 * Command line configuration. 570 * Command line configuration.
571 */ 571 */
572 #include <config_cmd_default.h> 572 #include <config_cmd_default.h>
573 573
574 #define CONFIG_CMD_DATE 574 #define CONFIG_CMD_DATE
575 #define CONFIG_CMD_DHCP 575 #define CONFIG_CMD_DHCP
576 #define CONFIG_CMD_ELF 576 #define CONFIG_CMD_ELF
577 #define CONFIG_CMD_ERRATA 577 #define CONFIG_CMD_ERRATA
578 #define CONFIG_CMD_GREPENV 578 #define CONFIG_CMD_GREPENV
579 #define CONFIG_CMD_IRQ 579 #define CONFIG_CMD_IRQ
580 #define CONFIG_CMD_I2C 580 #define CONFIG_CMD_I2C
581 #define CONFIG_CMD_MII 581 #define CONFIG_CMD_MII
582 #define CONFIG_CMD_PING 582 #define CONFIG_CMD_PING
583 #define CONFIG_CMD_REGINFO 583 #define CONFIG_CMD_REGINFO
584 #define CONFIG_CMD_SETEXPR 584 #define CONFIG_CMD_SETEXPR
585 585
586 #ifdef CONFIG_PCI 586 #ifdef CONFIG_PCI
587 #define CONFIG_CMD_PCI 587 #define CONFIG_CMD_PCI
588 #define CONFIG_CMD_NET 588 #define CONFIG_CMD_NET
589 #endif 589 #endif
590 590
591 /* 591 /*
592 * Miscellaneous configurable options 592 * Miscellaneous configurable options
593 */ 593 */
594 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 594 #define CONFIG_SYS_LONGHELP /* undef to save memory */
595 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 595 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
596 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 596 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
597 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 597 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
598 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 598 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
599 #ifdef CONFIG_CMD_KGDB 599 #ifdef CONFIG_CMD_KGDB
600 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 600 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
601 #else 601 #else
602 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 602 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
603 #endif 603 #endif
604 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 604 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
605 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 605 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
606 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 606 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
607 607
608 /* 608 /*
609 * For booting Linux, the board info and command line data 609 * For booting Linux, the board info and command line data
610 * have to be in the first 64 MB of memory, since this is 610 * have to be in the first 64 MB of memory, since this is
611 * the maximum mapped by the Linux kernel during initialization. 611 * the maximum mapped by the Linux kernel during initialization.
612 */ 612 */
613 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 613 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
614 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 614 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
615 615
616 #ifdef CONFIG_CMD_KGDB 616 #ifdef CONFIG_CMD_KGDB
617 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 617 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
618 #endif 618 #endif
619 619
620 /* 620 /*
621 * Environment Configuration 621 * Environment Configuration
622 */ 622 */
623 #define CONFIG_ROOTPATH "/opt/nfsroot" 623 #define CONFIG_ROOTPATH "/opt/nfsroot"
624 #define CONFIG_BOOTFILE "uImage" 624 #define CONFIG_BOOTFILE "uImage"
625 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 625 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
626 626
627 /* default location for tftp and bootm */ 627 /* default location for tftp and bootm */
628 #define CONFIG_LOADADDR 1000000 628 #define CONFIG_LOADADDR 1000000
629 629
630 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ 630 #define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/
631 631
632 #define CONFIG_BAUDRATE 115200 632 #define CONFIG_BAUDRATE 115200
633 633
634 #define __USB_PHY_TYPE utmi 634 #define __USB_PHY_TYPE utmi
635 635
636 #define CONFIG_EXTRA_ENV_SETTINGS \ 636 #define CONFIG_EXTRA_ENV_SETTINGS \
637 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ 637 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
638 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 638 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
639 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 639 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
640 "netdev=eth0\0" \ 640 "netdev=eth0\0" \
641 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 641 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
642 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 642 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
643 "tftpflash=tftpboot $loadaddr $uboot && " \ 643 "tftpflash=tftpboot $loadaddr $uboot && " \
644 "protect off $ubootaddr +$filesize && " \ 644 "protect off $ubootaddr +$filesize && " \
645 "erase $ubootaddr +$filesize && " \ 645 "erase $ubootaddr +$filesize && " \
646 "cp.b $loadaddr $ubootaddr $filesize && " \ 646 "cp.b $loadaddr $ubootaddr $filesize && " \
647 "protect on $ubootaddr +$filesize && " \ 647 "protect on $ubootaddr +$filesize && " \
648 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 648 "cmp.b $loadaddr $ubootaddr $filesize\0" \
649 "consoledev=ttyS0\0" \ 649 "consoledev=ttyS0\0" \
650 "ramdiskaddr=2000000\0" \ 650 "ramdiskaddr=2000000\0" \
651 "ramdiskfile=t1040rdb_pi/ramdisk.uboot\0" \ 651 "ramdiskfile=t1040rdb_pi/ramdisk.uboot\0" \
652 "fdtaddr=c00000\0" \ 652 "fdtaddr=c00000\0" \
653 "fdtfile=t1040rdb_pi/t1040rdb_pi.dtb\0" \ 653 "fdtfile=t1040rdb_pi/t1040rdb_pi.dtb\0" \
654 "bdev=sda3\0" \ 654 "bdev=sda3\0" \
655 "c=ffe\0" 655 "c=ffe\0"
656 656
657 #define CONFIG_LINUX \ 657 #define CONFIG_LINUX \
658 "setenv bootargs root=/dev/ram rw " \ 658 "setenv bootargs root=/dev/ram rw " \
659 "console=$consoledev,$baudrate $othbootargs;" \ 659 "console=$consoledev,$baudrate $othbootargs;" \
660 "setenv ramdiskaddr 0x02000000;" \ 660 "setenv ramdiskaddr 0x02000000;" \
661 "setenv fdtaddr 0x00c00000;" \ 661 "setenv fdtaddr 0x00c00000;" \
662 "setenv loadaddr 0x1000000;" \ 662 "setenv loadaddr 0x1000000;" \
663 "bootm $loadaddr $ramdiskaddr $fdtaddr" 663 "bootm $loadaddr $ramdiskaddr $fdtaddr"
664 664
665 #define CONFIG_HDBOOT \ 665 #define CONFIG_HDBOOT \
666 "setenv bootargs root=/dev/$bdev rw " \ 666 "setenv bootargs root=/dev/$bdev rw " \
667 "console=$consoledev,$baudrate $othbootargs;" \ 667 "console=$consoledev,$baudrate $othbootargs;" \
668 "tftp $loadaddr $bootfile;" \ 668 "tftp $loadaddr $bootfile;" \
669 "tftp $fdtaddr $fdtfile;" \ 669 "tftp $fdtaddr $fdtfile;" \
670 "bootm $loadaddr - $fdtaddr" 670 "bootm $loadaddr - $fdtaddr"
671 671
672 #define CONFIG_NFSBOOTCOMMAND \ 672 #define CONFIG_NFSBOOTCOMMAND \
673 "setenv bootargs root=/dev/nfs rw " \ 673 "setenv bootargs root=/dev/nfs rw " \
674 "nfsroot=$serverip:$rootpath " \ 674 "nfsroot=$serverip:$rootpath " \
675 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 675 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
676 "console=$consoledev,$baudrate $othbootargs;" \ 676 "console=$consoledev,$baudrate $othbootargs;" \
677 "tftp $loadaddr $bootfile;" \ 677 "tftp $loadaddr $bootfile;" \
678 "tftp $fdtaddr $fdtfile;" \ 678 "tftp $fdtaddr $fdtfile;" \
679 "bootm $loadaddr - $fdtaddr" 679 "bootm $loadaddr - $fdtaddr"
680 680
681 #define CONFIG_RAMBOOTCOMMAND \ 681 #define CONFIG_RAMBOOTCOMMAND \
682 "setenv bootargs root=/dev/ram rw " \ 682 "setenv bootargs root=/dev/ram rw " \
683 "console=$consoledev,$baudrate $othbootargs;" \ 683 "console=$consoledev,$baudrate $othbootargs;" \
684 "tftp $ramdiskaddr $ramdiskfile;" \ 684 "tftp $ramdiskaddr $ramdiskfile;" \
685 "tftp $loadaddr $bootfile;" \ 685 "tftp $loadaddr $bootfile;" \
686 "tftp $fdtaddr $fdtfile;" \ 686 "tftp $fdtaddr $fdtfile;" \
687 "bootm $loadaddr $ramdiskaddr $fdtaddr" 687 "bootm $loadaddr $ramdiskaddr $fdtaddr"
688 688
689 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 689 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
690 690
691 #ifdef CONFIG_SECURE_BOOT 691 #ifdef CONFIG_SECURE_BOOT
692 #include <asm/fsl_secure_boot.h> 692 #include <asm/fsl_secure_boot.h>
693 #endif 693 #endif
694 694
695 #endif /* __CONFIG_H */ 695 #endif /* __CONFIG_H */
696 696
include/configs/T208xQDS.h
Diff comments   View file @ 247161b
1 /* 1 /*
2 * Copyright 2011-2013 Freescale Semiconductor, Inc. 2 * Copyright 2011-2013 Freescale Semiconductor, Inc.
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 /* 7 /*
8 * T2080/T2081 QDS board configuration file 8 * T2080/T2081 QDS board configuration file
9 */ 9 */
10 10
11 #ifndef __T208xQDS_H 11 #ifndef __T208xQDS_H
12 #define __T208xQDS_H 12 #define __T208xQDS_H
13 13
14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ 14 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
15 #define CONFIG_MMC 15 #define CONFIG_MMC
16 #define CONFIG_SPI_FLASH 16 #define CONFIG_SPI_FLASH
17 #define CONFIG_USB_EHCI 17 #define CONFIG_USB_EHCI
18 #if defined(CONFIG_PPC_T2080) 18 #if defined(CONFIG_PPC_T2080)
19 #define CONFIG_T2080QDS 19 #define CONFIG_T2080QDS
20 #define CONFIG_FSL_SATA_V2 20 #define CONFIG_FSL_SATA_V2
21 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ 21 #define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */
22 #define CONFIG_SRIO1 /* SRIO port 1 */ 22 #define CONFIG_SRIO1 /* SRIO port 1 */
23 #define CONFIG_SRIO2 /* SRIO port 2 */ 23 #define CONFIG_SRIO2 /* SRIO port 2 */
24 #elif defined(CONFIG_PPC_T2081) 24 #elif defined(CONFIG_PPC_T2081)
25 #define CONFIG_T2081QDS 25 #define CONFIG_T2081QDS
26 #endif 26 #endif
27 27
28 /* High Level Configuration Options */ 28 /* High Level Configuration Options */
29 #define CONFIG_PHYS_64BIT 29 #define CONFIG_PHYS_64BIT
30 #define CONFIG_BOOKE 30 #define CONFIG_BOOKE
31 #define CONFIG_E500 /* BOOKE e500 family */ 31 #define CONFIG_E500 /* BOOKE e500 family */
32 #define CONFIG_E500MC /* BOOKE e500mc family */ 32 #define CONFIG_E500MC /* BOOKE e500mc family */
33 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 33 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
34 #define CONFIG_MP /* support multiple processors */ 34 #define CONFIG_MP /* support multiple processors */
35 #define CONFIG_ENABLE_36BIT_PHYS 35 #define CONFIG_ENABLE_36BIT_PHYS
36 36
37 #ifdef CONFIG_PHYS_64BIT 37 #ifdef CONFIG_PHYS_64BIT
38 #define CONFIG_ADDR_MAP 1 38 #define CONFIG_ADDR_MAP 1
39 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 39 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
40 #endif 40 #endif
41 41
42 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 42 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
43 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 43 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
44 #define CONFIG_FSL_IFC /* Enable IFC Support */ 44 #define CONFIG_FSL_IFC /* Enable IFC Support */
45 #define CONFIG_FSL_LAW /* Use common FSL init code */ 45 #define CONFIG_FSL_LAW /* Use common FSL init code */
46 #define CONFIG_ENV_OVERWRITE 46 #define CONFIG_ENV_OVERWRITE
47 47
48 #ifdef CONFIG_RAMBOOT_PBL 48 #ifdef CONFIG_RAMBOOT_PBL
49 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 49 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
50 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 50 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
51 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xqds/t208x_pbi.cfg 51 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xqds/t208x_pbi.cfg
52 #if defined(CONFIG_PPC_T2080) 52 #if defined(CONFIG_PPC_T2080)
53 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2080_rcw.cfg 53 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2080_rcw.cfg
54 #elif defined(CONFIG_PPC_T2081) 54 #elif defined(CONFIG_PPC_T2081)
55 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2081_rcw.cfg 55 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xqds/t2081_rcw.cfg
56 #endif 56 #endif
57 #endif 57 #endif
58 58
59 #define CONFIG_SRIO_PCIE_BOOT_MASTER 59 #define CONFIG_SRIO_PCIE_BOOT_MASTER
60 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 60 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
61 /* Set 1M boot space */ 61 /* Set 1M boot space */
62 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 62 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
63 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 63 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
64 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 64 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
65 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 65 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
66 #define CONFIG_SYS_NO_FLASH 66 #define CONFIG_SYS_NO_FLASH
67 #endif 67 #endif
68 68
69 #ifndef CONFIG_SYS_TEXT_BASE 69 #ifndef CONFIG_SYS_TEXT_BASE
70 #define CONFIG_SYS_TEXT_BASE 0xeff40000 70 #define CONFIG_SYS_TEXT_BASE 0xeff40000
71 #endif 71 #endif
72 72
73 #ifndef CONFIG_RESET_VECTOR_ADDRESS 73 #ifndef CONFIG_RESET_VECTOR_ADDRESS
74 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 74 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
75 #endif 75 #endif
76 76
77 /* 77 /*
78 * These can be toggled for performance analysis, otherwise use default. 78 * These can be toggled for performance analysis, otherwise use default.
79 */ 79 */
80 #define CONFIG_SYS_CACHE_STASHING 80 #define CONFIG_SYS_CACHE_STASHING
81 #define CONFIG_BTB /* toggle branch predition */ 81 #define CONFIG_BTB /* toggle branch predition */
82 #define CONFIG_DDR_ECC 82 #define CONFIG_DDR_ECC
83 #ifdef CONFIG_DDR_ECC 83 #ifdef CONFIG_DDR_ECC
84 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 84 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
85 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 85 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
86 #endif 86 #endif
87 87
88 #ifdef CONFIG_SYS_NO_FLASH 88 #ifdef CONFIG_SYS_NO_FLASH
89 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 89 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
90 #define CONFIG_ENV_IS_NOWHERE 90 #define CONFIG_ENV_IS_NOWHERE
91 #endif 91 #endif
92 #else 92 #else
93 #define CONFIG_FLASH_CFI_DRIVER 93 #define CONFIG_FLASH_CFI_DRIVER
94 #define CONFIG_SYS_FLASH_CFI 94 #define CONFIG_SYS_FLASH_CFI
95 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 95 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
96 #endif 96 #endif
97 97
98 #if defined(CONFIG_SPIFLASH) 98 #if defined(CONFIG_SPIFLASH)
99 #define CONFIG_SYS_EXTRA_ENV_RELOC 99 #define CONFIG_SYS_EXTRA_ENV_RELOC
100 #define CONFIG_ENV_IS_IN_SPI_FLASH 100 #define CONFIG_ENV_IS_IN_SPI_FLASH
101 #define CONFIG_ENV_SPI_BUS 0 101 #define CONFIG_ENV_SPI_BUS 0
102 #define CONFIG_ENV_SPI_CS 0 102 #define CONFIG_ENV_SPI_CS 0
103 #define CONFIG_ENV_SPI_MAX_HZ 10000000 103 #define CONFIG_ENV_SPI_MAX_HZ 10000000
104 #define CONFIG_ENV_SPI_MODE 0 104 #define CONFIG_ENV_SPI_MODE 0
105 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 105 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
106 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 106 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
107 #define CONFIG_ENV_SECT_SIZE 0x10000 107 #define CONFIG_ENV_SECT_SIZE 0x10000
108 #elif defined(CONFIG_SDCARD) 108 #elif defined(CONFIG_SDCARD)
109 #define CONFIG_SYS_EXTRA_ENV_RELOC 109 #define CONFIG_SYS_EXTRA_ENV_RELOC
110 #define CONFIG_ENV_IS_IN_MMC 110 #define CONFIG_ENV_IS_IN_MMC
111 #define CONFIG_SYS_MMC_ENV_DEV 0 111 #define CONFIG_SYS_MMC_ENV_DEV 0
112 #define CONFIG_ENV_SIZE 0x2000 112 #define CONFIG_ENV_SIZE 0x2000
113 #define CONFIG_ENV_OFFSET (512 * 1658) 113 #define CONFIG_ENV_OFFSET (512 * 1658)
114 #elif defined(CONFIG_NAND) 114 #elif defined(CONFIG_NAND)
115 #define CONFIG_SYS_EXTRA_ENV_RELOC 115 #define CONFIG_SYS_EXTRA_ENV_RELOC
116 #define CONFIG_ENV_IS_IN_NAND 116 #define CONFIG_ENV_IS_IN_NAND
117 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 117 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
118 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 118 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
119 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 119 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
120 #define CONFIG_ENV_IS_IN_REMOTE 120 #define CONFIG_ENV_IS_IN_REMOTE
121 #define CONFIG_ENV_ADDR 0xffe20000 121 #define CONFIG_ENV_ADDR 0xffe20000
122 #define CONFIG_ENV_SIZE 0x2000 122 #define CONFIG_ENV_SIZE 0x2000
123 #elif defined(CONFIG_ENV_IS_NOWHERE) 123 #elif defined(CONFIG_ENV_IS_NOWHERE)
124 #define CONFIG_ENV_SIZE 0x2000 124 #define CONFIG_ENV_SIZE 0x2000
125 #else 125 #else
126 #define CONFIG_ENV_IS_IN_FLASH 126 #define CONFIG_ENV_IS_IN_FLASH
127 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 127 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
128 #define CONFIG_ENV_SIZE 0x2000 128 #define CONFIG_ENV_SIZE 0x2000
129 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 129 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
130 #endif 130 #endif
131 131
132 #ifndef __ASSEMBLY__ 132 #ifndef __ASSEMBLY__
133 unsigned long get_board_sys_clk(void); 133 unsigned long get_board_sys_clk(void);
134 unsigned long get_board_ddr_clk(void); 134 unsigned long get_board_ddr_clk(void);
135 #endif 135 #endif
136 136
137 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() 137 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
138 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 138 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
139 139
140 /* 140 /*
141 * Config the L3 Cache as L3 SRAM 141 * Config the L3 Cache as L3 SRAM
142 */ 142 */
143 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 143 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
144 144
145 #define CONFIG_SYS_DCSRBAR 0xf0000000 145 #define CONFIG_SYS_DCSRBAR 0xf0000000
146 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 146 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
147 147
148 /* EEPROM */ 148 /* EEPROM */
149 #define CONFIG_ID_EEPROM 149 #define CONFIG_ID_EEPROM
150 #define CONFIG_SYS_I2C_EEPROM_NXID 150 #define CONFIG_SYS_I2C_EEPROM_NXID
151 #define CONFIG_SYS_EEPROM_BUS_NUM 0 151 #define CONFIG_SYS_EEPROM_BUS_NUM 0
152 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 152 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
153 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 153 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
154 154
155 /* 155 /*
156 * DDR Setup 156 * DDR Setup
157 */ 157 */
158 #define CONFIG_VERY_BIG_RAM 158 #define CONFIG_VERY_BIG_RAM
159 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 159 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
160 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 160 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
161 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 161 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
162 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 162 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
163 #define CONFIG_DDR_SPD 163 #define CONFIG_DDR_SPD
164 #define CONFIG_SYS_FSL_DDR3 164 #define CONFIG_SYS_FSL_DDR3
165 #undef CONFIG_FSL_DDR_INTERACTIVE 165 #undef CONFIG_FSL_DDR_INTERACTIVE
166 #define CONFIG_SYS_SPD_BUS_NUM 0 166 #define CONFIG_SYS_SPD_BUS_NUM 0
167 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 167 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
168 #define SPD_EEPROM_ADDRESS1 0x51 168 #define SPD_EEPROM_ADDRESS1 0x51
169 #define SPD_EEPROM_ADDRESS2 0x52 169 #define SPD_EEPROM_ADDRESS2 0x52
170 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 170 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
171 #define CTRL_INTLV_PREFERED cacheline 171 #define CTRL_INTLV_PREFERED cacheline
172 172
173 /* 173 /*
174 * IFC Definitions 174 * IFC Definitions
175 */ 175 */
176 #define CONFIG_SYS_FLASH_BASE 0xe0000000 176 #define CONFIG_SYS_FLASH_BASE 0xe0000000
177 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 177 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
178 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 178 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
179 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 179 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
180 + 0x8000000) | \ 180 + 0x8000000) | \
181 CSPR_PORT_SIZE_16 | \ 181 CSPR_PORT_SIZE_16 | \
182 CSPR_MSEL_NOR | \ 182 CSPR_MSEL_NOR | \
183 CSPR_V) 183 CSPR_V)
184 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 184 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
185 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 185 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
186 CSPR_PORT_SIZE_16 | \ 186 CSPR_PORT_SIZE_16 | \
187 CSPR_MSEL_NOR | \ 187 CSPR_MSEL_NOR | \
188 CSPR_V) 188 CSPR_V)
189 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 189 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
190 /* NOR Flash Timing Params */ 190 /* NOR Flash Timing Params */
191 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 191 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
192 192
193 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 193 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
194 FTIM0_NOR_TEADC(0x5) | \ 194 FTIM0_NOR_TEADC(0x5) | \
195 FTIM0_NOR_TEAHC(0x5)) 195 FTIM0_NOR_TEAHC(0x5))
196 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 196 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
197 FTIM1_NOR_TRAD_NOR(0x1A) |\ 197 FTIM1_NOR_TRAD_NOR(0x1A) |\
198 FTIM1_NOR_TSEQRAD_NOR(0x13)) 198 FTIM1_NOR_TSEQRAD_NOR(0x13))
199 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 199 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
200 FTIM2_NOR_TCH(0x4) | \ 200 FTIM2_NOR_TCH(0x4) | \
201 FTIM2_NOR_TWPH(0x0E) | \ 201 FTIM2_NOR_TWPH(0x0E) | \
202 FTIM2_NOR_TWP(0x1c)) 202 FTIM2_NOR_TWP(0x1c))
203 #define CONFIG_SYS_NOR_FTIM3 0x0 203 #define CONFIG_SYS_NOR_FTIM3 0x0
204 204
205 #define CONFIG_SYS_FLASH_QUIET_TEST 205 #define CONFIG_SYS_FLASH_QUIET_TEST
206 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 206 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
207 207
208 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 208 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
209 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 209 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
210 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 210 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
211 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 211 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
212 212
213 #define CONFIG_SYS_FLASH_EMPTY_INFO 213 #define CONFIG_SYS_FLASH_EMPTY_INFO
214 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 214 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
215 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 215 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
216 216
217 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 217 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
218 #define QIXIS_BASE 0xffdf0000 218 #define QIXIS_BASE 0xffdf0000
219 #define QIXIS_LBMAP_SWITCH 6 219 #define QIXIS_LBMAP_SWITCH 6
220 #define QIXIS_LBMAP_MASK 0x0f 220 #define QIXIS_LBMAP_MASK 0x0f
221 #define QIXIS_LBMAP_SHIFT 0 221 #define QIXIS_LBMAP_SHIFT 0
222 #define QIXIS_LBMAP_DFLTBANK 0x00 222 #define QIXIS_LBMAP_DFLTBANK 0x00
223 #define QIXIS_LBMAP_ALTBANK 0x04 223 #define QIXIS_LBMAP_ALTBANK 0x04
224 #define QIXIS_RST_CTL_RESET 0x83 224 #define QIXIS_RST_CTL_RESET 0x83
225 #define QIXIS_RST_FORCE_MEM 0x1 225 #define QIXIS_RST_FORCE_MEM 0x1
226 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 226 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
227 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 227 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
228 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 228 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
229 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 229 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
230 230
231 #define CONFIG_SYS_CSPR3_EXT (0xf) 231 #define CONFIG_SYS_CSPR3_EXT (0xf)
232 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 232 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
233 | CSPR_PORT_SIZE_8 \ 233 | CSPR_PORT_SIZE_8 \
234 | CSPR_MSEL_GPCM \ 234 | CSPR_MSEL_GPCM \
235 | CSPR_V) 235 | CSPR_V)
236 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024) 236 #define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
237 #define CONFIG_SYS_CSOR3 0x0 237 #define CONFIG_SYS_CSOR3 0x0
238 /* QIXIS Timing parameters for IFC CS3 */ 238 /* QIXIS Timing parameters for IFC CS3 */
239 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 239 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
240 FTIM0_GPCM_TEADC(0x0e) | \ 240 FTIM0_GPCM_TEADC(0x0e) | \
241 FTIM0_GPCM_TEAHC(0x0e)) 241 FTIM0_GPCM_TEAHC(0x0e))
242 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ 242 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
243 FTIM1_GPCM_TRAD(0x3f)) 243 FTIM1_GPCM_TRAD(0x3f))
244 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 244 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
245 FTIM2_GPCM_TCH(0x0) | \ 245 FTIM2_GPCM_TCH(0x8) | \
246 FTIM2_GPCM_TWP(0x1f)) 246 FTIM2_GPCM_TWP(0x1f))
247 #define CONFIG_SYS_CS3_FTIM3 0x0 247 #define CONFIG_SYS_CS3_FTIM3 0x0
248 248
249 /* NAND Flash on IFC */ 249 /* NAND Flash on IFC */
250 #define CONFIG_NAND_FSL_IFC 250 #define CONFIG_NAND_FSL_IFC
251 #define CONFIG_SYS_NAND_BASE 0xff800000 251 #define CONFIG_SYS_NAND_BASE 0xff800000
252 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 252 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
253 253
254 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 254 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
255 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 255 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
256 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 256 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
257 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 257 | CSPR_MSEL_NAND /* MSEL = NAND */ \
258 | CSPR_V) 258 | CSPR_V)
259 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 259 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
260 260
261 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 261 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
262 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 262 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
263 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 263 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
264 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 264 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
265 | CSOR_NAND_PGS_2K /* Page Size = 2K */\ 265 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
266 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ 266 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
267 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 267 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
268 268
269 #define CONFIG_SYS_NAND_ONFI_DETECTION 269 #define CONFIG_SYS_NAND_ONFI_DETECTION
270 270
271 /* ONFI NAND Flash mode0 Timing Params */ 271 /* ONFI NAND Flash mode0 Timing Params */
272 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 272 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
273 FTIM0_NAND_TWP(0x18) | \ 273 FTIM0_NAND_TWP(0x18) | \
274 FTIM0_NAND_TWCHT(0x07) | \ 274 FTIM0_NAND_TWCHT(0x07) | \
275 FTIM0_NAND_TWH(0x0a)) 275 FTIM0_NAND_TWH(0x0a))
276 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 276 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
277 FTIM1_NAND_TWBE(0x39) | \ 277 FTIM1_NAND_TWBE(0x39) | \
278 FTIM1_NAND_TRR(0x0e) | \ 278 FTIM1_NAND_TRR(0x0e) | \
279 FTIM1_NAND_TRP(0x18)) 279 FTIM1_NAND_TRP(0x18))
280 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 280 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
281 FTIM2_NAND_TREH(0x0a) | \ 281 FTIM2_NAND_TREH(0x0a) | \
282 FTIM2_NAND_TWHRE(0x1e)) 282 FTIM2_NAND_TWHRE(0x1e))
283 #define CONFIG_SYS_NAND_FTIM3 0x0 283 #define CONFIG_SYS_NAND_FTIM3 0x0
284 284
285 #define CONFIG_SYS_NAND_DDR_LAW 11 285 #define CONFIG_SYS_NAND_DDR_LAW 11
286 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 286 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
287 #define CONFIG_SYS_MAX_NAND_DEVICE 1 287 #define CONFIG_SYS_MAX_NAND_DEVICE 1
288 #define CONFIG_MTD_NAND_VERIFY_WRITE 288 #define CONFIG_MTD_NAND_VERIFY_WRITE
289 #define CONFIG_CMD_NAND 289 #define CONFIG_CMD_NAND
290 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 290 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
291 291
292 #if defined(CONFIG_NAND) 292 #if defined(CONFIG_NAND)
293 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 293 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
294 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 294 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
295 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 295 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
296 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 296 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
297 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 297 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
298 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 298 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
299 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 299 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
300 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 300 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
301 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 301 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
302 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 302 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
303 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 303 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
304 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 304 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
305 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 305 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
306 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 306 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
307 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 307 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
308 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 308 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
309 #else 309 #else
310 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 310 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
311 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 311 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
312 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 312 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
313 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 313 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
314 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 314 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
315 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 315 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
316 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 316 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
317 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 317 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
318 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 318 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
319 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 319 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
320 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 320 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
321 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 321 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
322 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 322 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
323 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 323 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
324 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 324 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
325 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 325 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
326 #endif 326 #endif
327 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 327 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
328 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 328 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
329 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 329 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
330 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 330 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
331 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 331 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
332 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 332 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
333 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 333 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
334 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 334 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
335 335
336 #if defined(CONFIG_RAMBOOT_PBL) 336 #if defined(CONFIG_RAMBOOT_PBL)
337 #define CONFIG_SYS_RAMBOOT 337 #define CONFIG_SYS_RAMBOOT
338 #endif 338 #endif
339 339
340 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 340 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
341 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 341 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
342 #define CONFIG_MISC_INIT_R 342 #define CONFIG_MISC_INIT_R
343 #define CONFIG_HWCONFIG 343 #define CONFIG_HWCONFIG
344 344
345 /* define to use L1 as initial stack */ 345 /* define to use L1 as initial stack */
346 #define CONFIG_L1_INIT_RAM 346 #define CONFIG_L1_INIT_RAM
347 #define CONFIG_SYS_INIT_RAM_LOCK 347 #define CONFIG_SYS_INIT_RAM_LOCK
348 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 348 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
349 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 349 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
350 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 350 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
351 /* The assembler doesn't like typecast */ 351 /* The assembler doesn't like typecast */
352 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 352 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
353 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 353 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
354 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 354 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
355 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 355 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
356 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 356 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
357 GENERATED_GBL_DATA_SIZE) 357 GENERATED_GBL_DATA_SIZE)
358 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 358 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
359 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 359 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
360 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 360 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
361 361
362 /* 362 /*
363 * Serial Port 363 * Serial Port
364 */ 364 */
365 #define CONFIG_CONS_INDEX 1 365 #define CONFIG_CONS_INDEX 1
366 #define CONFIG_SYS_NS16550 366 #define CONFIG_SYS_NS16550
367 #define CONFIG_SYS_NS16550_SERIAL 367 #define CONFIG_SYS_NS16550_SERIAL
368 #define CONFIG_SYS_NS16550_REG_SIZE 1 368 #define CONFIG_SYS_NS16550_REG_SIZE 1
369 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 369 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
370 #define CONFIG_SYS_BAUDRATE_TABLE \ 370 #define CONFIG_SYS_BAUDRATE_TABLE \
371 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 371 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
372 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 372 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
373 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 373 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
374 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 374 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
375 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 375 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
376 376
377 /* Use the HUSH parser */ 377 /* Use the HUSH parser */
378 #define CONFIG_SYS_HUSH_PARSER 378 #define CONFIG_SYS_HUSH_PARSER
379 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 379 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
380 380
381 /* pass open firmware flat tree */ 381 /* pass open firmware flat tree */
382 #define CONFIG_OF_LIBFDT 382 #define CONFIG_OF_LIBFDT
383 #define CONFIG_OF_BOARD_SETUP 383 #define CONFIG_OF_BOARD_SETUP
384 #define CONFIG_OF_STDOUT_VIA_ALIAS 384 #define CONFIG_OF_STDOUT_VIA_ALIAS
385 385
386 /* new uImage format support */ 386 /* new uImage format support */
387 #define CONFIG_FIT 387 #define CONFIG_FIT
388 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 388 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
389 389
390 /* 390 /*
391 * I2C 391 * I2C
392 */ 392 */
393 #define CONFIG_SYS_I2C 393 #define CONFIG_SYS_I2C
394 #define CONFIG_SYS_I2C_FSL 394 #define CONFIG_SYS_I2C_FSL
395 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 395 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
396 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 396 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
397 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 397 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
398 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 398 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
399 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 399 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
400 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 400 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
401 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 401 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
402 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 402 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
403 #define CONFIG_SYS_FSL_I2C_SPEED 100000 403 #define CONFIG_SYS_FSL_I2C_SPEED 100000
404 #define CONFIG_SYS_FSL_I2C2_SPEED 100000 404 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
405 #define CONFIG_SYS_FSL_I2C3_SPEED 100000 405 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
406 #define CONFIG_SYS_FSL_I2C4_SPEED 100000 406 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
407 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ 407 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
408 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ 408 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
409 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ 409 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
410 #define I2C_MUX_CH_DEFAULT 0x8 410 #define I2C_MUX_CH_DEFAULT 0x8
411 411
412 412
413 /* 413 /*
414 * RapidIO 414 * RapidIO
415 */ 415 */
416 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 416 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
417 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 417 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
418 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 418 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
419 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 419 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
420 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 420 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
421 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 421 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
422 /* 422 /*
423 * for slave u-boot IMAGE instored in master memory space, 423 * for slave u-boot IMAGE instored in master memory space,
424 * PHYS must be aligned based on the SIZE 424 * PHYS must be aligned based on the SIZE
425 */ 425 */
426 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 426 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
427 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 427 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
428 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 428 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
429 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 429 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
430 /* 430 /*
431 * for slave UCODE and ENV instored in master memory space, 431 * for slave UCODE and ENV instored in master memory space,
432 * PHYS must be aligned based on the SIZE 432 * PHYS must be aligned based on the SIZE
433 */ 433 */
434 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 434 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
435 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 435 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
436 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 436 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
437 437
438 /* slave core release by master*/ 438 /* slave core release by master*/
439 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 439 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
440 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 440 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
441 441
442 /* 442 /*
443 * SRIO_PCIE_BOOT - SLAVE 443 * SRIO_PCIE_BOOT - SLAVE
444 */ 444 */
445 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 445 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
446 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 446 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
447 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 447 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
448 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 448 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
449 #endif 449 #endif
450 450
451 /* 451 /*
452 * eSPI - Enhanced SPI 452 * eSPI - Enhanced SPI
453 */ 453 */
454 #ifdef CONFIG_SPI_FLASH 454 #ifdef CONFIG_SPI_FLASH
455 #define CONFIG_FSL_ESPI 455 #define CONFIG_FSL_ESPI
456 #define CONFIG_SPI_FLASH_SST 456 #define CONFIG_SPI_FLASH_SST
457 #define CONFIG_SPI_FLASH_STMICRO 457 #define CONFIG_SPI_FLASH_STMICRO
458 #if defined(CONFIG_T2080QDS) 458 #if defined(CONFIG_T2080QDS)
459 #define CONFIG_SPI_FLASH_SPANSION 459 #define CONFIG_SPI_FLASH_SPANSION
460 #elif defined(CONFIG_T2081QDS) 460 #elif defined(CONFIG_T2081QDS)
461 #define CONFIG_SPI_FLASH_EON 461 #define CONFIG_SPI_FLASH_EON
462 #endif 462 #endif
463 463
464 #define CONFIG_CMD_SF 464 #define CONFIG_CMD_SF
465 #define CONFIG_SF_DEFAULT_SPEED 10000000 465 #define CONFIG_SF_DEFAULT_SPEED 10000000
466 #define CONFIG_SF_DEFAULT_MODE 0 466 #define CONFIG_SF_DEFAULT_MODE 0
467 #endif 467 #endif
468 468
469 /* 469 /*
470 * General PCI 470 * General PCI
471 * Memory space is mapped 1-1, but I/O space must start from 0. 471 * Memory space is mapped 1-1, but I/O space must start from 0.
472 */ 472 */
473 #define CONFIG_PCI /* Enable PCI/PCIE */ 473 #define CONFIG_PCI /* Enable PCI/PCIE */
474 #define CONFIG_PCIE1 /* PCIE controler 1 */ 474 #define CONFIG_PCIE1 /* PCIE controler 1 */
475 #define CONFIG_PCIE2 /* PCIE controler 2 */ 475 #define CONFIG_PCIE2 /* PCIE controler 2 */
476 #define CONFIG_PCIE3 /* PCIE controler 3 */ 476 #define CONFIG_PCIE3 /* PCIE controler 3 */
477 #define CONFIG_PCIE4 /* PCIE controler 4 */ 477 #define CONFIG_PCIE4 /* PCIE controler 4 */
478 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 478 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
479 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 479 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
480 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 480 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
481 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 481 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
482 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 482 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
483 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 483 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
484 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 484 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
485 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 485 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
486 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 486 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
487 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 487 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
488 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 488 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
489 489
490 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 490 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
491 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 491 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
492 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 492 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
493 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 493 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
494 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ 494 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
495 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 495 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
496 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 496 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
497 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 497 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
498 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 498 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
499 499
500 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 500 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
501 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 501 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
502 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 502 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
503 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull 503 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
504 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ 504 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
505 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 505 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
506 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 506 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
507 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 507 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
508 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 508 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
509 509
510 /* controller 4, Base address 203000 */ 510 /* controller 4, Base address 203000 */
511 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 511 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
512 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 512 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
513 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull 513 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
514 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ 514 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
515 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 515 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
516 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 516 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
517 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 517 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
518 518
519 #ifdef CONFIG_PCI 519 #ifdef CONFIG_PCI
520 #define CONFIG_PCI_INDIRECT_BRIDGE 520 #define CONFIG_PCI_INDIRECT_BRIDGE
521 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 521 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
522 #define CONFIG_NET_MULTI 522 #define CONFIG_NET_MULTI
523 #define CONFIG_E1000 523 #define CONFIG_E1000
524 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 524 #define CONFIG_PCI_PNP /* do pci plug-and-play */
525 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 525 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
526 #define CONFIG_DOS_PARTITION 526 #define CONFIG_DOS_PARTITION
527 #endif 527 #endif
528 528
529 /* Qman/Bman */ 529 /* Qman/Bman */
530 #ifndef CONFIG_NOBQFMAN 530 #ifndef CONFIG_NOBQFMAN
531 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 531 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
532 #define CONFIG_SYS_BMAN_NUM_PORTALS 18 532 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
533 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 533 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
534 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 534 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
535 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 535 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
536 #define CONFIG_SYS_QMAN_NUM_PORTALS 18 536 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
537 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 537 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
538 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 538 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
539 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 539 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
540 540
541 #define CONFIG_SYS_DPAA_FMAN 541 #define CONFIG_SYS_DPAA_FMAN
542 #define CONFIG_SYS_DPAA_PME 542 #define CONFIG_SYS_DPAA_PME
543 #define CONFIG_SYS_PMAN 543 #define CONFIG_SYS_PMAN
544 #define CONFIG_SYS_DPAA_DCE 544 #define CONFIG_SYS_DPAA_DCE
545 #define CONFIG_SYS_DPAA_RMAN /* RMan */ 545 #define CONFIG_SYS_DPAA_RMAN /* RMan */
546 #define CONFIG_SYS_INTERLAKEN 546 #define CONFIG_SYS_INTERLAKEN
547 547
548 /* Default address of microcode for the Linux Fman driver */ 548 /* Default address of microcode for the Linux Fman driver */
549 #if defined(CONFIG_SPIFLASH) 549 #if defined(CONFIG_SPIFLASH)
550 /* 550 /*
551 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 551 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
552 * env, so we got 0x110000. 552 * env, so we got 0x110000.
553 */ 553 */
554 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 554 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
555 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 555 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
556 #elif defined(CONFIG_SDCARD) 556 #elif defined(CONFIG_SDCARD)
557 /* 557 /*
558 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 558 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
559 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 559 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
560 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 560 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
561 */ 561 */
562 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 562 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
563 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) 563 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
564 #elif defined(CONFIG_NAND) 564 #elif defined(CONFIG_NAND)
565 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 565 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
566 #define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 566 #define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
567 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 567 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
568 /* 568 /*
569 * Slave has no ucode locally, it can fetch this from remote. When implementing 569 * Slave has no ucode locally, it can fetch this from remote. When implementing
570 * in two corenet boards, slave's ucode could be stored in master's memory 570 * in two corenet boards, slave's ucode could be stored in master's memory
571 * space, the address can be mapped from slave TLB->slave LAW-> 571 * space, the address can be mapped from slave TLB->slave LAW->
572 * slave SRIO or PCIE outbound window->master inbound window-> 572 * slave SRIO or PCIE outbound window->master inbound window->
573 * master LAW->the ucode address in master's memory space. 573 * master LAW->the ucode address in master's memory space.
574 */ 574 */
575 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 575 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
576 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 576 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
577 #else 577 #else
578 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 578 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
579 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 579 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
580 #endif 580 #endif
581 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 581 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
582 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 582 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
583 #endif /* CONFIG_NOBQFMAN */ 583 #endif /* CONFIG_NOBQFMAN */
584 584
585 #ifdef CONFIG_SYS_DPAA_FMAN 585 #ifdef CONFIG_SYS_DPAA_FMAN
586 #define CONFIG_FMAN_ENET 586 #define CONFIG_FMAN_ENET
587 #define CONFIG_PHYLIB_10G 587 #define CONFIG_PHYLIB_10G
588 #define CONFIG_PHY_VITESSE 588 #define CONFIG_PHY_VITESSE
589 #define CONFIG_PHY_REALTEK 589 #define CONFIG_PHY_REALTEK
590 #define CONFIG_PHY_TERANETICS 590 #define CONFIG_PHY_TERANETICS
591 #define RGMII_PHY1_ADDR 0x1 591 #define RGMII_PHY1_ADDR 0x1
592 #define RGMII_PHY2_ADDR 0x2 592 #define RGMII_PHY2_ADDR 0x2
593 #define FM1_10GEC1_PHY_ADDR 0x3 593 #define FM1_10GEC1_PHY_ADDR 0x3
594 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 594 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
595 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D 595 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
596 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 596 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
597 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F 597 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
598 #endif 598 #endif
599 599
600 #ifdef CONFIG_FMAN_ENET 600 #ifdef CONFIG_FMAN_ENET
601 #define CONFIG_MII /* MII PHY management */ 601 #define CONFIG_MII /* MII PHY management */
602 #define CONFIG_ETHPRIME "FM1@DTSEC3" 602 #define CONFIG_ETHPRIME "FM1@DTSEC3"
603 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 603 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
604 #endif 604 #endif
605 605
606 /* 606 /*
607 * SATA 607 * SATA
608 */ 608 */
609 #ifdef CONFIG_FSL_SATA_V2 609 #ifdef CONFIG_FSL_SATA_V2
610 #define CONFIG_LIBATA 610 #define CONFIG_LIBATA
611 #define CONFIG_FSL_SATA 611 #define CONFIG_FSL_SATA
612 #define CONFIG_SYS_SATA_MAX_DEVICE 2 612 #define CONFIG_SYS_SATA_MAX_DEVICE 2
613 #define CONFIG_SATA1 613 #define CONFIG_SATA1
614 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 614 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
615 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 615 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
616 #define CONFIG_SATA2 616 #define CONFIG_SATA2
617 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 617 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
618 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 618 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
619 #define CONFIG_LBA48 619 #define CONFIG_LBA48
620 #define CONFIG_CMD_SATA 620 #define CONFIG_CMD_SATA
621 #define CONFIG_DOS_PARTITION 621 #define CONFIG_DOS_PARTITION
622 #define CONFIG_CMD_EXT2 622 #define CONFIG_CMD_EXT2
623 #endif 623 #endif
624 624
625 /* 625 /*
626 * USB 626 * USB
627 */ 627 */
628 #ifdef CONFIG_USB_EHCI 628 #ifdef CONFIG_USB_EHCI
629 #define CONFIG_CMD_USB 629 #define CONFIG_CMD_USB
630 #define CONFIG_USB_STORAGE 630 #define CONFIG_USB_STORAGE
631 #define CONFIG_USB_EHCI_FSL 631 #define CONFIG_USB_EHCI_FSL
632 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 632 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
633 #define CONFIG_CMD_EXT2 633 #define CONFIG_CMD_EXT2
634 #define CONFIG_HAS_FSL_DR_USB 634 #define CONFIG_HAS_FSL_DR_USB
635 #endif 635 #endif
636 636
637 /* 637 /*
638 * SDHC 638 * SDHC
639 */ 639 */
640 #ifdef CONFIG_MMC 640 #ifdef CONFIG_MMC
641 #define CONFIG_CMD_MMC 641 #define CONFIG_CMD_MMC
642 #define CONFIG_FSL_ESDHC 642 #define CONFIG_FSL_ESDHC
643 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 643 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
644 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 644 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
645 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 645 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
646 #define CONFIG_GENERIC_MMC 646 #define CONFIG_GENERIC_MMC
647 #define CONFIG_CMD_EXT2 647 #define CONFIG_CMD_EXT2
648 #define CONFIG_CMD_FAT 648 #define CONFIG_CMD_FAT
649 #define CONFIG_DOS_PARTITION 649 #define CONFIG_DOS_PARTITION
650 #endif 650 #endif
651 651
652 /* 652 /*
653 * Environment 653 * Environment
654 */ 654 */
655 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 655 #define CONFIG_LOADS_ECHO /* echo on for serial download */
656 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 656 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
657 657
658 /* 658 /*
659 * Command line configuration. 659 * Command line configuration.
660 */ 660 */
661 #include <config_cmd_default.h> 661 #include <config_cmd_default.h>
662 662
663 #define CONFIG_CMD_DHCP 663 #define CONFIG_CMD_DHCP
664 #define CONFIG_CMD_ELF 664 #define CONFIG_CMD_ELF
665 #define CONFIG_CMD_ERRATA 665 #define CONFIG_CMD_ERRATA
666 #define CONFIG_CMD_GREPENV 666 #define CONFIG_CMD_GREPENV
667 #define CONFIG_CMD_IRQ 667 #define CONFIG_CMD_IRQ
668 #define CONFIG_CMD_I2C 668 #define CONFIG_CMD_I2C
669 #define CONFIG_CMD_MII 669 #define CONFIG_CMD_MII
670 #define CONFIG_CMD_PING 670 #define CONFIG_CMD_PING
671 #define CONFIG_CMD_SETEXPR 671 #define CONFIG_CMD_SETEXPR
672 #define CONFIG_CMD_REGINFO 672 #define CONFIG_CMD_REGINFO
673 #define CONFIG_CMD_BDI 673 #define CONFIG_CMD_BDI
674 674
675 #ifdef CONFIG_PCI 675 #ifdef CONFIG_PCI
676 #define CONFIG_CMD_PCI 676 #define CONFIG_CMD_PCI
677 #define CONFIG_CMD_NET 677 #define CONFIG_CMD_NET
678 #endif 678 #endif
679 679
680 /* 680 /*
681 * Miscellaneous configurable options 681 * Miscellaneous configurable options
682 */ 682 */
683 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 683 #define CONFIG_SYS_LONGHELP /* undef to save memory */
684 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 684 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
685 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 685 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
686 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 686 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
687 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 687 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
688 #ifdef CONFIG_CMD_KGDB 688 #ifdef CONFIG_CMD_KGDB
689 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 689 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
690 #else 690 #else
691 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 691 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
692 #endif 692 #endif
693 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 693 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
694 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 694 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
695 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 695 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
696 696
697 /* 697 /*
698 * For booting Linux, the board info and command line data 698 * For booting Linux, the board info and command line data
699 * have to be in the first 64 MB of memory, since this is 699 * have to be in the first 64 MB of memory, since this is
700 * the maximum mapped by the Linux kernel during initialization. 700 * the maximum mapped by the Linux kernel during initialization.
701 */ 701 */
702 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 702 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
703 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 703 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
704 704
705 #ifdef CONFIG_CMD_KGDB 705 #ifdef CONFIG_CMD_KGDB
706 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 706 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
707 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 707 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
708 #endif 708 #endif
709 709
710 /* 710 /*
711 * Environment Configuration 711 * Environment Configuration
712 */ 712 */
713 #define CONFIG_ROOTPATH "/opt/nfsroot" 713 #define CONFIG_ROOTPATH "/opt/nfsroot"
714 #define CONFIG_BOOTFILE "uImage" 714 #define CONFIG_BOOTFILE "uImage"
715 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ 715 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
716 716
717 /* default location for tftp and bootm */ 717 /* default location for tftp and bootm */
718 #define CONFIG_LOADADDR 1000000 718 #define CONFIG_LOADADDR 1000000
719 #define CONFIG_BAUDRATE 115200 719 #define CONFIG_BAUDRATE 115200
720 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 720 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
721 #define __USB_PHY_TYPE utmi 721 #define __USB_PHY_TYPE utmi
722 722
723 #define CONFIG_EXTRA_ENV_SETTINGS \ 723 #define CONFIG_EXTRA_ENV_SETTINGS \
724 "hwconfig=fsl_ddr:" \ 724 "hwconfig=fsl_ddr:" \
725 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ 725 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
726 "bank_intlv=auto;" \ 726 "bank_intlv=auto;" \
727 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 727 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
728 "netdev=eth0\0" \ 728 "netdev=eth0\0" \
729 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 729 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
730 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 730 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
731 "tftpflash=tftpboot $loadaddr $uboot && " \ 731 "tftpflash=tftpboot $loadaddr $uboot && " \
732 "protect off $ubootaddr +$filesize && " \ 732 "protect off $ubootaddr +$filesize && " \
733 "erase $ubootaddr +$filesize && " \ 733 "erase $ubootaddr +$filesize && " \
734 "cp.b $loadaddr $ubootaddr $filesize && " \ 734 "cp.b $loadaddr $ubootaddr $filesize && " \
735 "protect on $ubootaddr +$filesize && " \ 735 "protect on $ubootaddr +$filesize && " \
736 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 736 "cmp.b $loadaddr $ubootaddr $filesize\0" \
737 "consoledev=ttyS0\0" \ 737 "consoledev=ttyS0\0" \
738 "ramdiskaddr=2000000\0" \ 738 "ramdiskaddr=2000000\0" \
739 "ramdiskfile=t2080qds/ramdisk.uboot\0" \ 739 "ramdiskfile=t2080qds/ramdisk.uboot\0" \
740 "fdtaddr=c00000\0" \ 740 "fdtaddr=c00000\0" \
741 "fdtfile=t2080qds/t2080qds.dtb\0" \ 741 "fdtfile=t2080qds/t2080qds.dtb\0" \
742 "bdev=sda3\0" \ 742 "bdev=sda3\0" \
743 "c=ffe\0" 743 "c=ffe\0"
744 744
745 /* 745 /*
746 * For emulation this causes u-boot to jump to the start of the 746 * For emulation this causes u-boot to jump to the start of the
747 * proof point app code automatically 747 * proof point app code automatically
748 */ 748 */
749 #define CONFIG_PROOF_POINTS \ 749 #define CONFIG_PROOF_POINTS \
750 "setenv bootargs root=/dev/$bdev rw " \ 750 "setenv bootargs root=/dev/$bdev rw " \
751 "console=$consoledev,$baudrate $othbootargs;" \ 751 "console=$consoledev,$baudrate $othbootargs;" \
752 "cpu 1 release 0x29000000 - - -;" \ 752 "cpu 1 release 0x29000000 - - -;" \
753 "cpu 2 release 0x29000000 - - -;" \ 753 "cpu 2 release 0x29000000 - - -;" \
754 "cpu 3 release 0x29000000 - - -;" \ 754 "cpu 3 release 0x29000000 - - -;" \
755 "cpu 4 release 0x29000000 - - -;" \ 755 "cpu 4 release 0x29000000 - - -;" \
756 "cpu 5 release 0x29000000 - - -;" \ 756 "cpu 5 release 0x29000000 - - -;" \
757 "cpu 6 release 0x29000000 - - -;" \ 757 "cpu 6 release 0x29000000 - - -;" \
758 "cpu 7 release 0x29000000 - - -;" \ 758 "cpu 7 release 0x29000000 - - -;" \
759 "go 0x29000000" 759 "go 0x29000000"
760 760
761 #define CONFIG_HVBOOT \ 761 #define CONFIG_HVBOOT \
762 "setenv bootargs config-addr=0x60000000; " \ 762 "setenv bootargs config-addr=0x60000000; " \
763 "bootm 0x01000000 - 0x00f00000" 763 "bootm 0x01000000 - 0x00f00000"
764 764
765 #define CONFIG_ALU \ 765 #define CONFIG_ALU \
766 "setenv bootargs root=/dev/$bdev rw " \ 766 "setenv bootargs root=/dev/$bdev rw " \
767 "console=$consoledev,$baudrate $othbootargs;" \ 767 "console=$consoledev,$baudrate $othbootargs;" \
768 "cpu 1 release 0x01000000 - - -;" \ 768 "cpu 1 release 0x01000000 - - -;" \
769 "cpu 2 release 0x01000000 - - -;" \ 769 "cpu 2 release 0x01000000 - - -;" \
770 "cpu 3 release 0x01000000 - - -;" \ 770 "cpu 3 release 0x01000000 - - -;" \
771 "cpu 4 release 0x01000000 - - -;" \ 771 "cpu 4 release 0x01000000 - - -;" \
772 "cpu 5 release 0x01000000 - - -;" \ 772 "cpu 5 release 0x01000000 - - -;" \
773 "cpu 6 release 0x01000000 - - -;" \ 773 "cpu 6 release 0x01000000 - - -;" \
774 "cpu 7 release 0x01000000 - - -;" \ 774 "cpu 7 release 0x01000000 - - -;" \
775 "go 0x01000000" 775 "go 0x01000000"
776 776
777 #define CONFIG_LINUX \ 777 #define CONFIG_LINUX \
778 "setenv bootargs root=/dev/ram rw " \ 778 "setenv bootargs root=/dev/ram rw " \
779 "console=$consoledev,$baudrate $othbootargs;" \ 779 "console=$consoledev,$baudrate $othbootargs;" \
780 "setenv ramdiskaddr 0x02000000;" \ 780 "setenv ramdiskaddr 0x02000000;" \
781 "setenv fdtaddr 0x00c00000;" \ 781 "setenv fdtaddr 0x00c00000;" \
782 "setenv loadaddr 0x1000000;" \ 782 "setenv loadaddr 0x1000000;" \
783 "bootm $loadaddr $ramdiskaddr $fdtaddr" 783 "bootm $loadaddr $ramdiskaddr $fdtaddr"
784 784
785 #define CONFIG_HDBOOT \ 785 #define CONFIG_HDBOOT \
786 "setenv bootargs root=/dev/$bdev rw " \ 786 "setenv bootargs root=/dev/$bdev rw " \
787 "console=$consoledev,$baudrate $othbootargs;" \ 787 "console=$consoledev,$baudrate $othbootargs;" \
788 "tftp $loadaddr $bootfile;" \ 788 "tftp $loadaddr $bootfile;" \
789 "tftp $fdtaddr $fdtfile;" \ 789 "tftp $fdtaddr $fdtfile;" \
790 "bootm $loadaddr - $fdtaddr" 790 "bootm $loadaddr - $fdtaddr"
791 791
792 #define CONFIG_NFSBOOTCOMMAND \ 792 #define CONFIG_NFSBOOTCOMMAND \
793 "setenv bootargs root=/dev/nfs rw " \ 793 "setenv bootargs root=/dev/nfs rw " \
794 "nfsroot=$serverip:$rootpath " \ 794 "nfsroot=$serverip:$rootpath " \
795 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 795 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
796 "console=$consoledev,$baudrate $othbootargs;" \ 796 "console=$consoledev,$baudrate $othbootargs;" \
797 "tftp $loadaddr $bootfile;" \ 797 "tftp $loadaddr $bootfile;" \
798 "tftp $fdtaddr $fdtfile;" \ 798 "tftp $fdtaddr $fdtfile;" \
799 "bootm $loadaddr - $fdtaddr" 799 "bootm $loadaddr - $fdtaddr"
800 800
801 #define CONFIG_RAMBOOTCOMMAND \ 801 #define CONFIG_RAMBOOTCOMMAND \
802 "setenv bootargs root=/dev/ram rw " \ 802 "setenv bootargs root=/dev/ram rw " \
803 "console=$consoledev,$baudrate $othbootargs;" \ 803 "console=$consoledev,$baudrate $othbootargs;" \
804 "tftp $ramdiskaddr $ramdiskfile;" \ 804 "tftp $ramdiskaddr $ramdiskfile;" \
805 "tftp $loadaddr $bootfile;" \ 805 "tftp $loadaddr $bootfile;" \
806 "tftp $fdtaddr $fdtfile;" \ 806 "tftp $fdtaddr $fdtfile;" \
807 "bootm $loadaddr $ramdiskaddr $fdtaddr" 807 "bootm $loadaddr $ramdiskaddr $fdtaddr"
808 808
809 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 809 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
810 810
811 #ifdef CONFIG_SECURE_BOOT 811 #ifdef CONFIG_SECURE_BOOT
812 #include <asm/fsl_secure_boot.h> 812 #include <asm/fsl_secure_boot.h>
813 #undef CONFIG_CMD_USB 813 #undef CONFIG_CMD_USB
814 #endif 814 #endif
815 815
816 #endif /* __T208xQDS_H */ 816 #endif /* __T208xQDS_H */
817 817
include/configs/T208xRDB.h
Diff comments   View file @ 247161b
File was created 1 /*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 /*
8 * T2080 RDB/PCIe board configuration file
9 */
10
11 #ifndef __T2080RDB_H
12 #define __T2080RDB_H
13
14 #define CONFIG_T2080RDB
15 #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
16 #define CONFIG_MMC
17 #define CONFIG_SPI_FLASH
18 #define CONFIG_USB_EHCI
19 #define CONFIG_FSL_SATA_V2
20
21 /* High Level Configuration Options */
22 #define CONFIG_PHYS_64BIT
23 #define CONFIG_BOOKE
24 #define CONFIG_E500 /* BOOKE e500 family */
25 #define CONFIG_E500MC /* BOOKE e500mc family */
26 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
27 #define CONFIG_MP /* support multiple processors */
28 #define CONFIG_ENABLE_36BIT_PHYS
29
30 #ifdef CONFIG_PHYS_64BIT
31 #define CONFIG_ADDR_MAP 1
32 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
33 #endif
34
35 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
36 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
37 #define CONFIG_FSL_IFC /* Enable IFC Support */
38 #define CONFIG_FSL_LAW /* Use common FSL init code */
39 #define CONFIG_ENV_OVERWRITE
40
41 #ifdef CONFIG_RAMBOOT_PBL
42 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
43 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
44 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xrdb/t2080_pbi.cfg
45 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xrdb/t2080_rcw.cfg
46 #endif
47
48 #define CONFIG_SRIO_PCIE_BOOT_MASTER
49 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
50 /* Set 1M boot space */
51 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
52 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
53 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
54 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
55 #define CONFIG_SYS_NO_FLASH
56 #endif
57
58 #ifndef CONFIG_SYS_TEXT_BASE
59 #define CONFIG_SYS_TEXT_BASE 0xeff40000
60 #endif
61
62 #ifndef CONFIG_RESET_VECTOR_ADDRESS
63 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
64 #endif
65
66 /*
67 * These can be toggled for performance analysis, otherwise use default.
68 */
69 #define CONFIG_SYS_CACHE_STASHING
70 #define CONFIG_BTB /* toggle branch predition */
71 #define CONFIG_DDR_ECC
72 #ifdef CONFIG_DDR_ECC
73 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
74 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
75 #endif
76
77 #ifdef CONFIG_SYS_NO_FLASH
78 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
79 #define CONFIG_ENV_IS_NOWHERE
80 #endif
81 #else
82 #define CONFIG_FLASH_CFI_DRIVER
83 #define CONFIG_SYS_FLASH_CFI
84 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
85 #endif
86
87 #if defined(CONFIG_SPIFLASH)
88 #define CONFIG_SYS_EXTRA_ENV_RELOC
89 #define CONFIG_ENV_IS_IN_SPI_FLASH
90 #define CONFIG_ENV_SPI_BUS 0
91 #define CONFIG_ENV_SPI_CS 0
92 #define CONFIG_ENV_SPI_MAX_HZ 10000000
93 #define CONFIG_ENV_SPI_MODE 0
94 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
95 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
96 #define CONFIG_ENV_SECT_SIZE 0x10000
97 #elif defined(CONFIG_SDCARD)
98 #define CONFIG_SYS_EXTRA_ENV_RELOC
99 #define CONFIG_ENV_IS_IN_MMC
100 #define CONFIG_SYS_MMC_ENV_DEV 0
101 #define CONFIG_ENV_SIZE 0x2000
102 #define CONFIG_ENV_OFFSET (512 * 1658)
103 #elif defined(CONFIG_NAND)
104 #define CONFIG_SYS_EXTRA_ENV_RELOC
105 #define CONFIG_ENV_IS_IN_NAND
106 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
107 #define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
108 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
109 #define CONFIG_ENV_IS_IN_REMOTE
110 #define CONFIG_ENV_ADDR 0xffe20000
111 #define CONFIG_ENV_SIZE 0x2000
112 #elif defined(CONFIG_ENV_IS_NOWHERE)
113 #define CONFIG_ENV_SIZE 0x2000
114 #else
115 #define CONFIG_ENV_IS_IN_FLASH
116 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
117 #define CONFIG_ENV_SIZE 0x2000
118 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
119 #endif
120
121 #ifndef __ASSEMBLY__
122 unsigned long get_board_sys_clk(void);
123 unsigned long get_board_ddr_clk(void);
124 #endif
125
126 #define CONFIG_SYS_CLK_FREQ 66660000
127 #define CONFIG_DDR_CLK_FREQ 133330000
128
129 /*
130 * Config the L3 Cache as L3 SRAM
131 */
132 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
133
134 #define CONFIG_SYS_DCSRBAR 0xf0000000
135 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
136
137 /* EEPROM */
138 #define CONFIG_ID_EEPROM
139 #define CONFIG_SYS_I2C_EEPROM_NXID
140 #define CONFIG_SYS_EEPROM_BUS_NUM 0
141 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
142 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
143
144 /*
145 * DDR Setup
146 */
147 #define CONFIG_VERY_BIG_RAM
148 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
149 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
150 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
151 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
152 #define CONFIG_DDR_SPD
153 #define CONFIG_SYS_FSL_DDR3
154 #undef CONFIG_FSL_DDR_INTERACTIVE
155 #define CONFIG_SYS_SPD_BUS_NUM 0
156 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
157 #define SPD_EEPROM_ADDRESS1 0x51
158 #define SPD_EEPROM_ADDRESS2 0x52
159 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
160 #define CTRL_INTLV_PREFERED cacheline
161
162 /*
163 * IFC Definitions
164 */
165 #define CONFIG_SYS_FLASH_BASE 0xe8000000
166 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
167 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
168 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
169 CSPR_PORT_SIZE_16 | \
170 CSPR_MSEL_NOR | \
171 CSPR_V)
172 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
173
174 /* NOR Flash Timing Params */
175 #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
176
177 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
178 FTIM0_NOR_TEADC(0x5) | \
179 FTIM0_NOR_TEAHC(0x5))
180 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
181 FTIM1_NOR_TRAD_NOR(0x1A) |\
182 FTIM1_NOR_TSEQRAD_NOR(0x13))
183 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
184 FTIM2_NOR_TCH(0x4) | \
185 FTIM2_NOR_TWPH(0x0E) | \
186 FTIM2_NOR_TWP(0x1c))
187 #define CONFIG_SYS_NOR_FTIM3 0x0
188
189 #define CONFIG_SYS_FLASH_QUIET_TEST
190 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
191
192 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
193 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
194 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
195 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
196 #define CONFIG_SYS_FLASH_EMPTY_INFO
197 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
198
199 /* CPLD on IFC */
200 #define CONFIG_SYS_CPLD_BASE 0xffdf0000
201 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
202 #define CONFIG_SYS_CSPR2_EXT (0xf)
203 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
204 | CSPR_PORT_SIZE_8 \
205 | CSPR_MSEL_GPCM \
206 | CSPR_V)
207 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
208 #define CONFIG_SYS_CSOR2 0x0
209
210 /* CPLD Timing parameters for IFC CS2 */
211 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
212 FTIM0_GPCM_TEADC(0x0e) | \
213 FTIM0_GPCM_TEAHC(0x0e))
214 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
215 FTIM1_GPCM_TRAD(0x1f))
216 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
217 FTIM2_GPCM_TCH(0x0) | \
218 FTIM2_GPCM_TWP(0x1f))
219 #define CONFIG_SYS_CS2_FTIM3 0x0
220
221 /* NAND Flash on IFC */
222 #define CONFIG_NAND_FSL_IFC
223 #define CONFIG_SYS_NAND_BASE 0xff800000
224 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
225
226 #define CONFIG_SYS_NAND_CSPR_EXT (0xf)
227 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
228 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
229 | CSPR_MSEL_NAND /* MSEL = NAND */ \
230 | CSPR_V)
231 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
232
233 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
234 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
235 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
236 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
237 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
238 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
239 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
240
241 #define CONFIG_SYS_NAND_ONFI_DETECTION
242
243 /* ONFI NAND Flash mode0 Timing Params */
244 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
245 FTIM0_NAND_TWP(0x18) | \
246 FTIM0_NAND_TWCHT(0x07) | \
247 FTIM0_NAND_TWH(0x0a))
248 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
249 FTIM1_NAND_TWBE(0x39) | \
250 FTIM1_NAND_TRR(0x0e) | \
251 FTIM1_NAND_TRP(0x18))
252 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
253 FTIM2_NAND_TREH(0x0a) | \
254 FTIM2_NAND_TWHRE(0x1e))
255 #define CONFIG_SYS_NAND_FTIM3 0x0
256
257 #define CONFIG_SYS_NAND_DDR_LAW 11
258 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
259 #define CONFIG_SYS_MAX_NAND_DEVICE 1
260 #define CONFIG_MTD_NAND_VERIFY_WRITE
261 #define CONFIG_CMD_NAND
262 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
263
264 #if defined(CONFIG_NAND)
265 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
266 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
267 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
268 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
269 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
270 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
271 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
272 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
273 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
274 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
275 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
276 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
277 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
278 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
279 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
280 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
281 #else
282 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
283 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
284 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
285 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
286 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
287 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
288 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
289 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
290 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
291 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
292 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
293 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
294 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
295 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
296 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
297 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
298 #endif
299
300 #if defined(CONFIG_RAMBOOT_PBL)
301 #define CONFIG_SYS_RAMBOOT
302 #endif
303
304 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
305 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
306 #define CONFIG_MISC_INIT_R
307 #define CONFIG_HWCONFIG
308
309 /* define to use L1 as initial stack */
310 #define CONFIG_L1_INIT_RAM
311 #define CONFIG_SYS_INIT_RAM_LOCK
312 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
313 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
315 /* The assembler doesn't like typecast */
316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
317 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
318 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
319 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
320 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
321 GENERATED_GBL_DATA_SIZE)
322 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
323 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
324 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
325
326 /*
327 * Serial Port
328 */
329 #define CONFIG_CONS_INDEX 1
330 #define CONFIG_SYS_NS16550
331 #define CONFIG_SYS_NS16550_SERIAL
332 #define CONFIG_SYS_NS16550_REG_SIZE 1
333 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
334 #define CONFIG_SYS_BAUDRATE_TABLE \
335 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
336 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
337 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
338 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
339 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
340
341 /* Use the HUSH parser */
342 #define CONFIG_SYS_HUSH_PARSER
343 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
344
345 /* pass open firmware flat tree */
346 #define CONFIG_OF_LIBFDT
347 #define CONFIG_OF_BOARD_SETUP
348 #define CONFIG_OF_STDOUT_VIA_ALIAS
349
350 /* new uImage format support */
351 #define CONFIG_FIT
352 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
353
354 /*
355 * I2C
356 */
357 #define CONFIG_SYS_I2C
358 #define CONFIG_SYS_I2C_FSL
359 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
360 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
361 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
362 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
363 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
364 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
365 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
366 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
367 #define CONFIG_SYS_FSL_I2C_SPEED 100000
368 #define CONFIG_SYS_FSL_I2C2_SPEED 100000
369 #define CONFIG_SYS_FSL_I2C3_SPEED 100000
370 #define CONFIG_SYS_FSL_I2C4_SPEED 100000
371 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
372 #define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
373 #define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
374 #define I2C_MUX_CH_DEFAULT 0x8
375
376
377 /*
378 * RapidIO
379 */
380 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
381 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
382 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
383 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
384 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
385 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
386 /*
387 * for slave u-boot IMAGE instored in master memory space,
388 * PHYS must be aligned based on the SIZE
389 */
390 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
391 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
392 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
393 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
394 /*
395 * for slave UCODE and ENV instored in master memory space,
396 * PHYS must be aligned based on the SIZE
397 */
398 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
399 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
400 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
401
402 /* slave core release by master*/
403 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
404 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
405
406 /*
407 * SRIO_PCIE_BOOT - SLAVE
408 */
409 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
410 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
411 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
412 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
413 #endif
414
415 /*
416 * eSPI - Enhanced SPI
417 */
418 #ifdef CONFIG_SPI_FLASH
419 #define CONFIG_FSL_ESPI
420 #define CONFIG_SPI_FLASH_STMICRO
421 #define CONFIG_SPI_FLASH_BAR
422 #define CONFIG_CMD_SF
423 #define CONFIG_SF_DEFAULT_SPEED 10000000
424 #define CONFIG_SF_DEFAULT_MODE 0
425 #endif
426
427 /*
428 * General PCI
429 * Memory space is mapped 1-1, but I/O space must start from 0.
430 */
431 #define CONFIG_PCI /* Enable PCI/PCIE */
432 #define CONFIG_PCIE1 /* PCIE controler 1 */
433 #define CONFIG_PCIE2 /* PCIE controler 2 */
434 #define CONFIG_PCIE3 /* PCIE controler 3 */
435 #define CONFIG_PCIE4 /* PCIE controler 4 */
436 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
437 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
438 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
439 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
440 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
441 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
442 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
443 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
444 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
445 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
446 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
447
448 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
449 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
450 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
451 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
452 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
453 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
454 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
455 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
456 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
457
458 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
459 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
460 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
461 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
462 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
463 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
464 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
465 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
466 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
467
468 /* controller 4, Base address 203000 */
469 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
470 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
471 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
472 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
473 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
474 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
475 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
476
477 #ifdef CONFIG_PCI
478 #define CONFIG_PCI_INDIRECT_BRIDGE
479 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
480 #define CONFIG_NET_MULTI
481 #define CONFIG_E1000
482 #define CONFIG_PCI_PNP /* do pci plug-and-play */
483 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
484 #define CONFIG_DOS_PARTITION
485 #endif
486
487 /* Qman/Bman */
488 #ifndef CONFIG_NOBQFMAN
489 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
490 #define CONFIG_SYS_BMAN_NUM_PORTALS 18
491 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
492 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
493 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
494 #define CONFIG_SYS_QMAN_NUM_PORTALS 18
495 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
496 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
497 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
498
499 #define CONFIG_SYS_DPAA_FMAN
500 #define CONFIG_SYS_DPAA_PME
501 #define CONFIG_SYS_PMAN
502 #define CONFIG_SYS_DPAA_DCE
503 #define CONFIG_SYS_DPAA_RMAN /* RMan */
504 #define CONFIG_SYS_INTERLAKEN
505
506 /* Default address of microcode for the Linux Fman driver */
507 #if defined(CONFIG_SPIFLASH)
508 /*
509 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
510 * env, so we got 0x110000.
511 */
512 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
513 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
514 #define CONFIG_CORTINA_FW_ADDR 0x120000
515
516 #elif defined(CONFIG_SDCARD)
517 /*
518 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
519 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
520 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
521 */
522 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
523 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
524 #define CONFIG_CORTINA_FW_ADDR (512 * 1808)
525
526 #elif defined(CONFIG_NAND)
527 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
528 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
529 #define CONFIG_CORTINA_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
530 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
531 /*
532 * Slave has no ucode locally, it can fetch this from remote. When implementing
533 * in two corenet boards, slave's ucode could be stored in master's memory
534 * space, the address can be mapped from slave TLB->slave LAW->
535 * slave SRIO or PCIE outbound window->master inbound window->
536 * master LAW->the ucode address in master's memory space.
537 */
538 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
539 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
540 #define CONFIG_CORTINA_FW_ADDR 0xFFE10000
541 #else
542 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
543 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
544 #define CONFIG_CORTINA_FW_ADDR 0xEFE00000
545 #endif
546 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
547 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
548 #endif /* CONFIG_NOBQFMAN */
549
550 #ifdef CONFIG_SYS_DPAA_FMAN
551 #define CONFIG_FMAN_ENET
552 #define CONFIG_PHYLIB_10G
553 #define CONFIG_PHY_CORTINA
554 #define CONFIG_PHY_AQ1202
555 #define CONFIG_PHY_REALTEK
556 #define CONFIG_CORTINA_FW_LENGTH 0x40000
557 #define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
558 #define RGMII_PHY2_ADDR 0x02
559 #define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
560 #define CORTINA_PHY_ADDR2 0x0d
561 #define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
562 #define FM1_10GEC4_PHY_ADDR 0x01
563 #endif
564
565
566 #ifdef CONFIG_FMAN_ENET
567 #define CONFIG_MII /* MII PHY management */
568 #define CONFIG_ETHPRIME "FM1@DTSEC3"
569 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
570 #endif
571
572 /*
573 * SATA
574 */
575 #ifdef CONFIG_FSL_SATA_V2
576 #define CONFIG_LIBATA
577 #define CONFIG_FSL_SATA
578 #define CONFIG_SYS_SATA_MAX_DEVICE 2
579 #define CONFIG_SATA1
580 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
581 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
582 #define CONFIG_SATA2
583 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
584 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
585 #define CONFIG_LBA48
586 #define CONFIG_CMD_SATA
587 #define CONFIG_DOS_PARTITION
588 #define CONFIG_CMD_EXT2
589 #endif
590
591 /*
592 * USB
593 */
594 #ifdef CONFIG_USB_EHCI
595 #define CONFIG_CMD_USB
596 #define CONFIG_USB_STORAGE
597 #define CONFIG_USB_EHCI_FSL
598 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
599 #define CONFIG_CMD_EXT2
600 #define CONFIG_HAS_FSL_DR_USB
601 #endif
602
603 /*
604 * SDHC
605 */
606 #ifdef CONFIG_MMC
607 #define CONFIG_CMD_MMC
608 #define CONFIG_FSL_ESDHC
609 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
610 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
611 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
612 #define CONFIG_GENERIC_MMC
613 #define CONFIG_CMD_EXT2
614 #define CONFIG_CMD_FAT
615 #define CONFIG_DOS_PARTITION
616 #endif
617
618 /*
619 * Environment
620 */
621
622 /*
623 * Command line configuration.
624 */
625 #include <config_cmd_default.h>
626
627 #define CONFIG_CMD_DHCP
628 #define CONFIG_CMD_ELF
629 #define CONFIG_CMD_MII
630 #define CONFIG_CMD_I2C
631 #define CONFIG_CMD_PING
632 #define CONFIG_CMD_ECHO
633 #define CONFIG_CMD_SETEXPR
634 #define CONFIG_CMD_REGINFO
635 #define CONFIG_CMD_BDI
636
637 #ifdef CONFIG_PCI
638 #define CONFIG_CMD_PCI
639 #define CONFIG_CMD_NET
640 #endif
641
642 /*
643 * Miscellaneous configurable options
644 */
645 #define CONFIG_SYS_LONGHELP /* undef to save memory */
646 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
647 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
648 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
649 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
650 #ifdef CONFIG_CMD_KGDB
651 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
652 #else
653 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
654 #endif
655 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
656 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
657 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
658 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
659
660 /*
661 * For booting Linux, the board info and command line data
662 * have to be in the first 64 MB of memory, since this is
663 * the maximum mapped by the Linux kernel during initialization.
664 */
665 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
666 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
667
668 #ifdef CONFIG_CMD_KGDB
669 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
670 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
671 #endif
672
673 /*
674 * Environment Configuration
675 */
676 #define CONFIG_ROOTPATH "/opt/nfsroot"
677 #define CONFIG_BOOTFILE "uImage"
678 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
679
680 /* default location for tftp and bootm */
681 #define CONFIG_LOADADDR 1000000
682 #define CONFIG_BAUDRATE 115200
683 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
684 #define __USB_PHY_TYPE utmi
685
686 #define CONFIG_EXTRA_ENV_SETTINGS \
687 "hwconfig=fsl_ddr:" \
688 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
689 "bank_intlv=auto;" \
690 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
691 "netdev=eth0\0" \
692 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
693 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
694 "tftpflash=tftpboot $loadaddr $uboot && " \
695 "protect off $ubootaddr +$filesize && " \
696 "erase $ubootaddr +$filesize && " \
697 "cp.b $loadaddr $ubootaddr $filesize && " \
698 "protect on $ubootaddr +$filesize && " \
699 "cmp.b $loadaddr $ubootaddr $filesize\0" \
700 "consoledev=ttyS0\0" \
701 "ramdiskaddr=2000000\0" \
702 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
703 "fdtaddr=c00000\0" \
704 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
705 "bdev=sda3\0" \
706 "c=ffe\0"
707
708 /*
709 * For emulation this causes u-boot to jump to the start of the
710 * proof point app code automatically
711 */
712 #define CONFIG_PROOF_POINTS \
713 "setenv bootargs root=/dev/$bdev rw " \
714 "console=$consoledev,$baudrate $othbootargs;" \
715 "cpu 1 release 0x29000000 - - -;" \
716 "cpu 2 release 0x29000000 - - -;" \
717 "cpu 3 release 0x29000000 - - -;" \
718 "cpu 4 release 0x29000000 - - -;" \
719 "cpu 5 release 0x29000000 - - -;" \
720 "cpu 6 release 0x29000000 - - -;" \
721 "cpu 7 release 0x29000000 - - -;" \
722 "go 0x29000000"
723
724 #define CONFIG_HVBOOT \
725 "setenv bootargs config-addr=0x60000000; " \
726 "bootm 0x01000000 - 0x00f00000"
727
728 #define CONFIG_ALU \
729 "setenv bootargs root=/dev/$bdev rw " \
730 "console=$consoledev,$baudrate $othbootargs;" \
731 "cpu 1 release 0x01000000 - - -;" \
732 "cpu 2 release 0x01000000 - - -;" \
733 "cpu 3 release 0x01000000 - - -;" \
734 "cpu 4 release 0x01000000 - - -;" \
735 "cpu 5 release 0x01000000 - - -;" \
736 "cpu 6 release 0x01000000 - - -;" \
737 "cpu 7 release 0x01000000 - - -;" \
738 "go 0x01000000"
739
740 #define CONFIG_LINUX \
741 "setenv bootargs root=/dev/ram rw " \
742 "console=$consoledev,$baudrate $othbootargs;" \
743 "setenv ramdiskaddr 0x02000000;" \
744 "setenv fdtaddr 0x00c00000;" \
745 "setenv loadaddr 0x1000000;" \
746 "bootm $loadaddr $ramdiskaddr $fdtaddr"
747
748 #define CONFIG_HDBOOT \
749 "setenv bootargs root=/dev/$bdev rw " \
750 "console=$consoledev,$baudrate $othbootargs;" \
751 "tftp $loadaddr $bootfile;" \
752 "tftp $fdtaddr $fdtfile;" \
753 "bootm $loadaddr - $fdtaddr"
754
755 #define CONFIG_NFSBOOTCOMMAND \
756 "setenv bootargs root=/dev/nfs rw " \
757 "nfsroot=$serverip:$rootpath " \
758 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
759 "console=$consoledev,$baudrate $othbootargs;" \
760 "tftp $loadaddr $bootfile;" \
761 "tftp $fdtaddr $fdtfile;" \
762 "bootm $loadaddr - $fdtaddr"
763
764 #define CONFIG_RAMBOOTCOMMAND \
765 "setenv bootargs root=/dev/ram rw " \
766 "console=$consoledev,$baudrate $othbootargs;" \
767 "tftp $ramdiskaddr $ramdiskfile;" \
768 "tftp $loadaddr $bootfile;" \
769 "tftp $fdtaddr $fdtfile;" \
770 "bootm $loadaddr $ramdiskaddr $fdtaddr"
771
772 #define CONFIG_BOOTCOMMAND CONFIG_LINUX
773
774 #ifdef CONFIG_SECURE_BOOT
775 #include <asm/fsl_secure_boot.h>
776 #undef CONFIG_CMD_USB
777 #endif
778
779 #endif /* __T2080RDB_H */
780
1 /* 1 /*
2 * Freescale USB Controller 2 * Freescale USB Controller
3 * 3 *
4 * Copyright 2013 Freescale Semiconductor, Inc. 4 * Copyright 2013 Freescale Semiconductor, Inc.
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 */ 7 */
8 8
9 #ifndef _ASM_FSL_USB_H_ 9 #ifndef _ASM_FSL_USB_H_
10 #define _ASM_FSL_USB_H_ 10 #define _ASM_FSL_USB_H_
11 11
12 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE 12 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
13 struct ccsr_usb_port_ctrl { 13 struct ccsr_usb_port_ctrl {
14 u32 ctrl; 14 u32 ctrl;
15 u32 drvvbuscfg; 15 u32 drvvbuscfg;
16 u32 pwrfltcfg; 16 u32 pwrfltcfg;
17 u32 sts; 17 u32 sts;
18 u8 res_14[0xc]; 18 u8 res_14[0xc];
19 u32 bistcfg; 19 u32 bistcfg;
20 u32 biststs; 20 u32 biststs;
21 u32 abistcfg; 21 u32 abistcfg;
22 u32 abiststs; 22 u32 abiststs;
23 u8 res_30[0x10]; 23 u8 res_30[0x10];
24 u32 xcvrprg; 24 u32 xcvrprg;
25 u32 anaprg; 25 u32 anaprg;
26 u32 anadrv; 26 u32 anadrv;
27 u32 anasts; 27 u32 anasts;
28 }; 28 };
29 29
30 struct ccsr_usb_phy { 30 struct ccsr_usb_phy {
31 u32 id; 31 u32 id;
32 struct ccsr_usb_port_ctrl port1; 32 struct ccsr_usb_port_ctrl port1;
33 u8 res_50[0xc]; 33 u8 res_50[0xc];
34 u32 tvr; 34 u32 tvr;
35 u32 pllprg[4]; 35 u32 pllprg[4];
36 u8 res_70[0x4]; 36 u8 res_70[0x4];
37 u32 anaccfg; 37 u32 anaccfg;
38 u32 dbg; 38 u32 dbg;
39 u8 res_7c[0x4]; 39 u8 res_7c[0x4];
40 struct ccsr_usb_port_ctrl port2; 40 struct ccsr_usb_port_ctrl port2;
41 u8 res_dc[0x334]; 41 u8 res_dc[0x334];
42 }; 42 };
43 43
44 #define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0) 44 #define CONFIG_SYS_FSL_USB_CTRL_PHY_EN (1 << 0)
45 #define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1) 45 #define CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN (1 << 1)
46 #define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1) 46 #define CONFIG_SYS_FSL_USB_PWRFLT_CR_EN (1 << 1)
47 #define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0) 47 #define CONFIG_SYS_FSL_USB_PLLPRG1_PHY_DIV (1 << 0)
48 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0) 48 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN (1 << 0)
49 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1) 49 #define CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN (1 << 1)
50 #define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13) 50 #define CONFIG_SYS_FSL_USB_PLLPRG2_FRAC_LPF_EN (1 << 13)
51 #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4) 51 #define CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV (1 << 4)
52 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16) 52 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
53 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21) 53 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
54 #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0) 54 #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
55 #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
56 #define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
57
58 #define INC_DCNT_THRESHOLD_25MV (0 << 4)
59 #define INC_DCNT_THRESHOLD_50MV (1 << 4)
60 #define DEC_DCNT_THRESHOLD_25MV (2 << 4)
61 #define DEC_DCNT_THRESHOLD_50MV (3 << 4)
55 #else 62 #else
56 struct ccsr_usb_phy { 63 struct ccsr_usb_phy {
57 u8 res0[0x18]; 64 u32 config1;
65 u32 config2;
66 u32 config3;
67 u32 config4;
68 u32 config5;
69 u32 status1;
58 u32 usb_enable_override; 70 u32 usb_enable_override;
59 u8 res[0xe4]; 71 u8 res[0xe4];
60 }; 72 };
61 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 73 #define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
74 #define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
75 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
76 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
77 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
78 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
79 #define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
80 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
62 #endif 81 #endif
63 82
64 #endif /*_ASM_FSL_USB_H_ */ 83 #endif /*_ASM_FSL_USB_H_ */
65 84