Eric Lee / smarc-uboot

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Commit 247161b8160fc699b0a517f081220bb50bc502a8

Authored by Tom Rini
2 parents d57d60cf24 96ac18c9cc
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

Showing 38 changed files Side-by-side Diff

arch/powerpc/cpu/mpc85xx/b4860_serdes.c
Diff comments   View file @ 247161b
... ... @@ -18,12 +18,32 @@
18 18 #ifdef CONFIG_PPC_B4860
19 19 static struct serdes_config serdes1_cfg_tbl[] = {
20 20 /* SerDes 1 */
  21 + {0x02, {AURORA, AURORA, CPRI6, CPRI5,
  22 + CPRI4, CPRI3, CPRI2, CPRI1} },
  23 + {0x04, {AURORA, AURORA, CPRI6, CPRI5,
  24 + CPRI4, CPRI3, CPRI2, CPRI1} },
  25 + {0x05, {AURORA, AURORA, CPRI6, CPRI5,
  26 + CPRI4, CPRI3, CPRI2, CPRI1} },
  27 + {0x06, {AURORA, AURORA, CPRI6, CPRI5,
  28 + CPRI4, CPRI3, CPRI2, CPRI1} },
  29 + {0x08, {AURORA, AURORA, CPRI6, CPRI5,
  30 + CPRI4, CPRI3, CPRI2, CPRI1} },
  31 + {0x09, {AURORA, AURORA, CPRI6, CPRI5,
  32 + CPRI4, CPRI3, CPRI2, CPRI1} },
  33 + {0x0A, {AURORA, AURORA, CPRI6, CPRI5,
  34 + CPRI4, CPRI3, CPRI2, CPRI1} },
  35 + {0x0B, {AURORA, AURORA, CPRI6, CPRI5,
  36 + CPRI4, CPRI3, CPRI2, CPRI1} },
  37 + {0x0C, {AURORA, AURORA, CPRI6, CPRI5,
  38 + CPRI4, CPRI3, CPRI2, CPRI1} },
21 39 {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
22 40 CPRI4, CPRI3, CPRI2, CPRI1}},
23 41 {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
24 42 CPRI4, CPRI3, CPRI2, CPRI1}},
25 43 {0x12, {CPRI8, CPRI7, CPRI6, CPRI5,
26 44 CPRI4, CPRI3, CPRI2, CPRI1}},
  45 + {0x29, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
  46 + CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1} },
27 47 {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
28 48 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
29 49 {0x2C, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
... ... @@ -32,6 +52,9 @@
32 52 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
33 53 {0x2E, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
34 54 CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}},
  55 + {0x2F, {AURORA, AURORA,
  56 + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  57 + CPRI4, CPRI3, CPRI2, CPRI1} },
35 58 {0x30, {AURORA, AURORA,
36 59 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
37 60 CPRI4, CPRI3, CPRI2, CPRI1}},
38 61  
39 62  
40 63  
... ... @@ -44,18 +67,38 @@
44 67 {0x34, {AURORA, AURORA,
45 68 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
46 69 CPRI4, CPRI3, CPRI2, CPRI1}},
  70 + {0x39, {AURORA, AURORA, CPRI6, CPRI5,
  71 + CPRI4, CPRI3, CPRI2, CPRI1} },
  72 + {0x3A, {AURORA, AURORA, CPRI6, CPRI5,
  73 + CPRI4, CPRI3, CPRI2, CPRI1} },
  74 + {0x3C, {AURORA, AURORA, CPRI6, CPRI5,
  75 + CPRI4, CPRI3, CPRI2, CPRI1} },
  76 + {0x3D, {AURORA, AURORA, CPRI6, CPRI5,
  77 + CPRI4, CPRI3, CPRI2, CPRI1} },
47 78 {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
48 79 CPRI4, CPRI3, CPRI2, CPRI1}},
  80 + {0x5C, {AURORA, AURORA,
  81 + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  82 + CPRI4, CPRI3, CPRI2, CPRI1} },
  83 + {0x5D, {AURORA, AURORA,
  84 + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  85 + CPRI4, CPRI3, CPRI2, CPRI1} },
49 86 {}
50 87 };
51 88 static struct serdes_config serdes2_cfg_tbl[] = {
52 89 /* SerDes 2 */
  90 + {0x17, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  91 + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  92 + AURORA, AURORA, SRIO1, SRIO1} },
53 93 {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
54 94 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
55 95 AURORA, AURORA, SRIO1, SRIO1}},
56 96 {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
57 97 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
58 98 AURORA, AURORA, SRIO1, SRIO1}},
  99 + {0x2A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  100 + SRIO2, SRIO2,
  101 + AURORA, AURORA, SRIO1, SRIO1} },
59 102 {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
60 103 SRIO2, SRIO2,
61 104 AURORA, AURORA, SRIO1, SRIO1}},
... ... @@ -63,6 +106,9 @@
63 106 SRIO2, SRIO2,
64 107 AURORA, AURORA,
65 108 SRIO1, SRIO1}},
  109 + {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  110 + SGMII_FM1_DTSEC3, AURORA,
  111 + SRIO1, SRIO1, SRIO1, SRIO1} },
66 112 {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
67 113 SGMII_FM1_DTSEC3, AURORA,
68 114 SRIO1, SRIO1, SRIO1, SRIO1}},
69 115  
70 116  
71 117  
... ... @@ -75,18 +121,30 @@
75 121 {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
76 122 SGMII_FM1_DTSEC3, AURORA,
77 123 SRIO1, SRIO1, SRIO1, SRIO1}},
  124 + {0x79, {SRIO2, SRIO2, SRIO2, SRIO2,
  125 + SRIO1, SRIO1, SRIO1, SRIO1} },
78 126 {0x7A, {SRIO2, SRIO2, SRIO2, SRIO2,
79 127 SRIO1, SRIO1, SRIO1, SRIO1}},
  128 + {0x83, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  129 + SRIO2, SRIO2, AURORA, AURORA,
  130 + XFI_FM1_MAC9, XFI_FM1_MAC10} },
80 131 {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
81 132 SRIO2, SRIO2, AURORA, AURORA,
82 133 XFI_FM1_MAC9, XFI_FM1_MAC10}},
83 134 {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
84 135 SRIO2, SRIO2, AURORA, AURORA,
85 136 XFI_FM1_MAC9, XFI_FM1_MAC10}},
  137 + {0x86, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
  138 + SRIO2, SRIO2,
  139 + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  140 + XFI_FM1_MAC9, XFI_FM1_MAC10} },
86 141 {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
87 142 SRIO2, SRIO2,
88 143 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
89 144 XFI_FM1_MAC9, XFI_FM1_MAC10}},
  145 + {0x8C, {SRIO2, SRIO2, SRIO2, SRIO2,
  146 + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  147 + XFI_FM1_MAC9, XFI_FM1_MAC10} },
90 148 {0x8D, {SRIO2, SRIO2, SRIO2, SRIO2,
91 149 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
92 150 XFI_FM1_MAC9, XFI_FM1_MAC10}},
... ... @@ -101,6 +159,9 @@
101 159 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
102 160 XAUI_FM1_MAC10, XAUI_FM1_MAC10,
103 161 XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
  162 + {0xB1, {PCIE1, PCIE1, PCIE1, PCIE1,
  163 + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
  164 + XFI_FM1_MAC9, XFI_FM1_MAC10} },
104 165 {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1,
105 166 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
106 167 XFI_FM1_MAC9, XFI_FM1_MAC10}},
arch/powerpc/cpu/mpc85xx/cmd_errata.c
Diff comments   View file @ 247161b
... ... @@ -229,6 +229,14 @@
229 229 if (IS_SVR_REV(svr, 1, 0))
230 230 puts("Work-around for Erratum A005871 enabled\n");
231 231 #endif
  232 +#ifdef CONFIG_SYS_FSL_ERRATUM_A006475
  233 + if (SVR_MAJ(get_svr()) == 1)
  234 + puts("Work-around for Erratum A006475 enabled\n");
  235 +#endif
  236 +#ifdef CONFIG_SYS_FSL_ERRATUM_A006384
  237 + if (SVR_MAJ(get_svr()) == 1)
  238 + puts("Work-around for Erratum A006384 enabled\n");
  239 +#endif
232 240 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
233 241 /* This work-around is implemented in PBI, so just check for it */
234 242 check_erratum_a4849(svr);
... ... @@ -264,6 +272,10 @@
264 272 if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
265 273 (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
266 274 puts("Work-around for Erratum I2C-A004447 enabled\n");
  275 +#endif
  276 +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  277 + if (has_erratum_a006261())
  278 + puts("Work-around for Erratum A006261 enabled\n");
267 279 #endif
268 280 return 0;
269 281 }
arch/powerpc/cpu/mpc85xx/cpu_init.c
Diff comments   View file @ 247161b
... ... @@ -36,6 +36,54 @@
36 36  
37 37 DECLARE_GLOBAL_DATA_PTR;
38 38  
  39 +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  40 +void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
  41 +{
  42 +#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
  43 + u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
  44 +
  45 + /* Increase Disconnect Threshold by 50mV */
  46 + xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  47 + INC_DCNT_THRESHOLD_50MV;
  48 + /* Enable programming of USB High speed Disconnect threshold */
  49 + xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  50 + out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
  51 +
  52 + xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
  53 + /* Increase Disconnect Threshold by 50mV */
  54 + xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
  55 + INC_DCNT_THRESHOLD_50MV;
  56 + /* Enable programming of USB High speed Disconnect threshold */
  57 + xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
  58 + out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
  59 +#else
  60 +
  61 + u32 temp = 0;
  62 + u32 status = in_be32(&usb_phy->status1);
  63 +
  64 + u32 squelch_prog_rd_0_2 =
  65 + (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
  66 + & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
  67 +
  68 + u32 squelch_prog_rd_3_5 =
  69 + (status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
  70 + & CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
  71 +
  72 + setbits_be32(&usb_phy->config1,
  73 + CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
  74 + setbits_be32(&usb_phy->config2,
  75 + CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
  76 +
  77 + temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
  78 + out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
  79 +
  80 + temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
  81 + out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
  82 +#endif
  83 +}
  84 +#endif
  85 +
  86 +
39 87 #ifdef CONFIG_QE
40 88 extern qe_iop_conf_t qe_iop_conf_tab[];
41 89 extern void qe_config_iopin(u8 port, u8 pin, int dir,
... ... @@ -625,6 +673,10 @@
625 673 {
626 674 struct ccsr_usb_phy __iomem *usb_phy1 =
627 675 (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
  676 +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  677 + if (has_erratum_a006261())
  678 + fsl_erratum_a006261_workaround(usb_phy1);
  679 +#endif
628 680 out_be32(&usb_phy1->usb_enable_override,
629 681 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
630 682 }
... ... @@ -633,6 +685,10 @@
633 685 {
634 686 struct ccsr_usb_phy __iomem *usb_phy2 =
635 687 (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
  688 +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  689 + if (has_erratum_a006261())
  690 + fsl_erratum_a006261_workaround(usb_phy2);
  691 +#endif
636 692 out_be32(&usb_phy2->usb_enable_override,
637 693 CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
638 694 }
639 695  
... ... @@ -672,7 +728,13 @@
672 728 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
673 729 setbits_be32(&usb_phy->port2.pwrfltcfg,
674 730 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
  731 +
  732 +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  733 + if (has_erratum_a006261())
  734 + fsl_erratum_a006261_workaround(usb_phy);
675 735 #endif
  736 +
  737 +#endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
676 738  
677 739 #ifdef CONFIG_FMAN_ENET
678 740 fman_enet_init();
arch/powerpc/include/asm/config_mpc85xx.h
Diff comments   View file @ 247161b
... ... @@ -154,6 +154,7 @@
154 154 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
155 155 #define CONFIG_SYS_FSL_ERRATUM_A005125
156 156 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  157 +#define CONFIG_SYS_FSL_ERRATUM_A006261
157 158 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
158 159 #define CONFIG_ESDHC_HC_BLK_ADDR
159 160  
... ... @@ -386,6 +387,7 @@
386 387 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
387 388 #define CONFIG_SYS_FSL_ERRATUM_A004849
388 389 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  390 +#define CONFIG_SYS_FSL_ERRATUM_A006261
389 391 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
390 392  
391 393 #elif defined(CONFIG_PPC_P3041)
... ... @@ -424,6 +426,7 @@
424 426 #define CONFIG_SYS_FSL_ERRATUM_A004849
425 427 #define CONFIG_SYS_FSL_ERRATUM_A005812
426 428 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  429 +#define CONFIG_SYS_FSL_ERRATUM_A006261
427 430 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
428 431  
429 432 #elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
... ... @@ -507,6 +510,7 @@
507 510 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
508 511 #define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
509 512 #define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
  513 +#define CONFIG_SYS_FSL_ERRATUM_A006261
510 514 #define CONFIG_SYS_FSL_A004447_SVR_REV 0x20
511 515  
512 516 #elif defined(CONFIG_PPC_P5040)
... ... @@ -538,6 +542,7 @@
538 542 #define CONFIG_SYS_FSL_ERRATUM_A004699
539 543 #define CONFIG_SYS_FSL_ERRATUM_A004510
540 544 #define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
  545 +#define CONFIG_SYS_FSL_ERRATUM_A006261
541 546 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
542 547 #define CONFIG_SYS_FSL_ERRATUM_A005812
543 548  
... ... @@ -633,6 +638,7 @@
633 638 #define CONFIG_SYS_FSL_ERRATUM_A004468
634 639 #define CONFIG_SYS_FSL_ERRATUM_A_004934
635 640 #define CONFIG_SYS_FSL_ERRATUM_A005871
  641 +#define CONFIG_SYS_FSL_ERRATUM_A006261
636 642 #define CONFIG_SYS_FSL_ERRATUM_A006379
637 643 #define CONFIG_SYS_FSL_ERRATUM_A006593
638 644 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
639 645  
... ... @@ -662,11 +668,14 @@
662 668 #define CONFIG_SYS_FSL_ERRATUM_A005871
663 669 #define CONFIG_SYS_FSL_ERRATUM_A006379
664 670 #define CONFIG_SYS_FSL_ERRATUM_A006593
  671 +#define CONFIG_SYS_FSL_ERRATUM_A006475
  672 +#define CONFIG_SYS_FSL_ERRATUM_A006384
665 673 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
666 674  
667 675 #ifdef CONFIG_PPC_B4860
668 676 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
669 677 #define CONFIG_MAX_CPUS 4
  678 +#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
670 679 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
671 680 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
672 681 #define CONFIG_SYS_NUM_FM1_DTSEC 6
... ... @@ -679,6 +688,7 @@
679 688 #define CONFIG_SYS_FSL_SRIO_LIODN
680 689 #else
681 690 #define CONFIG_MAX_CPUS 2
  691 +#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
682 692 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
683 693 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
684 694 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
... ... @@ -722,6 +732,7 @@
722 732 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
723 733 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
724 734 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  735 +#define CONFIG_SYS_FSL_ERRATUM_A006261
725 736 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
726 737  
727 738 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
arch/powerpc/include/asm/fsl_errata.h
Diff comments   View file @ 247161b
... ... @@ -26,5 +26,39 @@
26 26 }
27 27 #endif
28 28  
  29 +#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
  30 +static inline bool has_erratum_a006261(void)
  31 +{
  32 + u32 svr = get_svr();
  33 + u32 soc = SVR_SOC_VER(svr);
  34 +
  35 + switch (soc) {
  36 + case SVR_P1010:
  37 + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
  38 + case SVR_P2041:
  39 + case SVR_P2040:
  40 + return IS_SVR_REV(svr, 1, 0) ||
  41 + IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
  42 + case SVR_P3041:
  43 + return IS_SVR_REV(svr, 1, 0) ||
  44 + IS_SVR_REV(svr, 1, 1) ||
  45 + IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
  46 + case SVR_P5010:
  47 + case SVR_P5020:
  48 + case SVR_P5021:
  49 + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
  50 + case SVR_T4240:
  51 + case SVR_T4160:
  52 + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
  53 + case SVR_T1040:
  54 + return IS_SVR_REV(svr, 1, 0);
  55 + case SVR_P5040:
  56 + return IS_SVR_REV(svr, 1, 0);
  57 + }
  58 +
  59 + return false;
  60 +}
  61 +#endif
  62 +
29 63 #endif
arch/powerpc/include/asm/immap_85xx.h
Diff comments   View file @ 247161b
... ... @@ -1722,6 +1722,9 @@
1722 1722 u32 rstrqpblsr; /* Reset request preboot loader status */
1723 1723 u8 res11[8];
1724 1724 u32 rstrqmr1; /* Reset request mask */
  1725 +#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
  1726 +#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x00000800
  1727 +#endif
1725 1728 u8 res12[4];
1726 1729 u32 rstrqsr1; /* Reset request status */
1727 1730 u8 res13[4];
... ... @@ -1770,6 +1773,10 @@
1770 1773 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
1771 1774 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
1772 1775 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x80000000
  1776 +#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
  1777 +#define PXCKEN_MASK 0x80000000
  1778 +#define PXCK_MASK 0x00FF0000
  1779 +#define PXCK_BITS_START 16
1773 1780 #elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
1774 1781 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
1775 1782 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
... ... @@ -2492,6 +2499,7 @@
2492 2499 #define SRDS_RSTCTL_SDEN 0x00000020
2493 2500 #define SRDS_RSTCTL_SDRST_B 0x00000040
2494 2501 #define SRDS_RSTCTL_PLLRST_B 0x00000080
  2502 +#define SRDS_RSTCTL_RSTERR_SHIFT 29
2495 2503 u32 pllcr0; /* PLL Control Register 0 */
2496 2504 #define SRDS_PLLCR0_POFF 0x80000000
2497 2505 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
... ... @@ -2501,6 +2509,7 @@
2501 2509 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
2502 2510 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
2503 2511 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
  2512 +#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
2504 2513 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
2505 2514 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
2506 2515 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
2507 2516  
... ... @@ -2508,9 +2517,22 @@
2508 2517 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
2509 2518 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
2510 2519 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
  2520 +#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
  2521 +#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
2511 2522 u32 pllcr1; /* PLL Control Register 1 */
2512   -#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
2513   - u32 res_0c; /* 0x00c */
  2523 +#define SRDS_PLLCR1_BCAP_EN 0x20000000
  2524 +#define SRDS_PLLCR1_BCAP_OVD 0x10000000
  2525 +#define SRDS_PLLCR1_PLL_FCAP 0x001F8000
  2526 +#define SRDS_PLLCR1_PLL_FCAP_SHIFT 15
  2527 +#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
  2528 +#define SRDS_PLLCR1_BYP_CAL 0x02000000
  2529 + u32 pllsr2; /* At 0x00c, PLL Status Register 2 */
  2530 +#define SRDS_PLLSR2_BCAP_EN 0x00800000
  2531 +#define SRDS_PLLSR2_BCAP_EN_SHIFT 23
  2532 +#define SRDS_PLLSR2_FCAP 0x003F0000
  2533 +#define SRDS_PLLSR2_FCAP_SHIFT 16
  2534 +#define SRDS_PLLSR2_DCBIAS 0x000F0000
  2535 +#define SRDS_PLLSR2_DCBIAS_SHIFT 16
2514 2536 u32 pllcr3;
2515 2537 u32 pllcr4;
2516 2538 u8 res_18[0x20-0x18];
... ... @@ -2845,6 +2867,7 @@
2845 2867 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
2846 2868 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
2847 2869 #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
  2870 +#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
2848 2871 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
2849 2872 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000
2850 2873 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000
... ... @@ -2962,6 +2985,10 @@
2962 2985  
2963 2986 #define CONFIG_SYS_FSL_CPC_ADDR \
2964 2987 (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
  2988 +#define CONFIG_SYS_FSL_SCFG_ADDR \
  2989 + (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
  2990 +#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
  2991 + (CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
2965 2992 #define CONFIG_SYS_FSL_QMAN_ADDR \
2966 2993 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
2967 2994 #define CONFIG_SYS_FSL_BMAN_ADDR \
arch/powerpc/lib/bootm.c
Diff comments   View file @ 247161b
... ... @@ -53,6 +53,13 @@
53 53  
54 54 bootstage_mark(BOOTSTAGE_ID_RUN_OS);
55 55  
  56 +#ifdef CONFIG_BOOTSTAGE_FDT
  57 + bootstage_fdt_add_report();
  58 +#endif
  59 +#ifdef CONFIG_BOOTSTAGE_REPORT
  60 + bootstage_report();
  61 +#endif
  62 +
56 63 #if defined(CONFIG_SYS_INIT_RAM_LOCK) && !defined(CONFIG_E500)
57 64 unlock_ram_in_cache();
58 65 #endif
board/freescale/b4860qds/b4860qds.c
Diff comments   View file @ 247161b
... ... @@ -11,6 +11,7 @@
11 11 #include <linux/compiler.h>
12 12 #include <asm/mmu.h>
13 13 #include <asm/processor.h>
  14 +#include <asm/errno.h>
14 15 #include <asm/cache.h>
15 16 #include <asm/immap_85xx.h>
16 17 #include <asm/fsl_law.h>
... ... @@ -28,7 +29,6 @@
28 29  
29 30 #define CLK_MUX_SEL_MASK 0x4
30 31 #define ETH_PHY_CLK_OUT 0x4
31   -#define PLL_NUM 2
32 32  
33 33 DECLARE_GLOBAL_DATA_PTR;
34 34  
... ... @@ -120,6 +120,7 @@
120 120 debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
121 121  
122 122 switch (serdes1_prtcl) {
  123 + case 0x29:
123 124 case 0x2a:
124 125 case 0x2C:
125 126 case 0x2D:
126 127  
... ... @@ -151,7 +152,55 @@
151 152 }
152 153 break;
153 154  
  155 + case 0x02:
  156 + case 0x04:
  157 + case 0x05:
  158 + case 0x06:
  159 + case 0x08:
  160 + case 0x09:
  161 + case 0x0A:
  162 + case 0x0B:
  163 + case 0x0C:
  164 + case 0x30:
  165 + case 0x32:
  166 + case 0x33:
  167 + case 0x34:
  168 + case 0x39:
  169 + case 0x3A:
  170 + case 0x3C:
  171 + case 0x3D:
  172 + case 0x5C:
  173 + case 0x5D:
  174 + /*
  175 + * Configuration:
  176 + * SERDES: 1
  177 + * Lanes: A,B: AURORA
  178 + * Lanes: C,d: SGMII
  179 + * Lanes: E,F,G,H: CPRI
  180 + */
  181 + debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
  182 + " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
  183 + num_vsc16_con = NUM_CON_VSC3316;
  184 + /* Configure VSC3316 crossbar switch */
  185 + ret = select_i2c_ch_pca(I2C_CH_VSC3316);
  186 + if (!ret) {
  187 + ret = vsc3316_config(VSC3316_TX_ADDRESS,
  188 + vsc16_tx_sfp_sgmii_aurora,
  189 + num_vsc16_con);
  190 + if (ret)
  191 + return ret;
  192 + ret = vsc3316_config(VSC3316_RX_ADDRESS,
  193 + vsc16_rx_sfp_sgmii_aurora,
  194 + num_vsc16_con);
  195 + if (ret)
  196 + return ret;
  197 + } else {
  198 + return ret;
  199 + }
  200 + break;
  201 +
154 202 #ifdef CONFIG_PPC_B4420
  203 + case 0x17:
155 204 case 0x18:
156 205 /*
157 206 * Configuration:
158 207  
... ... @@ -239,14 +288,191 @@
239 288 return 0;
240 289 }
241 290  
  291 +static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
  292 +{
  293 + u32 rst_err;
  294 +
  295 + /* Steps For SerDes PLLs reset and reconfiguration
  296 + * or PLL power-up procedure
  297 + */
  298 + debug("CALIBRATE PLL:%d\n", pll_num);
  299 + clrbits_be32(&srds_regs->bank[pll_num].rstctl,
  300 + SRDS_RSTCTL_SDRST_B);
  301 + udelay(10);
  302 + clrbits_be32(&srds_regs->bank[pll_num].rstctl,
  303 + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
  304 + udelay(10);
  305 + setbits_be32(&srds_regs->bank[pll_num].rstctl,
  306 + SRDS_RSTCTL_RST);
  307 + setbits_be32(&srds_regs->bank[pll_num].rstctl,
  308 + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
  309 + | SRDS_RSTCTL_SDRST_B));
  310 +
  311 + udelay(20);
  312 +
  313 + /* Check whether PLL has been locked or not */
  314 + rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
  315 + SRDS_RSTCTL_RSTERR;
  316 + rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
  317 + debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
  318 + if (rst_err)
  319 + return rst_err;
  320 +
  321 + return rst_err;
  322 +}
  323 +
  324 +static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
  325 +{
  326 + int ret = 0;
  327 + u32 fcap, dcbias, bcap, pllcr1, pllcr0;
  328 +
  329 + if (calibrate_pll(srds_regs, pll_num)) {
  330 + /* STEP 1 */
  331 + /* Read fcap, dcbias and bcap value */
  332 + clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
  333 + SRDS_PLLCR0_DCBIAS_OUT_EN);
  334 + fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
  335 + SRDS_PLLSR2_FCAP;
  336 + fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
  337 + bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
  338 + SRDS_PLLSR2_BCAP_EN;
  339 + bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
  340 + setbits_be32(&srds_regs->bank[pll_num].pllcr0,
  341 + SRDS_PLLCR0_DCBIAS_OUT_EN);
  342 + dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
  343 + SRDS_PLLSR2_DCBIAS;
  344 + dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
  345 + debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
  346 + bcap, fcap, dcbias);
  347 + if (fcap == 0 && bcap == 1) {
  348 + /* Step 3 */
  349 + clrbits_be32(&srds_regs->bank[pll_num].rstctl,
  350 + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
  351 + | SRDS_RSTCTL_SDRST_B));
  352 + clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
  353 + SRDS_PLLCR1_BCAP_EN);
  354 + setbits_be32(&srds_regs->bank[pll_num].pllcr1,
  355 + SRDS_PLLCR1_BCAP_OVD);
  356 + if (calibrate_pll(srds_regs, pll_num)) {
  357 + /*save the fcap, dcbias and bcap values*/
  358 + clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
  359 + SRDS_PLLCR0_DCBIAS_OUT_EN);
  360 + fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
  361 + & SRDS_PLLSR2_FCAP;
  362 + fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
  363 + bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
  364 + & SRDS_PLLSR2_BCAP_EN;
  365 + bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
  366 + setbits_be32(&srds_regs->bank[pll_num].pllcr0,
  367 + SRDS_PLLCR0_DCBIAS_OUT_EN);
  368 + dcbias = in_be32
  369 + (&srds_regs->bank[pll_num].pllsr2) &
  370 + SRDS_PLLSR2_DCBIAS;
  371 + dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
  372 +
  373 + /* Step 4*/
  374 + clrbits_be32(&srds_regs->bank[pll_num].rstctl,
  375 + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
  376 + | SRDS_RSTCTL_SDRST_B));
  377 + setbits_be32(&srds_regs->bank[pll_num].pllcr1,
  378 + SRDS_PLLCR1_BYP_CAL);
  379 + clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
  380 + SRDS_PLLCR1_BCAP_EN);
  381 + setbits_be32(&srds_regs->bank[pll_num].pllcr1,
  382 + SRDS_PLLCR1_BCAP_OVD);
  383 + /* change the fcap and dcbias to the saved
  384 + * values from Step 3 */
  385 + clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
  386 + SRDS_PLLCR1_PLL_FCAP);
  387 + pllcr1 = (in_be32
  388 + (&srds_regs->bank[pll_num].pllcr1)|
  389 + (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
  390 + out_be32(&srds_regs->bank[pll_num].pllcr1,
  391 + pllcr1);
  392 + clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
  393 + SRDS_PLLCR0_DCBIAS_OVRD);
  394 + pllcr0 = (in_be32
  395 + (&srds_regs->bank[pll_num].pllcr0)|
  396 + (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
  397 + out_be32(&srds_regs->bank[pll_num].pllcr0,
  398 + pllcr0);
  399 + ret = calibrate_pll(srds_regs, pll_num);
  400 + if (ret)
  401 + return ret;
  402 + } else {
  403 + goto out;
  404 + }
  405 + } else { /* Step 5 */
  406 + clrbits_be32(&srds_regs->bank[pll_num].rstctl,
  407 + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
  408 + | SRDS_RSTCTL_SDRST_B));
  409 + udelay(10);
  410 + /* Change the fcap, dcbias, and bcap to the
  411 + * values from Step 1 */
  412 + setbits_be32(&srds_regs->bank[pll_num].pllcr1,
  413 + SRDS_PLLCR1_BYP_CAL);
  414 + clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
  415 + SRDS_PLLCR1_PLL_FCAP);
  416 + pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
  417 + (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
  418 + out_be32(&srds_regs->bank[pll_num].pllcr1,
  419 + pllcr1);
  420 + clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
  421 + SRDS_PLLCR0_DCBIAS_OVRD);
  422 + pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
  423 + (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
  424 + out_be32(&srds_regs->bank[pll_num].pllcr0,
  425 + pllcr0);
  426 + clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
  427 + SRDS_PLLCR1_BCAP_EN);
  428 + setbits_be32(&srds_regs->bank[pll_num].pllcr1,
  429 + SRDS_PLLCR1_BCAP_OVD);
  430 + ret = calibrate_pll(srds_regs, pll_num);
  431 + if (ret)
  432 + return ret;
  433 + }
  434 + }
  435 +out:
  436 + return 0;
  437 +}
  438 +
  439 +static int check_serdes_pll_locks(void)
  440 +{
  441 + serdes_corenet_t *srds1_regs =
  442 + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  443 + serdes_corenet_t *srds2_regs =
  444 + (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
  445 + int i, ret1, ret2;
  446 +
  447 + debug("\nSerDes1 Lock check\n");
  448 + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
  449 + ret1 = check_pll_locks(srds1_regs, i);
  450 + if (ret1) {
  451 + printf("SerDes1, PLL:%d didnt lock\n", i);
  452 + return ret1;
  453 + }
  454 + }
  455 + debug("\nSerDes2 Lock check\n");
  456 + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
  457 + ret2 = check_pll_locks(srds2_regs, i);
  458 + if (ret2) {
  459 + printf("SerDes2, PLL:%d didnt lock\n", i);
  460 + return ret2;
  461 + }
  462 + }
  463 +
  464 + return 0;
  465 +}
  466 +
242 467 int config_serdes1_refclks(void)
243 468 {
244 469 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
245 470 serdes_corenet_t *srds_regs =
246 471 (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
247 472 u32 serdes1_prtcl, lane;
248   - unsigned int flag_sgmii_prtcl = 0;
249   - int ret, i;
  473 + unsigned int flag_sgmii_aurora_prtcl = 0;
  474 + int i;
  475 + int ret = 0;
250 476  
251 477 serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
252 478 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
253 479  
... ... @@ -257,10 +483,12 @@
257 483 serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
258 484 debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
259 485  
260   - /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks
  486 + /* To prevent generation of reset request from SerDes
  487 + * while changing the refclks, By setting SRDS_RST_MSK bit,
  488 + * SerDes reset event cannot cause a reset request
261 489 */
262   - for (i = 0; i < PLL_NUM; i++)
263   - clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST);
  490 + setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
  491 +
264 492 /* Reconfigure IDT idt8t49n222a device for CPRI to work
265 493 * For this SerDes1's Refclk1 and refclk2 need to be set
266 494 * to 122.88MHz
... ... @@ -270,6 +498,25 @@
270 498 case 0x2C:
271 499 case 0x2D:
272 500 case 0x2E:
  501 + case 0x02:
  502 + case 0x04:
  503 + case 0x05:
  504 + case 0x06:
  505 + case 0x08:
  506 + case 0x09:
  507 + case 0x0A:
  508 + case 0x0B:
  509 + case 0x0C:
  510 + case 0x30:
  511 + case 0x32:
  512 + case 0x33:
  513 + case 0x34:
  514 + case 0x39:
  515 + case 0x3A:
  516 + case 0x3C:
  517 + case 0x3D:
  518 + case 0x5C:
  519 + case 0x5D:
273 520 debug("Configuring idt8t49n222a for CPRI SerDes clks:"
274 521 " for srds_prctl:%x\n", serdes1_prtcl);
275 522 ret = select_i2c_ch_pca(I2C_CH_IDT);
276 523  
277 524  
278 525  
... ... @@ -279,16 +526,16 @@
279 526 SERDES_REFCLK_122_88, 0);
280 527 if (ret) {
281 528 printf("IDT8T49N222A configuration failed.\n");
282   - return ret;
  529 + goto out;
283 530 } else
284   - printf("IDT8T49N222A configured.\n");
  531 + debug("IDT8T49N222A configured.\n");
285 532 } else {
286   - return ret;
  533 + goto out;
287 534 }
288 535 select_i2c_ch_pca(I2C_CH_DEFAULT);
289 536  
290 537 /* Change SerDes1's Refclk1 to 125MHz for on board
291   - * SGMIIs to work
  538 + * SGMIIs or Aurora to work
292 539 */
293 540 for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
294 541 enum srds_prtcl lane_prtcl = serdes_get_prtcl
295 542  
296 543  
... ... @@ -300,20 +547,21 @@
300 547 case SGMII_FM1_DTSEC4:
301 548 case SGMII_FM1_DTSEC5:
302 549 case SGMII_FM1_DTSEC6:
303   - flag_sgmii_prtcl++;
  550 + case AURORA:
  551 + flag_sgmii_aurora_prtcl++;
304 552 break;
305 553 default:
306 554 break;
307 555 }
308 556 }
309 557  
310   - if (flag_sgmii_prtcl)
  558 + if (flag_sgmii_aurora_prtcl)
311 559 QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
312 560  
313 561 /* Steps For SerDes PLLs reset and reconfiguration after
314 562 * changing SerDes's refclks
315 563 */
316   - for (i = 0; i < PLL_NUM; i++) {
  564 + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
317 565 debug("For PLL%d reset and reconfiguration after"
318 566 " changing refclks\n", i+1);
319 567 clrbits_be32(&srds_regs->bank[i].rstctl,
320 568  
321 569  
322 570  
... ... @@ -333,16 +581,101 @@
333 581 printf("WARNING:IDT8T49N222A configuration not"
334 582 " supported for:%x SerDes1 Protocol.\n",
335 583 serdes1_prtcl);
336   - return -1;
337 584 }
338 585  
339   - return 0;
  586 +out:
  587 + /* Clearing SRDS_RST_MSK bit as now
  588 + * SerDes reset event can cause a reset request
  589 + */
  590 + clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
  591 + return ret;
340 592 }
341 593  
  594 +int config_serdes2_refclks(void)
  595 +{
  596 + ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  597 + serdes_corenet_t *srds2_regs =
  598 + (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
  599 + u32 serdes2_prtcl;
  600 + int ret = 0;
  601 + int i;
  602 +
  603 + serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
  604 + FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  605 + if (!serdes2_prtcl) {
  606 + debug("SERDES2 is not enabled\n");
  607 + return -ENODEV;
  608 + }
  609 + serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  610 + debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
  611 +
  612 + /* To prevent generation of reset request from SerDes
  613 + * while changing the refclks, By setting SRDS_RST_MSK bit,
  614 + * SerDes reset event cannot cause a reset request
  615 + */
  616 + setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
  617 +
  618 + /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
  619 + * For this SerDes2's Refclk1 need to be set to 100MHz
  620 + */
  621 + switch (serdes2_prtcl) {
  622 + case 0x9E:
  623 + case 0x9A:
  624 + case 0xb2:
  625 + debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
  626 + serdes2_prtcl);
  627 + ret = select_i2c_ch_pca(I2C_CH_IDT);
  628 + if (!ret) {
  629 + ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
  630 + SERDES_REFCLK_100,
  631 + SERDES_REFCLK_156_25, 0);
  632 + if (ret) {
  633 + printf("IDT8T49N222A configuration failed.\n");
  634 + goto out;
  635 + } else
  636 + debug("IDT8T49N222A configured.\n");
  637 + } else {
  638 + goto out;
  639 + }
  640 + select_i2c_ch_pca(I2C_CH_DEFAULT);
  641 +
  642 + /* Steps For SerDes PLLs reset and reconfiguration after
  643 + * changing SerDes's refclks
  644 + */
  645 + for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
  646 + clrbits_be32(&srds2_regs->bank[i].rstctl,
  647 + SRDS_RSTCTL_SDRST_B);
  648 + udelay(10);
  649 + clrbits_be32(&srds2_regs->bank[i].rstctl,
  650 + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
  651 + udelay(10);
  652 + setbits_be32(&srds2_regs->bank[i].rstctl,
  653 + SRDS_RSTCTL_RST);
  654 + setbits_be32(&srds2_regs->bank[i].rstctl,
  655 + (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
  656 + | SRDS_RSTCTL_SDRST_B));
  657 +
  658 + udelay(10);
  659 + }
  660 + break;
  661 + default:
  662 + printf("IDT configuration not supported for:%x S2 Protocol.\n",
  663 + serdes2_prtcl);
  664 + }
  665 +
  666 +out:
  667 + /* Clearing SRDS_RST_MSK bit as now
  668 + * SerDes reset event can cause a reset request
  669 + */
  670 + clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
  671 + return ret;
  672 +}
  673 +
342 674 int board_early_init_r(void)
343 675 {
344 676 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
345 677 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  678 + int ret;
346 679  
347 680 /*
348 681 * Remap Boot flash + PROMJET region to caching-inhibited
... ... @@ -374,6 +707,35 @@
374 707 printf("SerDes1 Refclks couldn't set properly.\n");
375 708 else
376 709 printf("SerDes1 Refclks have been set.\n");
  710 +
  711 + /* SerDes2 refclks need to be set again, as default clks
  712 + * are not suitable for PCIe SATA to work
  713 + * This function will set SerDes2's Refclk1 and refclk2
  714 + * for SerDes2 protocols having PCIe in them
  715 + * for PCIe SATA to work
  716 + */
  717 + ret = config_serdes2_refclks();
  718 + if (!ret)
  719 + printf("SerDes2 Refclks have been set.\n");
  720 + else if (ret == -ENODEV)
  721 + printf("SerDes disable, Refclks couldn't change.\n");
  722 + else
  723 + printf("SerDes2 Refclk reconfiguring failed.\n");
  724 +
  725 +#if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
  726 + defined(CONFIG_SYS_FSL_ERRATUM_A006475)
  727 + /* Rechecking the SerDes locks after all SerDes configurations
  728 + * are done, As SerDes PLLs may not lock reliably at 5 G VCO
  729 + * and at cold temperatures.
  730 + * Following sequence ensure the proper locking of SerDes PLLs.
  731 + */
  732 + if (SVR_MAJ(get_svr()) == 1) {
  733 + if (check_serdes_pll_locks())
  734 + printf("SerDes plls still not locked properly.\n");
  735 + else
  736 + printf("SerDes plls have been locked well.\n");
  737 + }
  738 +#endif
377 739  
378 740 /* Configure VSC3316 and VSC3308 crossbar switches */
379 741 if (configure_vsc3316_3308())
board/freescale/b4860qds/b4860qds_crossbar_con.h
Diff comments   View file @ 247161b
... ... @@ -24,6 +24,10 @@
24 24 {7, 8}, {9, 0}, {5, 14}, {4, 15},
25 25 {-1, -1}, {-1, -1} };
26 26  
  27 +static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
  28 + {7, 8}, {9, 0}, {5, 14},
  29 + {4, 15}, {2, 12}, {12, 13} };
  30 +
27 31 #ifdef CONFIG_PPC_B4420
28 32 static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
29 33 {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
... ... @@ -45,6 +49,10 @@
45 49 static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
46 50 {7, 8}, {1, 9}, {14, 11}, {15, 10},
47 51 {-1, -1}, {-1, -1} };
  52 +
  53 +static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
  54 + {7, 8}, {1, 9}, {14, 11},
  55 + {15, 10}, {13, 3}, {12, 12} };
48 56  
49 57 #ifdef CONFIG_PPC_B4420
50 58 static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
board/freescale/b4860qds/eth_b4860qds.c
Diff comments   View file @ 247161b
... ... @@ -66,6 +66,7 @@
66 66 serdes2_prtcl);
67 67  
68 68 switch (serdes2_prtcl) {
  69 + case 0x17:
69 70 case 0x18:
70 71 /*
71 72 * Configuration:
... ... @@ -198,6 +199,7 @@
198 199 fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
199 200  
200 201 switch (serdes1_prtcl) {
  202 + case 0x29:
201 203 case 0x2a:
202 204 /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
203 205 debug("Setting phy addresses for FM1_DTSEC5: %x and"
... ... @@ -209,6 +211,7 @@
209 211 CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
210 212 break;
211 213 #ifdef CONFIG_PPC_B4420
  214 + case 0x17:
212 215 case 0x18:
213 216 /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
214 217 debug("Setting phy addresses for FM1_DTSEC3: %x and"
... ... @@ -228,6 +231,7 @@
228 231 break;
229 232 }
230 233 switch (serdes2_prtcl) {
  234 + case 0x17:
231 235 case 0x18:
232 236 debug("Setting phy addresses on SGMII Riser card for"
233 237 "FM1_DTSEC ports: \n");
... ... @@ -240,6 +244,7 @@
240 244 fm_info_set_phy_address(FM1_DTSEC4,
241 245 CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
242 246 break;
  247 + case 0x48:
243 248 case 0x49:
244 249 debug("Setting phy addresses on SGMII Riser card for"
245 250 "FM1_DTSEC ports: \n");
board/freescale/t1040qds/Makefile
Diff comments   View file @ 247161b
... ... @@ -10,4 +10,5 @@
10 10 obj-y += law.o
11 11 obj-y += tlb.o
12 12 obj-y += eth.o
  13 +obj-y += diu.o
board/freescale/t1040qds/diu.c
Diff comments   View file @ 247161b
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + * Author: Priyanka Jain <Priyanka.Jain@freescale.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <command.h>
  10 +#include <linux/ctype.h>
  11 +#include <asm/io.h>
  12 +#include <stdio_dev.h>
  13 +#include <video_fb.h>
  14 +#include <fsl_diu_fb.h>
  15 +#include "../common/qixis.h"
  16 +#include "t1040qds.h"
  17 +#include "t1040qds_qixis.h"
  18 +#include <i2c.h>
  19 +
  20 +
  21 +#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F
  22 +#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33
  23 +#define I2C_DVI_PLL_DIVIDER_REG 0x34
  24 +#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35
  25 +#define I2C_DVI_PLL_FILTER_REG 0x36
  26 +#define I2C_DVI_TEST_PATTERN_REG 0x48
  27 +#define I2C_DVI_POWER_MGMT_REG 0x49
  28 +#define I2C_DVI_LOCK_STATE_REG 0x4D
  29 +#define I2C_DVI_SYNC_POLARITY_REG 0x56
  30 +
  31 +/*
  32 + * Set VSYNC/HSYNC to active high. This is polarity of sync signals
  33 + * from DIU->DVI. The DIU default is active igh, so DVI is set to
  34 + * active high.
  35 + */
  36 +#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98
  37 +
  38 +#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
  39 +#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26
  40 +#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0
  41 +#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08
  42 +#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16
  43 +#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60
  44 +
  45 +/* Clear test pattern */
  46 +#define I2C_DVI_TEST_PATTERN_VAL 0x18
  47 +/* Exit Power-down mode */
  48 +#define I2C_DVI_POWER_MGMT_VAL 0xC0
  49 +
  50 +/* Monitor polarity is handled via DVI Sync Polarity Register */
  51 +#define I2C_DVI_SYNC_POLARITY_VAL 0x00
  52 +
  53 +/*
  54 + * DIU Area Descriptor
  55 + *
  56 + * Note that we need to byte-swap the value before it's written to the AD
  57 + * register. So even though the registers don't look like they're in the same
  58 + * bit positions as they are on the MPC8610, the same value is written to the
  59 + * AD register on the MPC8610 and on the P1022.
  60 + */
  61 +#define AD_BYTE_F 0x10000000
  62 +#define AD_ALPHA_C_SHIFT 25
  63 +#define AD_BLUE_C_SHIFT 23
  64 +#define AD_GREEN_C_SHIFT 21
  65 +#define AD_RED_C_SHIFT 19
  66 +#define AD_PIXEL_S_SHIFT 16
  67 +#define AD_COMP_3_SHIFT 12
  68 +#define AD_COMP_2_SHIFT 8
  69 +#define AD_COMP_1_SHIFT 4
  70 +#define AD_COMP_0_SHIFT 0
  71 +
  72 +/* Programming of HDMI Chrontel CH7301 connector */
  73 +int diu_set_dvi_encoder(unsigned int pixclock)
  74 +{
  75 + int ret;
  76 + u8 temp;
  77 + select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
  78 +
  79 + temp = I2C_DVI_TEST_PATTERN_VAL;
  80 + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
  81 + &temp, 1);
  82 + if (ret) {
  83 + puts("I2C: failed to select proper dvi test pattern\n");
  84 + return ret;
  85 + }
  86 + temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
  87 + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
  88 + 1, &temp, 1);
  89 + if (ret) {
  90 + puts("I2C: failed to select dvi input data format\n");
  91 + return ret;
  92 + }
  93 +
  94 + /* Set Sync polarity register */
  95 + temp = I2C_DVI_SYNC_POLARITY_VAL;
  96 + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
  97 + &temp, 1);
  98 + if (ret) {
  99 + puts("I2C: failed to select dvi syc polarity\n");
  100 + return ret;
  101 + }
  102 +
  103 + /* Set PLL registers based on pixel clock rate*/
  104 + if (pixclock > 65000000) {
  105 + temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
  106 + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
  107 + I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
  108 + if (ret) {
  109 + puts("I2C: failed to select dvi pll charge_cntl\n");
  110 + return ret;
  111 + }
  112 + temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
  113 + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
  114 + I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
  115 + if (ret) {
  116 + puts("I2C: failed to select dvi pll divider\n");
  117 + return ret;
  118 + }
  119 + temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
  120 + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
  121 + I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
  122 + if (ret) {
  123 + puts("I2C: failed to select dvi pll filter\n");
  124 + return ret;
  125 + }
  126 + } else {
  127 + temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
  128 + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
  129 + I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
  130 + if (ret) {
  131 + puts("I2C: failed to select dvi pll charge_cntl\n");
  132 + return ret;
  133 + }
  134 + temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
  135 + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
  136 + I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
  137 + if (ret) {
  138 + puts("I2C: failed to select dvi pll divider\n");
  139 + return ret;
  140 + }
  141 + temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
  142 + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
  143 + I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
  144 + if (ret) {
  145 + puts("I2C: failed to select dvi pll filter\n");
  146 + return ret;
  147 + }
  148 + }
  149 +
  150 + temp = I2C_DVI_POWER_MGMT_VAL;
  151 + ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
  152 + &temp, 1);
  153 + if (ret) {
  154 + puts("I2C: failed to select dvi power mgmt\n");
  155 + return ret;
  156 + }
  157 +
  158 + udelay(500);
  159 +
  160 + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  161 + return 0;
  162 +}
  163 +
  164 +void diu_set_pixel_clock(unsigned int pixclock)
  165 +{
  166 + unsigned long speed_ccb, temp;
  167 + u32 pixval;
  168 + int ret = 0;
  169 + speed_ccb = get_bus_freq(0);
  170 + temp = 1000000000 / pixclock;
  171 + temp *= 1000;
  172 + pixval = speed_ccb / temp;
  173 +
  174 + /* Program HDMI encoder */
  175 + ret = diu_set_dvi_encoder(temp);
  176 + if (ret) {
  177 + puts("Failed to set DVI encoder\n");
  178 + return;
  179 + }
  180 +
  181 + /* Program pixel clock */
  182 + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
  183 + ((pixval << PXCK_BITS_START) & PXCK_MASK));
  184 + /* enable clock*/
  185 + out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
  186 + ((pixval << PXCK_BITS_START) & PXCK_MASK));
  187 +}
  188 +
  189 +int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
  190 +{
  191 + u32 pixel_format;
  192 + u8 sw;
  193 +
  194 + /*Route I2C4 to DIU system as HSYNC/VSYNC*/
  195 + sw = QIXIS_READ(brdcfg[5]);
  196 + QIXIS_WRITE(brdcfg[5],
  197 + ((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
  198 +
  199 + /*Configure Display ouput port as HDMI*/
  200 + sw = QIXIS_READ(brdcfg[15]);
  201 + QIXIS_WRITE(brdcfg[15],
  202 + ((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
  203 + | (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
  204 +
  205 + pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
  206 + (0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
  207 + (2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
  208 + (8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
  209 + (8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
  210 +
  211 + printf("DIU: Switching to monitor @ %ux%u\n", xres, yres);
  212 +
  213 +
  214 + return fsl_diu_init(xres, yres, pixel_format, 0);
  215 +}
board/freescale/t1040qds/t1040qds.h
Diff comments   View file @ 247161b
... ... @@ -9,6 +9,7 @@
9 9  
10 10 void fdt_fixup_board_enet(void *blob);
11 11 void pci_of_setup(void *blob, bd_t *bd);
  12 +int select_i2c_ch_pca9547(u8 ch);
12 13  
13 14 #endif
board/freescale/t1040qds/t1040qds_qixis.h
Diff comments   View file @ 247161b
... ... @@ -13,6 +13,18 @@
13 13 #define BRDCFG4_EMISEL_MASK 0xE0
14 14 #define BRDCFG4_EMISEL_SHIFT 5
15 15  
  16 +/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
  17 +#define BRDCFG5_IMX_MASK 0xC0
  18 +#define BRDCFG5_IMX_DIU 0x80
  19 +
  20 +/* BRDCFG15[3] controls LCD Panel Powerdown*/
  21 +#define BRDCFG15_LCDPD_MASK 0x10
  22 +#define BRDCFG15_LCDPD_ENABLED 0x00
  23 +
  24 +/* BRDCFG15[6:7] controls DIU MUX selction*/
  25 +#define BRDCFG15_DIUSEL_MASK 0x03
  26 +#define BRDCFG15_DIUSEL_HDMI 0x00
  27 +
16 28 /* SYSCLK */
17 29 #define QIXIS_SYSCLK_66 0x0
18 30 #define QIXIS_SYSCLK_83 0x1
board/freescale/t104xrdb/ddr.c
Diff comments   View file @ 247161b
... ... @@ -46,7 +46,7 @@
46 46  
47 47 pbsp = udimms[0];
48 48  
49   - /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
  49 + /* Get clk_adjust according to the board ddr
50 50 * freqency and n_banks specified in board_specific_parameters table.
51 51 */
52 52 ddr_freq = get_ddr_freq(0) / 1000000;
53 53  
... ... @@ -54,14 +54,10 @@
54 54 if (pbsp->n_ranks == pdimm->n_ranks &&
55 55 (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
56 56 if (ddr_freq <= pbsp->datarate_mhz_high) {
57   - popts->cpo_override = pbsp->cpo;
58   - popts->write_data_delay =
59   - pbsp->write_data_delay;
60 57 popts->clk_adjust = pbsp->clk_adjust;
61 58 popts->wrlvl_start = pbsp->wrlvl_start;
62 59 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
63 60 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
64   - popts->twot_en = pbsp->force_2t;
65 61 goto found;
66 62 }
67 63 pbsp_highest = pbsp;
68 64  
... ... @@ -74,13 +70,10 @@
74 70 printf("for data rate %lu MT/s\n", ddr_freq);
75 71 printf("Trying to use the highest speed (%u) parameters\n",
76 72 pbsp_highest->datarate_mhz_high);
77   - popts->cpo_override = pbsp_highest->cpo;
78   - popts->write_data_delay = pbsp_highest->write_data_delay;
79 73 popts->clk_adjust = pbsp_highest->clk_adjust;
80 74 popts->wrlvl_start = pbsp_highest->wrlvl_start;
81 75 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
82 76 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
83   - popts->twot_en = pbsp_highest->force_2t;
84 77 } else {
85 78 panic("DIMM is not supported by this board");
86 79 }
... ... @@ -112,8 +105,8 @@
112 105 popts->zq_en = 1;
113 106  
114 107 /* DHC_EN =1, ODT = 75 Ohm */
115   - popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
116   - popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  108 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
  109 + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
117 110 }
118 111  
119 112 phys_size_t initdram(int board_type)
board/freescale/t104xrdb/ddr.h
Diff comments   View file @ 247161b
... ... @@ -6,7 +6,6 @@
6 6  
7 7 #ifndef __DDR_H__
8 8 #define __DDR_H__
9   -
10 9 dimm_params_t ddr_raw_timing = {
11 10 .n_ranks = 2,
12 11 .rank_density = 2147483648u,
13 12  
14 13  
15 14  
16 15  
17 16  
... ... @@ -14,22 +13,21 @@
14 13 .primary_sdram_width = 64,
15 14 .ec_sdram_width = 8,
16 15 .registered_dimm = 0,
17   - .mirrored_dimm = 1,
  16 + .mirrored_dimm = 0,
18 17 .n_row_addr = 15,
19 18 .n_col_addr = 10,
20 19 .n_banks_per_sdram_device = 8,
21 20 .edc_config = 2, /* ECC */
22 21 .burst_lengths_bitmask = 0x0c,
23   -
24 22 .tckmin_x_ps = 1071,
25   - .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
26   - .taa_ps = 13910,
  23 + .caslat_x = 0xfe << 4, /* 5,6,7,8,9,10,11 */
  24 + .taa_ps = 13125,
27 25 .twr_ps = 15000,
28   - .trcd_ps = 13910,
  26 + .trcd_ps = 13125,
29 27 .trrd_ps = 6000,
30   - .trp_ps = 13910,
  28 + .trp_ps = 13125,
31 29 .tras_ps = 34000,
32   - .trc_ps = 48910,
  30 + .trc_ps = 48125,
33 31 .trfc_ps = 260000,
34 32 .twtr_ps = 7500,
35 33 .trtp_ps = 7500,
... ... @@ -45,9 +43,6 @@
45 43 u32 wrlvl_start;
46 44 u32 wrlvl_ctl_2;
47 45 u32 wrlvl_ctl_3;
48   - u32 cpo;
49   - u32 write_data_delay;
50   - u32 force_2t;
51 46 };
52 47  
53 48 /*
54 49  
... ... @@ -59,14 +54,21 @@
59 54 static const struct board_specific_parameters udimm0[] = {
60 55 /*
61 56 * memory controller 0
62   - * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
63   - * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
  57 + * num| hi| rank| clk| wrlvl | wrlvl
  58 + * ranks| mhz| GB |adjst| start | ctl2
64 59 */
65   - {2, 1066, 4, 8, 4, 0x05070609, 0x08090a08, 0xff, 2, 0},
66   - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
67   - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
68   - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
69   - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
  60 + {2, 833, 4, 4, 6, 0x06060607, 0x08080807},
  61 + {2, 833, 0, 4, 6, 0x06060607, 0x08080807},
  62 + {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
  63 + {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
  64 + {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
  65 + {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
  66 + {1, 833, 4, 4, 6, 0x06060607, 0x08080807},
  67 + {1, 833, 0, 4, 6, 0x06060607, 0x08080807},
  68 + {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09},
  69 + {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09},
  70 + {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A},
  71 + {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A},
70 72 {}
71 73 };
72 74  
board/freescale/t208xqds/eth_t208xqds.c
Diff comments   View file @ 247161b
... ... @@ -36,14 +36,15 @@
36 36 #define EMI1_SLOT3 3
37 37 #define EMI1_SLOT4 4
38 38 #define EMI1_SLOT5 5
  39 +#define EMI2 7
39 40 #elif defined(CONFIG_T2081QDS)
40 41 #define EMI1_SLOT2 3
41 42 #define EMI1_SLOT3 4
42 43 #define EMI1_SLOT5 5
43 44 #define EMI1_SLOT6 6
44 45 #define EMI1_SLOT7 7
45   -#endif
46 46 #define EMI2 8
  47 +#endif
47 48  
48 49 static int mdio_mux[NUM_FM_PORTS];
49 50  
board/freescale/t208xrdb/Makefile
Diff comments   View file @ 247161b
  1 +#
  2 +# Copyright 2014 Freescale Semiconductor, Inc.
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-$(CONFIG_T2080RDB) += t208xrdb.o
  8 +obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
  9 +obj-$(CONFIG_T2080RDB) += cpld.o
  10 +obj-$(CONFIG_PCI) += pci.o
  11 +obj-y += ddr.o
  12 +obj-y += law.o
  13 +obj-y += tlb.o
board/freescale/t208xrdb/README
Diff comments   View file @ 247161b
  1 +T2080PCIe-RDB is a Freescale Reference Design Board that hosts the T2080 SoC.
  2 +It can work in two mode: standalone mode and PCIe endpoint mode.
  3 +
  4 +T2080 SoC Overview
  5 +------------------
  6 +The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
  7 +Architecture processor cores with high-performance datapath acceleration
  8 +logic and network and peripheral bus interfaces required for networking,
  9 +telecom/datacom, wireless infrastructure, and mil/aerospace applications.
  10 +
  11 +T2080 includes the following functions and features:
  12 + - Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
  13 + - 2MB L2 cache and 512KB CoreNet platform cache (CPC)
  14 + - Hierarchical interconnect fabric
  15 + - One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
  16 + - Data Path Acceleration Architecture (DPAA) incorporating acceleration
  17 + - 16 SerDes lanes up to 10.3125 GHz
  18 + - 8 Ethernet interfaces, supporting combinations of the following:
  19 + - Up to four 10 Gbps Ethernet MACs
  20 + - Up to eight 1 Gbps Ethernet MACs
  21 + - Up to four 2.5 Gbps Ethernet MACs
  22 + - High-speed peripheral interfaces
  23 + - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
  24 + - Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
  25 + - Additional peripheral interfaces
  26 + - Two serial ATA (SATA 2.0) controllers
  27 + - Two high-speed USB 2.0 controllers with integrated PHY
  28 + - Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
  29 + - Enhanced serial peripheral interface (eSPI)
  30 + - Four I2C controllers
  31 + - Four 2-pin UARTs or two 4-pin UARTs
  32 + - Integrated Flash Controller supporting NAND and NOR flash
  33 + - Three eight-channel DMA engines
  34 + - Support for hardware virtualization and partitioning enforcement
  35 + - QorIQ Platform's Trust Architecture 2.0
  36 +
  37 +Differences between T2080 and T2081
  38 +-----------------------------------
  39 + Feature T2080 T2081
  40 + 1G Ethernet numbers: 8 6
  41 + 10G Ethernet numbers: 4 2
  42 + SerDes lanes: 16 8
  43 + Serial RapidIO,RMan: 2 no
  44 + SATA Controller: 2 no
  45 + Aurora: yes no
  46 + SoC Package: 896-pins 780-pins
  47 +
  48 +
  49 +T2080PCIe-RDB board Overview
  50 +----------------------------
  51 + - SERDES Configuration
  52 + - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
  53 + - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
  54 + - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3)
  55 + - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2)
  56 + - SerDes-2 Lane E-F: to C293 secure co-processor (PCIe2 x2)
  57 + - SerDes-2 Lane G-H: to SATA1 & SATA2
  58 + - Ethernet
  59 + - Two on-board 10M/100M/1G RGMII ethernet ports
  60 + - Two on-board 10Gbps XFI fiber ports
  61 + - Two on-board 10Gbps Base-T copper ports
  62 + - DDR Memory
  63 + - Supports 72bit 4GB DDR3-LP SODIMM
  64 + - PCIe
  65 + - One PCIe x4 gold-finger
  66 + - One PCIe x4 connector
  67 + - One PCIe x2 end-point device (C293 Crypto co-processor)
  68 + - IFC/Local Bus
  69 + - NOR: 128MB 16-bit NOR Flash
  70 + - NAND: 512MB 8-bit NAND flash
  71 + - CPLD: for system controlling with programable header on-board
  72 + - SATA
  73 + - Two SATA 2.0 onnectors on-board
  74 + - USB
  75 + - Supports two USB 2.0 ports with integrated PHYs
  76 + - Two type A ports with 5V@1.5A per port.
  77 + - SDHC
  78 + - one TF-card connector on-board
  79 + - SPI
  80 + - On-board 64MB SPI flash
  81 + - Other
  82 + - Two Serial ports
  83 + - Four I2C ports
  84 +
  85 +
  86 +System Memory map
  87 +-----------------
  88 +Start Address End Address Description Size
  89 +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
  90 +0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
  91 +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
  92 +0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
  93 +0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
  94 +0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
  95 +0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
  96 +0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
  97 +0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
  98 +0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
  99 +0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
  100 +0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
  101 +0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
  102 +0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
  103 +0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
  104 +0x0_0000_0000 0x0_ffff_ffff DDR 4GB
  105 +
  106 +
  107 +128M NOR Flash memory Map
  108 +-------------------------
  109 +Start Address End Address Definition Max size
  110 +0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
  111 +0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
  112 +0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
  113 +0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256KB
  114 +0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
  115 +0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
  116 +0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
  117 +0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
  118 +0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
  119 +0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
  120 +0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
  121 +0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB
  122 +0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
  123 +0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
  124 +0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
  125 +0xE8000000 0xE801FFFF RCW (current bank) 128KB
  126 +
  127 +
  128 +T2080PCIe-RDB Ethernet Port Map
  129 +-------------------------------
  130 +Label In Uboot In Linux FMan Address Comments PHY
  131 +ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315)
  132 +ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315)
  133 +ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202)
  134 +ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202)
  135 +ETH4 FM1@DTSEC3 fm1-mac3 0xfe4e4000 1G RGMII (RTL8211E)
  136 +ETH5 FM1@DTSEC4 fm1-mac4 0xfe4e6000 1G RGMII (RTL8211E)
  137 +
  138 +
  139 +T2080PCIe-RDB Default DIP-Switch setting
  140 +----------------------------------------
  141 +SW1[1:8] = '00010011'
  142 +SW2[1:8] = '10111111'
  143 +SW3[1:8] = '11100001'
  144 +
  145 +Software configurations and board settings
  146 +------------------------------------------
  147 +1. NOR boot:
  148 + a. build NOR boot image
  149 + $ make T2080RDB
  150 + b. program u-boot.bin image to NOR flash
  151 + => tftp 1000000 u-boot.bin
  152 + => pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
  153 + set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
  154 +
  155 + Switching between default bank and alternate bank on NOR flash
  156 + To change boot source to vbank4:
  157 + via software: run command 'cpld reset altbank' in u-boot.
  158 + via DIP-switch: set SW3[5:7] = '011'
  159 +
  160 + To change boot source to vbank0:
  161 + via software: run command 'cpld reset' in u-boot.
  162 + via DIP-Switch: set SW3[5:7] = '111'
  163 +
  164 +2. NAND Boot:
  165 + a. build PBL image for NAND boot
  166 + $ make T2080RDB_NAND_config
  167 + $ make u-boot.pbl
  168 + b. program u-boot.pbl to NAND flash
  169 + => tftp 1000000 u-boot.pbl
  170 + => nand erase 0 d0000
  171 + => nand write 1000000 0 $filesize
  172 + set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
  173 +
  174 +3. SPI Boot:
  175 + a. build PBL image for SPI boot
  176 + $ make T2080RDB_SPIFLASH_config
  177 + $ make u-boot.pbl
  178 + b. program u-boot.pbl to SPI flash
  179 + => tftp 1000000 u-boot.pbl
  180 + => sf probe 0
  181 + => sf erase 0 d0000
  182 + => sf write 1000000 0 $filesize
  183 + set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
  184 +
  185 +4. SD Boot:
  186 + a. build PBL image for SD boot
  187 + $ make T2080RDB_SDCARD_config
  188 + $ make u-boot.pbl
  189 + b. program u-boot.pbl to TF card
  190 + => tftp 1000000 u-boot.pbl
  191 + => mmc write 1000000 8 1650
  192 + set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
  193 +
  194 +
  195 +How to update the ucode of Cortina CS4315/CS4340 10G PHY
  196 +--------------------------------------------------------
  197 +=> tftp 1000000 CS4315-CS4340-PHY-ucode.txt
  198 +=> pro off all;era 0xefe00000 0xefefffff;cp.b 1000000 0xefe00000 $filesize
  199 +
  200 +
  201 +How to update the ucode of Freescale FMAN
  202 +-----------------------------------------
  203 +=> tftp 1000000 fsl_fman_ucode_t2080_r1.0.bin
  204 +=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
  205 +
  206 +
  207 +For more details, please refer to T2080PCIe-RDB User Guide and access
  208 +website www.freescale.com and Freescale QorIQ SDK Infocenter document.
board/freescale/t208xrdb/cpld.c
Diff comments   View file @ 247161b
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Freescale T2080RDB board-specific CPLD controlling supports.
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <command.h>
  11 +#include "cpld.h"
  12 +
  13 +u8 cpld_read(unsigned int reg)
  14 +{
  15 + void *p = (void *)CONFIG_SYS_CPLD_BASE;
  16 +
  17 + return in_8(p + reg);
  18 +}
  19 +
  20 +void cpld_write(unsigned int reg, u8 value)
  21 +{
  22 + void *p = (void *)CONFIG_SYS_CPLD_BASE;
  23 +
  24 + out_8(p + reg, value);
  25 +}
  26 +
  27 +/* Set the boot bank to the alternate bank */
  28 +void cpld_set_altbank(void)
  29 +{
  30 + u8 reg = CPLD_READ(flash_csr);
  31 +
  32 + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
  33 + CPLD_WRITE(flash_csr, reg);
  34 + CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
  35 +}
  36 +
  37 +/* Set the boot bank to the default bank */
  38 +void cpld_set_defbank(void)
  39 +{
  40 + u8 reg = CPLD_READ(flash_csr);
  41 +
  42 + reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
  43 + CPLD_WRITE(flash_csr, reg);
  44 + CPLD_WRITE(reset_ctl, CPLD_LBMAP_RESET);
  45 +}
  46 +
  47 +int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  48 +{
  49 + int rc = 0;
  50 +
  51 + if (argc <= 1)
  52 + return cmd_usage(cmdtp);
  53 +
  54 + if (strcmp(argv[1], "reset") == 0) {
  55 + if (strcmp(argv[2], "altbank") == 0)
  56 + cpld_set_altbank();
  57 + else
  58 + cpld_set_defbank();
  59 + } else {
  60 + rc = cmd_usage(cmdtp);
  61 + }
  62 +
  63 + return rc;
  64 +}
  65 +
  66 +U_BOOT_CMD(
  67 + cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
  68 + "Reset the board or alternate bank",
  69 + "reset: reset to default bank\n"
  70 + "cpld reset altbank: reset to alternate bank\n"
  71 +);
board/freescale/t208xrdb/cpld.h
Diff comments   View file @ 247161b
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +/*
  8 + * CPLD register set of T2080RDB board-specific.
  9 + */
  10 +struct cpld_data {
  11 + u8 chip_id1; /* 0x00 - Chip ID1 register */
  12 + u8 chip_id2; /* 0x01 - Chip ID2 register */
  13 + u8 hw_ver; /* 0x02 - Hardware Revision Register */
  14 + u8 sw_ver; /* 0x03 - Software Revision register */
  15 + u8 res0[12]; /* 0x04 - 0x0F - not used */
  16 + u8 reset_ctl; /* 0x10 - Reset control Register */
  17 + u8 flash_csr; /* 0x11 - Flash control and status register */
  18 + u8 thermal_csr; /* 0x12 - Thermal control and status register */
  19 + u8 led_csr; /* 0x13 - LED control and status register */
  20 + u8 sfp_csr; /* 0x14 - SFP+ control and status register */
  21 + u8 misc_csr; /* 0x15 - Misc control and status register */
  22 + u8 boot_or; /* 0x16 - Boot config override register */
  23 + u8 boot_cfg1; /* 0x17 - Boot configuration register 1 */
  24 + u8 boot_cfg2; /* 0x18 - Boot configuration register 2 */
  25 +} cpld_data_t;
  26 +
  27 +u8 cpld_read(unsigned int reg);
  28 +void cpld_write(unsigned int reg, u8 value);
  29 +
  30 +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
  31 +#define CPLD_WRITE(reg, value) \
  32 + cpld_write(offsetof(struct cpld_data, reg), value)
  33 +
  34 +/* CPLD on IFC */
  35 +#define CPLD_LBMAP_MASK 0x3F
  36 +#define CPLD_BANK_SEL_MASK 0x07
  37 +#define CPLD_BANK_OVERRIDE 0x40
  38 +#define CPLD_LBMAP_ALTBANK 0x43 /* BANK OR | BANK 4 */
  39 +#define CPLD_LBMAP_DFLTBANK 0x47 /* BANK OR | BANK 0 */
  40 +#define CPLD_LBMAP_RESET 0xFF
  41 +#define CPLD_LBMAP_SHIFT 0x03
  42 +#define CPLD_BOOT_SEL 0x80
board/freescale/t208xrdb/ddr.c
Diff comments   View file @ 247161b
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or
  5 + * modify it under the terms of the GNU General Public License
  6 + * Version 2 or later as published by the Free Software Foundation.
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <i2c.h>
  11 +#include <hwconfig.h>
  12 +#include <asm/mmu.h>
  13 +#include <fsl_ddr_sdram.h>
  14 +#include <fsl_ddr_dimm_params.h>
  15 +#include <asm/fsl_law.h>
  16 +#include "ddr.h"
  17 +
  18 +DECLARE_GLOBAL_DATA_PTR;
  19 +
  20 +void fsl_ddr_board_options(memctl_options_t *popts,
  21 + dimm_params_t *pdimm,
  22 + unsigned int ctrl_num)
  23 +{
  24 + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  25 + ulong ddr_freq;
  26 +
  27 + if (ctrl_num > 1) {
  28 + printf("Not supported controller number %d\n", ctrl_num);
  29 + return;
  30 + }
  31 + if (!pdimm->n_ranks)
  32 + return;
  33 +
  34 + pbsp = udimms[0];
  35 +
  36 + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  37 + * freqency and n_banks specified in board_specific_parameters table.
  38 + */
  39 + ddr_freq = get_ddr_freq(0) / 1000000;
  40 + while (pbsp->datarate_mhz_high) {
  41 + if (pbsp->n_ranks == pdimm->n_ranks &&
  42 + (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  43 + if (ddr_freq <= pbsp->datarate_mhz_high) {
  44 + popts->clk_adjust = pbsp->clk_adjust;
  45 + popts->wrlvl_start = pbsp->wrlvl_start;
  46 + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  47 + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  48 + goto found;
  49 + }
  50 + pbsp_highest = pbsp;
  51 + }
  52 + pbsp++;
  53 + }
  54 +
  55 + if (pbsp_highest) {
  56 + printf("Error: board specific timing not found");
  57 + printf("for data rate %lu MT/s\n", ddr_freq);
  58 + printf("Trying to use the highest speed (%u) parameters\n",
  59 + pbsp_highest->datarate_mhz_high);
  60 + popts->clk_adjust = pbsp_highest->clk_adjust;
  61 + popts->wrlvl_start = pbsp_highest->wrlvl_start;
  62 + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  63 + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  64 + } else {
  65 + panic("DIMM is not supported by this board");
  66 + }
  67 +found:
  68 + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  69 + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
  70 + "wrlvl_ctrl_3 0x%x\n",
  71 + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  72 + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  73 + pbsp->wrlvl_ctl_3);
  74 +
  75 + /*
  76 + * Factors to consider for half-strength driver enable:
  77 + * - number of DIMMs installed
  78 + */
  79 + popts->half_strength_driver_enable = 0;
  80 + /*
  81 + * Write leveling override
  82 + */
  83 + popts->wrlvl_override = 1;
  84 + popts->wrlvl_sample = 0xf;
  85 +
  86 + /*
  87 + * Rtt and Rtt_WR override
  88 + */
  89 + popts->rtt_override = 0;
  90 +
  91 + /* Enable ZQ calibration */
  92 + popts->zq_en = 1;
  93 +
  94 + /* DHC_EN =1, ODT = 75 Ohm */
  95 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  96 + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  97 +}
  98 +
  99 +phys_size_t initdram(int board_type)
  100 +{
  101 + phys_size_t dram_size;
  102 +
  103 + puts("Initializing....using SPD\n");
  104 +
  105 + dram_size = fsl_ddr_sdram();
  106 +
  107 + dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  108 + dram_size *= 0x100000;
  109 +
  110 + puts(" DDR: ");
  111 + return dram_size;
  112 +}
board/freescale/t208xrdb/ddr.h
Diff comments   View file @ 247161b
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __DDR_H__
  8 +#define __DDR_H__
  9 +struct board_specific_parameters {
  10 + u32 n_ranks;
  11 + u32 datarate_mhz_high;
  12 + u32 rank_gb;
  13 + u32 clk_adjust;
  14 + u32 wrlvl_start;
  15 + u32 wrlvl_ctl_2;
  16 + u32 wrlvl_ctl_3;
  17 +};
  18 +
  19 +/*
  20 + * These tables contain all valid speeds we want to override with board
  21 + * specific parameters. datarate_mhz_high values need to be in ascending order
  22 + * for each n_ranks group.
  23 + */
  24 +
  25 +static const struct board_specific_parameters udimm0[] = {
  26 + /*
  27 + * memory controller 0
  28 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
  29 + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
  30 + */
  31 + {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
  32 + {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
  33 + {2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
  34 + {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
  35 + {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
  36 + {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
  37 + {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
  38 + {1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a},
  39 + {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
  40 + {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
  41 + {}
  42 +};
  43 +
  44 +static const struct board_specific_parameters *udimms[] = {
  45 + udimm0,
  46 +};
  47 +#endif
board/freescale/t208xrdb/eth_t208xrdb.c
Diff comments   View file @ 247161b
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * Shengzhou Liu <Shengzhou.Liu@freescale.com>
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <command.h>
  11 +#include <netdev.h>
  12 +#include <asm/mmu.h>
  13 +#include <asm/processor.h>
  14 +#include <asm/immap_85xx.h>
  15 +#include <asm/fsl_law.h>
  16 +#include <asm/fsl_serdes.h>
  17 +#include <asm/fsl_portals.h>
  18 +#include <asm/fsl_liodn.h>
  19 +#include <malloc.h>
  20 +#include <fm_eth.h>
  21 +#include <fsl_mdio.h>
  22 +#include <miiphy.h>
  23 +#include <phy.h>
  24 +#include <asm/fsl_dtsec.h>
  25 +#include <asm/fsl_serdes.h>
  26 +
  27 +int board_eth_init(bd_t *bis)
  28 +{
  29 +#if defined(CONFIG_FMAN_ENET)
  30 + int i, interface;
  31 + struct memac_mdio_info dtsec_mdio_info;
  32 + struct memac_mdio_info tgec_mdio_info;
  33 + struct mii_dev *dev;
  34 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  35 + u32 srds_s1;
  36 +
  37 + srds_s1 = in_be32(&gur->rcwsr[4]) &
  38 + FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  39 + srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  40 +
  41 + dtsec_mdio_info.regs =
  42 + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
  43 +
  44 + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  45 +
  46 + /* Register the 1G MDIO bus */
  47 + fm_memac_mdio_init(bis, &dtsec_mdio_info);
  48 +
  49 + tgec_mdio_info.regs =
  50 + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
  51 + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
  52 +
  53 + /* Register the 10G MDIO bus */
  54 + fm_memac_mdio_init(bis, &tgec_mdio_info);
  55 +
  56 + /* Set the two on-board RGMII PHY address */
  57 + fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
  58 + fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
  59 +
  60 + switch (srds_s1) {
  61 + case 0x66:
  62 + case 0x6b:
  63 + fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
  64 + fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
  65 + fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
  66 + fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
  67 + break;
  68 + default:
  69 + printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
  70 + srds_s1);
  71 + break;
  72 + }
  73 +
  74 + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  75 + interface = fm_info_get_enet_if(i);
  76 + switch (interface) {
  77 + case PHY_INTERFACE_MODE_RGMII:
  78 + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
  79 + fm_info_set_mdio(i, dev);
  80 + break;
  81 + default:
  82 + break;
  83 + }
  84 + }
  85 +
  86 + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
  87 + switch (fm_info_get_enet_if(i)) {
  88 + case PHY_INTERFACE_MODE_XGMII:
  89 + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
  90 + fm_info_set_mdio(i, dev);
  91 + break;
  92 + default:
  93 + break;
  94 + }
  95 + }
  96 +
  97 + cpu_eth_init(bis);
  98 +#endif /* CONFIG_FMAN_ENET */
  99 +
  100 + return pci_eth_init(bis);
  101 +}
  102 +
  103 +void fdt_fixup_board_enet(void *fdt)
  104 +{
  105 + return;
  106 +}
board/freescale/t208xrdb/law.c
Diff comments   View file @ 247161b
  1 +/*
  2 + * Copyright 2008-2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * (C) Copyright 2000
  5 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +#include <common.h>
  11 +#include <asm/fsl_law.h>
  12 +#include <asm/mmu.h>
  13 +
  14 +struct law_entry law_table[] = {
  15 + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
  16 +#ifdef CONFIG_SYS_BMAN_MEM_PHYS
  17 + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
  18 +#endif
  19 +#ifdef CONFIG_SYS_QMAN_MEM_PHYS
  20 + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
  21 +#endif
  22 +#ifdef CONFIG_SYS_CPLD_BASE_PHYS
  23 + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
  24 +#endif
  25 +#ifdef CONFIG_SYS_DCSRBAR_PHYS
  26 + /* Limit DCSR to 32M to access NPC Trace Buffer */
  27 + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
  28 +#endif
  29 +#ifdef CONFIG_SYS_NAND_BASE_PHYS
  30 + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
  31 +#endif
  32 +};
  33 +
  34 +int num_law_entries = ARRAY_SIZE(law_table);
board/freescale/t208xrdb/pci.c
Diff comments   View file @ 247161b
  1 +/*
  2 + * Copyright 2007-2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <command.h>
  9 +#include <pci.h>
  10 +#include <asm/fsl_pci.h>
  11 +#include <libfdt.h>
  12 +#include <fdt_support.h>
  13 +#include <asm/fsl_serdes.h>
  14 +
  15 +void pci_init_board(void)
  16 +{
  17 + fsl_pcie_init_board(0);
  18 +}
  19 +
  20 +void pci_of_setup(void *blob, bd_t *bd)
  21 +{
  22 + FT_FSL_PCI_SETUP;
  23 +}
board/freescale/t208xrdb/t2080_pbi.cfg
Diff comments   View file @ 247161b
  1 +#
  2 +# Copyright 2013 Freescale Semiconductor, Inc.
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +# Refer doc/README.pblimage for more details about how-to configure
  7 +# and create PBL boot image
  8 +#
  9 +
  10 +#PBI commands
  11 +#Initialize CPC1
  12 +09010000 00200400
  13 +09138000 00000000
  14 +091380c0 00000100
  15 +#512KB SRAM
  16 +09010100 00000000
  17 +09010104 fff80009
  18 +09010f00 08000000
  19 +#enable CPC1
  20 +09010000 80000000
  21 +#Configure LAW for CPC1
  22 +09000d00 00000000
  23 +09000d04 fff80000
  24 +09000d08 81000012
  25 +#Initialize eSPI controller, default configuration is slow for eSPI to
  26 +#load data, this configuration comes from u-boot eSPI driver.
  27 +09110000 80000403
  28 +09110020 2d170008
  29 +09110024 00100008
  30 +09110028 00100008
  31 +0911002c 00100008
  32 +#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
  33 +094fc030 00008148
  34 +094fd030 00008148
  35 +#Configure alternate space
  36 +09000010 00000000
  37 +09000014 ff000000
  38 +09000018 81000000
  39 +#Flush PBL data
  40 +09138000 00000000
  41 +091380c0 00000000
board/freescale/t208xrdb/t2080_rcw.cfg
Diff comments   View file @ 247161b
  1 +#PBL preamble and RCW header for T2080RDB
  2 +aa55aa55 010e0100
  3 +#SerDes Protocol: 0x66_0x16
  4 +#Core/DDR: 1533Mhz/1600MT/s
  5 +120c0017 15000000 00000000 00000000
  6 +66160002 00008400 ec104000 c1000000
  7 +00000000 00000000 00000000 000307fc
  8 +00000000 00000000 00000000 00000004
board/freescale/t208xrdb/t208xrdb.c
Diff comments   View file @ 247161b
  1 +/*
  2 + * Copyright 2009-2013 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <command.h>
  9 +#include <i2c.h>
  10 +#include <netdev.h>
  11 +#include <linux/compiler.h>
  12 +#include <asm/mmu.h>
  13 +#include <asm/processor.h>
  14 +#include <asm/immap_85xx.h>
  15 +#include <asm/fsl_law.h>
  16 +#include <asm/fsl_serdes.h>
  17 +#include <asm/fsl_portals.h>
  18 +#include <asm/fsl_liodn.h>
  19 +#include <fm_eth.h>
  20 +#include "t208xrdb.h"
  21 +#include "cpld.h"
  22 +
  23 +DECLARE_GLOBAL_DATA_PTR;
  24 +
  25 +int checkboard(void)
  26 +{
  27 + struct cpu_type *cpu = gd->arch.cpu;
  28 + static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
  29 +
  30 + printf("Board: %sRDB, ", cpu->name);
  31 + printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
  32 + CPLD_READ(hw_ver), CPLD_READ(sw_ver));
  33 +
  34 +#ifdef CONFIG_SDCARD
  35 + puts("SD/MMC\n");
  36 +#elif CONFIG_SPIFLASH
  37 + puts("SPI\n");
  38 +#else
  39 + u8 reg;
  40 +
  41 + reg = CPLD_READ(flash_csr);
  42 +
  43 + if (reg & CPLD_BOOT_SEL) {
  44 + puts("NAND\n");
  45 + } else {
  46 + reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
  47 + printf("NOR vBank%d\n", ~reg & 0x7);
  48 + }
  49 +#endif
  50 +
  51 + puts("SERDES Reference Clocks:\n");
  52 + printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
  53 + printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[0], freq[0]);
  54 +
  55 + return 0;
  56 +}
  57 +
  58 +int board_early_init_r(void)
  59 +{
  60 + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  61 + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  62 + /*
  63 + * Remap Boot flash + PROMJET region to caching-inhibited
  64 + * so that flash can be erased properly.
  65 + */
  66 +
  67 + /* Flush d-cache and invalidate i-cache of any FLASH data */
  68 + flush_dcache();
  69 + invalidate_icache();
  70 +
  71 + /* invalidate existing TLB entry for flash + promjet */
  72 + disable_tlb(flash_esel);
  73 +
  74 + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  75 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  76 + 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  77 +
  78 + set_liodns();
  79 +#ifdef CONFIG_SYS_DPAA_QBMAN
  80 + setup_portals();
  81 +#endif
  82 +
  83 + return 0;
  84 +}
  85 +
  86 +unsigned long get_board_sys_clk(void)
  87 +{
  88 + return CONFIG_SYS_CLK_FREQ;
  89 +}
  90 +
  91 +unsigned long get_board_ddr_clk(void)
  92 +{
  93 + return CONFIG_DDR_CLK_FREQ;
  94 +}
  95 +
  96 +int misc_init_r(void)
  97 +{
  98 + return 0;
  99 +}
  100 +
  101 +void ft_board_setup(void *blob, bd_t *bd)
  102 +{
  103 + phys_addr_t base;
  104 + phys_size_t size;
  105 +
  106 + ft_cpu_setup(blob, bd);
  107 +
  108 + base = getenv_bootm_low();
  109 + size = getenv_bootm_size();
  110 +
  111 + fdt_fixup_memory(blob, (u64)base, (u64)size);
  112 +
  113 +#ifdef CONFIG_PCI
  114 + pci_of_setup(blob, bd);
  115 +#endif
  116 +
  117 + fdt_fixup_liodn(blob);
  118 + fdt_fixup_dr_usb(blob, bd);
  119 +
  120 +#ifdef CONFIG_SYS_DPAA_FMAN
  121 + fdt_fixup_fman_ethernet(blob);
  122 + fdt_fixup_board_enet(blob);
  123 +#endif
  124 +}
board/freescale/t208xrdb/t208xrdb.h
Diff comments   View file @ 247161b
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __CORENET_DS_H__
  8 +#define __CORENET_DS_H__
  9 +
  10 +void fdt_fixup_board_enet(void *blob);
  11 +void pci_of_setup(void *blob, bd_t *bd);
  12 +
  13 +#endif
board/freescale/t208xrdb/tlb.c
Diff comments   View file @ 247161b
  1 +/*
  2 + * Copyright 2008-2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * (C) Copyright 2000
  5 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 + */
  9 +
  10 +#include <common.h>
  11 +#include <asm/mmu.h>
  12 +
  13 +struct fsl_e_tlb_entry tlb_table[] = {
  14 + /* TLB 0 - for temp stack in cache */
  15 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  16 + CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  17 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  18 + 0, 0, BOOKE_PAGESZ_4K, 0),
  19 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  20 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  21 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  22 + 0, 0, BOOKE_PAGESZ_4K, 0),
  23 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  24 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  25 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  26 + 0, 0, BOOKE_PAGESZ_4K, 0),
  27 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  28 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  29 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  30 + 0, 0, BOOKE_PAGESZ_4K, 0),
  31 +
  32 + /* TLB 1 */
  33 + /* *I*** - Covers boot page */
  34 +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  35 + /*
  36 + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  37 + * SRAM is at 0xfff00000, it covered the 0xfffff000.
  38 + */
  39 + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  40 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  41 + 0, 0, BOOKE_PAGESZ_1M, 1),
  42 +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  43 + /*
  44 + * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
  45 + * space is at 0xfff00000, it covered the 0xfffff000.
  46 + */
  47 + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
  48 + CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
  49 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
  50 + 0, 0, BOOKE_PAGESZ_1M, 1),
  51 +#else
  52 + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  53 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54 + 0, 0, BOOKE_PAGESZ_4K, 1),
  55 +#endif
  56 +
  57 + /* *I*G* - CCSRBAR */
  58 + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  59 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  60 + 0, 1, BOOKE_PAGESZ_16M, 1),
  61 +
  62 + /* *I*G* - Flash, localbus */
  63 + /* This will be changed to *I*G* after relocation to RAM. */
  64 + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  65 + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  66 + 0, 2, BOOKE_PAGESZ_256M, 1),
  67 +
  68 + /* *I*G* - PCIe 1, 0x80000000 */
  69 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  70 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  71 + 0, 3, BOOKE_PAGESZ_512M, 1),
  72 +
  73 + /* *I*G* - PCIe 2, 0xa0000000 */
  74 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
  75 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  76 + 0, 4, BOOKE_PAGESZ_256M, 1),
  77 +
  78 + /* *I*G* - PCIe 3, 0xb0000000 */
  79 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
  80 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  81 + 0, 5, BOOKE_PAGESZ_256M, 1),
  82 +
  83 +
  84 + /* *I*G* - PCIe 4, 0xc0000000 */
  85 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
  86 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  87 + 0, 6, BOOKE_PAGESZ_256M, 1),
  88 +
  89 + /* *I*G* - PCI I/O */
  90 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  91 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  92 + 0, 7, BOOKE_PAGESZ_256K, 1),
  93 +
  94 + /* Bman/Qman */
  95 +#ifdef CONFIG_SYS_BMAN_MEM_PHYS
  96 + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  97 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  98 + 0, 9, BOOKE_PAGESZ_16M, 1),
  99 + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
  100 + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
  101 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  102 + 0, 10, BOOKE_PAGESZ_16M, 1),
  103 +#endif
  104 +#ifdef CONFIG_SYS_QMAN_MEM_PHYS
  105 + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  106 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  107 + 0, 11, BOOKE_PAGESZ_16M, 1),
  108 + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
  109 + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
  110 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  111 + 0, 12, BOOKE_PAGESZ_16M, 1),
  112 +#endif
  113 +#ifdef CONFIG_SYS_DCSRBAR_PHYS
  114 + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  115 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  116 + 0, 13, BOOKE_PAGESZ_32M, 1),
  117 +#endif
  118 +#ifdef CONFIG_SYS_NAND_BASE
  119 + /*
  120 + * *I*G - NAND
  121 + * entry 14 and 15 has been used hard coded, they will be disabled
  122 + * in cpu_init_f, so we use entry 16 for nand.
  123 + */
  124 + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  125 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  126 + 0, 16, BOOKE_PAGESZ_64K, 1),
  127 +#endif
  128 +#ifdef CONFIG_SYS_CPLD_BASE
  129 + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
  130 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  131 + 0, 17, BOOKE_PAGESZ_4K, 1),
  132 +#endif
  133 +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  134 + /*
  135 + * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
  136 + * fetching ucode and ENV from master
  137 + */
  138 + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
  139 + CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
  140 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
  141 + 0, 18, BOOKE_PAGESZ_1M, 1),
  142 +#endif
  143 +#if defined(CONFIG_SYS_RAMBOOT)
  144 + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  145 + MAS3_SX|MAS3_SW|MAS3_SR, 0,
  146 + 0, 19, BOOKE_PAGESZ_2G, 1)
  147 +#endif
  148 +
  149 +};
  150 +
  151 +int num_tlb_entries = ARRAY_SIZE(tlb_table);
... ... @@ -983,6 +983,11 @@
983 983 Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
984 984 Active powerpc mpc85xx - freescale t208xqds T2081QDS_NAND T208xQDS:PPC_T2081,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
985 985 Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
  986 +Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080
  987 +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000
  988 +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000
  989 +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000
  990 +Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000
986 991 Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
987 992 Active powerpc mpc85xx - freescale t4qds T4160QDS_SDCARD T4240QDS:PPC_T4160,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
988 993 Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
include/configs/T1040QDS.h
Diff comments   View file @ 247161b
... ... @@ -375,7 +375,7 @@
375 375 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
376 376  
377 377 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
378   -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  378 +#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
379 379  
380 380 /* Serial Port - controlled on board with jumper J8
381 381 * open - index 2
... ... @@ -401,6 +401,25 @@
401 401 #define CONFIG_SYS_HUSH_PARSER
402 402 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
403 403  
  404 +/* Video */
  405 +#define CONFIG_FSL_DIU_FB
  406 +#ifdef CONFIG_FSL_DIU_FB
  407 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
  408 +#define CONFIG_VIDEO
  409 +#define CONFIG_CMD_BMP
  410 +#define CONFIG_CFB_CONSOLE
  411 +#define CONFIG_VIDEO_SW_CURSOR
  412 +#define CONFIG_VGA_AS_SINGLE_DEVICE
  413 +#define CONFIG_VIDEO_LOGO
  414 +#define CONFIG_VIDEO_BMP_LOGO
  415 +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
  416 +/*
  417 + * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
  418 + * disable empty flash sector detection, which is I/O-intensive.
  419 + */
  420 +#undef CONFIG_SYS_FLASH_EMPTY_INFO
  421 +#endif
  422 +
404 423 /* pass open firmware flat tree */
405 424 #define CONFIG_OF_LIBFDT
406 425 #define CONFIG_OF_BOARD_SETUP
407 426  
... ... @@ -426,7 +445,12 @@
426 445  
427 446 /* I2C bus multiplexer */
428 447 #define I2C_MUX_CH_DEFAULT 0x8
  448 +#define I2C_MUX_CH_DIU 0xC
429 449  
  450 +/* LDI/DVI Encoder for display */
  451 +#define CONFIG_SYS_I2C_LDI_ADDR 0x38
  452 +#define CONFIG_SYS_I2C_DVI_ADDR 0x75
  453 +
430 454 /*
431 455 * RTC configuration
432 456 */
... ... @@ -703,6 +727,7 @@
703 727 "bank_intlv=cs0_cs1;" \
704 728 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
705 729 "netdev=eth0\0" \
  730 + "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
706 731 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
707 732 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
708 733 "tftpflash=tftpboot $loadaddr $uboot && " \
include/configs/T1040RDB.h
Diff comments   View file @ 247161b
... ... @@ -147,7 +147,7 @@
147 147  
148 148 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
149 149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
150   -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  150 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
151 151  
152 152 #define CONFIG_DDR_SPD
153 153 #define CONFIG_SYS_DDR_RAW_TIMING
include/configs/T1042RDB_PI.h
Diff comments   View file @ 247161b
... ... @@ -147,7 +147,7 @@
147 147  
148 148 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
149 149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
150   -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  150 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
151 151  
152 152 #define CONFIG_DDR_SPD
153 153 #define CONFIG_SYS_DDR_RAW_TIMING
include/configs/T208xQDS.h
Diff comments   View file @ 247161b
... ... @@ -242,7 +242,7 @@
242 242 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
243 243 FTIM1_GPCM_TRAD(0x3f))
244 244 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
245   - FTIM2_GPCM_TCH(0x0) | \
  245 + FTIM2_GPCM_TCH(0x8) | \
246 246 FTIM2_GPCM_TWP(0x1f))
247 247 #define CONFIG_SYS_CS3_FTIM3 0x0
248 248  
include/configs/T208xRDB.h
Diff comments   View file @ 247161b
  1 +/*
  2 + * Copyright 2014 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +/*
  8 + * T2080 RDB/PCIe board configuration file
  9 + */
  10 +
  11 +#ifndef __T2080RDB_H
  12 +#define __T2080RDB_H
  13 +
  14 +#define CONFIG_T2080RDB
  15 +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
  16 +#define CONFIG_MMC
  17 +#define CONFIG_SPI_FLASH
  18 +#define CONFIG_USB_EHCI
  19 +#define CONFIG_FSL_SATA_V2
  20 +
  21 +/* High Level Configuration Options */
  22 +#define CONFIG_PHYS_64BIT
  23 +#define CONFIG_BOOKE
  24 +#define CONFIG_E500 /* BOOKE e500 family */
  25 +#define CONFIG_E500MC /* BOOKE e500mc family */
  26 +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  27 +#define CONFIG_MP /* support multiple processors */
  28 +#define CONFIG_ENABLE_36BIT_PHYS
  29 +
  30 +#ifdef CONFIG_PHYS_64BIT
  31 +#define CONFIG_ADDR_MAP 1
  32 +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  33 +#endif
  34 +
  35 +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  36 +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
  37 +#define CONFIG_FSL_IFC /* Enable IFC Support */
  38 +#define CONFIG_FSL_LAW /* Use common FSL init code */
  39 +#define CONFIG_ENV_OVERWRITE
  40 +
  41 +#ifdef CONFIG_RAMBOOT_PBL
  42 +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  43 +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  44 +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t208xrdb/t2080_pbi.cfg
  45 +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t208xrdb/t2080_rcw.cfg
  46 +#endif
  47 +
  48 +#define CONFIG_SRIO_PCIE_BOOT_MASTER
  49 +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  50 +/* Set 1M boot space */
  51 +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  52 +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  53 + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  54 +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  55 +#define CONFIG_SYS_NO_FLASH
  56 +#endif
  57 +
  58 +#ifndef CONFIG_SYS_TEXT_BASE
  59 +#define CONFIG_SYS_TEXT_BASE 0xeff40000
  60 +#endif
  61 +
  62 +#ifndef CONFIG_RESET_VECTOR_ADDRESS
  63 +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  64 +#endif
  65 +
  66 +/*
  67 + * These can be toggled for performance analysis, otherwise use default.
  68 + */
  69 +#define CONFIG_SYS_CACHE_STASHING
  70 +#define CONFIG_BTB /* toggle branch predition */
  71 +#define CONFIG_DDR_ECC
  72 +#ifdef CONFIG_DDR_ECC
  73 +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  74 +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  75 +#endif
  76 +
  77 +#ifdef CONFIG_SYS_NO_FLASH
  78 +#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
  79 +#define CONFIG_ENV_IS_NOWHERE
  80 +#endif
  81 +#else
  82 +#define CONFIG_FLASH_CFI_DRIVER
  83 +#define CONFIG_SYS_FLASH_CFI
  84 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  85 +#endif
  86 +
  87 +#if defined(CONFIG_SPIFLASH)
  88 +#define CONFIG_SYS_EXTRA_ENV_RELOC
  89 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  90 +#define CONFIG_ENV_SPI_BUS 0
  91 +#define CONFIG_ENV_SPI_CS 0
  92 +#define CONFIG_ENV_SPI_MAX_HZ 10000000
  93 +#define CONFIG_ENV_SPI_MODE 0
  94 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  95 +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
  96 +#define CONFIG_ENV_SECT_SIZE 0x10000
  97 +#elif defined(CONFIG_SDCARD)
  98 +#define CONFIG_SYS_EXTRA_ENV_RELOC
  99 +#define CONFIG_ENV_IS_IN_MMC
  100 +#define CONFIG_SYS_MMC_ENV_DEV 0
  101 +#define CONFIG_ENV_SIZE 0x2000
  102 +#define CONFIG_ENV_OFFSET (512 * 1658)
  103 +#elif defined(CONFIG_NAND)
  104 +#define CONFIG_SYS_EXTRA_ENV_RELOC
  105 +#define CONFIG_ENV_IS_IN_NAND
  106 +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  107 +#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
  108 +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  109 +#define CONFIG_ENV_IS_IN_REMOTE
  110 +#define CONFIG_ENV_ADDR 0xffe20000
  111 +#define CONFIG_ENV_SIZE 0x2000
  112 +#elif defined(CONFIG_ENV_IS_NOWHERE)
  113 +#define CONFIG_ENV_SIZE 0x2000
  114 +#else
  115 +#define CONFIG_ENV_IS_IN_FLASH
  116 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  117 +#define CONFIG_ENV_SIZE 0x2000
  118 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  119 +#endif
  120 +
  121 +#ifndef __ASSEMBLY__
  122 +unsigned long get_board_sys_clk(void);
  123 +unsigned long get_board_ddr_clk(void);
  124 +#endif
  125 +
  126 +#define CONFIG_SYS_CLK_FREQ 66660000
  127 +#define CONFIG_DDR_CLK_FREQ 133330000
  128 +
  129 +/*
  130 + * Config the L3 Cache as L3 SRAM
  131 + */
  132 +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  133 +
  134 +#define CONFIG_SYS_DCSRBAR 0xf0000000
  135 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  136 +
  137 +/* EEPROM */
  138 +#define CONFIG_ID_EEPROM
  139 +#define CONFIG_SYS_I2C_EEPROM_NXID
  140 +#define CONFIG_SYS_EEPROM_BUS_NUM 0
  141 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
  142 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  143 +
  144 +/*
  145 + * DDR Setup
  146 + */
  147 +#define CONFIG_VERY_BIG_RAM
  148 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  149 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  150 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
  151 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  152 +#define CONFIG_DDR_SPD
  153 +#define CONFIG_SYS_FSL_DDR3
  154 +#undef CONFIG_FSL_DDR_INTERACTIVE
  155 +#define CONFIG_SYS_SPD_BUS_NUM 0
  156 +#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
  157 +#define SPD_EEPROM_ADDRESS1 0x51
  158 +#define SPD_EEPROM_ADDRESS2 0x52
  159 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  160 +#define CTRL_INTLV_PREFERED cacheline
  161 +
  162 +/*
  163 + * IFC Definitions
  164 + */
  165 +#define CONFIG_SYS_FLASH_BASE 0xe8000000
  166 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
  167 +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
  168 +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  169 + CSPR_PORT_SIZE_16 | \
  170 + CSPR_MSEL_NOR | \
  171 + CSPR_V)
  172 +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  173 +
  174 +/* NOR Flash Timing Params */
  175 +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
  176 +
  177 +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  178 + FTIM0_NOR_TEADC(0x5) | \
  179 + FTIM0_NOR_TEAHC(0x5))
  180 +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  181 + FTIM1_NOR_TRAD_NOR(0x1A) |\
  182 + FTIM1_NOR_TSEQRAD_NOR(0x13))
  183 +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  184 + FTIM2_NOR_TCH(0x4) | \
  185 + FTIM2_NOR_TWPH(0x0E) | \
  186 + FTIM2_NOR_TWP(0x1c))
  187 +#define CONFIG_SYS_NOR_FTIM3 0x0
  188 +
  189 +#define CONFIG_SYS_FLASH_QUIET_TEST
  190 +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  191 +
  192 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  193 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  194 +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  195 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  196 +#define CONFIG_SYS_FLASH_EMPTY_INFO
  197 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
  198 +
  199 +/* CPLD on IFC */
  200 +#define CONFIG_SYS_CPLD_BASE 0xffdf0000
  201 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
  202 +#define CONFIG_SYS_CSPR2_EXT (0xf)
  203 +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
  204 + | CSPR_PORT_SIZE_8 \
  205 + | CSPR_MSEL_GPCM \
  206 + | CSPR_V)
  207 +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
  208 +#define CONFIG_SYS_CSOR2 0x0
  209 +
  210 +/* CPLD Timing parameters for IFC CS2 */
  211 +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  212 + FTIM0_GPCM_TEADC(0x0e) | \
  213 + FTIM0_GPCM_TEAHC(0x0e))
  214 +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
  215 + FTIM1_GPCM_TRAD(0x1f))
  216 +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
  217 + FTIM2_GPCM_TCH(0x0) | \
  218 + FTIM2_GPCM_TWP(0x1f))
  219 +#define CONFIG_SYS_CS2_FTIM3 0x0
  220 +
  221 +/* NAND Flash on IFC */
  222 +#define CONFIG_NAND_FSL_IFC
  223 +#define CONFIG_SYS_NAND_BASE 0xff800000
  224 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
  225 +
  226 +#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
  227 +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  228 + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  229 + | CSPR_MSEL_NAND /* MSEL = NAND */ \
  230 + | CSPR_V)
  231 +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
  232 +
  233 +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  234 + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  235 + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  236 + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
  237 + | CSOR_NAND_PGS_2K /* Page Size = 2K */\
  238 + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
  239 + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  240 +
  241 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  242 +
  243 +/* ONFI NAND Flash mode0 Timing Params */
  244 +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  245 + FTIM0_NAND_TWP(0x18) | \
  246 + FTIM0_NAND_TWCHT(0x07) | \
  247 + FTIM0_NAND_TWH(0x0a))
  248 +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  249 + FTIM1_NAND_TWBE(0x39) | \
  250 + FTIM1_NAND_TRR(0x0e) | \
  251 + FTIM1_NAND_TRP(0x18))
  252 +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  253 + FTIM2_NAND_TREH(0x0a) | \
  254 + FTIM2_NAND_TWHRE(0x1e))
  255 +#define CONFIG_SYS_NAND_FTIM3 0x0
  256 +
  257 +#define CONFIG_SYS_NAND_DDR_LAW 11
  258 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  259 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
  260 +#define CONFIG_MTD_NAND_VERIFY_WRITE
  261 +#define CONFIG_CMD_NAND
  262 +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
  263 +
  264 +#if defined(CONFIG_NAND)
  265 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  266 +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  267 +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  268 +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  269 +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  270 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  271 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  272 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  273 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  274 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
  275 +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  276 +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  277 +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  278 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  279 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  280 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  281 +#else
  282 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  283 +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
  284 +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  285 +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  286 +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  287 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  288 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  289 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  290 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
  291 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
  292 +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
  293 +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
  294 +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
  295 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
  296 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
  297 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
  298 +#endif
  299 +
  300 +#if defined(CONFIG_RAMBOOT_PBL)
  301 +#define CONFIG_SYS_RAMBOOT
  302 +#endif
  303 +
  304 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  305 +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  306 +#define CONFIG_MISC_INIT_R
  307 +#define CONFIG_HWCONFIG
  308 +
  309 +/* define to use L1 as initial stack */
  310 +#define CONFIG_L1_INIT_RAM
  311 +#define CONFIG_SYS_INIT_RAM_LOCK
  312 +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  313 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  314 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
  315 +/* The assembler doesn't like typecast */
  316 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  317 + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  318 + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  319 +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  320 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  321 + GENERATED_GBL_DATA_SIZE)
  322 +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  323 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  324 +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
  325 +
  326 +/*
  327 + * Serial Port
  328 + */
  329 +#define CONFIG_CONS_INDEX 1
  330 +#define CONFIG_SYS_NS16550
  331 +#define CONFIG_SYS_NS16550_SERIAL
  332 +#define CONFIG_SYS_NS16550_REG_SIZE 1
  333 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  334 +#define CONFIG_SYS_BAUDRATE_TABLE \
  335 + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  336 +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  337 +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  338 +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  339 +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  340 +
  341 +/* Use the HUSH parser */
  342 +#define CONFIG_SYS_HUSH_PARSER
  343 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  344 +
  345 +/* pass open firmware flat tree */
  346 +#define CONFIG_OF_LIBFDT
  347 +#define CONFIG_OF_BOARD_SETUP
  348 +#define CONFIG_OF_STDOUT_VIA_ALIAS
  349 +
  350 +/* new uImage format support */
  351 +#define CONFIG_FIT
  352 +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  353 +
  354 +/*
  355 + * I2C
  356 + */
  357 +#define CONFIG_SYS_I2C
  358 +#define CONFIG_SYS_I2C_FSL
  359 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  360 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  361 +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  362 +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  363 +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  364 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  365 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  366 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  367 +#define CONFIG_SYS_FSL_I2C_SPEED 100000
  368 +#define CONFIG_SYS_FSL_I2C2_SPEED 100000
  369 +#define CONFIG_SYS_FSL_I2C3_SPEED 100000
  370 +#define CONFIG_SYS_FSL_I2C4_SPEED 100000
  371 +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
  372 +#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
  373 +#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
  374 +#define I2C_MUX_CH_DEFAULT 0x8
  375 +
  376 +
  377 +/*
  378 + * RapidIO
  379 + */
  380 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
  381 +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
  382 +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
  383 +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
  384 +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
  385 +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
  386 +/*
  387 + * for slave u-boot IMAGE instored in master memory space,
  388 + * PHYS must be aligned based on the SIZE
  389 + */
  390 +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
  391 +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
  392 +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */
  393 +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
  394 +/*
  395 + * for slave UCODE and ENV instored in master memory space,
  396 + * PHYS must be aligned based on the SIZE
  397 + */
  398 +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
  399 +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
  400 +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
  401 +
  402 +/* slave core release by master*/
  403 +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
  404 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
  405 +
  406 +/*
  407 + * SRIO_PCIE_BOOT - SLAVE
  408 + */
  409 +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  410 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
  411 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
  412 + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
  413 +#endif
  414 +
  415 +/*
  416 + * eSPI - Enhanced SPI
  417 + */
  418 +#ifdef CONFIG_SPI_FLASH
  419 +#define CONFIG_FSL_ESPI
  420 +#define CONFIG_SPI_FLASH_STMICRO
  421 +#define CONFIG_SPI_FLASH_BAR
  422 +#define CONFIG_CMD_SF
  423 +#define CONFIG_SF_DEFAULT_SPEED 10000000
  424 +#define CONFIG_SF_DEFAULT_MODE 0
  425 +#endif
  426 +
  427 +/*
  428 + * General PCI
  429 + * Memory space is mapped 1-1, but I/O space must start from 0.
  430 + */
  431 +#define CONFIG_PCI /* Enable PCI/PCIE */
  432 +#define CONFIG_PCIE1 /* PCIE controler 1 */
  433 +#define CONFIG_PCIE2 /* PCIE controler 2 */
  434 +#define CONFIG_PCIE3 /* PCIE controler 3 */
  435 +#define CONFIG_PCIE4 /* PCIE controler 4 */
  436 +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  437 +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  438 +/* controller 1, direct to uli, tgtid 3, Base address 20000 */
  439 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  440 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  441 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  442 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  443 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  444 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  445 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  446 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  447 +
  448 +/* controller 2, Slot 2, tgtid 2, Base address 201000 */
  449 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  450 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  451 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  452 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
  453 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  454 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  455 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  456 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  457 +
  458 +/* controller 3, Slot 1, tgtid 1, Base address 202000 */
  459 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
  460 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  461 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
  462 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
  463 +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  464 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  465 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  466 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  467 +
  468 +/* controller 4, Base address 203000 */
  469 +#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
  470 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  471 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
  472 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
  473 +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  474 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  475 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  476 +
  477 +#ifdef CONFIG_PCI
  478 +#define CONFIG_PCI_INDIRECT_BRIDGE
  479 +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
  480 +#define CONFIG_NET_MULTI
  481 +#define CONFIG_E1000
  482 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
  483 +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  484 +#define CONFIG_DOS_PARTITION
  485 +#endif
  486 +
  487 +/* Qman/Bman */
  488 +#ifndef CONFIG_NOBQFMAN
  489 +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
  490 +#define CONFIG_SYS_BMAN_NUM_PORTALS 18
  491 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  492 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  493 +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
  494 +#define CONFIG_SYS_QMAN_NUM_PORTALS 18
  495 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
  496 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
  497 +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
  498 +
  499 +#define CONFIG_SYS_DPAA_FMAN
  500 +#define CONFIG_SYS_DPAA_PME
  501 +#define CONFIG_SYS_PMAN
  502 +#define CONFIG_SYS_DPAA_DCE
  503 +#define CONFIG_SYS_DPAA_RMAN /* RMan */
  504 +#define CONFIG_SYS_INTERLAKEN
  505 +
  506 +/* Default address of microcode for the Linux Fman driver */
  507 +#if defined(CONFIG_SPIFLASH)
  508 +/*
  509 + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
  510 + * env, so we got 0x110000.
  511 + */
  512 +#define CONFIG_SYS_QE_FW_IN_SPIFLASH
  513 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
  514 +#define CONFIG_CORTINA_FW_ADDR 0x120000
  515 +
  516 +#elif defined(CONFIG_SDCARD)
  517 +/*
  518 + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  519 + * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  520 + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  521 + */
  522 +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  523 +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680)
  524 +#define CONFIG_CORTINA_FW_ADDR (512 * 1808)
  525 +
  526 +#elif defined(CONFIG_NAND)
  527 +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
  528 +#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
  529 +#define CONFIG_CORTINA_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
  530 +#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  531 +/*
  532 + * Slave has no ucode locally, it can fetch this from remote. When implementing
  533 + * in two corenet boards, slave's ucode could be stored in master's memory
  534 + * space, the address can be mapped from slave TLB->slave LAW->
  535 + * slave SRIO or PCIE outbound window->master inbound window->
  536 + * master LAW->the ucode address in master's memory space.
  537 + */
  538 +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
  539 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000
  540 +#define CONFIG_CORTINA_FW_ADDR 0xFFE10000
  541 +#else
  542 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
  543 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000
  544 +#define CONFIG_CORTINA_FW_ADDR 0xEFE00000
  545 +#endif
  546 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  547 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  548 +#endif /* CONFIG_NOBQFMAN */
  549 +
  550 +#ifdef CONFIG_SYS_DPAA_FMAN
  551 +#define CONFIG_FMAN_ENET
  552 +#define CONFIG_PHYLIB_10G
  553 +#define CONFIG_PHY_CORTINA
  554 +#define CONFIG_PHY_AQ1202
  555 +#define CONFIG_PHY_REALTEK
  556 +#define CONFIG_CORTINA_FW_LENGTH 0x40000
  557 +#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
  558 +#define RGMII_PHY2_ADDR 0x02
  559 +#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
  560 +#define CORTINA_PHY_ADDR2 0x0d
  561 +#define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
  562 +#define FM1_10GEC4_PHY_ADDR 0x01
  563 +#endif
  564 +
  565 +
  566 +#ifdef CONFIG_FMAN_ENET
  567 +#define CONFIG_MII /* MII PHY management */
  568 +#define CONFIG_ETHPRIME "FM1@DTSEC3"
  569 +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  570 +#endif
  571 +
  572 +/*
  573 + * SATA
  574 + */
  575 +#ifdef CONFIG_FSL_SATA_V2
  576 +#define CONFIG_LIBATA
  577 +#define CONFIG_FSL_SATA
  578 +#define CONFIG_SYS_SATA_MAX_DEVICE 2
  579 +#define CONFIG_SATA1
  580 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  581 +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  582 +#define CONFIG_SATA2
  583 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  584 +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  585 +#define CONFIG_LBA48
  586 +#define CONFIG_CMD_SATA
  587 +#define CONFIG_DOS_PARTITION
  588 +#define CONFIG_CMD_EXT2
  589 +#endif
  590 +
  591 +/*
  592 + * USB
  593 + */
  594 +#ifdef CONFIG_USB_EHCI
  595 +#define CONFIG_CMD_USB
  596 +#define CONFIG_USB_STORAGE
  597 +#define CONFIG_USB_EHCI_FSL
  598 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  599 +#define CONFIG_CMD_EXT2
  600 +#define CONFIG_HAS_FSL_DR_USB
  601 +#endif
  602 +
  603 +/*
  604 + * SDHC
  605 + */
  606 +#ifdef CONFIG_MMC
  607 +#define CONFIG_CMD_MMC
  608 +#define CONFIG_FSL_ESDHC
  609 +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  610 +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  611 +#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  612 +#define CONFIG_GENERIC_MMC
  613 +#define CONFIG_CMD_EXT2
  614 +#define CONFIG_CMD_FAT
  615 +#define CONFIG_DOS_PARTITION
  616 +#endif
  617 +
  618 +/*
  619 + * Environment
  620 + */
  621 +
  622 +/*
  623 + * Command line configuration.
  624 + */
  625 +#include <config_cmd_default.h>
  626 +
  627 +#define CONFIG_CMD_DHCP
  628 +#define CONFIG_CMD_ELF
  629 +#define CONFIG_CMD_MII
  630 +#define CONFIG_CMD_I2C
  631 +#define CONFIG_CMD_PING
  632 +#define CONFIG_CMD_ECHO
  633 +#define CONFIG_CMD_SETEXPR
  634 +#define CONFIG_CMD_REGINFO
  635 +#define CONFIG_CMD_BDI
  636 +
  637 +#ifdef CONFIG_PCI
  638 +#define CONFIG_CMD_PCI
  639 +#define CONFIG_CMD_NET
  640 +#endif
  641 +
  642 +/*
  643 + * Miscellaneous configurable options
  644 + */
  645 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  646 +#define CONFIG_CMDLINE_EDITING /* Command-line editing */
  647 +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  648 +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  649 +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  650 +#ifdef CONFIG_CMD_KGDB
  651 +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  652 +#else
  653 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  654 +#endif
  655 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
  656 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  657 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  658 +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/
  659 +
  660 +/*
  661 + * For booting Linux, the board info and command line data
  662 + * have to be in the first 64 MB of memory, since this is
  663 + * the maximum mapped by the Linux kernel during initialization.
  664 + */
  665 +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
  666 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  667 +
  668 +#ifdef CONFIG_CMD_KGDB
  669 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  670 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  671 +#endif
  672 +
  673 +/*
  674 + * Environment Configuration
  675 + */
  676 +#define CONFIG_ROOTPATH "/opt/nfsroot"
  677 +#define CONFIG_BOOTFILE "uImage"
  678 +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
  679 +
  680 +/* default location for tftp and bootm */
  681 +#define CONFIG_LOADADDR 1000000
  682 +#define CONFIG_BAUDRATE 115200
  683 +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  684 +#define __USB_PHY_TYPE utmi
  685 +
  686 +#define CONFIG_EXTRA_ENV_SETTINGS \
  687 + "hwconfig=fsl_ddr:" \
  688 + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
  689 + "bank_intlv=auto;" \
  690 + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  691 + "netdev=eth0\0" \
  692 + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  693 + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  694 + "tftpflash=tftpboot $loadaddr $uboot && " \
  695 + "protect off $ubootaddr +$filesize && " \
  696 + "erase $ubootaddr +$filesize && " \
  697 + "cp.b $loadaddr $ubootaddr $filesize && " \
  698 + "protect on $ubootaddr +$filesize && " \
  699 + "cmp.b $loadaddr $ubootaddr $filesize\0" \
  700 + "consoledev=ttyS0\0" \
  701 + "ramdiskaddr=2000000\0" \
  702 + "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
  703 + "fdtaddr=c00000\0" \
  704 + "fdtfile=t2080rdb/t2080rdb.dtb\0" \
  705 + "bdev=sda3\0" \
  706 + "c=ffe\0"
  707 +
  708 +/*
  709 + * For emulation this causes u-boot to jump to the start of the
  710 + * proof point app code automatically
  711 + */
  712 +#define CONFIG_PROOF_POINTS \
  713 + "setenv bootargs root=/dev/$bdev rw " \
  714 + "console=$consoledev,$baudrate $othbootargs;" \
  715 + "cpu 1 release 0x29000000 - - -;" \
  716 + "cpu 2 release 0x29000000 - - -;" \
  717 + "cpu 3 release 0x29000000 - - -;" \
  718 + "cpu 4 release 0x29000000 - - -;" \
  719 + "cpu 5 release 0x29000000 - - -;" \
  720 + "cpu 6 release 0x29000000 - - -;" \
  721 + "cpu 7 release 0x29000000 - - -;" \
  722 + "go 0x29000000"
  723 +
  724 +#define CONFIG_HVBOOT \
  725 + "setenv bootargs config-addr=0x60000000; " \
  726 + "bootm 0x01000000 - 0x00f00000"
  727 +
  728 +#define CONFIG_ALU \
  729 + "setenv bootargs root=/dev/$bdev rw " \
  730 + "console=$consoledev,$baudrate $othbootargs;" \
  731 + "cpu 1 release 0x01000000 - - -;" \
  732 + "cpu 2 release 0x01000000 - - -;" \
  733 + "cpu 3 release 0x01000000 - - -;" \
  734 + "cpu 4 release 0x01000000 - - -;" \
  735 + "cpu 5 release 0x01000000 - - -;" \
  736 + "cpu 6 release 0x01000000 - - -;" \
  737 + "cpu 7 release 0x01000000 - - -;" \
  738 + "go 0x01000000"
  739 +
  740 +#define CONFIG_LINUX \
  741 + "setenv bootargs root=/dev/ram rw " \
  742 + "console=$consoledev,$baudrate $othbootargs;" \
  743 + "setenv ramdiskaddr 0x02000000;" \
  744 + "setenv fdtaddr 0x00c00000;" \
  745 + "setenv loadaddr 0x1000000;" \
  746 + "bootm $loadaddr $ramdiskaddr $fdtaddr"
  747 +
  748 +#define CONFIG_HDBOOT \
  749 + "setenv bootargs root=/dev/$bdev rw " \
  750 + "console=$consoledev,$baudrate $othbootargs;" \
  751 + "tftp $loadaddr $bootfile;" \
  752 + "tftp $fdtaddr $fdtfile;" \
  753 + "bootm $loadaddr - $fdtaddr"
  754 +
  755 +#define CONFIG_NFSBOOTCOMMAND \
  756 + "setenv bootargs root=/dev/nfs rw " \
  757 + "nfsroot=$serverip:$rootpath " \
  758 + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  759 + "console=$consoledev,$baudrate $othbootargs;" \
  760 + "tftp $loadaddr $bootfile;" \
  761 + "tftp $fdtaddr $fdtfile;" \
  762 + "bootm $loadaddr - $fdtaddr"
  763 +
  764 +#define CONFIG_RAMBOOTCOMMAND \
  765 + "setenv bootargs root=/dev/ram rw " \
  766 + "console=$consoledev,$baudrate $othbootargs;" \
  767 + "tftp $ramdiskaddr $ramdiskfile;" \
  768 + "tftp $loadaddr $bootfile;" \
  769 + "tftp $fdtaddr $fdtfile;" \
  770 + "bootm $loadaddr $ramdiskaddr $fdtaddr"
  771 +
  772 +#define CONFIG_BOOTCOMMAND CONFIG_LINUX
  773 +
  774 +#ifdef CONFIG_SECURE_BOOT
  775 +#include <asm/fsl_secure_boot.h>
  776 +#undef CONFIG_CMD_USB
  777 +#endif
  778 +
  779 +#endif /* __T2080RDB_H */
... ... @@ -52,13 +52,32 @@
52 52 #define CONFIG_SYS_FSL_USB_PLLPRG2_MFI (5 << 16)
53 53 #define CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN (1 << 21)
54 54 #define CONFIG_SYS_FSL_USB_SYS_CLK_VALID (1 << 0)
  55 +#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN (1 << 7)
  56 +#define CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK (3 << 4)
  57 +
  58 +#define INC_DCNT_THRESHOLD_25MV (0 << 4)
  59 +#define INC_DCNT_THRESHOLD_50MV (1 << 4)
  60 +#define DEC_DCNT_THRESHOLD_25MV (2 << 4)
  61 +#define DEC_DCNT_THRESHOLD_50MV (3 << 4)
55 62 #else
56 63 struct ccsr_usb_phy {
57   - u8 res0[0x18];
  64 + u32 config1;
  65 + u32 config2;
  66 + u32 config3;
  67 + u32 config4;
  68 + u32 config5;
  69 + u32 status1;
58 70 u32 usb_enable_override;
59 71 u8 res[0xe4];
60 72 };
61   -#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
  73 +#define CONFIG_SYS_FSL_USB_HS_DISCNCT_INC (3 << 22)
  74 +#define CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL (1 << 20)
  75 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0 13
  76 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3 16
  77 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0 0
  78 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3 3
  79 +#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1
  80 +#define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
62 81 #endif
63 82  
64 83 #endif /*_ASM_FSL_USB_H_ */