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Commit 29fc6f24926e2c9d37dbbc37a2e2df2eced4c678

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent a2f39e830e
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: remove a320evb board support 

This is still a non-generic board.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Po-Yu Chuang <ratbert@faraday-tech.com>
Acked-by: Marek Vasut <marex@denx.de>

Showing 14 changed files with 1 additions and 573 deletions Side-by-side Diff

... ... @@ -73,10 +73,6 @@
73 73 bool "Support integratorcp_cm920t"
74 74 select CPU_ARM920T
75 75  
76   -config TARGET_A320EVB
77   - bool "Support a320evb"
78   - select CPU_ARM920T
79   -
80 76 config ARCH_AT91
81 77 bool "Atmel AT91"
82 78  
... ... @@ -770,7 +766,6 @@
770 766 source "board/denx/m53evk/Kconfig"
771 767 source "board/embest/mx6boards/Kconfig"
772 768 source "board/esg/ima3-mx53/Kconfig"
773   -source "board/faraday/a320evb/Kconfig"
774 769 source "board/freescale/ls2085a/Kconfig"
775 770 source "board/freescale/ls1021aqds/Kconfig"
776 771 source "board/freescale/ls1021atwr/Kconfig"
arch/arm/cpu/arm920t/Makefile
Diff comments   View file @ 29fc6f2
... ... @@ -10,7 +10,6 @@
10 10 obj-y += cpu.o
11 11 obj-$(CONFIG_USE_IRQ) += interrupts.o
12 12  
13   -obj-$(if $(filter a320,$(SOC)),y) += a320/
14 13 obj-$(CONFIG_EP93XX) += ep93xx/
15 14 obj-$(CONFIG_IMX) += imx/
16 15 obj-$(CONFIG_S3C24X0) += s3c24x0/
arch/arm/cpu/arm920t/a320/Makefile
View file @ 29fc6f2
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y += reset.o
9   -obj-y += timer.o
arch/arm/cpu/arm920t/a320/reset.S
View file @ 29fc6f2
1   -/*
2   - * (C) Copyright 2009 Faraday Technology
3   - * Po-Yu Chuang <ratbert@faraday-tech.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -.global reset_cpu
9   -reset_cpu:
10   - b reset_cpu
arch/arm/cpu/arm920t/a320/timer.c
View file @ 29fc6f2
1   -/*
2   - * (C) Copyright 2009 Faraday Technology
3   - * Po-Yu Chuang <ratbert@faraday-tech.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <div64.h>
10   -#include <asm/io.h>
11   -#include <faraday/ftpmu010.h>
12   -#include <faraday/fttmr010.h>
13   -
14   -DECLARE_GLOBAL_DATA_PTR;
15   -
16   -#define TIMER_CLOCK 32768
17   -#define TIMER_LOAD_VAL 0xffffffff
18   -
19   -static inline unsigned long long tick_to_time(unsigned long long tick)
20   -{
21   - tick *= CONFIG_SYS_HZ;
22   - do_div(tick, gd->arch.timer_rate_hz);
23   -
24   - return tick;
25   -}
26   -
27   -static inline unsigned long long usec_to_tick(unsigned long long usec)
28   -{
29   - usec *= gd->arch.timer_rate_hz;
30   - do_div(usec, 1000000);
31   -
32   - return usec;
33   -}
34   -
35   -int timer_init(void)
36   -{
37   - struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
38   - unsigned int cr;
39   -
40   - debug("%s()\n", __func__);
41   -
42   - /* disable timers */
43   - writel(0, &tmr->cr);
44   -
45   - /* use 32768Hz oscillator for RTC, WDT, TIMER */
46   - ftpmu010_32768osc_enable();
47   -
48   - /* setup timer */
49   - writel(TIMER_LOAD_VAL, &tmr->timer3_load);
50   - writel(TIMER_LOAD_VAL, &tmr->timer3_counter);
51   - writel(0, &tmr->timer3_match1);
52   - writel(0, &tmr->timer3_match2);
53   -
54   - /* we don't want timer to issue interrupts */
55   - writel(FTTMR010_TM3_MATCH1 |
56   - FTTMR010_TM3_MATCH2 |
57   - FTTMR010_TM3_OVERFLOW,
58   - &tmr->interrupt_mask);
59   -
60   - cr = readl(&tmr->cr);
61   - cr |= FTTMR010_TM3_CLOCK; /* use external clock */
62   - cr |= FTTMR010_TM3_ENABLE;
63   - writel(cr, &tmr->cr);
64   -
65   - gd->arch.timer_rate_hz = TIMER_CLOCK;
66   - gd->arch.tbu = gd->arch.tbl = 0;
67   -
68   - return 0;
69   -}
70   -
71   -/*
72   - * Get the current 64 bit timer tick count
73   - */
74   -unsigned long long get_ticks(void)
75   -{
76   - struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE;
77   - ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter);
78   -
79   - /* increment tbu if tbl has rolled over */
80   - if (now < gd->arch.tbl)
81   - gd->arch.tbu++;
82   - gd->arch.tbl = now;
83   - return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
84   -}
85   -
86   -void __udelay(unsigned long usec)
87   -{
88   - unsigned long long start;
89   - ulong tmo;
90   -
91   - start = get_ticks(); /* get current timestamp */
92   - tmo = usec_to_tick(usec); /* convert usecs to ticks */
93   - while ((get_ticks() - start) < tmo)
94   - ; /* loop till time has passed */
95   -}
96   -
97   -/*
98   - * get_timer(base) can be used to check for timeouts or
99   - * to measure elasped time relative to an event:
100   - *
101   - * ulong start_time = get_timer(0) sets start_time to the current
102   - * time value.
103   - * get_timer(start_time) returns the time elapsed since then.
104   - *
105   - * The time is used in CONFIG_SYS_HZ units!
106   - */
107   -ulong get_timer(ulong base)
108   -{
109   - return tick_to_time(get_ticks()) - base;
110   -}
111   -
112   -/*
113   - * Return the number of timer ticks per second.
114   - */
115   -ulong get_tbclk(void)
116   -{
117   - return gd->arch.timer_rate_hz;
118   -}
arch/arm/include/asm/arch-a320/a320.h
View file @ 29fc6f2
1   -/*
2   - * (C) Copyright 2009 Faraday Technology
3   - * Po-Yu Chuang <ratbert@faraday-tech.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#ifndef __A320_H
9   -#define __A320_H
10   -
11   -/*
12   - * Hardware register bases
13   - */
14   -#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */
15   -#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */
16   -#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */
17   -#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */
18   -#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */
19   -#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */
20   -#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/
21   -
22   -#endif /* __A320_H */
board/faraday/a320evb/Kconfig
View file @ 29fc6f2
1   -if TARGET_A320EVB
2   -
3   -config SYS_BOARD
4   - default "a320evb"
5   -
6   -config SYS_VENDOR
7   - default "faraday"
8   -
9   -config SYS_SOC
10   - default "a320"
11   -
12   -config SYS_CONFIG_NAME
13   - default "a320evb"
14   -
15   -endif
board/faraday/a320evb/MAINTAINERS
View file @ 29fc6f2
1   -A320EVB BOARD
2   -M: Po-Yu Chuang <ratbert@faraday-tech.com>
3   -S: Maintained
4   -F: board/faraday/a320evb/
5   -F: include/configs/a320evb.h
6   -F: configs/a320evb_defconfig
board/faraday/a320evb/Makefile
View file @ 29fc6f2
1   -#
2   -# (C) Copyright 2000-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y := a320evb.o
9   -obj-y += lowlevel_init.o
board/faraday/a320evb/a320evb.c
View file @ 29fc6f2
1   -/*
2   - * (C) Copyright 2009 Faraday Technology
3   - * Po-Yu Chuang <ratbert@faraday-tech.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <netdev.h>
10   -#include <asm/io.h>
11   -
12   -#include <faraday/ftsmc020.h>
13   -
14   -DECLARE_GLOBAL_DATA_PTR;
15   -
16   -/*
17   - * Miscellaneous platform dependent initialisations
18   - */
19   -
20   -int board_init(void)
21   -{
22   - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
23   -
24   - ftsmc020_init(); /* initialize Flash */
25   - return 0;
26   -}
27   -
28   -int dram_init(void)
29   -{
30   - unsigned long sdram_base = PHYS_SDRAM_1;
31   - unsigned long expected_size = PHYS_SDRAM_1_SIZE;
32   - unsigned long actual_size;
33   -
34   - actual_size = get_ram_size((void *)sdram_base, expected_size);
35   -
36   - gd->ram_size = actual_size;
37   -
38   - if (expected_size != actual_size)
39   - printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
40   - actual_size >> 20, expected_size >> 20);
41   -
42   - return 0;
43   -}
44   -
45   -int board_eth_init(bd_t *bd)
46   -{
47   - return ftmac100_initialize(bd);
48   -}
49   -
50   -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
51   -{
52   - if (banknum == 0) { /* non-CFI boot flash */
53   - info->portwidth = FLASH_CFI_8BIT;
54   - info->chipwidth = FLASH_CFI_BY8;
55   - info->interface = FLASH_CFI_X8;
56   - return 1;
57   - } else
58   - return 0;
59   -}
board/faraday/a320evb/lowlevel_init.S
View file @ 29fc6f2
1   -/*
2   - * (C) Copyright 2009 Faraday Technology
3   - * Po-Yu Chuang <ratbert@faraday-tech.com>
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <config.h>
9   -#include <version.h>
10   -
11   -#include <asm/macro.h>
12   -#include <faraday/ftsdmc020.h>
13   -
14   -/*
15   - * parameters for the SDRAM controller
16   - */
17   -#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
18   -#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
19   -#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
20   -#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
21   -#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
22   -
23   -#define TP0_D CONFIG_SYS_FTSDMC020_TP0
24   -#define TP1_D CONFIG_SYS_FTSDMC020_TP1
25   -#define CR_D1 FTSDMC020_CR_IPREC
26   -#define CR_D2 FTSDMC020_CR_ISMR
27   -#define CR_D3 FTSDMC020_CR_IREF
28   -
29   -#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
30   - FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
31   -#define ACR_D FTSDMC020_ACR_TOC(0x18)
32   -
33   -/*
34   - * numeric 7 segment display
35   - */
36   -.macro led, num
37   - write32 CONFIG_DEBUG_LED, \num
38   -.endm
39   -
40   -/*
41   - * Waiting for SDRAM to set up
42   - */
43   -.macro wait_sdram
44   - ldr r0, =CONFIG_FTSDMC020_BASE
45   -1:
46   - ldr r1, [r0, #FTSDMC020_OFFSET_CR]
47   - cmp r1, #0
48   - bne 1b
49   -.endm
50   -
51   -.globl lowlevel_init
52   -lowlevel_init:
53   - mov r11, lr
54   -
55   - led 0x0
56   -
57   - bl init_sdmc
58   -
59   - led 0x1
60   -
61   - /* everything is fine now */
62   - mov lr, r11
63   - mov pc, lr
64   -
65   -/*
66   - * memory initialization
67   - */
68   -init_sdmc:
69   - led 0x10
70   -
71   - /* set SDRAM register */
72   -
73   - write32 TP0_A, TP0_D
74   - led 0x11
75   -
76   - write32 TP1_A, TP1_D
77   - led 0x12
78   -
79   - /* set to precharge */
80   - write32 CR_A, CR_D1
81   - led 0x13
82   -
83   - wait_sdram
84   - led 0x14
85   -
86   - /* set mode register */
87   - write32 CR_A, CR_D2
88   - led 0x15
89   -
90   - wait_sdram
91   - led 0x16
92   -
93   - /* set to refresh */
94   - write32 CR_A, CR_D3
95   - led 0x17
96   -
97   - wait_sdram
98   - led 0x18
99   -
100   - write32 B0_BSR_A, B0_BSR_D
101   - led 0x19
102   -
103   - write32 ACR_A, ACR_D
104   - led 0x1a
105   -
106   - mov pc, lr
configs/a320evb_defconfig
View file @ 29fc6f2
1   -CONFIG_ARM=y
2   -CONFIG_TARGET_A320EVB=y
doc/README.scrapyard
Diff comments   View file @ 29fc6f2
... ... @@ -12,6 +12,7 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +a320evb arm arm920t - - Po-Yu Chuang <ratbert@faraday-tech.com>
15 16 cm4008 arm arm920t - - Greg Ungerer <greg.ungerer@opengear.com>
16 17 cm41xx arm arm920t - -
17 18 dkb arm arm926ejs - - Lei Wen <leiwen@marvell.com>
include/configs/a320evb.h
View file @ 29fc6f2
1   -/*
2   - * (C) Copyright 2009 Faraday Technology
3   - * Po-Yu Chuang <ratbert@faraday-tech.com>
4   - *
5   - * Configuation settings for the Faraday A320 board.
6   - *
7   - * SPDX-License-Identifier: GPL-2.0+
8   - */
9   -
10   -#ifndef __CONFIG_H
11   -#define __CONFIG_H
12   -
13   -#include <asm/arch/a320.h>
14   -
15   -/*
16   - * mach-type definition
17   - */
18   -#define MACH_TYPE_FARADAY 758
19   -#define CONFIG_MACH_TYPE MACH_TYPE_FARADAY
20   -
21   -/*
22   - * Linux kernel tagged list
23   - */
24   -#define CONFIG_CMDLINE_TAG
25   -#define CONFIG_SETUP_MEMORY_TAGS
26   -
27   -/*
28   - * CPU and Board Configuration Options
29   - */
30   -#undef CONFIG_SKIP_LOWLEVEL_INIT
31   -
32   -/*
33   - * Power Management Unit
34   - */
35   -#define CONFIG_FTPMU010_POWER
36   -
37   -/*
38   - * Timer
39   - */
40   -
41   -/*
42   - * Real Time Clock
43   - */
44   -#define CONFIG_RTC_FTRTC010
45   -
46   -/*
47   - * Serial console configuration
48   - */
49   -
50   -/* FTUART is a high speed NS 16C550A compatible UART */
51   -#define CONFIG_BAUDRATE 38400
52   -#define CONFIG_CONS_INDEX 1
53   -#define CONFIG_SYS_NS16550
54   -#define CONFIG_SYS_NS16550_SERIAL
55   -#define CONFIG_SYS_NS16550_COM1 0x98200000
56   -#define CONFIG_SYS_NS16550_REG_SIZE -4
57   -#define CONFIG_SYS_NS16550_CLK 18432000
58   -
59   -/*
60   - * Ethernet
61   - */
62   -#define CONFIG_FTMAC100
63   -
64   -#define CONFIG_BOOTDELAY 3
65   -
66   -/*
67   - * Command line configuration.
68   - */
69   -#include <config_cmd_default.h>
70   -
71   -#define CONFIG_CMD_CACHE
72   -#define CONFIG_CMD_DATE
73   -#define CONFIG_CMD_PING
74   -
75   -/*
76   - * Miscellaneous configurable options
77   - */
78   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
79   -#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
80   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
81   -
82   -/* Print Buffer Size */
83   -#define CONFIG_SYS_PBSIZE \
84   - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
85   -
86   -/* max number of command args */
87   -#define CONFIG_SYS_MAXARGS 16
88   -
89   -/* Boot Argument Buffer Size */
90   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
91   -
92   -/*
93   - * Size of malloc() pool
94   - */
95   -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
96   -
97   -/*
98   - * SDRAM controller configuration
99   - */
100   -#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
101   - FTSDMC020_TP0_TRP(1) | \
102   - FTSDMC020_TP0_TRCD(1) | \
103   - FTSDMC020_TP0_TRF(3) | \
104   - FTSDMC020_TP0_TWR(1) | \
105   - FTSDMC020_TP0_TCL(2))
106   -
107   -#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
108   - FTSDMC020_TP1_INI_REFT(8) | \
109   - FTSDMC020_TP1_REF_INTV(0x180))
110   -
111   -#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
112   - FTSDMC020_BANK_DDW_X16 | \
113   - FTSDMC020_BANK_DSZ_256M | \
114   - FTSDMC020_BANK_MBW_32 | \
115   - FTSDMC020_BANK_SIZE_64M)
116   -
117   -/*
118   - * Physical Memory Map
119   - */
120   -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
121   -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
122   -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
123   -
124   -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
125   -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
126   - GENERATED_GBL_DATA_SIZE)
127   -
128   -/*
129   - * Load address and memory test area should agree with
130   - * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
131   - */
132   -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000)
133   -
134   -/* memtest works on 63 MB in DRAM */
135   -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
136   -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000)
137   -
138   -#define CONFIG_SYS_TEXT_BASE 0
139   -
140   -/*
141   - * Static memory controller configuration
142   - */
143   -
144   -#define CONFIG_FTSMC020
145   -#include <faraday/ftsmc020.h>
146   -
147   -#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
148   - FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
149   - FTSMC020_BANK_SIZE_1M | \
150   - FTSMC020_BANK_MBW_8)
151   -
152   -#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
153   - FTSMC020_TPR_AST(3) | \
154   - FTSMC020_TPR_CTW(3) | \
155   - FTSMC020_TPR_ATI(0xf) | \
156   - FTSMC020_TPR_AT2(3) | \
157   - FTSMC020_TPR_WTC(3) | \
158   - FTSMC020_TPR_AHT(3) | \
159   - FTSMC020_TPR_TRNA(0xf))
160   -
161   -#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
162   - FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
163   - FTSMC020_BANK_SIZE_32M | \
164   - FTSMC020_BANK_MBW_32)
165   -
166   -#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
167   - FTSMC020_TPR_CTW(3) | \
168   - FTSMC020_TPR_ATI(0xf) | \
169   - FTSMC020_TPR_AT2(3) | \
170   - FTSMC020_TPR_WTC(3) | \
171   - FTSMC020_TPR_AHT(3) | \
172   - FTSMC020_TPR_TRNA(0xf))
173   -
174   -#define CONFIG_SYS_FTSMC020_CONFIGS { \
175   - { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
176   - { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
177   -}
178   -
179   -/*
180   - * FLASH and environment organization
181   - */
182   -
183   -/* use CFI framework */
184   -#define CONFIG_SYS_FLASH_CFI
185   -#define CONFIG_FLASH_CFI_DRIVER
186   -
187   -/* support JEDEC */
188   -#define CONFIG_FLASH_CFI_LEGACY
189   -#define CONFIG_SYS_FLASH_LEGACY_512Kx8
190   -
191   -#define PHYS_FLASH_1 0x00000000
192   -#define PHYS_FLASH_2 0x00400000
193   -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
194   -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
195   -
196   -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
197   -
198   -/* max number of memory banks */
199   -#define CONFIG_SYS_MAX_FLASH_BANKS 2
200   -
201   -/* max number of sectors on one chip */
202   -#define CONFIG_SYS_MAX_FLASH_SECT 512
203   -
204   -#undef CONFIG_SYS_FLASH_EMPTY_INFO
205   -
206   -/* environments */
207   -#define CONFIG_ENV_IS_IN_FLASH
208   -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
209   -#define CONFIG_ENV_SIZE 0x20000
210   -
211   -#endif /* __CONFIG_H */