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Commit 2a5c6cdc48fb68615fecc6c2cbe8016d7980f590

Authored by Eric Lee 2016-03-22 17:49:04 +0800

1 parent 0cea25608d

Exists in v2015.07-smarct33-emmc and in 1 other branch

Optimize DDR3L parameter for Samsung and Micron DDR3L

Showing 3 changed files with 112 additions and 36 deletions Inline Diff

arch/arm/cpu/armv7/am33xx/board.c
arch/arm/include/asm/arch-am33xx/ddr_defs.h
board/embedian/smarct335x/board.c

arch/arm/cpu/armv7/am33xx/board.c

Diff comments View file @ 2a5c6cd

 /*
  * board.c
  *
  * Common board functions for AM33XX based boards
  *
  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <dm.h>
 #include <errno.h>
 #include <ns16550.h>
 #include <spl.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/omap.h>
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 #include <asm/emif.h>
 #include <asm/gpio.h>
 #include <i2c.h>
 #include <miiphy.h>
 #include <cpsw.h>
 #include <asm/errno.h>
 #include <linux/compiler.h>
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
 #include <linux/usb/musb.h>
 #include <asm/omap_musb.h>
 #include <asm/davinci_rtc.h>
 DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_DM_GPIO
 static const struct omap_gpio_platdata am33xx_gpio[] = {
 	{ 0, AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
 	{ 1, AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
 	{ 2, AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
 	{ 3, AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
 #ifdef CONFIG_AM43XX
 	{ 4, AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
 	{ 5, AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
 #endif
 };
 U_BOOT_DEVICES(am33xx_gpios) = {
 	{ "gpio_omap", &am33xx_gpio[0] },
 	{ "gpio_omap", &am33xx_gpio[1] },
 	{ "gpio_omap", &am33xx_gpio[2] },
 	{ "gpio_omap", &am33xx_gpio[3] },
 #ifdef CONFIG_AM43XX
 	{ "gpio_omap", &am33xx_gpio[4] },
 	{ "gpio_omap", &am33xx_gpio[5] },
 #endif
 };
 # ifndef CONFIG_OF_CONTROL
 /*
  * TODO(sjg@chromium.org): When we can move SPL serial to DM, we can remove
  * the CONFIGs. At the same time, we should move this to the board files.
  */
 static const struct ns16550_platdata am33xx_serial[] = {
 	{ CONFIG_SYS_NS16550_COM1, 2, CONFIG_SYS_NS16550_CLK },
 #  ifdef CONFIG_SYS_NS16550_COM2
 	{ CONFIG_SYS_NS16550_COM2, 2, CONFIG_SYS_NS16550_CLK },
 #   ifdef CONFIG_SYS_NS16550_COM3
 	{ CONFIG_SYS_NS16550_COM3, 2, CONFIG_SYS_NS16550_CLK },
 	{ CONFIG_SYS_NS16550_COM4, 2, CONFIG_SYS_NS16550_CLK },
 	{ CONFIG_SYS_NS16550_COM5, 2, CONFIG_SYS_NS16550_CLK },
 	{ CONFIG_SYS_NS16550_COM6, 2, CONFIG_SYS_NS16550_CLK },
 #   endif
 #  endif
 };
 U_BOOT_DEVICES(am33xx_uarts) = {
 	{ "serial_omap", &am33xx_serial[0] },
 #  ifdef CONFIG_SYS_NS16550_COM2
 	{ "serial_omap", &am33xx_serial[1] },
 #   ifdef CONFIG_SYS_NS16550_COM3
 	{ "serial_omap", &am33xx_serial[2] },
 	{ "serial_omap", &am33xx_serial[3] },
 	{ "serial_omap", &am33xx_serial[4] },
 	{ "serial_omap", &am33xx_serial[5] },
 #   endif
 #  endif
 };
 # endif
 #else
 static const struct gpio_bank gpio_bank_am33xx[] = {
 	{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
 	{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
 	{ (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
 	{ (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
 #ifdef CONFIG_AM43XX
 	{ (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
 	{ (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
 #endif
 };
 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
 #endif
 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
 int cpu_mmc_init(bd_t *bis)
 {
 	int ret;
 	ret = omap_mmc_init(0, 0, 0, -1, -1);
 	if (ret)
 		return ret;
 	return omap_mmc_init(1, 0, 0, -1, -1);
 }
 #endif
 /*
  * RTC only mode magic value, checked against during boot to see if we have
  * a valid config
  */
 #define RTC_MAGIC_VAL		0x8cd0
 /* Board type field bit shift for RTC only mode */
 #define RTC_BOARD_TYPE_SHIFT	16
 /* AM33XX has two MUSB controllers which can be host or gadget */
 #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
 	(defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 /* USB 2.0 PHY Control */
 #define CM_PHY_PWRDN			(1 << 0)
 #define CM_PHY_OTG_PWRDN		(1 << 1)
 #define OTGVDET_EN			(1 << 19)
 #define OTGSESSENDEN			(1 << 20)
 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
 {
 	if (on) {
 		clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
 				OTGVDET_EN | OTGSESSENDEN);
 	} else {
 		clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
 	}
 }
 static struct musb_hdrc_config musb_config = {
 	.multipoint     = 1,
 	.dyn_fifo       = 1,
 	.num_eps        = 16,
 	.ram_bits       = 12,
 };
 #ifdef CONFIG_AM335X_USB0
 static void am33xx_otg0_set_phy_power(u8 on)
 {
 	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
 }
 struct omap_musb_board_data otg0_board_data = {
 	.set_phy_power = am33xx_otg0_set_phy_power,
 };
 static struct musb_hdrc_platform_data otg0_plat = {
 	.mode           = CONFIG_AM335X_USB0_MODE,
 	.config         = &musb_config,
 	.power          = 50,
 	.platform_ops	= &musb_dsps_ops,
 	.board_data	= &otg0_board_data,
 };
 #endif
 #ifdef CONFIG_AM335X_USB1
 static void am33xx_otg1_set_phy_power(u8 on)
 {
 	am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
 }
 struct omap_musb_board_data otg1_board_data = {
 	.set_phy_power = am33xx_otg1_set_phy_power,
 };
 static struct musb_hdrc_platform_data otg1_plat = {
 	.mode           = CONFIG_AM335X_USB1_MODE,
 	.config         = &musb_config,
 	.power          = 50,
 	.platform_ops	= &musb_dsps_ops,
 	.board_data	= &otg1_board_data,
 };
 #endif
 #endif
 int arch_misc_init(void)
 {
 #ifdef CONFIG_AM335X_USB0
 	musb_register(&otg0_plat, &otg0_board_data,
 		(void *)USB0_OTG_BASE);
 #endif
 #ifdef CONFIG_AM335X_USB1
 	musb_register(&otg1_plat, &otg1_board_data,
 		(void *)USB1_OTG_BASE);
 #endif
 	return 0;
 }
 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
 	(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT))
 static void rtc32k_unlock(struct davinci_rtc *rtc)
 {
 	/*
 	 * Unlock the RTC's registers.  For more details please see the
 	 * RTC_SS section of the TRM.  In order to unlock we need to
 	 * write these specific values (keys) in this order.
 	 */
 	writel(RTC_KICK0R_WE, &rtc->kick0r);
 	writel(RTC_KICK1R_WE, &rtc->kick1r);
 }
 #endif
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT)
 /*
  * Write contents of the RTC_SCRATCH1 register based on board type
  * Two things are passed
  * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
  * control gets to kernel, kernel reads the scratchpad register and gets to
  * know that bootloader has rtc_only support.
  *
  * Second important thing is the board type  (16:31). This is needed in the
  * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
  * identify the board type and we go ahead and copy the board strings to
  * am43xx_board_name.
  */
 void update_rtc_magic(void)
 {
 	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
 	u32 magic = RTC_MAGIC_VAL;
 	magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
 	rtc32k_unlock(rtc);
 	/* write magic */
 	writel(magic, &rtc->scratch1);
 }
 #endif
 /*
  * In the case of non-SPL based booting we'll want to call these
  * functions a tiny bit later as it will require gd to be set and cleared
  * and that's not true in s_init in this case so we cannot do it there.
  */
 int board_early_init_f(void)
 {
-#ifdef CONFIG_NOR_BOOT
-        gd->baudrate = CONFIG_BAUDRATE;
-        serial_init();
-        gd->have_console = 1;
-#elif defined(CONFIG_SPL_BUILD)
-        preloader_console_init();
-#endif
 	prcm_init();
 	set_mux_conf_regs();
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT)
 	update_rtc_magic();
 #endif
 	return 0;
 }
 /*
  * This function is the place to do per-board things such as ramp up the
  * MPU clock frequency.
  */
 __weak void am33xx_spl_board_init(void)
 {
 	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }
 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 static void rtc32k_enable(void)
 {
 	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
 	rtc32k_unlock(rtc);
 	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
 	writel((1 << 3) | (1 << 6), &rtc->osc);
 }
 #endif
 static void uart_soft_reset(void)
 {
 	struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
 	u32 regval;
 	regval = readl(&uart_base->uartsyscfg);
 	regval |= UART_RESET;
 	writel(regval, &uart_base->uartsyscfg);
 	while ((readl(&uart_base->uartsyssts) &
 		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
 		;
 	/* Disable smart idle */
 	regval = readl(&uart_base->uartsyscfg);
 	regval |= UART_SMART_IDLE_EN;
 	writel(regval, &uart_base->uartsyscfg);
 }
 static void watchdog_disable(void)
 {
 	struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
 	writel(0xAAAA, &wdtimer->wdtwspr);
 	while (readl(&wdtimer->wdtwwps) != 0x0)
 		;
 	writel(0x5555, &wdtimer->wdtwspr);
 	while (readl(&wdtimer->wdtwwps) != 0x0)
 		;
 }
 #ifdef CONFIG_SPL_BUILD
 void board_init_f(ulong dummy)
 {
 	board_early_init_f();
 	sdram_init();
 }
 #endif
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT)
 /*
  * Check if we are executing rtc-only mode, and resume from it if needed
  */
 static void rtc_only(void)
 {
 	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
 	u32 scratch1;
 	void (*resume_func)(void);
 	scratch1 = readl(&rtc->scratch1);
 	/*
 	 * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
 	 * written to this register when we want to wake up from RTC only
 	 * mode. Contents of the RTC_SCRATCH1:
 	 * bits 0-15:  RTC_MAGIC_VAL
 	 * bits 16-31: board type (needed for sdram_init)
 	 */
 	if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
 		return;
 	rtc32k_unlock(rtc);
 	/* Clear RTC magic */
 	writel(0, &rtc->scratch1);
 	/*
 	 * Update board type based on value stored on RTC_SCRATCH1, this
 	 * is done so that we don't need to read the board type from eeprom
 	 * over i2c bus which is expensive
 	 */
 	rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
 	rtc_only_prcm_init();
 	sdram_init();
 	resume_func = (void *)readl(&rtc->scratch0);
 	if (resume_func)
 		resume_func();
 }
 #endif
 void s_init(void)
 {
 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT)
 	rtc_only();
 #endif
 	/*
 	 * The ROM will only have set up sufficient pinmux to allow for the
 	 * first 4KiB NOR to be read, we must finish doing what we know of
 	 * the NOR mux in this space in order to continue.
 	 */
 #ifdef CONFIG_NOR_BOOT
 	enable_norboot_pin_mux();
 #endif
 	watchdog_disable();
 	set_uart_mux_conf();
 	setup_clocks_for_console();
 	uart_soft_reset();
 #if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
 	/* TODO: This does not work, gd is not available yet */
 	gd->baudrate = CONFIG_BAUDRATE;
 	serial_init();
 	gd->have_console = 1;
 #endif
 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 	/* Enable RTC32K clock */
 	rtc32k_enable();
 #endif
 }
 #endif

arch/arm/include/asm/arch-am33xx/ddr_defs.h

Diff comments View file @ 2a5c6cd

 /*
  * ddr_defs.h
  *
  * ddr specific header
  *
  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _DDR_DEFS_H
 #define _DDR_DEFS_H
 #include <asm/arch/hardware.h>
 #include <asm/emif.h>
 /* AM335X EMIF Register values */
 #define VTP_CTRL_READY		(0x1 << 5)
 #define VTP_CTRL_ENABLE		(0x1 << 6)
 #define VTP_CTRL_START_EN	(0x1)
 #ifdef CONFIG_AM43XX
 #define DDR_CKE_CTRL_NORMAL	0x3
 #else
 #define DDR_CKE_CTRL_NORMAL	0x1
 #endif
 #define PHY_EN_DYN_PWRDN	(0x1 << 20)
 /* Micron MT47H128M16RT-25E */
 #define MT47H128M16RT25E_EMIF_READ_LATENCY	0x100005
 #define MT47H128M16RT25E_EMIF_TIM1		0x0666B3C9
 #define MT47H128M16RT25E_EMIF_TIM2		0x243631CA
 #define MT47H128M16RT25E_EMIF_TIM3		0x0000033F
 #define MT47H128M16RT25E_EMIF_SDCFG		0x41805332
 #define MT47H128M16RT25E_EMIF_SDREF		0x0000081a
 #define MT47H128M16RT25E_RATIO			0x80
 #define MT47H128M16RT25E_RD_DQS			0x12
 #define MT47H128M16RT25E_PHY_WR_DATA		0x40
 #define MT47H128M16RT25E_PHY_FIFO_WE		0x80
 #define MT47H128M16RT25E_IOCTRL_VALUE		0x18B
 /* Micron MT41J128M16JT-125 */
 #define MT41J128MJT125_EMIF_READ_LATENCY	0x100006
 #define MT41J128MJT125_EMIF_TIM1		0x0888A39B
 #define MT41J128MJT125_EMIF_TIM2		0x26337FDA
 #define MT41J128MJT125_EMIF_TIM3		0x501F830F
 #define MT41J128MJT125_EMIF_SDCFG		0x61C04AB2
 #define MT41J128MJT125_EMIF_SDREF		0x0000093B
 #define MT41J128MJT125_ZQ_CFG			0x50074BE4
 #define MT41J128MJT125_RATIO			0x40
 #define MT41J128MJT125_INVERT_CLKOUT		0x1
 #define MT41J128MJT125_RD_DQS			0x3B
 #define MT41J128MJT125_WR_DQS			0x85
 #define MT41J128MJT125_PHY_WR_DATA		0xC1
 #define MT41J128MJT125_PHY_FIFO_WE		0x100
 #define MT41J128MJT125_IOCTRL_VALUE		0x18B
 /* Micron MT41K128M16JT-187E */
 #define MT41K128MJT187E_EMIF_READ_LATENCY	0x06
 #define MT41K128MJT187E_EMIF_TIM1		0x0888B3DB
 #define MT41K128MJT187E_EMIF_TIM2		0x36337FDA
 #define MT41K128MJT187E_EMIF_TIM3		0x501F830F
 #define MT41K128MJT187E_EMIF_SDCFG		0x61C04AB2
 #define MT41K128MJT187E_EMIF_SDREF		0x0000093B
 #define MT41K128MJT187E_ZQ_CFG			0x50074BE4
 #define MT41K128MJT187E_RATIO			0x40
 #define MT41K128MJT187E_INVERT_CLKOUT		0x1
 #define MT41K128MJT187E_RD_DQS			0x3B
 #define MT41K128MJT187E_WR_DQS			0x85
 #define MT41K128MJT187E_PHY_WR_DATA		0xC1
 #define MT41K128MJT187E_PHY_FIFO_WE		0x100
 #define MT41K128MJT187E_IOCTRL_VALUE		0x18B
 /* Micron MT41J64M16JT-125 */
 #define MT41J64MJT125_EMIF_SDCFG		0x61C04A32
 /* Micron MT41J256M16JT-125 */
 #define MT41J256MJT125_EMIF_SDCFG		0x61C04B32
 /* Micron MT41J256M8HX-15E */
 #define MT41J256M8HX15E_EMIF_READ_LATENCY	0x100006
 #define MT41J256M8HX15E_EMIF_TIM1		0x0888A39B
 #define MT41J256M8HX15E_EMIF_TIM2		0x26337FDA
 #define MT41J256M8HX15E_EMIF_TIM3		0x501F830F
 #define MT41J256M8HX15E_EMIF_SDCFG		0x61C04B32
 #define MT41J256M8HX15E_EMIF_SDREF		0x0000093B
 #define MT41J256M8HX15E_ZQ_CFG			0x50074BE4
 #define MT41J256M8HX15E_RATIO			0x40
 #define MT41J256M8HX15E_INVERT_CLKOUT		0x1
 #define MT41J256M8HX15E_RD_DQS			0x3B
 #define MT41J256M8HX15E_WR_DQS			0x85
 #define MT41J256M8HX15E_PHY_WR_DATA		0xC1
 #define MT41J256M8HX15E_PHY_FIFO_WE		0x100
 #define MT41J256M8HX15E_IOCTRL_VALUE		0x18B
 /* Micron MT41K256M16HA-125E */
 #define MT41K256M16HA125E_EMIF_READ_LATENCY	0x100007
 #define MT41K256M16HA125E_EMIF_TIM1		0x0AAAD4DB
 #define MT41K256M16HA125E_EMIF_TIM2		0x266B7FDA
 #define MT41K256M16HA125E_EMIF_TIM3		0x501F867F
 #define MT41K256M16HA125E_EMIF_SDCFG		0x61C05332
 #define MT41K256M16HA125E_EMIF_SDREF		0xC30
 #define MT41K256M16HA125E_ZQ_CFG		0x50074BE4
 #define MT41K256M16HA125E_RATIO			0x80
 #define MT41K256M16HA125E_INVERT_CLKOUT		0x0
 #define MT41K256M16HA125E_RD_DQS		0x38
 #define MT41K256M16HA125E_WR_DQS		0x44
 #define MT41K256M16HA125E_PHY_WR_DATA		0x7D
 #define MT41K256M16HA125E_PHY_FIFO_WE		0x94
 #define MT41K256M16HA125E_IOCTRL_VALUE		0x18B
+/* Samsung K4B4G1646E-BYK0 */
+#define K4B4G1646EBYK0_EMIF_READ_LATENCY        0x100007
+#define K4B4G1646EBYK0_EMIF_TIM1                0x0AAAE51B
+#define K4B4G1646EBYK0_EMIF_TIM2                0x267B7FDA
+#define K4B4G1646EBYK0_EMIF_TIM3                0x501F877F
+#define K4B4G1646EBYK0_EMIF_SDCFG               0x61C05332
+#define K4B4G1646EBYK0_EMIF_SDREF               0xC30
+#define K4B4G1646EBYK0_ZQ_CFG                   0x50074BE4
+#define K4B4G1646EBYK0_RATIO                    0x80
+#define K4B4G1646EBYK0_INVERT_CLKOUT            0x0
+#define K4B4G1646EBYK0_RD_DQS                   0x3B
+#define K4B4G1646EBYK0_WR_DQS                   0x4A
+#define K4B4G1646EBYK0_PHY_WR_DATA              0x83
+#define K4B4G1646EBYK0_PHY_FIFO_WE              0xA4
+#define K4B4G1646EBYK0_IOCTRL_VALUE             0x18B
+/* Micron MT41K256M16HA-125ITE */
+#define MT41K256M16HA125ITE_EMIF_READ_LATENCY   0x100007
+#define MT41K256M16HA125ITE_EMIF_TIM1           0x0AAAE51B
+#define MT41K256M16HA125ITE_EMIF_TIM2           0x267B7FDA
+#define MT41K256M16HA125ITE_EMIF_TIM3           0x501F877F
+#define MT41K256M16HA125ITE_EMIF_SDCFG          0x61C05332
+#define MT41K256M16HA125ITE_EMIF_SDREF          0xC30
+#define MT41K256M16HA125ITE_ZQ_CFG              0x50074BE4
+#define MT41K256M16HA125ITE_RATIO               0x80
+#define MT41K256M16HA125ITE_INVERT_CLKOUT       0x0
+#define MT41K256M16HA125ITE_RD_DQS              0x3D
+#define MT41K256M16HA125ITE_WR_DQS              0x4B
+#define MT41K256M16HA125ITE_PHY_WR_DATA         0x7F
+#define MT41K256M16HA125ITE_PHY_FIFO_WE         0x9D
+#define MT41K256M16HA125ITE_IOCTRL_VALUE        0x18B
 /* Micron MT41J512M8RH-125 on EVM v1.5 */
 #define MT41J512M8RH125_EMIF_READ_LATENCY	0x100006
 #define MT41J512M8RH125_EMIF_TIM1		0x0888A39B
 #define MT41J512M8RH125_EMIF_TIM2		0x26517FDA
 #define MT41J512M8RH125_EMIF_TIM3		0x501F84EF
 #define MT41J512M8RH125_EMIF_SDCFG		0x61C04BB2
 #define MT41J512M8RH125_EMIF_SDREF		0x0000093B
 #define MT41J512M8RH125_ZQ_CFG			0x50074BE4
 #define MT41J512M8RH125_RATIO			0x80
 #define MT41J512M8RH125_INVERT_CLKOUT		0x0
 #define MT41J512M8RH125_RD_DQS			0x3B
 #define MT41J512M8RH125_WR_DQS			0x3C
 #define MT41J512M8RH125_PHY_FIFO_WE		0xA5
 #define MT41J512M8RH125_PHY_WR_DATA		0x74
 #define MT41J512M8RH125_IOCTRL_VALUE		0x18B
 /* Samsung K4B2G1646E-BIH9 */
 #define K4B2G1646EBIH9_EMIF_READ_LATENCY	0x100007
 #define K4B2G1646EBIH9_EMIF_TIM1		0x0AAAE51B
 #define K4B2G1646EBIH9_EMIF_TIM2		0x2A1D7FDA
 #define K4B2G1646EBIH9_EMIF_TIM3		0x501F83FF
 #define K4B2G1646EBIH9_EMIF_SDCFG		0x61C052B2
 #define K4B2G1646EBIH9_EMIF_SDREF		0x00000C30
 #define K4B2G1646EBIH9_ZQ_CFG			0x50074BE4
 #define K4B2G1646EBIH9_RATIO			0x80
 #define K4B2G1646EBIH9_INVERT_CLKOUT		0x0
 #define K4B2G1646EBIH9_RD_DQS			0x35
 #define K4B2G1646EBIH9_WR_DQS			0x3A
 #define K4B2G1646EBIH9_PHY_FIFO_WE		0x97
 #define K4B2G1646EBIH9_PHY_WR_DATA		0x76
 #define K4B2G1646EBIH9_IOCTRL_VALUE		0x18B
 #define  LPDDR2_ADDRCTRL_IOCTRL_VALUE   0x294
 #define  LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
 #define  LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
 #define  LPDDR2_DATA0_IOCTRL_VALUE   0x20000294
 #define  LPDDR2_DATA1_IOCTRL_VALUE   0x20000294
 #define  LPDDR2_DATA2_IOCTRL_VALUE   0x20000294
 #define  LPDDR2_DATA3_IOCTRL_VALUE   0x20000294
 #define  DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
 #define  DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
 #define  DDR3_ADDRCTRL_IOCTRL_VALUE   0x84
 #define  DDR3_DATA0_IOCTRL_VALUE   0x84
 #define  DDR3_DATA1_IOCTRL_VALUE   0x84
 #define  DDR3_DATA2_IOCTRL_VALUE   0x84
 #define  DDR3_DATA3_IOCTRL_VALUE   0x84
 /**
  * Configure DMM
  */
 void config_dmm(const struct dmm_lisa_map_regs *regs);
 /**
  * Configure SDRAM
  */
 void config_sdram(const struct emif_regs *regs, int nr);
 void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
 /**
  * Set SDRAM timings
  */
 void set_sdram_timings(const struct emif_regs *regs, int nr);
 /**
  * Configure DDR PHY
  */
 void config_ddr_phy(const struct emif_regs *regs, int nr);
 struct ddr_cmd_regs {
 	unsigned int resv0[7];
 	unsigned int cm0csratio;	/* offset 0x01C */
 	unsigned int resv1[3];
 	unsigned int cm0iclkout;	/* offset 0x02C */
 	unsigned int resv2[8];
 	unsigned int cm1csratio;	/* offset 0x050 */
 	unsigned int resv3[3];
 	unsigned int cm1iclkout;	/* offset 0x060 */
 	unsigned int resv4[8];
 	unsigned int cm2csratio;	/* offset 0x084 */
 	unsigned int resv5[3];
 	unsigned int cm2iclkout;	/* offset 0x094 */
 	unsigned int resv6[3];
 };
 struct ddr_data_regs {
 	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
 	unsigned int resv1[4];
 	unsigned int dt0wdsratio0;	/* offset 0x0DC */
 	unsigned int resv2[4];
 	unsigned int dt0wiratio0;	/* offset 0x0F0 */
 	unsigned int resv3;
 	unsigned int dt0wimode0;	/* offset 0x0F8 */
 	unsigned int dt0giratio0;	/* offset 0x0FC */
 	unsigned int resv4;
 	unsigned int dt0gimode0;	/* offset 0x104 */
 	unsigned int dt0fwsratio0;	/* offset 0x108 */
 	unsigned int resv5[4];
 	unsigned int dt0dqoffset;	/* offset 0x11C */
 	unsigned int dt0wrsratio0;	/* offset 0x120 */
 	unsigned int resv6[4];
 	unsigned int dt0rdelays0;	/* offset 0x134 */
 	unsigned int dt0dldiff0;	/* offset 0x138 */
 	unsigned int resv7[12];
 };
 /**
  * This structure represents the DDR registers on AM33XX devices.
  * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
  * correspond to DATA1 registers defined here.
  */
 struct ddr_regs {
 	unsigned int resv0[3];
 	unsigned int cm0config;		/* offset 0x00C */
 	unsigned int cm0configclk;	/* offset 0x010 */
 	unsigned int resv1[2];
 	unsigned int cm0csratio;	/* offset 0x01C */
 	unsigned int resv2[3];
 	unsigned int cm0iclkout;	/* offset 0x02C */
 	unsigned int resv3[4];
 	unsigned int cm1config;		/* offset 0x040 */
 	unsigned int cm1configclk;	/* offset 0x044 */
 	unsigned int resv4[2];
 	unsigned int cm1csratio;	/* offset 0x050 */
 	unsigned int resv5[3];
 	unsigned int cm1iclkout;	/* offset 0x060 */
 	unsigned int resv6[4];
 	unsigned int cm2config;		/* offset 0x074 */
 	unsigned int cm2configclk;	/* offset 0x078 */
 	unsigned int resv7[2];
 	unsigned int cm2csratio;	/* offset 0x084 */
 	unsigned int resv8[3];
 	unsigned int cm2iclkout;	/* offset 0x094 */
 	unsigned int resv9[12];
 	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
 	unsigned int resv10[4];
 	unsigned int dt0wdsratio0;	/* offset 0x0DC */
 	unsigned int resv11[4];
 	unsigned int dt0wiratio0;	/* offset 0x0F0 */
 	unsigned int resv12;
 	unsigned int dt0wimode0;	/* offset 0x0F8 */
 	unsigned int dt0giratio0;	/* offset 0x0FC */
 	unsigned int resv13;
 	unsigned int dt0gimode0;	/* offset 0x104 */
 	unsigned int dt0fwsratio0;	/* offset 0x108 */
 	unsigned int resv14[4];
 	unsigned int dt0dqoffset;	/* offset 0x11C */
 	unsigned int dt0wrsratio0;	/* offset 0x120 */
 	unsigned int resv15[4];
 	unsigned int dt0rdelays0;	/* offset 0x134 */
 	unsigned int dt0dldiff0;	/* offset 0x138 */
 };
 /**
  * Encapsulates DDR CMD control registers.
  */
 struct cmd_control {
 	unsigned long cmd0csratio;
 	unsigned long cmd0csforce;
 	unsigned long cmd0csdelay;
 	unsigned long cmd0iclkout;
 	unsigned long cmd1csratio;
 	unsigned long cmd1csforce;
 	unsigned long cmd1csdelay;
 	unsigned long cmd1iclkout;
 	unsigned long cmd2csratio;
 	unsigned long cmd2csforce;
 	unsigned long cmd2csdelay;
 	unsigned long cmd2iclkout;
 };
 /**
  * Encapsulates DDR DATA registers.
  */
 struct ddr_data {
 	unsigned long datardsratio0;
 	unsigned long datawdsratio0;
 	unsigned long datawiratio0;
 	unsigned long datagiratio0;
 	unsigned long datafwsratio0;
 	unsigned long datawrsratio0;
 };
 /**
  * Configure DDR CMD control registers
  */
 void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
 /**
  * Configure DDR DATA registers
  */
 void config_ddr_data(const struct ddr_data *data, int nr);
 /**
  * This structure represents the DDR io control on AM33XX devices.
  */
 struct ddr_cmdtctrl {
 	unsigned int cm0ioctl;
 	unsigned int cm1ioctl;
 	unsigned int cm2ioctl;
 	unsigned int resv2[12];
 	unsigned int dt0ioctl;
 	unsigned int dt1ioctl;
 	unsigned int dt2ioctrl;
 	unsigned int dt3ioctrl;
 	unsigned int resv3[4];
 	unsigned int emif_sdram_config_ext;
 };
 struct ctrl_ioregs {
 	unsigned int cm0ioctl;
 	unsigned int cm1ioctl;
 	unsigned int cm2ioctl;
 	unsigned int dt0ioctl;
 	unsigned int dt1ioctl;
 	unsigned int dt2ioctrl;
 	unsigned int dt3ioctrl;
 	unsigned int emif_sdram_config_ext;
 };
 /**
  * Configure DDR io control registers
  */
 void config_io_ctrl(const struct ctrl_ioregs *ioregs);
 struct ddr_ctrl {
 	unsigned int ddrioctrl;
 	unsigned int resv1[325];
 	unsigned int ddrckectrl;
 };
 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
 		const struct ddr_data *data, const struct cmd_control *ctrl,
 		const struct emif_regs *regs, int nr);
 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
 #endif  /* _DDR_DEFS_H */

board/embedian/smarct335x/board.c

Diff comments View file @ 2a5c6cd

 /*
  * board.c
  *
  * Board functions for TI AM335X based boards
  *
  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <errno.h>
 #include <spl.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/omap.h>
 #include <asm/arch/ddr_defs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/mmc_host_def.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
 #include <asm/io.h>
 #include <asm/emif.h>
 #include <asm/gpio.h>
 #include <i2c.h>
 #include <miiphy.h>
 #include <cpsw.h>
 #include <power/tps65217.h>
 #include <power/tps65910.h>
 #include <environment.h>
 #include <watchdog.h>
 #include "board.h"
 DECLARE_GLOBAL_DATA_PTR;
 /* GPIO that controls power to DDR on EVM-SK */
 #define GPIO_DDR_VTT_EN		7
 /* GPIO that controls power of LCD backlight */
 #define GPIO_LCD_BKLT_EN       	54
 /* GPIO that controls LCD backlight PWM */
 #define GPIO_LCD_PWM_EN        	7
 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 /*
  * Read header information from EEPROM into global structure.
  */
 static int read_eeprom(struct am335x_baseboard_id *header)
 {
 	/* Check if baseboard eeprom is available */
 	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
 		puts("Could not probe the EEPROM; something fundamentally "
 			"wrong on the I2C bus.\n");
 		return -ENODEV;
 	}
 	/* read the eeprom using i2c */
 	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
 		     sizeof(struct am335x_baseboard_id))) {
 		puts("Could not read the EEPROM; something fundamentally"
 			" wrong on the I2C bus.\n");
 		return -EIO;
 	}
 	if (header->magic != 0xEE3355AA) {
 		/*
 		 * read the eeprom using i2c again,
 		 * but use only a 1 byte address
 		 */
 		if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
 			     sizeof(struct am335x_baseboard_id))) {
 			puts("Could not read the EEPROM; something "
 				"fundamentally wrong on the I2C bus.\n");
 			return -EIO;
 		}
 		if (header->magic != 0xEE3355AA) {
 			printf("Incorrect magic number (0x%x) in EEPROM\n",
 					header->magic);
 			return -EINVAL;
 		}
 	}
 	return 0;
 }
 /*#ifndef CONFIG_SKIP_LOWLEVEL_INIT*/
 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
 static const struct ddr_data ddr2_data = {
 	.datardsratio0 = MT47H128M16RT25E_RD_DQS,
 	.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
 	.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
 };
 static const struct cmd_control ddr2_cmd_ctrl_data = {
 	.cmd0csratio = MT47H128M16RT25E_RATIO,
 	.cmd1csratio = MT47H128M16RT25E_RATIO,
 	.cmd2csratio = MT47H128M16RT25E_RATIO,
 };
 static const struct emif_regs ddr2_emif_reg_data = {
 	.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
 	.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
 	.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
 	.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
 	.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
 	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 };
 static const struct ddr_data ddr3_data = {
 	.datardsratio0 = MT41J128MJT125_RD_DQS,
 	.datawdsratio0 = MT41J128MJT125_WR_DQS,
 	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
 };
 static const struct ddr_data ddr3_beagleblack_data = {
 	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
 	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
 };
 static const struct ddr_data ddr3_smarct335x_data = {
-        .datardsratio0 = MT41K256M16HA125E_RD_DQS,
+        .datardsratio0 = K4B4G1646EBYK0_RD_DQS,
-        .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+        .datawdsratio0 = K4B4G1646EBYK0_WR_DQS,
-        .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+        .datafwsratio0 = K4B4G1646EBYK0_PHY_FIFO_WE,
-        .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+        .datawrsratio0 = K4B4G1646EBYK0_PHY_WR_DATA,
 };
+static const struct ddr_data ddr3_smarct335x80_data = {
+        .datardsratio0 = MT41K256M16HA125ITE_RD_DQS,
+        .datawdsratio0 = MT41K256M16HA125ITE_WR_DQS,
+        .datafwsratio0 = MT41K256M16HA125ITE_PHY_FIFO_WE,
+        .datawrsratio0 = MT41K256M16HA125ITE_PHY_WR_DATA,
+};
 static const struct ddr_data ddr3_evm_data = {
 	.datardsratio0 = MT41J512M8RH125_RD_DQS,
 	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
 	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
 };
 static const struct cmd_control ddr3_cmd_ctrl_data = {
 	.cmd0csratio = MT41J128MJT125_RATIO,
 	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 	.cmd1csratio = MT41J128MJT125_RATIO,
 	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 	.cmd2csratio = MT41J128MJT125_RATIO,
 	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 };
 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 	.cmd0csratio = MT41K256M16HA125E_RATIO,
 	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 	.cmd1csratio = MT41K256M16HA125E_RATIO,
 	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 	.cmd2csratio = MT41K256M16HA125E_RATIO,
 	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 };
 static const struct cmd_control ddr3_smarct335x_cmd_ctrl_data = {
-        .cmd0csratio = MT41K256M16HA125E_RATIO,
+        .cmd0csratio = K4B4G1646EBYK0_RATIO,
-        .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+        .cmd0iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
-        .cmd1csratio = MT41K256M16HA125E_RATIO,
+        .cmd1csratio = K4B4G1646EBYK0_RATIO,
-        .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+        .cmd1iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
-        .cmd2csratio = MT41K256M16HA125E_RATIO,
+        .cmd2csratio = K4B4G1646EBYK0_RATIO,
-        .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+        .cmd2iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
 };
+static const struct cmd_control ddr3_smarct335x80_cmd_ctrl_data = {
+        .cmd0csratio = MT41K256M16HA125ITE_RATIO,
+        .cmd0iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
+        .cmd1csratio = MT41K256M16HA125ITE_RATIO,
+        .cmd1iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
+        .cmd2csratio = MT41K256M16HA125ITE_RATIO,
+        .cmd2iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
+};
 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 	.cmd0csratio = MT41J512M8RH125_RATIO,
 	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 	.cmd1csratio = MT41J512M8RH125_RATIO,
 	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 	.cmd2csratio = MT41J512M8RH125_RATIO,
 	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 };
 static struct emif_regs ddr3_emif_reg_data = {
 	.sdram_config = MT41J128MJT125_EMIF_SDCFG,
 	.ref_ctrl = MT41J128MJT125_EMIF_SDREF,
 	.sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
 	.sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
 	.sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
 	.zq_config = MT41J128MJT125_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
 				PHY_EN_DYN_PWRDN,
 };
 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
 	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
 	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
 	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
 	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
 	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
 	.zq_config = MT41K256M16HA125E_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
 };
 static struct emif_regs ddr3_smarct335x_emif_reg_data = {
-        .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+        .sdram_config = K4B4G1646EBYK0_EMIF_SDCFG,
-        .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+        .ref_ctrl = K4B4G1646EBYK0_EMIF_SDREF,
-        .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+        .sdram_tim1 = K4B4G1646EBYK0_EMIF_TIM1,
-        .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+        .sdram_tim2 = K4B4G1646EBYK0_EMIF_TIM2,
-        .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+        .sdram_tim3 = K4B4G1646EBYK0_EMIF_TIM3,
-        .zq_config = MT41K256M16HA125E_ZQ_CFG,
+        .zq_config = K4B4G1646EBYK0_ZQ_CFG,
-        .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+        .emif_ddr_phy_ctlr_1 = K4B4G1646EBYK0_EMIF_READ_LATENCY,
 };
+static struct emif_regs ddr3_smarct335x80_emif_reg_data = {
+        .sdram_config = MT41K256M16HA125ITE_EMIF_SDCFG,
+        .ref_ctrl = MT41K256M16HA125ITE_EMIF_SDREF,
+        .sdram_tim1 = MT41K256M16HA125ITE_EMIF_TIM1,
+        .sdram_tim2 = MT41K256M16HA125ITE_EMIF_TIM2,
+        .sdram_tim3 = MT41K256M16HA125ITE_EMIF_TIM3,
+        .zq_config = MT41K256M16HA125ITE_ZQ_CFG,
+        .emif_ddr_phy_ctlr_1 = MT41K256M16HA125ITE_EMIF_READ_LATENCY,
+};
 static struct emif_regs ddr3_evm_emif_reg_data = {
 	.sdram_config = MT41J512M8RH125_EMIF_SDCFG,
 	.ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
 	.sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
 	.sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
 	.sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
 	.zq_config = MT41J512M8RH125_ZQ_CFG,
 	.emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
 				PHY_EN_DYN_PWRDN,
 };
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {
 	/* break into full u-boot on 'c' */
 	if (serial_tstc() && serial_getc() == 'c')
 		return 1;
 #ifdef CONFIG_SPL_ENV_SUPPORT
 	env_init();
 	env_relocate_spec();
 	if (getenv_yesno("boot_os") != 1)
 		return 1;
 #endif
 	return 0;
 }
 #endif
 #define OSC	(V_OSCK/1000000)
 const struct dpll_params dpll_ddr = {
 		266, OSC-1, 1, -1, -1, -1, -1};
 const struct dpll_params dpll_ddr_evm_sk = {
 		303, OSC-1, 1, -1, -1, -1, -1};
 const struct dpll_params dpll_ddr_bone_black = {
 		400, OSC-1, 1, -1, -1, -1, -1};
 const struct dpll_params dpll_ddr_smarc_t335x = {
                 400, OSC-1, 1, -1, -1, -1, -1};
 void am33xx_spl_board_init(void)
 {
 	struct am335x_baseboard_id header;
 	int mpu_vdd;
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 	/* Get the frequency */
 	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
 	if (board_is_bone(&header) || board_is_bone_lt(&header) || board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header)) {
 		/* BeagleBone PMIC Code */
 		int usb_cur_lim;
 		/*
 		 * Only perform PMIC configurations if board rev > A1
 		 * on Beaglebone White
 		 */
 		if (board_is_bone(&header) && !strncmp(header.version,
 						       "00A1", 4))
 			return;
 		if (i2c_probe(TPS65217_CHIP_PM))
 			return;
 		/*
 		 * On Beaglebone White we need to ensure we have AC power
 		 * before increasing the frequency.
 		 */
 		if (board_is_bone(&header)) {
 			uchar pmic_status_reg;
 			if (tps65217_reg_read(TPS65217_STATUS,
 					      &pmic_status_reg))
 				return;
 			if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
 				puts("No AC power, disabling frequency switch\n");
 				return;
 			}
 		}
                 /*
                  * Override what we have detected since we know if we have
                  * a Beaglebone Black it supports 1GHz.
                  */
                 if ((board_is_bone_lt(&header) || board_is_smarc_t335x_1g(&header)))
                         dpll_mpu_opp100.m = MPUPLL_M_1000;
                 /*
                  * Increase USB current limit to 1300mA or 1800mA and set
                  * the MPU voltage controller as needed.
                  */
 		if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
 			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
 			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
 		} else {
 			usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
 			mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
 		}
 		if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 				       TPS65217_POWER_PATH,
 				       usb_cur_lim,
 				       TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 			puts("tps65217_reg_write failure\n");
 		/* Set DCDC3 (CORE) voltage to 1.125V */
 		if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 					    TPS65217_DCDC_VOLT_SEL_1125MV)) {
 			puts("tps65217_voltage_update failure\n");
 			return;
 		}
 		/* Set CORE Frequencies to OPP100 */
 		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 		/* Set DCDC2 (MPU) voltage */
 		if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 			puts("tps65217_voltage_update failure\n");
 			return;
 		}
 		/*
 		 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
 		 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
 		 */
 		if (board_is_bone(&header)) {
 			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 					       TPS65217_DEFLS1,
 					       TPS65217_LDO_VOLTAGE_OUT_3_3,
 					       TPS65217_LDO_MASK))
 				puts("tps65217_reg_write failure\n");
 		} else {
 			if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 					       TPS65217_DEFLS1,
 					       TPS65217_LDO_VOLTAGE_OUT_1_8,
 					       TPS65217_LDO_MASK))
 				puts("tps65217_reg_write failure\n");
 		}
 		if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 				       TPS65217_DEFLS2,
 				       TPS65217_LDO_VOLTAGE_OUT_3_3,
 				       TPS65217_LDO_MASK))
 			puts("tps65217_reg_write failure\n");
 	} else {
 		int sil_rev;
 		/*
 		 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
 		 * MPU frequencies we support we use a CORE voltage of
 		 * 1.1375V.  For MPU voltage we need to switch based on
 		 * the frequency we are running at.
 		 */
 		if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
 			return;
 		/*
 		 * Depending on MPU clock and PG we will need a different
 		 * VDD to drive at that speed.
 		 */
 		sil_rev = readl(&cdev->deviceid) >> 28;
 		mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
 						      dpll_mpu_opp100.m);
 		/* Tell the TPS65910 to use i2c */
 		tps65910_set_i2c_control();
 		/* First update MPU voltage. */
 		if (tps65910_voltage_update(MPU, mpu_vdd))
 			return;
 		/* Second, update the CORE voltage. */
 		if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
 			return;
 		/* Set CORE Frequencies to OPP100 */
 		do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 	}
 	/* Set MPU Frequency to what we detected now that voltages are set */
 	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }
 const struct dpll_params *get_dpll_ddr_params(void)
 {
 	struct am335x_baseboard_id header;
 	enable_i2c0_pin_mux();
 	i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 	if (board_is_evm_sk(&header))
 		return &dpll_ddr_evm_sk;
 	else if (board_is_bone_lt(&header))
 		return &dpll_ddr_bone_black;
         else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header))
                 return &dpll_ddr_smarc_t335x;
 	else if (board_is_evm_15_or_later(&header))
 		return &dpll_ddr_evm_sk;
 	else
 		return &dpll_ddr;
 }
 void set_uart_mux_conf(void)
 {
 #if CONFIG_CONS_INDEX == 1
 	enable_uart0_pin_mux();
 #elif CONFIG_CONS_INDEX == 2
 	enable_uart1_pin_mux();
 #elif CONFIG_CONS_INDEX == 3
 	enable_uart2_pin_mux();
 #elif CONFIG_CONS_INDEX == 4
 	enable_uart3_pin_mux();
 #elif CONFIG_CONS_INDEX == 5
 	enable_uart4_pin_mux();
 #elif CONFIG_CONS_INDEX == 6
 	enable_uart5_pin_mux();
 #endif
 }
 void set_mux_conf_regs(void)
 {
 	__maybe_unused struct am335x_baseboard_id header;
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 	enable_board_pin_mux(&header);
 }
 const struct ctrl_ioregs ioregs_evmsk = {
 	.cm0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.cm1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.cm2ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.dt0ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 	.dt1ioctl		= MT41J128MJT125_IOCTRL_VALUE,
 };
 const struct ctrl_ioregs ioregs_bonelt = {
 	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
 };
 const struct ctrl_ioregs ioregs_smarct335x = {
-        .cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+        .cm0ioctl               = K4B4G1646EBYK0_IOCTRL_VALUE,
-        .cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+        .cm1ioctl               = K4B4G1646EBYK0_IOCTRL_VALUE,
-        .cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+        .cm2ioctl               = K4B4G1646EBYK0_IOCTRL_VALUE,
-        .dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+        .dt0ioctl               = K4B4G1646EBYK0_IOCTRL_VALUE,
-        .dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+        .dt1ioctl               = K4B4G1646EBYK0_IOCTRL_VALUE,
 };
+const struct ctrl_ioregs ioregs_smarct335x80 = {
+        .cm0ioctl               = MT41K256M16HA125ITE_IOCTRL_VALUE,
+        .cm1ioctl               = MT41K256M16HA125ITE_IOCTRL_VALUE,
+        .cm2ioctl               = MT41K256M16HA125ITE_IOCTRL_VALUE,
+        .dt0ioctl               = MT41K256M16HA125ITE_IOCTRL_VALUE,
+        .dt1ioctl               = MT41K256M16HA125ITE_IOCTRL_VALUE,
+};
 const struct ctrl_ioregs ioregs_evm15 = {
 	.cm0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.cm1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.cm2ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.dt0ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 	.dt1ioctl		= MT41J512M8RH125_IOCTRL_VALUE,
 };
 const struct ctrl_ioregs ioregs = {
 	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
 };
 void sdram_init(void)
 {
 	__maybe_unused struct am335x_baseboard_id header;
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 	if (board_is_evm_sk(&header)) {
 		/*
 		 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
 		 * This is safe enough to do on older revs.
 		 */
 		gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
 		gpio_direction_output(GPIO_DDR_VTT_EN, 1);
 	}
 	if (board_is_evm_sk(&header))
 		config_ddr(303, &ioregs_evmsk, &ddr3_data,
 			   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
 	else if (board_is_bone_lt(&header))
 		config_ddr(400, &ioregs_bonelt,
 			   &ddr3_beagleblack_data,
 			   &ddr3_beagleblack_cmd_ctrl_data,
 			   &ddr3_beagleblack_emif_reg_data, 0);
-        else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header)) {
+        else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) {
                 /*
                  * SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM and gpio1_22 as LCD backlight enable.
                  * This is safe enough to do on older revs.
                  */
-               	gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en");
+                gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en");
                 gpio_direction_output(GPIO_LCD_BKLT_EN, 1);
                 gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en");
                 gpio_direction_output(GPIO_LCD_PWM_EN, 1);
                 config_ddr(400, &ioregs_smarct335x,
-                           &ddr3_smarct335x_data,
+			   &ddr3_smarct335x_data,
                            &ddr3_smarct335x_cmd_ctrl_data,
-                           &ddr3_smarct335x_emif_reg_data, 0);
+			   &ddr3_smarct335x_emif_reg_data, 0);
-                puts("Set DDR3 to 800MHz.\n");
+		udelay(1600);
+        }
+        else if (board_is_smarc_t335x_80(&header)) {
+                /*
+                 * SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM and gpio1_22 as LCD backlight enable.
+                 * This is safe enough to do on older revs.
+                 */
+                gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en");
+                gpio_direction_output(GPIO_LCD_BKLT_EN, 1);
+                gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en");
+                gpio_direction_output(GPIO_LCD_PWM_EN, 1);
+                config_ddr(400, &ioregs_smarct335x80,
+                           &ddr3_smarct335x80_data,
+                           &ddr3_smarct335x80_cmd_ctrl_data,
+                           &ddr3_smarct335x80_emif_reg_data, 0);
+		udelay(1600);
         }
 	else if (board_is_evm_15_or_later(&header))
 		config_ddr(400, &ioregs_evm15, &ddr3_evm_data,
 			   &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
 	else
 		config_ddr(266, &ioregs, &ddr2_data,
 			   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
 }
 #endif
 /*
  * Basic board specific setup.  Pinmux has been handled already.
  */
 int board_init(void)
 {
 	u32 sys_reboot;
 	sys_reboot = readl(PRM_RSTST);
 	if (sys_reboot & (1 << 9))
 		puts("Reset Source: IcePick reset has occurred.\n");
 	if (sys_reboot & (1 << 5))
 		puts("Reset Source: Global external warm reset has occurred.\n");
 	if (sys_reboot & (1 << 4))
 		puts("Reset Source: watchdog reset has occurred.\n");
 	if (sys_reboot & (1 << 1))
 		puts("Reset Source: Global warm SW reset has occurred.\n");
 	if (sys_reboot & (1 << 0))
 		puts("Reset Source: Power-on reset has occurred.\n");
 #if defined(CONFIG_HW_WATCHDOG)
 	hw_watchdog_init();
 #endif
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
 	gpmc_init();
 #endif
 	return 0;
 }
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 	char safe_string[HDR_NAME_LEN + 1];
 	struct am335x_baseboard_id header;
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 	/* Now set variables based on the header. */
 	strncpy(safe_string, (char *)header.name, sizeof(header.name));
 	safe_string[sizeof(header.name)] = 0;
 	setenv("board_name", safe_string);
 	/* BeagleBone Green has 0x1a at [0], they are free to increment 'a' */
 	if ( (header.version[0] != 0x30) && (header.version[0] & (1 << 4)) ) {
 		setenv("board_rev", "BBG1");
 	} else {
 		strncpy(safe_string, (char *)header.version, sizeof(header.version));
 		safe_string[sizeof(header.version)] = 0;
 		setenv("board_rev", safe_string);
 	}
 #endif
 	return 0;
 }
 #endif
 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 static void cpsw_control(int enabled)
 {
 	/* VTP can be added here */
 	return;
 }
 static struct cpsw_slave_data cpsw_slaves[] = {
 	{
 		.slave_reg_ofs	= 0x208,
 		.sliver_reg_ofs	= 0xd80,
 		.phy_addr	= 0,
 	},
 	{
 		.slave_reg_ofs	= 0x308,
 		.sliver_reg_ofs	= 0xdc0,
 		.phy_addr	= 1,
 	},
 };
 static struct cpsw_platform_data cpsw_data = {
 	.mdio_base		= CPSW_MDIO_BASE,
 	.cpsw_base		= CPSW_BASE,
 	.mdio_div		= 0xff,
 	.channels		= 8,
 	.cpdma_reg_ofs		= 0x800,
 	.slaves			= 1,
 	.slave_data		= cpsw_slaves,
 	.ale_reg_ofs		= 0xd00,
 	.ale_entries		= 1024,
 	.host_port_reg_ofs	= 0x108,
 	.hw_stats_reg_ofs	= 0x900,
 	.bd_ram_ofs		= 0x2000,
 	.mac_control		= (1 << 5),
 	.control		= cpsw_control,
 	.host_port_num		= 0,
 	.version		= CPSW_CTRL_VERSION_2,
 };
 #endif
 /*
  * This function will:
  * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
  * in the environment
  * Perform fixups to the PHY present on certain boards.  We only need this
  * function in:
  * - SPL with either CPSW or USB ethernet support
  * - Full U-Boot, with either CPSW or USB ethernet
  * Build in only these cases to avoid warnings about unused variables
  * when we build an SPL that has neither option but full U-Boot will.
  */
 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
 		&& defined(CONFIG_SPL_BUILD)) || \
 	((defined(CONFIG_DRIVER_TI_CPSW) || \
 	  defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
 	 !defined(CONFIG_SPL_BUILD))
 int board_eth_init(bd_t *bis)
 {
 	int rv, n = 0;
 	uint8_t mac_addr[6];
 	uint32_t mac_hi, mac_lo;
 	__maybe_unused struct am335x_baseboard_id header;
 	/* try reading mac address from efuse */
 	mac_lo = readl(&cdev->macid0l);
 	mac_hi = readl(&cdev->macid0h);
 	mac_addr[0] = mac_hi & 0xFF;
 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 	mac_addr[4] = mac_lo & 0xFF;
 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
 	if (!getenv("ethaddr")) {
 		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
 		if (is_valid_ethaddr(mac_addr))
 			eth_setenv_enetaddr("ethaddr", mac_addr);
 	}
 #ifdef CONFIG_DRIVER_TI_CPSW
 	mac_lo = readl(&cdev->macid1l);
 	mac_hi = readl(&cdev->macid1h);
 	mac_addr[0] = mac_hi & 0xFF;
 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
 	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
 	mac_addr[4] = mac_lo & 0xFF;
 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
 	if (!getenv("eth1addr")) {
 		if (is_valid_ethaddr(mac_addr))
 			eth_setenv_enetaddr("eth1addr", mac_addr);
 	}
 	if (read_eeprom(&header) < 0)
 		puts("Could not get board ID.\n");
 	if (board_is_bone(&header) || board_is_bone_lt(&header) ||
 	    board_is_idk(&header)) {
 		writel(MII_MODE_ENABLE, &cdev->miisel);
 		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 				PHY_INTERFACE_MODE_MII;
         } else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header)) {
                writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
                cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
                                PHY_INTERFACE_MODE_RMII;
 	} else {
 		writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
 		cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
 				PHY_INTERFACE_MODE_RGMII;
 	}
 	rv = cpsw_register(&cpsw_data);
 	if (rv < 0)
 		printf("Error %d registering CPSW switch\n", rv);
 	else
 		n += rv;
 #endif
 	/*
 	 *
 	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
 	 * operating points.  So we must set the TX clock delay feature
 	 * in the AR8051 PHY.  Since we only support a single ethernet
 	 * device in U-Boot, we only do this for the first instance.
 	 */
 #define AR8051_PHY_DEBUG_ADDR_REG	0x1d
 #define AR8051_PHY_DEBUG_DATA_REG	0x1e
 #define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
 #define AR8051_RGMII_TX_CLK_DLY		0x100
 	if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
 		const char *devname;
 		devname = miiphy_get_current_dev();
 		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 				AR8051_DEBUG_RGMII_CLK_DLY_REG);
 		miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 				AR8051_RGMII_TX_CLK_DLY);
 	}
 #endif
 #if defined(CONFIG_USB_ETHER) && \
 	(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
 	if (is_valid_ethaddr(mac_addr))
 		eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
 	rv = usb_eth_initialize(bis);
 	if (rv < 0)
 		printf("Error %d registering USB_ETHER\n", rv);
 	else
 		n += rv;
 #endif
 	return n;
 }
 #endif