Commit 2a5c6cdc48fb68615fecc6c2cbe8016d7980f590
1 parent
0cea25608d
Exists in
v2015.07-smarct33-emmc
and in
1 other branch
Optimize DDR3L parameter for Samsung and Micron DDR3L
Showing 3 changed files with 112 additions and 36 deletions Side-by-side Diff
arch/arm/cpu/armv7/am33xx/board.c
| ... | ... | @@ -261,13 +261,6 @@ |
| 261 | 261 | */ |
| 262 | 262 | int board_early_init_f(void) |
| 263 | 263 | { |
| 264 | -#ifdef CONFIG_NOR_BOOT | |
| 265 | - gd->baudrate = CONFIG_BAUDRATE; | |
| 266 | - serial_init(); | |
| 267 | - gd->have_console = 1; | |
| 268 | -#elif defined(CONFIG_SPL_BUILD) | |
| 269 | - preloader_console_init(); | |
| 270 | -#endif | |
| 271 | 264 | prcm_init(); |
| 272 | 265 | set_mux_conf_regs(); |
| 273 | 266 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_ONLY_SUPPORT) |
arch/arm/include/asm/arch-am33xx/ddr_defs.h
| ... | ... | @@ -108,6 +108,38 @@ |
| 108 | 108 | #define MT41K256M16HA125E_PHY_FIFO_WE 0x94 |
| 109 | 109 | #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B |
| 110 | 110 | |
| 111 | +/* Samsung K4B4G1646E-BYK0 */ | |
| 112 | +#define K4B4G1646EBYK0_EMIF_READ_LATENCY 0x100007 | |
| 113 | +#define K4B4G1646EBYK0_EMIF_TIM1 0x0AAAE51B | |
| 114 | +#define K4B4G1646EBYK0_EMIF_TIM2 0x267B7FDA | |
| 115 | +#define K4B4G1646EBYK0_EMIF_TIM3 0x501F877F | |
| 116 | +#define K4B4G1646EBYK0_EMIF_SDCFG 0x61C05332 | |
| 117 | +#define K4B4G1646EBYK0_EMIF_SDREF 0xC30 | |
| 118 | +#define K4B4G1646EBYK0_ZQ_CFG 0x50074BE4 | |
| 119 | +#define K4B4G1646EBYK0_RATIO 0x80 | |
| 120 | +#define K4B4G1646EBYK0_INVERT_CLKOUT 0x0 | |
| 121 | +#define K4B4G1646EBYK0_RD_DQS 0x3B | |
| 122 | +#define K4B4G1646EBYK0_WR_DQS 0x4A | |
| 123 | +#define K4B4G1646EBYK0_PHY_WR_DATA 0x83 | |
| 124 | +#define K4B4G1646EBYK0_PHY_FIFO_WE 0xA4 | |
| 125 | +#define K4B4G1646EBYK0_IOCTRL_VALUE 0x18B | |
| 126 | + | |
| 127 | +/* Micron MT41K256M16HA-125ITE */ | |
| 128 | +#define MT41K256M16HA125ITE_EMIF_READ_LATENCY 0x100007 | |
| 129 | +#define MT41K256M16HA125ITE_EMIF_TIM1 0x0AAAE51B | |
| 130 | +#define MT41K256M16HA125ITE_EMIF_TIM2 0x267B7FDA | |
| 131 | +#define MT41K256M16HA125ITE_EMIF_TIM3 0x501F877F | |
| 132 | +#define MT41K256M16HA125ITE_EMIF_SDCFG 0x61C05332 | |
| 133 | +#define MT41K256M16HA125ITE_EMIF_SDREF 0xC30 | |
| 134 | +#define MT41K256M16HA125ITE_ZQ_CFG 0x50074BE4 | |
| 135 | +#define MT41K256M16HA125ITE_RATIO 0x80 | |
| 136 | +#define MT41K256M16HA125ITE_INVERT_CLKOUT 0x0 | |
| 137 | +#define MT41K256M16HA125ITE_RD_DQS 0x3D | |
| 138 | +#define MT41K256M16HA125ITE_WR_DQS 0x4B | |
| 139 | +#define MT41K256M16HA125ITE_PHY_WR_DATA 0x7F | |
| 140 | +#define MT41K256M16HA125ITE_PHY_FIFO_WE 0x9D | |
| 141 | +#define MT41K256M16HA125ITE_IOCTRL_VALUE 0x18B | |
| 142 | + | |
| 111 | 143 | /* Micron MT41J512M8RH-125 on EVM v1.5 */ |
| 112 | 144 | #define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006 |
| 113 | 145 | #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B |
board/embedian/smarct335x/board.c
| ... | ... | @@ -127,12 +127,19 @@ |
| 127 | 127 | }; |
| 128 | 128 | |
| 129 | 129 | static const struct ddr_data ddr3_smarct335x_data = { |
| 130 | - .datardsratio0 = MT41K256M16HA125E_RD_DQS, | |
| 131 | - .datawdsratio0 = MT41K256M16HA125E_WR_DQS, | |
| 132 | - .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, | |
| 133 | - .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, | |
| 130 | + .datardsratio0 = K4B4G1646EBYK0_RD_DQS, | |
| 131 | + .datawdsratio0 = K4B4G1646EBYK0_WR_DQS, | |
| 132 | + .datafwsratio0 = K4B4G1646EBYK0_PHY_FIFO_WE, | |
| 133 | + .datawrsratio0 = K4B4G1646EBYK0_PHY_WR_DATA, | |
| 134 | 134 | }; |
| 135 | 135 | |
| 136 | +static const struct ddr_data ddr3_smarct335x80_data = { | |
| 137 | + .datardsratio0 = MT41K256M16HA125ITE_RD_DQS, | |
| 138 | + .datawdsratio0 = MT41K256M16HA125ITE_WR_DQS, | |
| 139 | + .datafwsratio0 = MT41K256M16HA125ITE_PHY_FIFO_WE, | |
| 140 | + .datawrsratio0 = MT41K256M16HA125ITE_PHY_WR_DATA, | |
| 141 | +}; | |
| 142 | + | |
| 136 | 143 | static const struct ddr_data ddr3_evm_data = { |
| 137 | 144 | .datardsratio0 = MT41J512M8RH125_RD_DQS, |
| 138 | 145 | .datawdsratio0 = MT41J512M8RH125_WR_DQS, |
| 139 | 146 | |
| 140 | 147 | |
| 141 | 148 | |
| ... | ... | @@ -163,16 +170,27 @@ |
| 163 | 170 | }; |
| 164 | 171 | |
| 165 | 172 | static const struct cmd_control ddr3_smarct335x_cmd_ctrl_data = { |
| 166 | - .cmd0csratio = MT41K256M16HA125E_RATIO, | |
| 167 | - .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, | |
| 173 | + .cmd0csratio = K4B4G1646EBYK0_RATIO, | |
| 174 | + .cmd0iclkout = K4B4G1646EBYK0_INVERT_CLKOUT, | |
| 168 | 175 | |
| 169 | - .cmd1csratio = MT41K256M16HA125E_RATIO, | |
| 170 | - .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, | |
| 176 | + .cmd1csratio = K4B4G1646EBYK0_RATIO, | |
| 177 | + .cmd1iclkout = K4B4G1646EBYK0_INVERT_CLKOUT, | |
| 171 | 178 | |
| 172 | - .cmd2csratio = MT41K256M16HA125E_RATIO, | |
| 173 | - .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, | |
| 179 | + .cmd2csratio = K4B4G1646EBYK0_RATIO, | |
| 180 | + .cmd2iclkout = K4B4G1646EBYK0_INVERT_CLKOUT, | |
| 174 | 181 | }; |
| 175 | 182 | |
| 183 | +static const struct cmd_control ddr3_smarct335x80_cmd_ctrl_data = { | |
| 184 | + .cmd0csratio = MT41K256M16HA125ITE_RATIO, | |
| 185 | + .cmd0iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT, | |
| 186 | + | |
| 187 | + .cmd1csratio = MT41K256M16HA125ITE_RATIO, | |
| 188 | + .cmd1iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT, | |
| 189 | + | |
| 190 | + .cmd2csratio = MT41K256M16HA125ITE_RATIO, | |
| 191 | + .cmd2iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT, | |
| 192 | +}; | |
| 193 | + | |
| 176 | 194 | static const struct cmd_control ddr3_evm_cmd_ctrl_data = { |
| 177 | 195 | .cmd0csratio = MT41J512M8RH125_RATIO, |
| 178 | 196 | .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, |
| 179 | 197 | |
| ... | ... | @@ -206,15 +224,25 @@ |
| 206 | 224 | }; |
| 207 | 225 | |
| 208 | 226 | static struct emif_regs ddr3_smarct335x_emif_reg_data = { |
| 209 | - .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, | |
| 210 | - .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, | |
| 211 | - .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, | |
| 212 | - .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, | |
| 213 | - .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, | |
| 214 | - .zq_config = MT41K256M16HA125E_ZQ_CFG, | |
| 215 | - .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, | |
| 227 | + .sdram_config = K4B4G1646EBYK0_EMIF_SDCFG, | |
| 228 | + .ref_ctrl = K4B4G1646EBYK0_EMIF_SDREF, | |
| 229 | + .sdram_tim1 = K4B4G1646EBYK0_EMIF_TIM1, | |
| 230 | + .sdram_tim2 = K4B4G1646EBYK0_EMIF_TIM2, | |
| 231 | + .sdram_tim3 = K4B4G1646EBYK0_EMIF_TIM3, | |
| 232 | + .zq_config = K4B4G1646EBYK0_ZQ_CFG, | |
| 233 | + .emif_ddr_phy_ctlr_1 = K4B4G1646EBYK0_EMIF_READ_LATENCY, | |
| 216 | 234 | }; |
| 217 | 235 | |
| 236 | +static struct emif_regs ddr3_smarct335x80_emif_reg_data = { | |
| 237 | + .sdram_config = MT41K256M16HA125ITE_EMIF_SDCFG, | |
| 238 | + .ref_ctrl = MT41K256M16HA125ITE_EMIF_SDREF, | |
| 239 | + .sdram_tim1 = MT41K256M16HA125ITE_EMIF_TIM1, | |
| 240 | + .sdram_tim2 = MT41K256M16HA125ITE_EMIF_TIM2, | |
| 241 | + .sdram_tim3 = MT41K256M16HA125ITE_EMIF_TIM3, | |
| 242 | + .zq_config = MT41K256M16HA125ITE_ZQ_CFG, | |
| 243 | + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125ITE_EMIF_READ_LATENCY, | |
| 244 | +}; | |
| 245 | + | |
| 218 | 246 | static struct emif_regs ddr3_evm_emif_reg_data = { |
| 219 | 247 | .sdram_config = MT41J512M8RH125_EMIF_SDCFG, |
| 220 | 248 | .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, |
| 221 | 249 | |
| ... | ... | @@ -463,13 +491,21 @@ |
| 463 | 491 | }; |
| 464 | 492 | |
| 465 | 493 | const struct ctrl_ioregs ioregs_smarct335x = { |
| 466 | - .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
| 467 | - .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
| 468 | - .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
| 469 | - .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
| 470 | - .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, | |
| 494 | + .cm0ioctl = K4B4G1646EBYK0_IOCTRL_VALUE, | |
| 495 | + .cm1ioctl = K4B4G1646EBYK0_IOCTRL_VALUE, | |
| 496 | + .cm2ioctl = K4B4G1646EBYK0_IOCTRL_VALUE, | |
| 497 | + .dt0ioctl = K4B4G1646EBYK0_IOCTRL_VALUE, | |
| 498 | + .dt1ioctl = K4B4G1646EBYK0_IOCTRL_VALUE, | |
| 471 | 499 | }; |
| 472 | 500 | |
| 501 | +const struct ctrl_ioregs ioregs_smarct335x80 = { | |
| 502 | + .cm0ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE, | |
| 503 | + .cm1ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE, | |
| 504 | + .cm2ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE, | |
| 505 | + .dt0ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE, | |
| 506 | + .dt1ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE, | |
| 507 | +}; | |
| 508 | + | |
| 473 | 509 | const struct ctrl_ioregs ioregs_evm15 = { |
| 474 | 510 | .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, |
| 475 | 511 | .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, |
| 476 | 512 | |
| 477 | 513 | |
| ... | ... | @@ -510,20 +546,35 @@ |
| 510 | 546 | &ddr3_beagleblack_data, |
| 511 | 547 | &ddr3_beagleblack_cmd_ctrl_data, |
| 512 | 548 | &ddr3_beagleblack_emif_reg_data, 0); |
| 513 | - else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header)) { | |
| 549 | + else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) { | |
| 514 | 550 | /* |
| 515 | 551 | * SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM and gpio1_22 as LCD backlight enable. |
| 516 | 552 | * This is safe enough to do on older revs. |
| 517 | 553 | */ |
| 518 | - gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en"); | |
| 554 | + gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en"); | |
| 519 | 555 | gpio_direction_output(GPIO_LCD_BKLT_EN, 1); |
| 520 | 556 | gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en"); |
| 521 | 557 | gpio_direction_output(GPIO_LCD_PWM_EN, 1); |
| 522 | - config_ddr(400, &ioregs_smarct335x, | |
| 523 | - &ddr3_smarct335x_data, | |
| 524 | - &ddr3_smarct335x_cmd_ctrl_data, | |
| 525 | - &ddr3_smarct335x_emif_reg_data, 0); | |
| 526 | - puts("Set DDR3 to 800MHz.\n"); | |
| 558 | + config_ddr(400, &ioregs_smarct335x, | |
| 559 | + &ddr3_smarct335x_data, | |
| 560 | + &ddr3_smarct335x_cmd_ctrl_data, | |
| 561 | + &ddr3_smarct335x_emif_reg_data, 0); | |
| 562 | + udelay(1600); | |
| 563 | + } | |
| 564 | + else if (board_is_smarc_t335x_80(&header)) { | |
| 565 | + /* | |
| 566 | + * SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM and gpio1_22 as LCD backlight enable. | |
| 567 | + * This is safe enough to do on older revs. | |
| 568 | + */ | |
| 569 | + gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en"); | |
| 570 | + gpio_direction_output(GPIO_LCD_BKLT_EN, 1); | |
| 571 | + gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en"); | |
| 572 | + gpio_direction_output(GPIO_LCD_PWM_EN, 1); | |
| 573 | + config_ddr(400, &ioregs_smarct335x80, | |
| 574 | + &ddr3_smarct335x80_data, | |
| 575 | + &ddr3_smarct335x80_cmd_ctrl_data, | |
| 576 | + &ddr3_smarct335x80_emif_reg_data, 0); | |
| 577 | + udelay(1600); | |
| 527 | 578 | } |
| 528 | 579 | else if (board_is_evm_15_or_later(&header)) |
| 529 | 580 | config_ddr(400, &ioregs_evm15, &ddr3_evm_data, |