Commit 3064d599afaed1e601479efa372a6e83d4ea9deb
Committed by
Albert ARIBAUD
1 parent
375a4496ff
Exists in
master
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50 other branches
ARM: align MVBAR on 32 byte boundary
The lower 5 bit of MVBAR is UNK/SBZP. So, Monitor Vector Base Address must be 32-byte aligned. On the other hand, the secure monitor handler does not need 32-byte alignment. This commit moves ".algin 5" directive to the correct place. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Andre Przywara <andre.przywara@linaro.org> Acked-by: Andre Przywara <andre.przywara@linaro.org>
Showing 1 changed file with 1 additions and 1 deletions Side-by-side Diff
arch/arm/cpu/armv7/nonsec_virt.S
... | ... | @@ -14,6 +14,7 @@ |
14 | 14 | .arch_extension sec |
15 | 15 | .arch_extension virt |
16 | 16 | |
17 | + .align 5 | |
17 | 18 | /* the vector table for secure state and HYP mode */ |
18 | 19 | _monitor_vectors: |
19 | 20 | .word 0 /* reset */ |
... | ... | @@ -32,7 +33,6 @@ |
32 | 33 | * to non-secure state. |
33 | 34 | * We use only r0 and r1 here, due to constraints in the caller. |
34 | 35 | */ |
35 | - .align 5 | |
36 | 36 | _secure_monitor: |
37 | 37 | mrc p15, 0, r1, c1, c1, 0 @ read SCR |
38 | 38 | bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits |