Eric Lee / smarc-uboot

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Commit 30ce7adebd443ef777e820c4a891cbb3b28ac671

Authored by Bai Ping
1 parent 911fcf93ba
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-13140 ARM: imx: update REFTOP_VBGADJ according to fuse setting 

On i.MX6ULL, according to the latest REFTOP_TRIM fuse define, we need
to set the REFTOP_VBGADJ bits in PMU_MISC0 register as below table:

    '000" - set REFTOP_VBGADJ[2:0] to 3'b000
    '001" - set REFTOP_VBGADJ[2:0] to 3'b001
    '010" - set REFTOP_VBGADJ[2:0] to 3'b010
    '011" - set REFTOP_VBGADJ[2:0] to 3'b011
    '100" - set REFTOP_VBGADJ[2:0] to 3'b100
    '101" - set REFTOP_VBGADJ[2:0] to 3'b101
    '110" - set REFTOP_VBGADJ[2:0] to 3'b110
    '111" - set REFTOP_VBGADJ[2:0] to 3'b111

Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit b2690f5cf54390999acb2f1f7b788bfd18fa11be)

Showing 1 changed file with 0 additions and 5 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ 30ce7ad
... ... @@ -349,11 +349,6 @@
349 349 val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
350 350 val &= 0x7;
351 351  
352   - if (val == 0) {
353   - val = 6;
354   - } else if (val == 6) {
355   - val = 0;
356   - }
357 352 writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
358 353 &anatop->ana_misc0_set);
359 354 }