Eric Lee / smarc-uboot

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Commit 911fcf93bad8c0a595c350b92f107b626029559b

Authored by Bai Ping
1 parent 44a84b44a8
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-13124 ARM: imx: update the REFTOP_VBGADJ setting 

Per to design team, we need to set REFTOP_VBGADJ
in PMU MISC0 according to the REFTOP_TRIM[2:0] fuse. the
actually table is as below:

  '000' - set REFTOP_VBGADJ[2:0] to 3b'110
  '110' - set REFTOP_VBGADJ[2:0] to 3b'000
  '001' - set REFTOP_VBGADJ[2:0] to 3b'001
  '010' - set REFTOP_VBGADJ[2:0] to 3b'010
  '011' - set REFTOP_VBGADJ[2:0] to 3b'011
  '100' - set REFTOP_VBGADJ[2:0] to 3b'100
  '101' - set REFTOP_VBGADJ[2:0] to 3b'101
  '111' - set REFTOP_VBGADJ[2:0] to 3b'111

Signed-off-by: Bai Ping <ping.bai@nxp.com>

Showing 2 changed files with 32 additions and 6 deletions Side-by-side Diff

arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ 911fcf9
... ... @@ -310,9 +310,17 @@
310 310 writel(reg, &mxc_ccm->ccdr);
311 311 }
312 312  
  313 +#define OCOTP_MEM0_REFTOP_TRIM_SHIFT 8
  314 +
313 315 static void init_bandgap(void)
314 316 {
315 317 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  318 + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  319 + struct fuse_bank *bank = &ocotp->bank[1];
  320 + struct fuse_bank1_regs *fuse =
  321 + (struct fuse_bank1_regs *)bank->fuse_regs;
  322 + uint32_t val;
  323 +
316 324 /*
317 325 * Ensure the bandgap has stabilized.
318 326 */
319 327  
320 328  
... ... @@ -325,13 +333,31 @@
325 333 */
326 334 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
327 335 /*
328   - * On i.MX6ULL, the LDO 1.2V bandgap voltage is 30mV higher. so set
329   - * VBGADJ bits to 2b'110 to adjust it.
  336 + * On i.MX6ULL,we need to set VBGADJ bits according to the
  337 + * REFTOP_TRIM[3:0] in fuse table
  338 + * 000 - set REFTOP_VBGADJ[2:0] to 3b'110,
  339 + * 110 - set REFTOP_VBGADJ[2:0] to 3b'000,
  340 + * 001 - set REFTOP_VBGADJ[2:0] to 3b'001,
  341 + * 010 - set REFTOP_VBGADJ[2:0] to 3b'010,
  342 + * 011 - set REFTOP_VBGADJ[2:0] to 3b'011,
  343 + * 100 - set REFTOP_VBGADJ[2:0] to 3b'100,
  344 + * 101 - set REFTOP_VBGADJ[2:0] to 3b'101,
  345 + * 111 - set REFTOP_VBGADJ[2:0] to 3b'111,
330 346 */
331   - if (is_cpu_type(MXC_CPU_MX6ULL))
332   - writel(BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ, &anatop->ana_misc0_set);
333   -}
  347 + if (is_cpu_type(MXC_CPU_MX6ULL)) {
  348 + val = readl(&fuse->mem0);
  349 + val >>= OCOTP_MEM0_REFTOP_TRIM_SHIFT;
  350 + val &= 0x7;
334 351  
  352 + if (val == 0) {
  353 + val = 6;
  354 + } else if (val == 6) {
  355 + val = 0;
  356 + }
  357 + writel(val << BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT,
  358 + &anatop->ana_misc0_set);
  359 + }
  360 +}
335 361  
336 362 #ifdef CONFIG_MX6SL
337 363 static void set_preclk_from_osc(void)
arch/arm/include/asm/arch-mx6/crm_regs.h
Diff comments   View file @ 911fcf9
... ... @@ -1272,7 +1272,7 @@
1272 1272 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
1273 1273  
1274 1274 #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
1275   -#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ 0x60
  1275 +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ_SHIFT 4
1276 1276  
1277 1277 #define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
1278 1278 #define BP_PMU_MISC2_AUDIO_DIV_MSB 23