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Commit 31993d6a3585d478d792fc70240129b0ca03f55f

Authored by Michal Simek
1 parent c83a35f652
Exists in master and in 49 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

fpga: zynqpl: Add support for zc7015 device 

Just extend tables with this new device.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Showing 2 changed files with 9 additions and 0 deletions Inline Diff

board/xilinx/zynq/board.c
Diff comments   View file @ 31993d6
1 /* 1 /*
2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu> 2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <netdev.h> 8 #include <netdev.h>
9 #include <zynqpl.h> 9 #include <zynqpl.h>
10 #include <asm/arch/hardware.h> 10 #include <asm/arch/hardware.h>
11 #include <asm/arch/sys_proto.h> 11 #include <asm/arch/sys_proto.h>
12 12
13 DECLARE_GLOBAL_DATA_PTR; 13 DECLARE_GLOBAL_DATA_PTR;
14 14
15 /* Bootmode setting values */ 15 /* Bootmode setting values */
16 #define ZYNQ_BM_MASK 0x0F 16 #define ZYNQ_BM_MASK 0x0F
17 #define ZYNQ_BM_NOR 0x02 17 #define ZYNQ_BM_NOR 0x02
18 #define ZYNQ_BM_SD 0x05 18 #define ZYNQ_BM_SD 0x05
19 #define ZYNQ_BM_JTAG 0x0 19 #define ZYNQ_BM_JTAG 0x0
20 20
21 #ifdef CONFIG_FPGA 21 #ifdef CONFIG_FPGA
22 Xilinx_desc fpga; 22 Xilinx_desc fpga;
23 23
24 /* It can be done differently */ 24 /* It can be done differently */
25 Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); 25 Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
26 Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
26 Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); 27 Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
27 Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); 28 Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
28 Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); 29 Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
29 Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); 30 Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
30 #endif 31 #endif
31 32
32 int board_init(void) 33 int board_init(void)
33 { 34 {
34 #ifdef CONFIG_FPGA 35 #ifdef CONFIG_FPGA
35 u32 idcode; 36 u32 idcode;
36 37
37 idcode = zynq_slcr_get_idcode(); 38 idcode = zynq_slcr_get_idcode();
38 39
39 switch (idcode) { 40 switch (idcode) {
40 case XILINX_ZYNQ_7010: 41 case XILINX_ZYNQ_7010:
41 fpga = fpga010; 42 fpga = fpga010;
43 break;
44 case XILINX_ZYNQ_7015:
45 fpga = fpga015;
42 break; 46 break;
43 case XILINX_ZYNQ_7020: 47 case XILINX_ZYNQ_7020:
44 fpga = fpga020; 48 fpga = fpga020;
45 break; 49 break;
46 case XILINX_ZYNQ_7030: 50 case XILINX_ZYNQ_7030:
47 fpga = fpga030; 51 fpga = fpga030;
48 break; 52 break;
49 case XILINX_ZYNQ_7045: 53 case XILINX_ZYNQ_7045:
50 fpga = fpga045; 54 fpga = fpga045;
51 break; 55 break;
52 case XILINX_ZYNQ_7100: 56 case XILINX_ZYNQ_7100:
53 fpga = fpga100; 57 fpga = fpga100;
54 break; 58 break;
55 } 59 }
56 #endif 60 #endif
57 61
58 icache_enable(); 62 icache_enable();
59 63
60 #ifdef CONFIG_FPGA 64 #ifdef CONFIG_FPGA
61 fpga_init(); 65 fpga_init();
62 fpga_add(fpga_xilinx, &fpga); 66 fpga_add(fpga_xilinx, &fpga);
63 #endif 67 #endif
64 68
65 return 0; 69 return 0;
66 } 70 }
67 71
68 int board_late_init(void) 72 int board_late_init(void)
69 { 73 {
70 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) { 74 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
71 case ZYNQ_BM_NOR: 75 case ZYNQ_BM_NOR:
72 setenv("modeboot", "norboot"); 76 setenv("modeboot", "norboot");
73 break; 77 break;
74 case ZYNQ_BM_SD: 78 case ZYNQ_BM_SD:
75 setenv("modeboot", "sdboot"); 79 setenv("modeboot", "sdboot");
76 break; 80 break;
77 case ZYNQ_BM_JTAG: 81 case ZYNQ_BM_JTAG:
78 setenv("modeboot", "jtagboot"); 82 setenv("modeboot", "jtagboot");
79 break; 83 break;
80 default: 84 default:
81 setenv("modeboot", ""); 85 setenv("modeboot", "");
82 break; 86 break;
83 } 87 }
84 88
85 return 0; 89 return 0;
86 } 90 }
87 91
88 #ifdef CONFIG_CMD_NET 92 #ifdef CONFIG_CMD_NET
89 int board_eth_init(bd_t *bis) 93 int board_eth_init(bd_t *bis)
90 { 94 {
91 u32 ret = 0; 95 u32 ret = 0;
92 96
93 #ifdef CONFIG_XILINX_AXIEMAC 97 #ifdef CONFIG_XILINX_AXIEMAC
94 ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR, 98 ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
95 XILINX_AXIDMA_BASEADDR); 99 XILINX_AXIDMA_BASEADDR);
96 #endif 100 #endif
97 #ifdef CONFIG_XILINX_EMACLITE 101 #ifdef CONFIG_XILINX_EMACLITE
98 u32 txpp = 0; 102 u32 txpp = 0;
99 u32 rxpp = 0; 103 u32 rxpp = 0;
100 # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG 104 # ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
101 txpp = 1; 105 txpp = 1;
102 # endif 106 # endif
103 # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG 107 # ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
104 rxpp = 1; 108 rxpp = 1;
105 # endif 109 # endif
106 ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR, 110 ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
107 txpp, rxpp); 111 txpp, rxpp);
108 #endif 112 #endif
109 113
110 #if defined(CONFIG_ZYNQ_GEM) 114 #if defined(CONFIG_ZYNQ_GEM)
111 # if defined(CONFIG_ZYNQ_GEM0) 115 # if defined(CONFIG_ZYNQ_GEM0)
112 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0, 116 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
113 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0); 117 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
114 # endif 118 # endif
115 # if defined(CONFIG_ZYNQ_GEM1) 119 # if defined(CONFIG_ZYNQ_GEM1)
116 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1, 120 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
117 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0); 121 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
118 # endif 122 # endif
119 #endif 123 #endif
120 return ret; 124 return ret;
121 } 125 }
122 #endif 126 #endif
123 127
124 #ifdef CONFIG_CMD_MMC 128 #ifdef CONFIG_CMD_MMC
125 int board_mmc_init(bd_t *bd) 129 int board_mmc_init(bd_t *bd)
126 { 130 {
127 int ret = 0; 131 int ret = 0;
128 132
129 #if defined(CONFIG_ZYNQ_SDHCI) 133 #if defined(CONFIG_ZYNQ_SDHCI)
130 # if defined(CONFIG_ZYNQ_SDHCI0) 134 # if defined(CONFIG_ZYNQ_SDHCI0)
131 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0); 135 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
132 # endif 136 # endif
133 # if defined(CONFIG_ZYNQ_SDHCI1) 137 # if defined(CONFIG_ZYNQ_SDHCI1)
134 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1); 138 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
135 # endif 139 # endif
136 #endif 140 #endif
137 return ret; 141 return ret;
138 } 142 }
139 #endif 143 #endif
140 144
141 int dram_init(void) 145 int dram_init(void)
142 { 146 {
143 gd->ram_size = CONFIG_SYS_SDRAM_SIZE; 147 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
144 148
145 zynq_ddrc_init(); 149 zynq_ddrc_init();
146 150
147 return 0; 151 return 0;
148 } 152 }
149 153
1 /* 1 /*
2 * (C) Copyright 2012-2013, Xilinx, Michal Simek 2 * (C) Copyright 2012-2013, Xilinx, Michal Simek
3 * 3 *
4 * (C) Copyright 2012 4 * (C) Copyright 2012
5 * Joe Hershberger <joe.hershberger@ni.com> 5 * Joe Hershberger <joe.hershberger@ni.com>
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #ifndef _ZYNQPL_H_ 10 #ifndef _ZYNQPL_H_
11 #define _ZYNQPL_H_ 11 #define _ZYNQPL_H_
12 12
13 #include <xilinx.h> 13 #include <xilinx.h>
14 14
15 extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size); 15 extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size);
16 extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize); 16 extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
17 extern int zynq_info(Xilinx_desc *desc); 17 extern int zynq_info(Xilinx_desc *desc);
18 18
19 #define XILINX_ZYNQ_7010 0x2 19 #define XILINX_ZYNQ_7010 0x2
20 #define XILINX_ZYNQ_7015 0x1b
20 #define XILINX_ZYNQ_7020 0x7 21 #define XILINX_ZYNQ_7020 0x7
21 #define XILINX_ZYNQ_7030 0xc 22 #define XILINX_ZYNQ_7030 0xc
22 #define XILINX_ZYNQ_7045 0x11 23 #define XILINX_ZYNQ_7045 0x11
23 #define XILINX_ZYNQ_7100 0x16 24 #define XILINX_ZYNQ_7100 0x16
24 25
25 /* Device Image Sizes */ 26 /* Device Image Sizes */
26 #define XILINX_XC7Z010_SIZE 16669920/8 27 #define XILINX_XC7Z010_SIZE 16669920/8
28 #define XILINX_XC7Z015_SIZE 28085344/8
27 #define XILINX_XC7Z020_SIZE 32364512/8 29 #define XILINX_XC7Z020_SIZE 32364512/8
28 #define XILINX_XC7Z030_SIZE 47839328/8 30 #define XILINX_XC7Z030_SIZE 47839328/8
29 #define XILINX_XC7Z045_SIZE 106571232/8 31 #define XILINX_XC7Z045_SIZE 106571232/8
30 #define XILINX_XC7Z100_SIZE 139330784/8 32 #define XILINX_XC7Z100_SIZE 139330784/8
31 33
32 /* Descriptor Macros */ 34 /* Descriptor Macros */
33 #define XILINX_XC7Z010_DESC(cookie) \ 35 #define XILINX_XC7Z010_DESC(cookie) \
34 { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" } 36 { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
37
38 #define XILINX_XC7Z015_DESC(cookie) \
39 { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" }
35 40
36 #define XILINX_XC7Z020_DESC(cookie) \ 41 #define XILINX_XC7Z020_DESC(cookie) \
37 { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" } 42 { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }
38 43
39 #define XILINX_XC7Z030_DESC(cookie) \ 44 #define XILINX_XC7Z030_DESC(cookie) \
40 { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, "7z030" } 45 { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, "7z030" }
41 46
42 #define XILINX_XC7Z045_DESC(cookie) \ 47 #define XILINX_XC7Z045_DESC(cookie) \
43 { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" } 48 { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }
44 49
45 #define XILINX_XC7Z100_DESC(cookie) \ 50 #define XILINX_XC7Z100_DESC(cookie) \
46 { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" } 51 { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" }
47 52
48 #endif /* _ZYNQPL_H_ */ 53 #endif /* _ZYNQPL_H_ */
49 54