fpga: zynqpl: Add support for zc7015 device

Just extend tables with this new device. Signed-off-by: Michal Simek <michal.simek@xilinx.com>

fpga: zynqpl: Add support for zc7015 device
Just extend tables with this new device. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek
1 parent c83a35f652
Showing 2 changed files with 9 additions and 0 deletions Side-by-side Diff
board/xilinx/zynq/board.c
include/zynqpl.h
@@ -23,6 +23,7 @@
  
 /* It can be done differently */
 Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
+Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
 Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
 Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
 Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
@@ -39,6 +40,9 @@
 	switch (idcode) {
 	case XILINX_ZYNQ_7010:
 		fpga = fpga010;
+		break;
+	case XILINX_ZYNQ_7015:
+		fpga = fpga015;
 		break;
 	case XILINX_ZYNQ_7020:
 		fpga = fpga020;
@@ -17,6 +17,7 @@
 extern int zynq_info(Xilinx_desc *desc);
  
 #define XILINX_ZYNQ_7010	0x2
+#define XILINX_ZYNQ_7015	0x1b
 #define XILINX_ZYNQ_7020	0x7
 #define XILINX_ZYNQ_7030	0xc
 #define XILINX_ZYNQ_7045	0x11
@@ -24,6 +25,7 @@
  
 /* Device Image Sizes */
 #define XILINX_XC7Z010_SIZE	16669920/8
+#define XILINX_XC7Z015_SIZE	28085344/8
 #define XILINX_XC7Z020_SIZE	32364512/8
 #define XILINX_XC7Z030_SIZE	47839328/8
 #define XILINX_XC7Z045_SIZE	106571232/8
@@ -32,6 +34,9 @@
 /* Descriptor Macros */
 #define XILINX_XC7Z010_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
+
+#define XILINX_XC7Z015_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" }
  
 #define XILINX_XC7Z020_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }
...	...	@@ -23,6 +23,7 @@
23	23
24	24	/* It can be done differently */
25	25	Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
	26	+Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
26	27	Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
27	28	Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
28	29	Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
...	...	@@ -39,6 +40,9 @@
39	40	switch (idcode) {
40	41	case XILINX_ZYNQ_7010:
41	42	fpga = fpga010;
	43	+ break;
	44	+ case XILINX_ZYNQ_7015:
	45	+ fpga = fpga015;
42	46	break;
43	47	case XILINX_ZYNQ_7020:
44	48	fpga = fpga020;
...	...	@@ -17,6 +17,7 @@
17	17	extern int zynq_info(Xilinx_desc *desc);
18	18
19	19	#define XILINX_ZYNQ_7010 0x2
	20	+#define XILINX_ZYNQ_7015 0x1b
20	21	#define XILINX_ZYNQ_7020 0x7
21	22	#define XILINX_ZYNQ_7030 0xc
22	23	#define XILINX_ZYNQ_7045 0x11
...	...	@@ -24,6 +25,7 @@
24	25
25	26	/* Device Image Sizes */
26	27	#define XILINX_XC7Z010_SIZE 16669920/8
	28	+#define XILINX_XC7Z015_SIZE 28085344/8
27	29	#define XILINX_XC7Z020_SIZE 32364512/8
28	30	#define XILINX_XC7Z030_SIZE 47839328/8
29	31	#define XILINX_XC7Z045_SIZE 106571232/8
...	...	@@ -32,6 +34,9 @@
32	34	/* Descriptor Macros */
33	35	#define XILINX_XC7Z010_DESC(cookie) \
34	36	{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" }
	37	+
	38	+#define XILINX_XC7Z015_DESC(cookie) \
	39	+{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" }
35	40
36	41	#define XILINX_XC7Z020_DESC(cookie) \
37	42	{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" }