Eric Lee / smarc-uboot

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Commit 338223a98b8ec6231c914232615ba628c7506f40

Authored by Ye Li
1 parent 8a86dcda13
Exists in emb_lf_v2022.04

MLK-24958-2 DTS: imx8qxp/dxl: Update LCDIF clock names 

Update the LCDIF clocks to align with u-boot clock driver.
Since u-boot imx8 clock driver can gate and divide on slice clock,
so it does not create two clocks on slice clock.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit c5fddad29b23cd74732b6aa3720bd8d62f41462e)
(cherry picked from commit dafd6bc77fc990d149bba38cacda06da57b4573f)
(cherry picked from commit cf86bcd31fa8d458c10af6cf9bb20c53d7690f31)
(cherry picked from commit 1c3df52da566d53d5b78079fe2fb105ec2034878)

Showing 2 changed files with 9 additions and 9 deletions Side-by-side Diff

arch/arm/dts/fsl-imx8dx.dtsi
Diff comments   View file @ 338223a
... ... @@ -1803,16 +1803,16 @@
1803 1803 adma_lcdif: lcdif@5a180000 {
1804 1804 compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif";
1805 1805 reg = <0x0 0x5a180000 0x0 0x10000>;
1806   - clocks = <&clk IMX8QXP_LCD_CLK>,
1807   - <&clk IMX8QXP_LCD_PXL_CLK>,
  1806 + clocks = <&clk IMX8QXP_LCD_DIV>,
  1807 + <&clk IMX8QXP_LCD_PXL_DIV>,
1808 1808 <&clk IMX8QXP_LCD_IPG_CLK>;
1809 1809 clock-names = "pix", "disp_axi", "axi";
1810 1810 assigned-clocks = <&clk IMX8QXP_LCD_SEL>,
1811 1811 <&clk IMX8QXP_LCD_PXL_SEL>,
1812   - <&clk IMX8QXP_ELCDIF_PLL_DIV>;
1813   - assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL>,
  1812 + <&clk IMX8QXP_ELCDIF_PLL_DIV>;
  1813 + assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL_DIV>,
1814 1814 <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>;
1815   - assigned-clock-rates = <0>, <24000000>, <804000000>;
  1815 + assigned-clock-rates = <0>, <0>, <804000000>;
1816 1816 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1817 1817 power-domains = <&pd_dma_lcd0>;
1818 1818 status = "disabled";
arch/arm/dts/fsl-imx8dxl.dtsi
Diff comments   View file @ 338223a
... ... @@ -962,16 +962,16 @@
962 962 adma_lcdif: lcdif@5a180000 {
963 963 compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif";
964 964 reg = <0x0 0x5a180000 0x0 0x10000>;
965   - clocks = <&clk IMX8QXP_LCD_CLK>,
966   - <&clk IMX8QXP_LCD_PXL_CLK>,
  965 + clocks = <&clk IMX8QXP_LCD_DIV>,
  966 + <&clk IMX8QXP_LCD_PXL_DIV>,
967 967 <&clk IMX8QXP_LCD_IPG_CLK>;
968 968 clock-names = "pix", "disp_axi", "axi";
969 969 assigned-clocks = <&clk IMX8QXP_LCD_SEL>,
970 970 <&clk IMX8QXP_LCD_PXL_SEL>,
971 971 <&clk IMX8QXP_ELCDIF_PLL_DIV>;
972   - assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL>,
  972 + assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL_DIV>,
973 973 <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>;
974   - assigned-clock-rates = <0>, <24000000>, <804000000>;
  974 + assigned-clock-rates = <0>, <0>, <804000000>;
975 975 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
976 976 power-domains = <&pd_dma_lcd0>;
977 977 status = "disabled";