Commit 35ba667df43ed662a294ee99ed66d3ddb9b95832
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d08a1baf61
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sf: probe: Enable RD_FULL and WR_QPP
This patch enabled RD_FULL and WR_QPP for supported flashes in micron, winbond and spansion. Remaining parts will be add in future patches. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Showing 1 changed file with 30 additions and 30 deletions Side-by-side Diff
drivers/mtd/spi/sf_probe.c
... | ... | @@ -78,15 +78,15 @@ |
78 | 78 | {"S25FL016A", 0x010214, 0x0, 64 * 1024, 32, 0, 0}, |
79 | 79 | {"S25FL032A", 0x010215, 0x0, 64 * 1024, 64, 0, 0}, |
80 | 80 | {"S25FL064A", 0x010216, 0x0, 64 * 1024, 128, 0, 0}, |
81 | - {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, 0, 0}, | |
82 | - {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, 0, 0}, | |
83 | - {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0, 0}, | |
84 | - {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0, 0}, | |
85 | - {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0, 0}, | |
81 | + {"S25FL128P_256K", 0x012018, 0x0300, 256 * 1024, 64, RD_FULL, WR_QPP}, | |
82 | + {"S25FL128P_64K", 0x012018, 0x0301, 64 * 1024, 256, RD_FULL, WR_QPP}, | |
83 | + {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, RD_FULL, WR_QPP}, | |
84 | + {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, RD_FULL, WR_QPP}, | |
85 | + {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, RD_FULL, WR_QPP}, | |
86 | 86 | {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, RD_FULL, WR_QPP}, |
87 | 87 | {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP}, |
88 | - {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0, 0}, | |
89 | - {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0, 0}, | |
88 | + {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, RD_FULL, WR_QPP}, | |
89 | + {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP}, | |
90 | 90 | #endif |
91 | 91 | #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ |
92 | 92 | {"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0}, |
... | ... | @@ -97,18 +97,18 @@ |
97 | 97 | {"M25P32", 0x202016, 0x0, 64 * 1024, 64, 0, 0}, |
98 | 98 | {"M25P64", 0x202017, 0x0, 64 * 1024, 128, 0, 0}, |
99 | 99 | {"M25P128", 0x202018, 0x0, 256 * 1024, 64, 0, 0}, |
100 | - {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, 0, SECT_4K}, | |
101 | - {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, 0, SECT_4K}, | |
102 | - {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, 0, SECT_4K}, | |
103 | - {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, 0, SECT_4K}, | |
104 | - {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, 0, SECT_4K}, | |
105 | - {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, 0, SECT_4K}, | |
106 | - {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, 0, SECT_4K}, | |
107 | - {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, 0, SECT_4K}, | |
108 | - {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K}, | |
109 | - {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, 0, E_FSR | SECT_4K}, | |
110 | - {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K}, | |
111 | - {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, 0, E_FSR | SECT_4K}, | |
100 | + {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, | |
101 | + {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, | |
102 | + {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, | |
103 | + {"N25Q64A", 0x20bb17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, | |
104 | + {"N25Q128", 0x20ba18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, | |
105 | + {"N25Q128A", 0x20bb18, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, | |
106 | + {"N25Q256", 0x20ba19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, | |
107 | + {"N25Q256A", 0x20bb19, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, | |
108 | + {"N25Q512", 0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, | |
109 | + {"N25Q512A", 0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL, WR_QPP | E_FSR | SECT_4K}, | |
110 | + {"N25Q1024", 0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, | |
111 | + {"N25Q1024A", 0x20bb21, 0x0, 64 * 1024, 2048, RD_FULL, WR_QPP | E_FSR | SECT_4K}, | |
112 | 112 | #endif |
113 | 113 | #ifdef CONFIG_SPI_FLASH_SST /* SST */ |
114 | 114 | {"SST25VF040B", 0xbf258d, 0x0, 64 * 1024, 8, 0, SECT_4K | SST_WP}, |
... | ... | @@ -130,17 +130,17 @@ |
130 | 130 | {"W25X16", 0xef3015, 0x0, 64 * 1024, 32, 0, SECT_4K}, |
131 | 131 | {"W25X32", 0xef3016, 0x0, 64 * 1024, 64, 0, SECT_4K}, |
132 | 132 | {"W25X64", 0xef3017, 0x0, 64 * 1024, 128, 0, SECT_4K}, |
133 | - {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, 0, SECT_4K}, | |
134 | - {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, 0, SECT_4K}, | |
135 | - {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, 0, SECT_4K}, | |
136 | - {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, 0, SECT_4K}, | |
137 | - {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, 0, SECT_4K}, | |
138 | - {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, 0, SECT_4K}, | |
139 | - {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, 0, SECT_4K}, | |
140 | - {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, 0, SECT_4K}, | |
141 | - {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, 0, SECT_4K}, | |
142 | - {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, 0, SECT_4K}, | |
143 | - {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, 0, SECT_4K}, | |
133 | + {"W25Q80BL", 0xef4014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, | |
134 | + {"W25Q16CL", 0xef4015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, | |
135 | + {"W25Q32BV", 0xef4016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, | |
136 | + {"W25Q64CV", 0xef4017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, | |
137 | + {"W25Q128BV", 0xef4018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, | |
138 | + {"W25Q256", 0xef4019, 0x0, 64 * 1024, 512, RD_FULL, WR_QPP | SECT_4K}, | |
139 | + {"W25Q80BW", 0xef5014, 0x0, 64 * 1024, 16, RD_FULL, WR_QPP | SECT_4K}, | |
140 | + {"W25Q16DW", 0xef6015, 0x0, 64 * 1024, 32, RD_FULL, WR_QPP | SECT_4K}, | |
141 | + {"W25Q32DW", 0xef6016, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, | |
142 | + {"W25Q64DW", 0xef6017, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, | |
143 | + {"W25Q128FW", 0xef6018, 0x0, 64 * 1024, 256, RD_FULL, WR_QPP | SECT_4K}, | |
144 | 144 | #endif |
145 | 145 | /* |
146 | 146 | * Note: |