Eric Lee / smarc-uboot

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Commit 369776edfebf022130a2a8ed986e73ede62ec7cd

Authored by Ye Li
1 parent 5274ae1eb9
Exists in smarc_8mm-imx_v2019.04_4.19.35_1.1.0 and in 1 other branch smarc_8m-imx_v2019.04_4.19.35_1.1.0

MLK-22851-3 imx8mq: Enable eMMC HS400 and SD UHS mode on EVK 

iMX8MQ EVK board has a eMMC5.0 chip and supports SD3.0, so enable the UHS
and HS400 configs to enhance the eMMC/SD access.

The change also needs to set usdhc clock to 400Mhz, and add the off-on-delay-us
to SD reset pin, otherwise some SD cards will fail to select UHS mode in
re-initialization.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 57e1bc5f634be231b2bfd10cf0cbbff86dadd2e1)

Showing 3 changed files with 6 additions and 4 deletions Inline Diff

arch/arm/dts/fsl-imx8mq-evk.dts
Diff comments   View file @ 369776e
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2018 NXP 3 * Copyright 2018 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 /* First 128KB is for PSCI ATF. */ 8 /* First 128KB is for PSCI ATF. */
9 /memreserve/ 0x40000000 0x00020000; 9 /memreserve/ 0x40000000 0x00020000;
10 10
11 #include "fsl-imx8mq.dtsi" 11 #include "fsl-imx8mq.dtsi"
12 12
13 / { 13 / {
14 model = "Freescale i.MX8MQ EVK"; 14 model = "Freescale i.MX8MQ EVK";
15 compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; 15 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
16 16
17 chosen { 17 chosen {
18 bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; 18 bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
19 stdout-path = &uart1; 19 stdout-path = &uart1;
20 }; 20 };
21 21
22 firmware { 22 firmware {
23 optee { 23 optee {
24 compatible = "linaro,optee-tz"; 24 compatible = "linaro,optee-tz";
25 method = "smc"; 25 method = "smc";
26 }; 26 };
27 }; 27 };
28 28
29 regulators { 29 regulators {
30 compatible = "simple-bus"; 30 compatible = "simple-bus";
31 #address-cells = <1>; 31 #address-cells = <1>;
32 #size-cells = <0>; 32 #size-cells = <0>;
33 33
34 reg_usdhc2_vmmc: usdhc2_vmmc { 34 reg_usdhc2_vmmc: usdhc2_vmmc {
35 compatible = "regulator-fixed"; 35 compatible = "regulator-fixed";
36 regulator-name = "VSD_3V3"; 36 regulator-name = "VSD_3V3";
37 regulator-min-microvolt = <3300000>; 37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>; 38 regulator-max-microvolt = <3300000>;
39 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 39 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
40 u-boot,off-on-delay-us = <20000>;
40 enable-active-high; 41 enable-active-high;
41 }; 42 };
42 }; 43 };
43 44
44 pwmleds { 45 pwmleds {
45 compatible = "pwm-leds"; 46 compatible = "pwm-leds";
46 47
47 ledpwm2 { 48 ledpwm2 {
48 label = "PWM2"; 49 label = "PWM2";
49 pwms = <&pwm2 0 50000>; 50 pwms = <&pwm2 0 50000>;
50 max-brightness = <255>; 51 max-brightness = <255>;
51 }; 52 };
52 }; 53 };
53 }; 54 };
54 55
55 &iomuxc { 56 &iomuxc {
56 pinctrl-names = "default"; 57 pinctrl-names = "default";
57 58
58 imx8mq-evk { 59 imx8mq-evk {
59 pinctrl_fec1: fec1grp { 60 pinctrl_fec1: fec1grp {
60 fsl,pins = < 61 fsl,pins = <
61 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 62 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
62 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 63 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
63 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 64 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
64 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 65 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
65 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 66 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
66 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 67 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
67 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 68 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
68 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 69 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
69 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 70 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
70 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 71 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
71 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 72 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
72 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 73 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
73 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 74 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
74 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 75 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
75 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 76 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
76 >; 77 >;
77 }; 78 };
78 79
79 pinctrl_i2c1: i2c1grp { 80 pinctrl_i2c1: i2c1grp {
80 fsl,pins = < 81 fsl,pins = <
81 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 82 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
82 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f 83 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
83 >; 84 >;
84 }; 85 };
85 86
86 pinctrl_i2c2: i2c2grp { 87 pinctrl_i2c2: i2c2grp {
87 fsl,pins = < 88 fsl,pins = <
88 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067 89 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067
89 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067 90 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067
90 >; 91 >;
91 }; 92 };
92 93
93 pinctrl_i2c1_gpio: i2c1grp-gpio { 94 pinctrl_i2c1_gpio: i2c1grp-gpio {
94 fsl,pins = < 95 fsl,pins = <
95 MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x7f 96 MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x7f
96 MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x7f 97 MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x7f
97 >; 98 >;
98 }; 99 };
99 100
100 pinctrl_i2c2_gpio: i2c2grp-gpio { 101 pinctrl_i2c2_gpio: i2c2grp-gpio {
101 fsl,pins = < 102 fsl,pins = <
102 MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x7f 103 MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x7f
103 MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x7f 104 MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x7f
104 >; 105 >;
105 }; 106 };
106 107
107 pinctrl_pwm2: pwm2grp { 108 pinctrl_pwm2: pwm2grp {
108 fsl,pins = < 109 fsl,pins = <
109 MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 110 MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
110 >; 111 >;
111 }; 112 };
112 113
113 pinctrl_qspi: qspigrp { 114 pinctrl_qspi: qspigrp {
114 fsl,pins = < 115 fsl,pins = <
115 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 116 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
116 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 117 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
117 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 118 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
118 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 119 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
119 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 120 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
120 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 121 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
121 122
122 >; 123 >;
123 }; 124 };
124 125
125 pinctrl_uart1: uart1grp { 126 pinctrl_uart1: uart1grp {
126 fsl,pins = < 127 fsl,pins = <
127 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 128 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
128 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 129 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
129 >; 130 >;
130 }; 131 };
131 132
132 pinctrl_uart3: uart3grp { 133 pinctrl_uart3: uart3grp {
133 fsl,pins = < 134 fsl,pins = <
134 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 135 MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
135 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 136 MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
136 MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 137 MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49
137 MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 138 MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49
138 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x49 139 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x49
139 >; 140 >;
140 }; 141 };
141 142
142 pinctrl_usdhc1: usdhc1grp { 143 pinctrl_usdhc1: usdhc1grp {
143 fsl,pins = < 144 fsl,pins = <
144 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 145 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
145 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 146 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
146 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 147 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
147 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 148 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
148 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 149 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
149 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 150 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
150 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 151 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
151 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 152 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
152 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 153 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
153 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 154 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
154 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 155 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
155 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 156 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
156 >; 157 >;
157 }; 158 };
158 159
159 pinctrl_usdhc1_100mhz: usdhc1grp100mhz { 160 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
160 fsl,pins = < 161 fsl,pins = <
161 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 162 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
162 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 163 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
163 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 164 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
164 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 165 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
165 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 166 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
166 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 167 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
167 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 168 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
168 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 169 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
169 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 170 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
170 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 171 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
171 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 172 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
172 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 173 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
173 >; 174 >;
174 }; 175 };
175 176
176 pinctrl_usdhc1_200mhz: usdhc1grp200mhz { 177 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
177 fsl,pins = < 178 fsl,pins = <
178 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 179 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
179 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 180 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
180 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 181 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
181 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 182 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
182 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 183 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
183 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 184 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
184 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 185 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
185 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 186 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
186 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 187 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
187 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 188 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
188 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 189 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
189 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 190 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
190 >; 191 >;
191 }; 192 };
192 193
193 pinctrl_usdhc2_gpio: usdhc2grpgpio { 194 pinctrl_usdhc2_gpio: usdhc2grpgpio {
194 fsl,pins = < 195 fsl,pins = <
195 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 196 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
196 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 197 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
197 >; 198 >;
198 }; 199 };
199 200
200 pinctrl_usdhc2: usdhc2grp { 201 pinctrl_usdhc2: usdhc2grp {
201 fsl,pins = < 202 fsl,pins = <
202 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 203 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
203 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 204 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
204 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 205 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
205 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 206 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
206 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 207 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
207 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 208 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
208 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 209 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
209 >; 210 >;
210 }; 211 };
211 212
212 pinctrl_usdhc2_100mhz: usdhc2grp100mhz { 213 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
213 fsl,pins = < 214 fsl,pins = <
214 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d 215 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
215 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd 216 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
216 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd 217 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
217 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd 218 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
218 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd 219 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
219 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd 220 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
220 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 221 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
221 >; 222 >;
222 }; 223 };
223 224
224 pinctrl_usdhc2_200mhz: usdhc2grp200mhz { 225 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
225 fsl,pins = < 226 fsl,pins = <
226 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f 227 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
227 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf 228 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
228 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf 229 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf
229 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf 230 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf
230 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf 231 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf
231 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf 232 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf
232 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 233 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
233 >; 234 >;
234 }; 235 };
235 236
236 pinctrl_sai2: sai2grp { 237 pinctrl_sai2: sai2grp {
237 fsl,pins = < 238 fsl,pins = <
238 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 239 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
239 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 240 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
240 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 241 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
241 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 242 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
242 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 243 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
243 >; 244 >;
244 }; 245 };
245 246
246 pinctrl_wdog: wdoggrp { 247 pinctrl_wdog: wdoggrp {
247 fsl,pins = < 248 fsl,pins = <
248 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 249 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
249 >; 250 >;
250 }; 251 };
251 }; 252 };
252 }; 253 };
253 254
254 &fec1 { 255 &fec1 {
255 pinctrl-names = "default"; 256 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_fec1>; 257 pinctrl-0 = <&pinctrl_fec1>;
257 phy-mode = "rgmii-id"; 258 phy-mode = "rgmii-id";
258 phy-handle = <&ethphy0>; 259 phy-handle = <&ethphy0>;
259 fsl,magic-packet; 260 fsl,magic-packet;
260 status = "okay"; 261 status = "okay";
261 262
262 mdio { 263 mdio {
263 #address-cells = <1>; 264 #address-cells = <1>;
264 #size-cells = <0>; 265 #size-cells = <0>;
265 266
266 ethphy0: ethernet-phy@0 { 267 ethphy0: ethernet-phy@0 {
267 compatible = "ethernet-phy-ieee802.3-c22"; 268 compatible = "ethernet-phy-ieee802.3-c22";
268 reg = <0>; 269 reg = <0>;
269 at803x,led-act-blind-workaround; 270 at803x,led-act-blind-workaround;
270 at803x,eee-disabled; 271 at803x,eee-disabled;
271 }; 272 };
272 }; 273 };
273 }; 274 };
274 275
275 &i2c1 { 276 &i2c1 {
276 clock-frequency = <100000>; 277 clock-frequency = <100000>;
277 pinctrl-names = "default", "gpio"; 278 pinctrl-names = "default", "gpio";
278 pinctrl-0 = <&pinctrl_i2c1>; 279 pinctrl-0 = <&pinctrl_i2c1>;
279 pinctrl-1 = <&pinctrl_i2c1_gpio>; 280 pinctrl-1 = <&pinctrl_i2c1_gpio>;
280 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; 281 scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
281 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; 282 sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
282 status = "okay"; 283 status = "okay";
283 284
284 pmic: pfuze100@08 { 285 pmic: pfuze100@08 {
285 compatible = "fsl,pfuze100"; 286 compatible = "fsl,pfuze100";
286 reg = <0x08>; 287 reg = <0x08>;
287 288
288 regulators { 289 regulators {
289 sw1a_reg: sw1ab { 290 sw1a_reg: sw1ab {
290 regulator-min-microvolt = <300000>; 291 regulator-min-microvolt = <300000>;
291 regulator-max-microvolt = <1875000>; 292 regulator-max-microvolt = <1875000>;
292 regulator-always-on; 293 regulator-always-on;
293 }; 294 };
294 295
295 sw1c_reg: sw1c { 296 sw1c_reg: sw1c {
296 regulator-min-microvolt = <300000>; 297 regulator-min-microvolt = <300000>;
297 regulator-max-microvolt = <1875000>; 298 regulator-max-microvolt = <1875000>;
298 regulator-always-on; 299 regulator-always-on;
299 }; 300 };
300 301
301 sw2_reg: sw2 { 302 sw2_reg: sw2 {
302 regulator-min-microvolt = <800000>; 303 regulator-min-microvolt = <800000>;
303 regulator-max-microvolt = <3300000>; 304 regulator-max-microvolt = <3300000>;
304 regulator-always-on; 305 regulator-always-on;
305 }; 306 };
306 307
307 sw3a_reg: sw3ab { 308 sw3a_reg: sw3ab {
308 regulator-min-microvolt = <400000>; 309 regulator-min-microvolt = <400000>;
309 regulator-max-microvolt = <1975000>; 310 regulator-max-microvolt = <1975000>;
310 regulator-always-on; 311 regulator-always-on;
311 }; 312 };
312 313
313 sw4_reg: sw4 { 314 sw4_reg: sw4 {
314 regulator-min-microvolt = <800000>; 315 regulator-min-microvolt = <800000>;
315 regulator-max-microvolt = <3300000>; 316 regulator-max-microvolt = <3300000>;
316 regulator-always-on; 317 regulator-always-on;
317 }; 318 };
318 319
319 swbst_reg: swbst { 320 swbst_reg: swbst {
320 regulator-min-microvolt = <5000000>; 321 regulator-min-microvolt = <5000000>;
321 regulator-max-microvolt = <5150000>; 322 regulator-max-microvolt = <5150000>;
322 }; 323 };
323 324
324 snvs_reg: vsnvs { 325 snvs_reg: vsnvs {
325 regulator-min-microvolt = <1000000>; 326 regulator-min-microvolt = <1000000>;
326 regulator-max-microvolt = <3000000>; 327 regulator-max-microvolt = <3000000>;
327 regulator-always-on; 328 regulator-always-on;
328 }; 329 };
329 330
330 vref_reg: vrefddr { 331 vref_reg: vrefddr {
331 regulator-always-on; 332 regulator-always-on;
332 }; 333 };
333 334
334 vgen1_reg: vgen1 { 335 vgen1_reg: vgen1 {
335 regulator-min-microvolt = <800000>; 336 regulator-min-microvolt = <800000>;
336 regulator-max-microvolt = <1550000>; 337 regulator-max-microvolt = <1550000>;
337 }; 338 };
338 339
339 vgen2_reg: vgen2 { 340 vgen2_reg: vgen2 {
340 regulator-min-microvolt = <800000>; 341 regulator-min-microvolt = <800000>;
341 regulator-max-microvolt = <1550000>; 342 regulator-max-microvolt = <1550000>;
342 regulator-always-on; 343 regulator-always-on;
343 }; 344 };
344 345
345 vgen3_reg: vgen3 { 346 vgen3_reg: vgen3 {
346 regulator-min-microvolt = <1800000>; 347 regulator-min-microvolt = <1800000>;
347 regulator-max-microvolt = <3300000>; 348 regulator-max-microvolt = <3300000>;
348 regulator-always-on; 349 regulator-always-on;
349 }; 350 };
350 351
351 vgen4_reg: vgen4 { 352 vgen4_reg: vgen4 {
352 regulator-min-microvolt = <1800000>; 353 regulator-min-microvolt = <1800000>;
353 regulator-max-microvolt = <3300000>; 354 regulator-max-microvolt = <3300000>;
354 regulator-always-on; 355 regulator-always-on;
355 }; 356 };
356 357
357 vgen5_reg: vgen5 { 358 vgen5_reg: vgen5 {
358 regulator-min-microvolt = <1800000>; 359 regulator-min-microvolt = <1800000>;
359 regulator-max-microvolt = <3300000>; 360 regulator-max-microvolt = <3300000>;
360 regulator-always-on; 361 regulator-always-on;
361 }; 362 };
362 363
363 vgen6_reg: vgen6 { 364 vgen6_reg: vgen6 {
364 regulator-min-microvolt = <1800000>; 365 regulator-min-microvolt = <1800000>;
365 regulator-max-microvolt = <3300000>; 366 regulator-max-microvolt = <3300000>;
366 }; 367 };
367 }; 368 };
368 }; 369 };
369 }; 370 };
370 371
371 &i2c2 { 372 &i2c2 {
372 clock-frequency = <100000>; 373 clock-frequency = <100000>;
373 pinctrl-names = "default", "gpio"; 374 pinctrl-names = "default", "gpio";
374 pinctrl-0 = <&pinctrl_i2c2>; 375 pinctrl-0 = <&pinctrl_i2c2>;
375 pinctrl-1 = <&pinctrl_i2c2_gpio>; 376 pinctrl-1 = <&pinctrl_i2c2_gpio>;
376 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; 377 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
377 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; 378 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
378 status = "disabled"; 379 status = "disabled";
379 }; 380 };
380 381
381 &pwm2 { 382 &pwm2 {
382 pinctrl-names = "default"; 383 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_pwm2>; 384 pinctrl-0 = <&pinctrl_pwm2>;
384 status = "okay"; 385 status = "okay";
385 }; 386 };
386 387
387 &uart1 { /* console */ 388 &uart1 { /* console */
388 pinctrl-names = "default"; 389 pinctrl-names = "default";
389 pinctrl-0 = <&pinctrl_uart1>; 390 pinctrl-0 = <&pinctrl_uart1>;
390 assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; 391 assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>;
391 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; 392 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
392 status = "okay"; 393 status = "okay";
393 }; 394 };
394 395
395 &lcdif { 396 &lcdif {
396 status = "okay"; 397 status = "okay";
397 disp-dev = "mipi_dsi_northwest"; 398 disp-dev = "mipi_dsi_northwest";
398 display = <&display0>; 399 display = <&display0>;
399 400
400 display0: display@0 { 401 display0: display@0 {
401 bits-per-pixel = <24>; 402 bits-per-pixel = <24>;
402 bus-width = <24>; 403 bus-width = <24>;
403 404
404 display-timings { 405 display-timings {
405 native-mode = <&timing0>; 406 native-mode = <&timing0>;
406 timing0: timing0 { 407 timing0: timing0 {
407 clock-frequency = <9200000>; 408 clock-frequency = <9200000>;
408 hactive = <480>; 409 hactive = <480>;
409 vactive = <272>; 410 vactive = <272>;
410 hfront-porch = <8>; 411 hfront-porch = <8>;
411 hback-porch = <4>; 412 hback-porch = <4>;
412 hsync-len = <41>; 413 hsync-len = <41>;
413 vback-porch = <2>; 414 vback-porch = <2>;
414 vfront-porch = <4>; 415 vfront-porch = <4>;
415 vsync-len = <10>; 416 vsync-len = <10>;
416 417
417 hsync-active = <0>; 418 hsync-active = <0>;
418 vsync-active = <0>; 419 vsync-active = <0>;
419 de-active = <1>; 420 de-active = <1>;
420 pixelclk-active = <0>; 421 pixelclk-active = <0>;
421 }; 422 };
422 }; 423 };
423 }; 424 };
424 }; 425 };
425 426
426 &qspi { 427 &qspi {
427 pinctrl-names = "default"; 428 pinctrl-names = "default";
428 pinctrl-0 = <&pinctrl_qspi>; 429 pinctrl-0 = <&pinctrl_qspi>;
429 status = "okay"; 430 status = "okay";
430 431
431 flash0: n25q256a@0 { 432 flash0: n25q256a@0 {
432 reg = <0>; 433 reg = <0>;
433 #address-cells = <1>; 434 #address-cells = <1>;
434 #size-cells = <1>; 435 #size-cells = <1>;
435 compatible = "spi-flash"; 436 compatible = "spi-flash";
436 spi-max-frequency = <29000000>; 437 spi-max-frequency = <29000000>;
437 spi-nor,ddr-quad-read-dummy = <6>; 438 spi-nor,ddr-quad-read-dummy = <6>;
438 }; 439 };
439 }; 440 };
440 441
441 &usdhc1 { 442 &usdhc1 {
442 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 443 pinctrl-names = "default", "state_100mhz", "state_200mhz";
443 pinctrl-0 = <&pinctrl_usdhc1>; 444 pinctrl-0 = <&pinctrl_usdhc1>;
444 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 445 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
445 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 446 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
446 bus-width = <8>; 447 bus-width = <8>;
447 non-removable; 448 non-removable;
448 status = "okay"; 449 status = "okay";
449 }; 450 };
450 451
451 &usdhc2 { 452 &usdhc2 {
452 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 453 pinctrl-names = "default", "state_100mhz", "state_200mhz";
453 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 454 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
454 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 455 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
455 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 456 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
456 bus-width = <4>; 457 bus-width = <4>;
457 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 458 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
458 vmmc-supply = <&reg_usdhc2_vmmc>; 459 vmmc-supply = <&reg_usdhc2_vmmc>;
459 status = "okay"; 460 status = "okay";
460 }; 461 };
461 462
462 &usb3_phy0 { 463 &usb3_phy0 {
463 status = "okay"; 464 status = "okay";
464 }; 465 };
465 466
466 &usb3_0 { 467 &usb3_0 {
467 status = "okay"; 468 status = "okay";
468 }; 469 };
469 470
470 &usb_dwc3_0 { 471 &usb_dwc3_0 {
471 status = "okay"; 472 status = "okay";
472 dr_mode = "peripheral"; 473 dr_mode = "peripheral";
473 }; 474 };
474 475
475 &usb3_phy1 { 476 &usb3_phy1 {
476 status = "okay"; 477 status = "okay";
477 }; 478 };
478 479
479 &usb3_1 { 480 &usb3_1 {
480 status = "okay"; 481 status = "okay";
481 }; 482 };
482 483
483 &usb_dwc3_1 { 484 &usb_dwc3_1 {
484 status = "okay"; 485 status = "okay";
485 dr_mode = "host"; 486 dr_mode = "host";
486 }; 487 };
487 488
488 &wdog1 { 489 &wdog1 {
489 pinctrl-names = "default"; 490 pinctrl-names = "default";
490 pinctrl-0 = <&pinctrl_wdog>; 491 pinctrl-0 = <&pinctrl_wdog>;
491 fsl,ext-reset-output; 492 fsl,ext-reset-output;
492 status = "okay"; 493 status = "okay";
493 }; 494 };
494 495
arch/arm/mach-imx/imx8m/clock_imx8mq.c
Diff comments   View file @ 369776e
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 * 4 *
5 * Peng Fan <peng.fan@nxp.com> 5 * Peng Fan <peng.fan@nxp.com>
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <asm/arch/clock.h> 9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/imx-regs.h>
11 #include <asm/io.h> 11 #include <asm/io.h>
12 #include <asm/arch/sys_proto.h> 12 #include <asm/arch/sys_proto.h>
13 #include <errno.h> 13 #include <errno.h>
14 #include <linux/iopoll.h> 14 #include <linux/iopoll.h>
15 15
16 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; 16 static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
17 17
18 static u32 decode_frac_pll(enum clk_root_src frac_pll) 18 static u32 decode_frac_pll(enum clk_root_src frac_pll)
19 { 19 {
20 u32 pll_cfg0, pll_cfg1, pllout; 20 u32 pll_cfg0, pll_cfg1, pllout;
21 u32 pll_refclk_sel, pll_refclk; 21 u32 pll_refclk_sel, pll_refclk;
22 u32 divr_val, divq_val, divf_val, divff, divfi; 22 u32 divr_val, divq_val, divf_val, divff, divfi;
23 u32 pllout_div_shift, pllout_div_mask, pllout_div; 23 u32 pllout_div_shift, pllout_div_mask, pllout_div;
24 24
25 switch (frac_pll) { 25 switch (frac_pll) {
26 case ARM_PLL_CLK: 26 case ARM_PLL_CLK:
27 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0); 27 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0);
28 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1); 28 pll_cfg1 = readl(&ana_pll->arm_pll_cfg1);
29 pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT; 29 pllout_div_shift = HW_FRAC_ARM_PLL_DIV_SHIFT;
30 pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK; 30 pllout_div_mask = HW_FRAC_ARM_PLL_DIV_MASK;
31 break; 31 break;
32 default: 32 default:
33 printf("Frac PLL %d not supporte\n", frac_pll); 33 printf("Frac PLL %d not supporte\n", frac_pll);
34 return 0; 34 return 0;
35 } 35 }
36 36
37 pllout_div = readl(&ana_pll->frac_pllout_div_cfg); 37 pllout_div = readl(&ana_pll->frac_pllout_div_cfg);
38 pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift; 38 pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
39 39
40 /* Power down */ 40 /* Power down */
41 if (pll_cfg0 & FRAC_PLL_PD_MASK) 41 if (pll_cfg0 & FRAC_PLL_PD_MASK)
42 return 0; 42 return 0;
43 43
44 /* output not enabled */ 44 /* output not enabled */
45 if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0) 45 if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0)
46 return 0; 46 return 0;
47 47
48 pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK; 48 pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK;
49 49
50 if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M) 50 if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_25M)
51 pll_refclk = 25000000u; 51 pll_refclk = 25000000u;
52 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M) 52 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_OSC_27M)
53 pll_refclk = 27000000u; 53 pll_refclk = 27000000u;
54 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M) 54 else if (pll_refclk_sel == FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M)
55 pll_refclk = 27000000u; 55 pll_refclk = 27000000u;
56 else 56 else
57 pll_refclk = 0; 57 pll_refclk = 0;
58 58
59 if (pll_cfg0 & FRAC_PLL_BYPASS_MASK) 59 if (pll_cfg0 & FRAC_PLL_BYPASS_MASK)
60 return pll_refclk; 60 return pll_refclk;
61 61
62 divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >> 62 divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >>
63 FRAC_PLL_REFCLK_DIV_VAL_SHIFT; 63 FRAC_PLL_REFCLK_DIV_VAL_SHIFT;
64 divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK; 64 divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK;
65 65
66 divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >> 66 divff = (pll_cfg1 & FRAC_PLL_FRAC_DIV_CTL_MASK) >>
67 FRAC_PLL_FRAC_DIV_CTL_SHIFT; 67 FRAC_PLL_FRAC_DIV_CTL_SHIFT;
68 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK; 68 divfi = pll_cfg1 & FRAC_PLL_INT_DIV_CTL_MASK;
69 69
70 divf_val = 1 + divfi + divff / (1 << 24); 70 divf_val = 1 + divfi + divff / (1 << 24);
71 71
72 pllout = pll_refclk / (divr_val + 1) * 8 * divf_val / 72 pllout = pll_refclk / (divr_val + 1) * 8 * divf_val /
73 ((divq_val + 1) * 2); 73 ((divq_val + 1) * 2);
74 74
75 return pllout / (pllout_div + 1); 75 return pllout / (pllout_div + 1);
76 } 76 }
77 77
78 static u32 decode_sscg_pll(enum clk_root_src sscg_pll) 78 static u32 decode_sscg_pll(enum clk_root_src sscg_pll)
79 { 79 {
80 u32 pll_cfg0, pll_cfg1, pll_cfg2; 80 u32 pll_cfg0, pll_cfg1, pll_cfg2;
81 u32 pll_refclk_sel, pll_refclk; 81 u32 pll_refclk_sel, pll_refclk;
82 u32 divr1, divr2, divf1, divf2, divq, div; 82 u32 divr1, divr2, divf1, divf2, divq, div;
83 u32 sse; 83 u32 sse;
84 u32 pll_clke; 84 u32 pll_clke;
85 u32 pllout_div_shift, pllout_div_mask, pllout_div; 85 u32 pllout_div_shift, pllout_div_mask, pllout_div;
86 u32 pllout; 86 u32 pllout;
87 87
88 switch (sscg_pll) { 88 switch (sscg_pll) {
89 case SYSTEM_PLL1_800M_CLK: 89 case SYSTEM_PLL1_800M_CLK:
90 case SYSTEM_PLL1_400M_CLK: 90 case SYSTEM_PLL1_400M_CLK:
91 case SYSTEM_PLL1_266M_CLK: 91 case SYSTEM_PLL1_266M_CLK:
92 case SYSTEM_PLL1_200M_CLK: 92 case SYSTEM_PLL1_200M_CLK:
93 case SYSTEM_PLL1_160M_CLK: 93 case SYSTEM_PLL1_160M_CLK:
94 case SYSTEM_PLL1_133M_CLK: 94 case SYSTEM_PLL1_133M_CLK:
95 case SYSTEM_PLL1_100M_CLK: 95 case SYSTEM_PLL1_100M_CLK:
96 case SYSTEM_PLL1_80M_CLK: 96 case SYSTEM_PLL1_80M_CLK:
97 case SYSTEM_PLL1_40M_CLK: 97 case SYSTEM_PLL1_40M_CLK:
98 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0); 98 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0);
99 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1); 99 pll_cfg1 = readl(&ana_pll->sys_pll1_cfg1);
100 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2); 100 pll_cfg2 = readl(&ana_pll->sys_pll1_cfg2);
101 pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT; 101 pllout_div_shift = HW_SSCG_SYSTEM_PLL1_DIV_SHIFT;
102 pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK; 102 pllout_div_mask = HW_SSCG_SYSTEM_PLL1_DIV_MASK;
103 break; 103 break;
104 case SYSTEM_PLL2_1000M_CLK: 104 case SYSTEM_PLL2_1000M_CLK:
105 case SYSTEM_PLL2_500M_CLK: 105 case SYSTEM_PLL2_500M_CLK:
106 case SYSTEM_PLL2_333M_CLK: 106 case SYSTEM_PLL2_333M_CLK:
107 case SYSTEM_PLL2_250M_CLK: 107 case SYSTEM_PLL2_250M_CLK:
108 case SYSTEM_PLL2_200M_CLK: 108 case SYSTEM_PLL2_200M_CLK:
109 case SYSTEM_PLL2_166M_CLK: 109 case SYSTEM_PLL2_166M_CLK:
110 case SYSTEM_PLL2_125M_CLK: 110 case SYSTEM_PLL2_125M_CLK:
111 case SYSTEM_PLL2_100M_CLK: 111 case SYSTEM_PLL2_100M_CLK:
112 case SYSTEM_PLL2_50M_CLK: 112 case SYSTEM_PLL2_50M_CLK:
113 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0); 113 pll_cfg0 = readl(&ana_pll->sys_pll2_cfg0);
114 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1); 114 pll_cfg1 = readl(&ana_pll->sys_pll2_cfg1);
115 pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2); 115 pll_cfg2 = readl(&ana_pll->sys_pll2_cfg2);
116 pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT; 116 pllout_div_shift = HW_SSCG_SYSTEM_PLL2_DIV_SHIFT;
117 pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK; 117 pllout_div_mask = HW_SSCG_SYSTEM_PLL2_DIV_MASK;
118 break; 118 break;
119 case SYSTEM_PLL3_CLK: 119 case SYSTEM_PLL3_CLK:
120 pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0); 120 pll_cfg0 = readl(&ana_pll->sys_pll3_cfg0);
121 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1); 121 pll_cfg1 = readl(&ana_pll->sys_pll3_cfg1);
122 pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2); 122 pll_cfg2 = readl(&ana_pll->sys_pll3_cfg2);
123 pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT; 123 pllout_div_shift = HW_SSCG_SYSTEM_PLL3_DIV_SHIFT;
124 pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK; 124 pllout_div_mask = HW_SSCG_SYSTEM_PLL3_DIV_MASK;
125 break; 125 break;
126 case DRAM_PLL1_CLK: 126 case DRAM_PLL1_CLK:
127 pll_cfg0 = readl(&ana_pll->dram_pll_cfg0); 127 pll_cfg0 = readl(&ana_pll->dram_pll_cfg0);
128 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1); 128 pll_cfg1 = readl(&ana_pll->dram_pll_cfg1);
129 pll_cfg2 = readl(&ana_pll->dram_pll_cfg2); 129 pll_cfg2 = readl(&ana_pll->dram_pll_cfg2);
130 pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT; 130 pllout_div_shift = HW_SSCG_DRAM_PLL_DIV_SHIFT;
131 pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK; 131 pllout_div_mask = HW_SSCG_DRAM_PLL_DIV_MASK;
132 break; 132 break;
133 default: 133 default:
134 printf("sscg pll %d not supporte\n", sscg_pll); 134 printf("sscg pll %d not supporte\n", sscg_pll);
135 return 0; 135 return 0;
136 } 136 }
137 137
138 switch (sscg_pll) { 138 switch (sscg_pll) {
139 case DRAM_PLL1_CLK: 139 case DRAM_PLL1_CLK:
140 pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK; 140 pll_clke = SSCG_PLL_DRAM_PLL_CLKE_MASK;
141 div = 1; 141 div = 1;
142 break; 142 break;
143 case SYSTEM_PLL3_CLK: 143 case SYSTEM_PLL3_CLK:
144 pll_clke = SSCG_PLL_PLL3_CLKE_MASK; 144 pll_clke = SSCG_PLL_PLL3_CLKE_MASK;
145 div = 1; 145 div = 1;
146 break; 146 break;
147 case SYSTEM_PLL2_1000M_CLK: 147 case SYSTEM_PLL2_1000M_CLK:
148 case SYSTEM_PLL1_800M_CLK: 148 case SYSTEM_PLL1_800M_CLK:
149 pll_clke = SSCG_PLL_CLKE_MASK; 149 pll_clke = SSCG_PLL_CLKE_MASK;
150 div = 1; 150 div = 1;
151 break; 151 break;
152 case SYSTEM_PLL2_500M_CLK: 152 case SYSTEM_PLL2_500M_CLK:
153 case SYSTEM_PLL1_400M_CLK: 153 case SYSTEM_PLL1_400M_CLK:
154 pll_clke = SSCG_PLL_DIV2_CLKE_MASK; 154 pll_clke = SSCG_PLL_DIV2_CLKE_MASK;
155 div = 2; 155 div = 2;
156 break; 156 break;
157 case SYSTEM_PLL2_333M_CLK: 157 case SYSTEM_PLL2_333M_CLK:
158 case SYSTEM_PLL1_266M_CLK: 158 case SYSTEM_PLL1_266M_CLK:
159 pll_clke = SSCG_PLL_DIV3_CLKE_MASK; 159 pll_clke = SSCG_PLL_DIV3_CLKE_MASK;
160 div = 3; 160 div = 3;
161 break; 161 break;
162 case SYSTEM_PLL2_250M_CLK: 162 case SYSTEM_PLL2_250M_CLK:
163 case SYSTEM_PLL1_200M_CLK: 163 case SYSTEM_PLL1_200M_CLK:
164 pll_clke = SSCG_PLL_DIV4_CLKE_MASK; 164 pll_clke = SSCG_PLL_DIV4_CLKE_MASK;
165 div = 4; 165 div = 4;
166 break; 166 break;
167 case SYSTEM_PLL2_200M_CLK: 167 case SYSTEM_PLL2_200M_CLK:
168 case SYSTEM_PLL1_160M_CLK: 168 case SYSTEM_PLL1_160M_CLK:
169 pll_clke = SSCG_PLL_DIV5_CLKE_MASK; 169 pll_clke = SSCG_PLL_DIV5_CLKE_MASK;
170 div = 5; 170 div = 5;
171 break; 171 break;
172 case SYSTEM_PLL2_166M_CLK: 172 case SYSTEM_PLL2_166M_CLK:
173 case SYSTEM_PLL1_133M_CLK: 173 case SYSTEM_PLL1_133M_CLK:
174 pll_clke = SSCG_PLL_DIV6_CLKE_MASK; 174 pll_clke = SSCG_PLL_DIV6_CLKE_MASK;
175 div = 6; 175 div = 6;
176 break; 176 break;
177 case SYSTEM_PLL2_125M_CLK: 177 case SYSTEM_PLL2_125M_CLK:
178 case SYSTEM_PLL1_100M_CLK: 178 case SYSTEM_PLL1_100M_CLK:
179 pll_clke = SSCG_PLL_DIV8_CLKE_MASK; 179 pll_clke = SSCG_PLL_DIV8_CLKE_MASK;
180 div = 8; 180 div = 8;
181 break; 181 break;
182 case SYSTEM_PLL2_100M_CLK: 182 case SYSTEM_PLL2_100M_CLK:
183 case SYSTEM_PLL1_80M_CLK: 183 case SYSTEM_PLL1_80M_CLK:
184 pll_clke = SSCG_PLL_DIV10_CLKE_MASK; 184 pll_clke = SSCG_PLL_DIV10_CLKE_MASK;
185 div = 10; 185 div = 10;
186 break; 186 break;
187 case SYSTEM_PLL2_50M_CLK: 187 case SYSTEM_PLL2_50M_CLK:
188 case SYSTEM_PLL1_40M_CLK: 188 case SYSTEM_PLL1_40M_CLK:
189 pll_clke = SSCG_PLL_DIV20_CLKE_MASK; 189 pll_clke = SSCG_PLL_DIV20_CLKE_MASK;
190 div = 20; 190 div = 20;
191 break; 191 break;
192 default: 192 default:
193 printf("sscg pll %d not supporte\n", sscg_pll); 193 printf("sscg pll %d not supporte\n", sscg_pll);
194 return 0; 194 return 0;
195 } 195 }
196 196
197 /* Power down */ 197 /* Power down */
198 if (pll_cfg0 & SSCG_PLL_PD_MASK) 198 if (pll_cfg0 & SSCG_PLL_PD_MASK)
199 return 0; 199 return 0;
200 200
201 /* output not enabled */ 201 /* output not enabled */
202 if ((pll_cfg0 & pll_clke) == 0) 202 if ((pll_cfg0 & pll_clke) == 0)
203 return 0; 203 return 0;
204 204
205 pllout_div = readl(&ana_pll->sscg_pllout_div_cfg); 205 pllout_div = readl(&ana_pll->sscg_pllout_div_cfg);
206 pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift; 206 pllout_div = (pllout_div & pllout_div_mask) >> pllout_div_shift;
207 207
208 pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK; 208 pll_refclk_sel = pll_cfg0 & SSCG_PLL_REFCLK_SEL_MASK;
209 209
210 if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M) 210 if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_25M)
211 pll_refclk = 25000000u; 211 pll_refclk = 25000000u;
212 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M) 212 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_OSC_27M)
213 pll_refclk = 27000000u; 213 pll_refclk = 27000000u;
214 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M) 214 else if (pll_refclk_sel == SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M)
215 pll_refclk = 27000000u; 215 pll_refclk = 27000000u;
216 else 216 else
217 pll_refclk = 0; 217 pll_refclk = 0;
218 218
219 /* We assume bypass1/2 are the same value */ 219 /* We assume bypass1/2 are the same value */
220 if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) || 220 if ((pll_cfg0 & SSCG_PLL_BYPASS1_MASK) ||
221 (pll_cfg0 & SSCG_PLL_BYPASS2_MASK)) 221 (pll_cfg0 & SSCG_PLL_BYPASS2_MASK))
222 return pll_refclk; 222 return pll_refclk;
223 223
224 divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >> 224 divr1 = (pll_cfg2 & SSCG_PLL_REF_DIVR1_MASK) >>
225 SSCG_PLL_REF_DIVR1_SHIFT; 225 SSCG_PLL_REF_DIVR1_SHIFT;
226 divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >> 226 divr2 = (pll_cfg2 & SSCG_PLL_REF_DIVR2_MASK) >>
227 SSCG_PLL_REF_DIVR2_SHIFT; 227 SSCG_PLL_REF_DIVR2_SHIFT;
228 divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >> 228 divf1 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F1_MASK) >>
229 SSCG_PLL_FEEDBACK_DIV_F1_SHIFT; 229 SSCG_PLL_FEEDBACK_DIV_F1_SHIFT;
230 divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >> 230 divf2 = (pll_cfg2 & SSCG_PLL_FEEDBACK_DIV_F2_MASK) >>
231 SSCG_PLL_FEEDBACK_DIV_F2_SHIFT; 231 SSCG_PLL_FEEDBACK_DIV_F2_SHIFT;
232 divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >> 232 divq = (pll_cfg2 & SSCG_PLL_OUTPUT_DIV_VAL_MASK) >>
233 SSCG_PLL_OUTPUT_DIV_VAL_SHIFT; 233 SSCG_PLL_OUTPUT_DIV_VAL_SHIFT;
234 sse = pll_cfg1 & SSCG_PLL_SSE_MASK; 234 sse = pll_cfg1 & SSCG_PLL_SSE_MASK;
235 235
236 if (sse) 236 if (sse)
237 sse = 8; 237 sse = 8;
238 else 238 else
239 sse = 2; 239 sse = 2;
240 240
241 pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) / 241 pllout = pll_refclk / (divr1 + 1) * sse * (divf1 + 1) /
242 (divr2 + 1) * (divf2 + 1) / (divq + 1); 242 (divr2 + 1) * (divf2 + 1) / (divq + 1);
243 243
244 return pllout / (pllout_div + 1) / div; 244 return pllout / (pllout_div + 1) / div;
245 } 245 }
246 246
247 static u32 get_root_src_clk(enum clk_root_src root_src) 247 static u32 get_root_src_clk(enum clk_root_src root_src)
248 { 248 {
249 switch (root_src) { 249 switch (root_src) {
250 case OSC_25M_CLK: 250 case OSC_25M_CLK:
251 return 25000000; 251 return 25000000;
252 case OSC_27M_CLK: 252 case OSC_27M_CLK:
253 return 27000000; 253 return 27000000;
254 case OSC_32K_CLK: 254 case OSC_32K_CLK:
255 return 32768; 255 return 32768;
256 case ARM_PLL_CLK: 256 case ARM_PLL_CLK:
257 return decode_frac_pll(root_src); 257 return decode_frac_pll(root_src);
258 case SYSTEM_PLL1_800M_CLK: 258 case SYSTEM_PLL1_800M_CLK:
259 case SYSTEM_PLL1_400M_CLK: 259 case SYSTEM_PLL1_400M_CLK:
260 case SYSTEM_PLL1_266M_CLK: 260 case SYSTEM_PLL1_266M_CLK:
261 case SYSTEM_PLL1_200M_CLK: 261 case SYSTEM_PLL1_200M_CLK:
262 case SYSTEM_PLL1_160M_CLK: 262 case SYSTEM_PLL1_160M_CLK:
263 case SYSTEM_PLL1_133M_CLK: 263 case SYSTEM_PLL1_133M_CLK:
264 case SYSTEM_PLL1_100M_CLK: 264 case SYSTEM_PLL1_100M_CLK:
265 case SYSTEM_PLL1_80M_CLK: 265 case SYSTEM_PLL1_80M_CLK:
266 case SYSTEM_PLL1_40M_CLK: 266 case SYSTEM_PLL1_40M_CLK:
267 case SYSTEM_PLL2_1000M_CLK: 267 case SYSTEM_PLL2_1000M_CLK:
268 case SYSTEM_PLL2_500M_CLK: 268 case SYSTEM_PLL2_500M_CLK:
269 case SYSTEM_PLL2_333M_CLK: 269 case SYSTEM_PLL2_333M_CLK:
270 case SYSTEM_PLL2_250M_CLK: 270 case SYSTEM_PLL2_250M_CLK:
271 case SYSTEM_PLL2_200M_CLK: 271 case SYSTEM_PLL2_200M_CLK:
272 case SYSTEM_PLL2_166M_CLK: 272 case SYSTEM_PLL2_166M_CLK:
273 case SYSTEM_PLL2_125M_CLK: 273 case SYSTEM_PLL2_125M_CLK:
274 case SYSTEM_PLL2_100M_CLK: 274 case SYSTEM_PLL2_100M_CLK:
275 case SYSTEM_PLL2_50M_CLK: 275 case SYSTEM_PLL2_50M_CLK:
276 case SYSTEM_PLL3_CLK: 276 case SYSTEM_PLL3_CLK:
277 return decode_sscg_pll(root_src); 277 return decode_sscg_pll(root_src);
278 default: 278 default:
279 return 0; 279 return 0;
280 } 280 }
281 281
282 return 0; 282 return 0;
283 } 283 }
284 284
285 static u32 get_root_clk(enum clk_root_index clock_id) 285 static u32 get_root_clk(enum clk_root_index clock_id)
286 { 286 {
287 enum clk_root_src root_src; 287 enum clk_root_src root_src;
288 u32 post_podf, pre_podf, root_src_clk; 288 u32 post_podf, pre_podf, root_src_clk;
289 289
290 if (clock_root_enabled(clock_id) <= 0) 290 if (clock_root_enabled(clock_id) <= 0)
291 return 0; 291 return 0;
292 292
293 if (clock_get_prediv(clock_id, &pre_podf) < 0) 293 if (clock_get_prediv(clock_id, &pre_podf) < 0)
294 return 0; 294 return 0;
295 295
296 if (clock_get_postdiv(clock_id, &post_podf) < 0) 296 if (clock_get_postdiv(clock_id, &post_podf) < 0)
297 return 0; 297 return 0;
298 298
299 if (clock_get_src(clock_id, &root_src) < 0) 299 if (clock_get_src(clock_id, &root_src) < 0)
300 return 0; 300 return 0;
301 301
302 root_src_clk = get_root_src_clk(root_src); 302 root_src_clk = get_root_src_clk(root_src);
303 303
304 return root_src_clk / (post_podf + 1) / (pre_podf + 1); 304 return root_src_clk / (post_podf + 1) / (pre_podf + 1);
305 } 305 }
306 306
307 #ifdef CONFIG_SECURE_BOOT 307 #ifdef CONFIG_SECURE_BOOT
308 void hab_caam_clock_enable(unsigned char enable) 308 void hab_caam_clock_enable(unsigned char enable)
309 { 309 {
310 /* The CAAM clock is always on for iMX8M */ 310 /* The CAAM clock is always on for iMX8M */
311 } 311 }
312 #endif 312 #endif
313 313
314 #ifdef CONFIG_MXC_OCOTP 314 #ifdef CONFIG_MXC_OCOTP
315 void enable_ocotp_clk(unsigned char enable) 315 void enable_ocotp_clk(unsigned char enable)
316 { 316 {
317 clock_enable(CCGR_OCOTP, !!enable); 317 clock_enable(CCGR_OCOTP, !!enable);
318 } 318 }
319 #endif 319 #endif
320 320
321 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num) 321 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
322 { 322 {
323 /* 0 - 3 is valid i2c num */ 323 /* 0 - 3 is valid i2c num */
324 if (i2c_num > 3) 324 if (i2c_num > 3)
325 return -EINVAL; 325 return -EINVAL;
326 326
327 clock_enable(CCGR_I2C1 + i2c_num, !!enable); 327 clock_enable(CCGR_I2C1 + i2c_num, !!enable);
328 328
329 return 0; 329 return 0;
330 } 330 }
331 331
332 unsigned int mxc_get_clock(enum mxc_clock clk) 332 unsigned int mxc_get_clock(enum mxc_clock clk)
333 { 333 {
334 u32 val; 334 u32 val;
335 335
336 switch (clk) { 336 switch (clk) {
337 case MXC_ARM_CLK: 337 case MXC_ARM_CLK:
338 return get_root_clk(ARM_A53_CLK_ROOT); 338 return get_root_clk(ARM_A53_CLK_ROOT);
339 case MXC_IPG_CLK: 339 case MXC_IPG_CLK:
340 clock_get_target_val(IPG_CLK_ROOT, &val); 340 clock_get_target_val(IPG_CLK_ROOT, &val);
341 val = val & 0x3; 341 val = val & 0x3;
342 return get_root_clk(AHB_CLK_ROOT) / (val + 1); 342 return get_root_clk(AHB_CLK_ROOT) / (val + 1);
343 case MXC_CSPI_CLK: 343 case MXC_CSPI_CLK:
344 return get_root_clk(ECSPI1_CLK_ROOT); 344 return get_root_clk(ECSPI1_CLK_ROOT);
345 case MXC_ESDHC_CLK: 345 case MXC_ESDHC_CLK:
346 return get_root_clk(USDHC1_CLK_ROOT); 346 return get_root_clk(USDHC1_CLK_ROOT);
347 case MXC_ESDHC2_CLK: 347 case MXC_ESDHC2_CLK:
348 return get_root_clk(USDHC2_CLK_ROOT); 348 return get_root_clk(USDHC2_CLK_ROOT);
349 case MXC_I2C_CLK: 349 case MXC_I2C_CLK:
350 return get_root_clk(I2C1_CLK_ROOT); 350 return get_root_clk(I2C1_CLK_ROOT);
351 case MXC_UART_CLK: 351 case MXC_UART_CLK:
352 return get_root_clk(UART1_CLK_ROOT); 352 return get_root_clk(UART1_CLK_ROOT);
353 case MXC_QSPI_CLK: 353 case MXC_QSPI_CLK:
354 return get_root_clk(QSPI_CLK_ROOT); 354 return get_root_clk(QSPI_CLK_ROOT);
355 default: 355 default:
356 printf("Unsupported mxc_clock %d\n", clk); 356 printf("Unsupported mxc_clock %d\n", clk);
357 break; 357 break;
358 } 358 }
359 359
360 return 0; 360 return 0;
361 } 361 }
362 362
363 u32 imx_get_uartclk(void) 363 u32 imx_get_uartclk(void)
364 { 364 {
365 return mxc_get_clock(MXC_UART_CLK); 365 return mxc_get_clock(MXC_UART_CLK);
366 } 366 }
367 367
368 void mxs_set_lcdclk(u32 base_addr, u32 freq) 368 void mxs_set_lcdclk(u32 base_addr, u32 freq)
369 { 369 {
370 /* 370 /*
371 * LCDIF_PIXEL_CLK: select 800MHz root clock, 371 * LCDIF_PIXEL_CLK: select 800MHz root clock,
372 * select pre divider 8, output is 100 MHz 372 * select pre divider 8, output is 100 MHz
373 */ 373 */
374 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON | 374 clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON |
375 CLK_ROOT_SOURCE_SEL(4) | 375 CLK_ROOT_SOURCE_SEL(4) |
376 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8)); 376 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV8));
377 } 377 }
378 378
379 void init_wdog_clk(void) 379 void init_wdog_clk(void)
380 { 380 {
381 clock_enable(CCGR_WDOG1, 0); 381 clock_enable(CCGR_WDOG1, 0);
382 clock_enable(CCGR_WDOG2, 0); 382 clock_enable(CCGR_WDOG2, 0);
383 clock_enable(CCGR_WDOG3, 0); 383 clock_enable(CCGR_WDOG3, 0);
384 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | 384 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
385 CLK_ROOT_SOURCE_SEL(0)); 385 CLK_ROOT_SOURCE_SEL(0));
386 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | 386 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
387 CLK_ROOT_SOURCE_SEL(0)); 387 CLK_ROOT_SOURCE_SEL(0));
388 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON | 388 clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
389 CLK_ROOT_SOURCE_SEL(0)); 389 CLK_ROOT_SOURCE_SEL(0));
390 clock_enable(CCGR_WDOG1, 1); 390 clock_enable(CCGR_WDOG1, 1);
391 clock_enable(CCGR_WDOG2, 1); 391 clock_enable(CCGR_WDOG2, 1);
392 clock_enable(CCGR_WDOG3, 1); 392 clock_enable(CCGR_WDOG3, 1);
393 } 393 }
394 394
395 void init_usb_clk(void) 395 void init_usb_clk(void)
396 { 396 {
397 if (!is_usb_boot()) { 397 if (!is_usb_boot()) {
398 clock_enable(CCGR_USB_CTRL1, 0); 398 clock_enable(CCGR_USB_CTRL1, 0);
399 clock_enable(CCGR_USB_CTRL2, 0); 399 clock_enable(CCGR_USB_CTRL2, 0);
400 clock_enable(CCGR_USB_PHY1, 0); 400 clock_enable(CCGR_USB_PHY1, 0);
401 clock_enable(CCGR_USB_PHY2, 0); 401 clock_enable(CCGR_USB_PHY2, 0);
402 /* 500MHz */ 402 /* 500MHz */
403 clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON | 403 clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON |
404 CLK_ROOT_SOURCE_SEL(1)); 404 CLK_ROOT_SOURCE_SEL(1));
405 /* 100MHz */ 405 /* 100MHz */
406 clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON | 406 clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON |
407 CLK_ROOT_SOURCE_SEL(1)); 407 CLK_ROOT_SOURCE_SEL(1));
408 /* 100MHz */ 408 /* 100MHz */
409 clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON | 409 clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON |
410 CLK_ROOT_SOURCE_SEL(1)); 410 CLK_ROOT_SOURCE_SEL(1));
411 clock_enable(CCGR_USB_CTRL1, 1); 411 clock_enable(CCGR_USB_CTRL1, 1);
412 clock_enable(CCGR_USB_CTRL2, 1); 412 clock_enable(CCGR_USB_CTRL2, 1);
413 clock_enable(CCGR_USB_PHY1, 1); 413 clock_enable(CCGR_USB_PHY1, 1);
414 clock_enable(CCGR_USB_PHY2, 1); 414 clock_enable(CCGR_USB_PHY2, 1);
415 } 415 }
416 } 416 }
417 417
418 void init_nand_clk(void) 418 void init_nand_clk(void)
419 { 419 {
420 /* 420 /*
421 * set rawnand root 421 * set rawnand root
422 * sys pll1 400M 422 * sys pll1 400M
423 */ 423 */
424 clock_enable(CCGR_RAWNAND, 0); 424 clock_enable(CCGR_RAWNAND, 0);
425 clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON | 425 clock_set_target_val(NAND_CLK_ROOT, CLK_ROOT_ON |
426 CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */ 426 CLK_ROOT_SOURCE_SEL(3) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4)); /* 100M */
427 clock_enable(CCGR_RAWNAND, 1); 427 clock_enable(CCGR_RAWNAND, 1);
428 } 428 }
429 429
430 void init_uart_clk(u32 index) 430 void init_uart_clk(u32 index)
431 { 431 {
432 /* Set uart clock root 25M OSC */ 432 /* Set uart clock root 25M OSC */
433 switch (index) { 433 switch (index) {
434 case 0: 434 case 0:
435 clock_enable(CCGR_UART1, 0); 435 clock_enable(CCGR_UART1, 0);
436 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON | 436 clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
437 CLK_ROOT_SOURCE_SEL(0)); 437 CLK_ROOT_SOURCE_SEL(0));
438 clock_enable(CCGR_UART1, 1); 438 clock_enable(CCGR_UART1, 1);
439 return; 439 return;
440 case 1: 440 case 1:
441 clock_enable(CCGR_UART2, 0); 441 clock_enable(CCGR_UART2, 0);
442 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON | 442 clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
443 CLK_ROOT_SOURCE_SEL(0)); 443 CLK_ROOT_SOURCE_SEL(0));
444 clock_enable(CCGR_UART2, 1); 444 clock_enable(CCGR_UART2, 1);
445 return; 445 return;
446 case 2: 446 case 2:
447 clock_enable(CCGR_UART3, 0); 447 clock_enable(CCGR_UART3, 0);
448 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON | 448 clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
449 CLK_ROOT_SOURCE_SEL(0)); 449 CLK_ROOT_SOURCE_SEL(0));
450 clock_enable(CCGR_UART3, 1); 450 clock_enable(CCGR_UART3, 1);
451 return; 451 return;
452 case 3: 452 case 3:
453 clock_enable(CCGR_UART4, 0); 453 clock_enable(CCGR_UART4, 0);
454 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON | 454 clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
455 CLK_ROOT_SOURCE_SEL(0)); 455 CLK_ROOT_SOURCE_SEL(0));
456 clock_enable(CCGR_UART4, 1); 456 clock_enable(CCGR_UART4, 1);
457 return; 457 return;
458 default: 458 default:
459 printf("Invalid uart index\n"); 459 printf("Invalid uart index\n");
460 return; 460 return;
461 } 461 }
462 } 462 }
463 463
464 void init_clk_usdhc(u32 index) 464 void init_clk_usdhc(u32 index)
465 { 465 {
466 /* 466 /*
467 * set usdhc clock root 467 * set usdhc clock root
468 * sys pll1 400M 468 * sys pll1 400M
469 */ 469 */
470 switch (index) { 470 switch (index) {
471 case 0: 471 case 0:
472 clock_enable(CCGR_USDHC1, 0); 472 clock_enable(CCGR_USDHC1, 0);
473 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | 473 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
474 CLK_ROOT_SOURCE_SEL(1) | 474 CLK_ROOT_SOURCE_SEL(1));
475 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
476 clock_enable(CCGR_USDHC1, 1); 475 clock_enable(CCGR_USDHC1, 1);
477 return; 476 return;
478 case 1: 477 case 1:
479 clock_enable(CCGR_USDHC2, 0); 478 clock_enable(CCGR_USDHC2, 0);
480 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | 479 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
481 CLK_ROOT_SOURCE_SEL(1) | 480 CLK_ROOT_SOURCE_SEL(1));
482 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
483 clock_enable(CCGR_USDHC2, 1); 481 clock_enable(CCGR_USDHC2, 1);
484 return; 482 return;
485 default: 483 default:
486 printf("Invalid usdhc index\n"); 484 printf("Invalid usdhc index\n");
487 return; 485 return;
488 } 486 }
489 } 487 }
490 488
491 int set_clk_qspi(void) 489 int set_clk_qspi(void)
492 { 490 {
493 /* 491 /*
494 * set qspi root 492 * set qspi root
495 * sys pll1 100M 493 * sys pll1 100M
496 */ 494 */
497 clock_enable(CCGR_QSPI, 0); 495 clock_enable(CCGR_QSPI, 0);
498 clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | 496 clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON |
499 CLK_ROOT_SOURCE_SEL(7)); 497 CLK_ROOT_SOURCE_SEL(7));
500 clock_enable(CCGR_QSPI, 1); 498 clock_enable(CCGR_QSPI, 1);
501 499
502 return 0; 500 return 0;
503 } 501 }
504 502
505 #ifdef CONFIG_FEC_MXC 503 #ifdef CONFIG_FEC_MXC
506 int set_clk_enet(enum enet_freq type) 504 int set_clk_enet(enum enet_freq type)
507 { 505 {
508 u32 target; 506 u32 target;
509 u32 enet1_ref; 507 u32 enet1_ref;
510 508
511 switch (type) { 509 switch (type) {
512 case ENET_125MHZ: 510 case ENET_125MHZ:
513 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; 511 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
514 break; 512 break;
515 case ENET_50MHZ: 513 case ENET_50MHZ:
516 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; 514 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
517 break; 515 break;
518 case ENET_25MHZ: 516 case ENET_25MHZ:
519 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; 517 enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
520 break; 518 break;
521 default: 519 default:
522 return -EINVAL; 520 return -EINVAL;
523 } 521 }
524 522
525 /* disable the clock first */ 523 /* disable the clock first */
526 clock_enable(CCGR_ENET1, 0); 524 clock_enable(CCGR_ENET1, 0);
527 clock_enable(CCGR_SIM_ENET, 0); 525 clock_enable(CCGR_SIM_ENET, 0);
528 526
529 /* set enet axi clock 266Mhz */ 527 /* set enet axi clock 266Mhz */
530 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | 528 target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
531 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 529 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
532 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 530 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
533 clock_set_target_val(ENET_AXI_CLK_ROOT, target); 531 clock_set_target_val(ENET_AXI_CLK_ROOT, target);
534 532
535 target = CLK_ROOT_ON | enet1_ref | 533 target = CLK_ROOT_ON | enet1_ref |
536 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 534 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
537 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); 535 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
538 clock_set_target_val(ENET_REF_CLK_ROOT, target); 536 clock_set_target_val(ENET_REF_CLK_ROOT, target);
539 537
540 target = CLK_ROOT_ON | 538 target = CLK_ROOT_ON |
541 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | 539 ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
542 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | 540 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
543 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); 541 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
544 clock_set_target_val(ENET_TIMER_CLK_ROOT, target); 542 clock_set_target_val(ENET_TIMER_CLK_ROOT, target);
545 543
546 /* enable clock */ 544 /* enable clock */
547 clock_enable(CCGR_SIM_ENET, 1); 545 clock_enable(CCGR_SIM_ENET, 1);
548 clock_enable(CCGR_ENET1, 1); 546 clock_enable(CCGR_ENET1, 1);
549 547
550 return 0; 548 return 0;
551 } 549 }
552 #endif 550 #endif
553 551
554 u32 imx_get_fecclk(void) 552 u32 imx_get_fecclk(void)
555 { 553 {
556 return get_root_clk(ENET_AXI_CLK_ROOT); 554 return get_root_clk(ENET_AXI_CLK_ROOT);
557 } 555 }
558 556
559 static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = { 557 static struct dram_bypass_clk_setting imx8mq_dram_bypass_tbl[] = {
560 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2, 558 DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
561 CLK_ROOT_PRE_DIV2), 559 CLK_ROOT_PRE_DIV2),
562 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2, 560 DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
563 CLK_ROOT_PRE_DIV2), 561 CLK_ROOT_PRE_DIV2),
564 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3, 562 DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
565 CLK_ROOT_PRE_DIV2), 563 CLK_ROOT_PRE_DIV2),
566 }; 564 };
567 565
568 void dram_enable_bypass(ulong clk_val) 566 void dram_enable_bypass(ulong clk_val)
569 { 567 {
570 int i; 568 int i;
571 struct dram_bypass_clk_setting *config; 569 struct dram_bypass_clk_setting *config;
572 570
573 for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) { 571 for (i = 0; i < ARRAY_SIZE(imx8mq_dram_bypass_tbl); i++) {
574 if (clk_val == imx8mq_dram_bypass_tbl[i].clk) 572 if (clk_val == imx8mq_dram_bypass_tbl[i].clk)
575 break; 573 break;
576 } 574 }
577 575
578 if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) { 576 if (i == ARRAY_SIZE(imx8mq_dram_bypass_tbl)) {
579 printf("No matched freq table %lu\n", clk_val); 577 printf("No matched freq table %lu\n", clk_val);
580 return; 578 return;
581 } 579 }
582 580
583 config = &imx8mq_dram_bypass_tbl[i]; 581 config = &imx8mq_dram_bypass_tbl[i];
584 582
585 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON | 583 clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
586 CLK_ROOT_SOURCE_SEL(config->alt_root_sel) | 584 CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
587 CLK_ROOT_PRE_DIV(config->alt_pre_div)); 585 CLK_ROOT_PRE_DIV(config->alt_pre_div));
588 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | 586 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
589 CLK_ROOT_SOURCE_SEL(config->apb_root_sel) | 587 CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
590 CLK_ROOT_PRE_DIV(config->apb_pre_div)); 588 CLK_ROOT_PRE_DIV(config->apb_pre_div));
591 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | 589 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
592 CLK_ROOT_SOURCE_SEL(1)); 590 CLK_ROOT_SOURCE_SEL(1));
593 } 591 }
594 592
595 void dram_disable_bypass(void) 593 void dram_disable_bypass(void)
596 { 594 {
597 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON | 595 clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
598 CLK_ROOT_SOURCE_SEL(0)); 596 CLK_ROOT_SOURCE_SEL(0));
599 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | 597 clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
600 CLK_ROOT_SOURCE_SEL(4) | 598 CLK_ROOT_SOURCE_SEL(4) |
601 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5)); 599 CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
602 } 600 }
603 601
604 #ifdef CONFIG_SPL_BUILD 602 #ifdef CONFIG_SPL_BUILD
605 void dram_pll_init(ulong pll_val) 603 void dram_pll_init(ulong pll_val)
606 { 604 {
607 u32 val; 605 u32 val;
608 void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0; 606 void __iomem *pll_control_reg = &ana_pll->dram_pll_cfg0;
609 void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2; 607 void __iomem *pll_cfg_reg2 = &ana_pll->dram_pll_cfg2;
610 608
611 /* Bypass */ 609 /* Bypass */
612 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK); 610 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
613 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK); 611 setbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
614 612
615 switch (pll_val) { 613 switch (pll_val) {
616 case MHZ(800): 614 case MHZ(800):
617 val = readl(pll_cfg_reg2); 615 val = readl(pll_cfg_reg2);
618 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | 616 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
619 SSCG_PLL_FEEDBACK_DIV_F2_MASK | 617 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
620 SSCG_PLL_FEEDBACK_DIV_F1_MASK | 618 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
621 SSCG_PLL_REF_DIVR2_MASK); 619 SSCG_PLL_REF_DIVR2_MASK);
622 val |= SSCG_PLL_OUTPUT_DIV_VAL(0); 620 val |= SSCG_PLL_OUTPUT_DIV_VAL(0);
623 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11); 621 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
624 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); 622 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
625 val |= SSCG_PLL_REF_DIVR2_VAL(29); 623 val |= SSCG_PLL_REF_DIVR2_VAL(29);
626 writel(val, pll_cfg_reg2); 624 writel(val, pll_cfg_reg2);
627 break; 625 break;
628 case MHZ(600): 626 case MHZ(600):
629 val = readl(pll_cfg_reg2); 627 val = readl(pll_cfg_reg2);
630 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | 628 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
631 SSCG_PLL_FEEDBACK_DIV_F2_MASK | 629 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
632 SSCG_PLL_FEEDBACK_DIV_F1_MASK | 630 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
633 SSCG_PLL_REF_DIVR2_MASK); 631 SSCG_PLL_REF_DIVR2_MASK);
634 val |= SSCG_PLL_OUTPUT_DIV_VAL(1); 632 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
635 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17); 633 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(17);
636 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); 634 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
637 val |= SSCG_PLL_REF_DIVR2_VAL(29); 635 val |= SSCG_PLL_REF_DIVR2_VAL(29);
638 writel(val, pll_cfg_reg2); 636 writel(val, pll_cfg_reg2);
639 break; 637 break;
640 case MHZ(400): 638 case MHZ(400):
641 val = readl(pll_cfg_reg2); 639 val = readl(pll_cfg_reg2);
642 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | 640 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
643 SSCG_PLL_FEEDBACK_DIV_F2_MASK | 641 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
644 SSCG_PLL_FEEDBACK_DIV_F1_MASK | 642 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
645 SSCG_PLL_REF_DIVR2_MASK); 643 SSCG_PLL_REF_DIVR2_MASK);
646 val |= SSCG_PLL_OUTPUT_DIV_VAL(1); 644 val |= SSCG_PLL_OUTPUT_DIV_VAL(1);
647 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11); 645 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(11);
648 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39); 646 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(39);
649 val |= SSCG_PLL_REF_DIVR2_VAL(29); 647 val |= SSCG_PLL_REF_DIVR2_VAL(29);
650 writel(val, pll_cfg_reg2); 648 writel(val, pll_cfg_reg2);
651 break; 649 break;
652 case MHZ(167): 650 case MHZ(167):
653 val = readl(pll_cfg_reg2); 651 val = readl(pll_cfg_reg2);
654 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK | 652 val &= ~(SSCG_PLL_OUTPUT_DIV_VAL_MASK |
655 SSCG_PLL_FEEDBACK_DIV_F2_MASK | 653 SSCG_PLL_FEEDBACK_DIV_F2_MASK |
656 SSCG_PLL_FEEDBACK_DIV_F1_MASK | 654 SSCG_PLL_FEEDBACK_DIV_F1_MASK |
657 SSCG_PLL_REF_DIVR2_MASK); 655 SSCG_PLL_REF_DIVR2_MASK);
658 val |= SSCG_PLL_OUTPUT_DIV_VAL(3); 656 val |= SSCG_PLL_OUTPUT_DIV_VAL(3);
659 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8); 657 val |= SSCG_PLL_FEEDBACK_DIV_F2_VAL(8);
660 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45); 658 val |= SSCG_PLL_FEEDBACK_DIV_F1_VAL(45);
661 val |= SSCG_PLL_REF_DIVR2_VAL(30); 659 val |= SSCG_PLL_REF_DIVR2_VAL(30);
662 writel(val, pll_cfg_reg2); 660 writel(val, pll_cfg_reg2);
663 break; 661 break;
664 default: 662 default:
665 break; 663 break;
666 } 664 }
667 665
668 /* Clear power down bit */ 666 /* Clear power down bit */
669 clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK); 667 clrbits_le32(pll_control_reg, SSCG_PLL_PD_MASK);
670 /* Eanble ARM_PLL/SYS_PLL */ 668 /* Eanble ARM_PLL/SYS_PLL */
671 setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK); 669 setbits_le32(pll_control_reg, SSCG_PLL_DRAM_PLL_CLKE_MASK);
672 670
673 /* Clear bypass */ 671 /* Clear bypass */
674 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK); 672 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS1_MASK);
675 __udelay(100); 673 __udelay(100);
676 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK); 674 clrbits_le32(pll_control_reg, SSCG_PLL_BYPASS2_MASK);
677 /* Wait lock */ 675 /* Wait lock */
678 while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK)) 676 while (!(readl(pll_control_reg) & SSCG_PLL_LOCK_MASK))
679 ; 677 ;
680 } 678 }
681 679
682 int frac_pll_init(u32 pll, enum frac_pll_out_val val) 680 int frac_pll_init(u32 pll, enum frac_pll_out_val val)
683 { 681 {
684 void __iomem *pll_cfg0, __iomem *pll_cfg1; 682 void __iomem *pll_cfg0, __iomem *pll_cfg1;
685 u32 val_cfg0, val_cfg1; 683 u32 val_cfg0, val_cfg1;
686 int ret; 684 int ret;
687 685
688 switch (pll) { 686 switch (pll) {
689 case ANATOP_ARM_PLL: 687 case ANATOP_ARM_PLL:
690 pll_cfg0 = &ana_pll->arm_pll_cfg0; 688 pll_cfg0 = &ana_pll->arm_pll_cfg0;
691 pll_cfg1 = &ana_pll->arm_pll_cfg1; 689 pll_cfg1 = &ana_pll->arm_pll_cfg1;
692 690
693 if (val == FRAC_PLL_OUT_1000M) 691 if (val == FRAC_PLL_OUT_1000M)
694 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49); 692 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(49);
695 else 693 else
696 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79); 694 val_cfg1 = FRAC_PLL_INT_DIV_CTL_VAL(79);
697 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M | 695 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M |
698 FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK | 696 FRAC_PLL_LOCK_SEL_MASK | FRAC_PLL_NEWDIV_VAL_MASK |
699 FRAC_PLL_REFCLK_DIV_VAL(4) | 697 FRAC_PLL_REFCLK_DIV_VAL(4) |
700 FRAC_PLL_OUTPUT_DIV_VAL(0); 698 FRAC_PLL_OUTPUT_DIV_VAL(0);
701 break; 699 break;
702 default: 700 default:
703 return -EINVAL; 701 return -EINVAL;
704 } 702 }
705 703
706 /* bypass the clock */ 704 /* bypass the clock */
707 setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK); 705 setbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
708 /* Set the value */ 706 /* Set the value */
709 writel(val_cfg1, pll_cfg1); 707 writel(val_cfg1, pll_cfg1);
710 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0); 708 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0);
711 val_cfg0 = readl(pll_cfg0); 709 val_cfg0 = readl(pll_cfg0);
712 /* unbypass the clock */ 710 /* unbypass the clock */
713 clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK); 711 clrbits_le32(pll_cfg0, FRAC_PLL_BYPASS_MASK);
714 ret = readl_poll_timeout(pll_cfg0, val_cfg0, 712 ret = readl_poll_timeout(pll_cfg0, val_cfg0,
715 val_cfg0 & FRAC_PLL_LOCK_MASK, 1); 713 val_cfg0 & FRAC_PLL_LOCK_MASK, 1);
716 if (ret) 714 if (ret)
717 printf("%s timeout\n", __func__); 715 printf("%s timeout\n", __func__);
718 clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK); 716 clrbits_le32(pll_cfg0, FRAC_PLL_NEWDIV_VAL_MASK);
719 717
720 return 0; 718 return 0;
721 } 719 }
722 720
723 int sscg_pll_init(u32 pll) 721 int sscg_pll_init(u32 pll)
724 { 722 {
725 void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2; 723 void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2;
726 u32 val_cfg0, val_cfg1, val_cfg2, val; 724 u32 val_cfg0, val_cfg1, val_cfg2, val;
727 u32 bypass1_mask = 0x20, bypass2_mask = 0x10; 725 u32 bypass1_mask = 0x20, bypass2_mask = 0x10;
728 int ret; 726 int ret;
729 727
730 switch (pll) { 728 switch (pll) {
731 case ANATOP_SYSTEM_PLL1: 729 case ANATOP_SYSTEM_PLL1:
732 pll_cfg0 = &ana_pll->sys_pll1_cfg0; 730 pll_cfg0 = &ana_pll->sys_pll1_cfg0;
733 pll_cfg1 = &ana_pll->sys_pll1_cfg1; 731 pll_cfg1 = &ana_pll->sys_pll1_cfg1;
734 pll_cfg2 = &ana_pll->sys_pll1_cfg2; 732 pll_cfg2 = &ana_pll->sys_pll1_cfg2;
735 /* 800MHz */ 733 /* 800MHz */
736 val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | 734 val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
737 SSCG_PLL_FEEDBACK_DIV_F2_VAL(3); 735 SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
738 val_cfg1 = 0; 736 val_cfg1 = 0;
739 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | 737 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
740 SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK | 738 SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
741 SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK | 739 SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
742 SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK | 740 SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
743 SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | 741 SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
744 SSCG_PLL_REFCLK_SEL_OSC_25M; 742 SSCG_PLL_REFCLK_SEL_OSC_25M;
745 break; 743 break;
746 case ANATOP_SYSTEM_PLL2: 744 case ANATOP_SYSTEM_PLL2:
747 pll_cfg0 = &ana_pll->sys_pll2_cfg0; 745 pll_cfg0 = &ana_pll->sys_pll2_cfg0;
748 pll_cfg1 = &ana_pll->sys_pll2_cfg1; 746 pll_cfg1 = &ana_pll->sys_pll2_cfg1;
749 pll_cfg2 = &ana_pll->sys_pll2_cfg2; 747 pll_cfg2 = &ana_pll->sys_pll2_cfg2;
750 /* 1000MHz */ 748 /* 1000MHz */
751 val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | 749 val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
752 SSCG_PLL_FEEDBACK_DIV_F2_VAL(4); 750 SSCG_PLL_FEEDBACK_DIV_F2_VAL(4);
753 val_cfg1 = 0; 751 val_cfg1 = 0;
754 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | 752 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK |
755 SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK | 753 SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK |
756 SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK | 754 SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK |
757 SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK | 755 SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK |
758 SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | 756 SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
759 SSCG_PLL_REFCLK_SEL_OSC_25M; 757 SSCG_PLL_REFCLK_SEL_OSC_25M;
760 break; 758 break;
761 case ANATOP_SYSTEM_PLL3: 759 case ANATOP_SYSTEM_PLL3:
762 pll_cfg0 = &ana_pll->sys_pll3_cfg0; 760 pll_cfg0 = &ana_pll->sys_pll3_cfg0;
763 pll_cfg1 = &ana_pll->sys_pll3_cfg1; 761 pll_cfg1 = &ana_pll->sys_pll3_cfg1;
764 pll_cfg2 = &ana_pll->sys_pll3_cfg2; 762 pll_cfg2 = &ana_pll->sys_pll3_cfg2;
765 /* 800MHz */ 763 /* 800MHz */
766 val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | 764 val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) |
767 SSCG_PLL_FEEDBACK_DIV_F2_VAL(3); 765 SSCG_PLL_FEEDBACK_DIV_F2_VAL(3);
768 val_cfg1 = 0; 766 val_cfg1 = 0;
769 val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | 767 val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK |
770 SSCG_PLL_REFCLK_SEL_OSC_25M; 768 SSCG_PLL_REFCLK_SEL_OSC_25M;
771 break; 769 break;
772 default: 770 default:
773 return -EINVAL; 771 return -EINVAL;
774 } 772 }
775 773
776 /*bypass*/ 774 /*bypass*/
777 setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask); 775 setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask);
778 /* set value */ 776 /* set value */
779 writel(val_cfg2, pll_cfg2); 777 writel(val_cfg2, pll_cfg2);
780 writel(val_cfg1, pll_cfg1); 778 writel(val_cfg1, pll_cfg1);
781 /*unbypass1 and wait 70us */ 779 /*unbypass1 and wait 70us */
782 writel(val_cfg0 | bypass2_mask, pll_cfg1); 780 writel(val_cfg0 | bypass2_mask, pll_cfg1);
783 781
784 __udelay(70); 782 __udelay(70);
785 783
786 /* unbypass2 and wait lock */ 784 /* unbypass2 and wait lock */
787 writel(val_cfg0, pll_cfg1); 785 writel(val_cfg0, pll_cfg1);
788 ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1); 786 ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1);
789 if (ret) 787 if (ret)
790 printf("%s timeout\n", __func__); 788 printf("%s timeout\n", __func__);
791 789
792 return ret; 790 return ret;
793 } 791 }
794 792
795 int clock_init(void) 793 int clock_init(void)
796 { 794 {
797 u32 grade; 795 u32 grade;
798 796
799 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | 797 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
800 CLK_ROOT_SOURCE_SEL(0)); 798 CLK_ROOT_SOURCE_SEL(0));
801 799
802 /* 800 /*
803 * 8MQ only supports two grades: consumer and industrial. 801 * 8MQ only supports two grades: consumer and industrial.
804 * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial 802 * We set ARM clock to 1Ghz for consumer, 800Mhz for industrial
805 */ 803 */
806 grade = get_cpu_temp_grade(NULL, NULL); 804 grade = get_cpu_temp_grade(NULL, NULL);
807 if (!grade) { 805 if (!grade) {
808 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M); 806 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1000M);
809 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | 807 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
810 CLK_ROOT_SOURCE_SEL(1) | 808 CLK_ROOT_SOURCE_SEL(1) |
811 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1)); 809 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1));
812 } else { 810 } else {
813 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M); 811 frac_pll_init(ANATOP_ARM_PLL, FRAC_PLL_OUT_1600M);
814 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON | 812 clock_set_target_val(ARM_A53_CLK_ROOT, CLK_ROOT_ON |
815 CLK_ROOT_SOURCE_SEL(1) | 813 CLK_ROOT_SOURCE_SEL(1) |
816 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); 814 CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
817 } 815 }
818 /* 816 /*
819 * According to ANAMIX SPEC 817 * According to ANAMIX SPEC
820 * sys pll1 fixed at 800MHz 818 * sys pll1 fixed at 800MHz
821 * sys pll2 fixed at 1GHz 819 * sys pll2 fixed at 1GHz
822 * Here we only enable the outputs. 820 * Here we only enable the outputs.
823 */ 821 */
824 setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK | 822 setbits_le32(&ana_pll->sys_pll1_cfg0, SSCG_PLL_CLKE_MASK |
825 SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK | 823 SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
826 SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK | 824 SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
827 SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK | 825 SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
828 SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK); 826 SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
829 827
830 setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK | 828 setbits_le32(&ana_pll->sys_pll2_cfg0, SSCG_PLL_CLKE_MASK |
831 SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK | 829 SSCG_PLL_DIV2_CLKE_MASK | SSCG_PLL_DIV3_CLKE_MASK |
832 SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK | 830 SSCG_PLL_DIV4_CLKE_MASK | SSCG_PLL_DIV5_CLKE_MASK |
833 SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK | 831 SSCG_PLL_DIV6_CLKE_MASK | SSCG_PLL_DIV8_CLKE_MASK |
834 SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK); 832 SSCG_PLL_DIV10_CLKE_MASK | SSCG_PLL_DIV20_CLKE_MASK);
835 833
836 clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON | 834 clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
837 CLK_ROOT_SOURCE_SEL(1)); 835 CLK_ROOT_SOURCE_SEL(1));
838 836
839 init_wdog_clk(); 837 init_wdog_clk();
840 clock_enable(CCGR_TSENSOR, 1); 838 clock_enable(CCGR_TSENSOR, 1);
841 clock_enable(CCGR_OCOTP, 1); 839 clock_enable(CCGR_OCOTP, 1);
842 840
843 /* config GIC to sys_pll2_200m */ 841 /* config GIC to sys_pll2_200m */
844 clock_enable(CCGR_GIC, 0); 842 clock_enable(CCGR_GIC, 0);
845 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); 843 clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1));
846 clock_enable(CCGR_GIC, 1); 844 clock_enable(CCGR_GIC, 1);
847 845
848 return 0; 846 return 0;
849 } 847 }
850 #endif 848 #endif
851 849
852 /* 850 /*
853 * Dump some clockes. 851 * Dump some clockes.
854 */ 852 */
855 #ifndef CONFIG_SPL_BUILD 853 #ifndef CONFIG_SPL_BUILD
856 int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, 854 int do_imx8m_showclocks(cmd_tbl_t *cmdtp, int flag, int argc,
857 char * const argv[]) 855 char * const argv[])
858 { 856 {
859 u32 freq; 857 u32 freq;
860 858
861 freq = decode_frac_pll(ARM_PLL_CLK); 859 freq = decode_frac_pll(ARM_PLL_CLK);
862 printf("ARM_PLL %8d MHz\n", freq / 1000000); 860 printf("ARM_PLL %8d MHz\n", freq / 1000000);
863 freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK); 861 freq = decode_sscg_pll(SYSTEM_PLL1_800M_CLK);
864 printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000); 862 printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000);
865 freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK); 863 freq = decode_sscg_pll(SYSTEM_PLL1_400M_CLK);
866 printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000); 864 printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000);
867 freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK); 865 freq = decode_sscg_pll(SYSTEM_PLL1_266M_CLK);
868 printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000); 866 printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000);
869 freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK); 867 freq = decode_sscg_pll(SYSTEM_PLL1_200M_CLK);
870 printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000); 868 printf("SYS_PLL1_200 %8d MHz\n", freq / 1000000);
871 freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK); 869 freq = decode_sscg_pll(SYSTEM_PLL1_160M_CLK);
872 printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000); 870 printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000);
873 freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK); 871 freq = decode_sscg_pll(SYSTEM_PLL1_133M_CLK);
874 printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000); 872 printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000);
875 freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK); 873 freq = decode_sscg_pll(SYSTEM_PLL1_100M_CLK);
876 printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000); 874 printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000);
877 freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK); 875 freq = decode_sscg_pll(SYSTEM_PLL1_80M_CLK);
878 printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000); 876 printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000);
879 freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK); 877 freq = decode_sscg_pll(SYSTEM_PLL1_40M_CLK);
880 printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000); 878 printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000);
881 freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK); 879 freq = decode_sscg_pll(SYSTEM_PLL2_1000M_CLK);
882 printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000); 880 printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000);
883 freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK); 881 freq = decode_sscg_pll(SYSTEM_PLL2_500M_CLK);
884 printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000); 882 printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000);
885 freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK); 883 freq = decode_sscg_pll(SYSTEM_PLL2_333M_CLK);
886 printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000); 884 printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000);
887 freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK); 885 freq = decode_sscg_pll(SYSTEM_PLL2_250M_CLK);
888 printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000); 886 printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000);
889 freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK); 887 freq = decode_sscg_pll(SYSTEM_PLL2_200M_CLK);
890 printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000); 888 printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000);
891 freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK); 889 freq = decode_sscg_pll(SYSTEM_PLL2_166M_CLK);
892 printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000); 890 printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000);
893 freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK); 891 freq = decode_sscg_pll(SYSTEM_PLL2_125M_CLK);
894 printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000); 892 printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000);
895 freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK); 893 freq = decode_sscg_pll(SYSTEM_PLL2_100M_CLK);
896 printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000); 894 printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000);
897 freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK); 895 freq = decode_sscg_pll(SYSTEM_PLL2_50M_CLK);
898 printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000); 896 printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000);
899 freq = decode_sscg_pll(SYSTEM_PLL3_CLK); 897 freq = decode_sscg_pll(SYSTEM_PLL3_CLK);
900 printf("SYS_PLL3 %8d MHz\n", freq / 1000000); 898 printf("SYS_PLL3 %8d MHz\n", freq / 1000000);
901 freq = mxc_get_clock(MXC_UART_CLK); 899 freq = mxc_get_clock(MXC_UART_CLK);
902 printf("UART1 %8d MHz\n", freq / 1000000); 900 printf("UART1 %8d MHz\n", freq / 1000000);
903 freq = mxc_get_clock(MXC_ESDHC_CLK); 901 freq = mxc_get_clock(MXC_ESDHC_CLK);
904 printf("USDHC1 %8d MHz\n", freq / 1000000); 902 printf("USDHC1 %8d MHz\n", freq / 1000000);
905 freq = mxc_get_clock(MXC_QSPI_CLK); 903 freq = mxc_get_clock(MXC_QSPI_CLK);
906 printf("QSPI %8d MHz\n", freq / 1000000); 904 printf("QSPI %8d MHz\n", freq / 1000000);
907 return 0; 905 return 0;
908 } 906 }
909 907
910 U_BOOT_CMD( 908 U_BOOT_CMD(
911 clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks, 909 clocks, CONFIG_SYS_MAXARGS, 1, do_imx8m_showclocks,
912 "display clocks", 910 "display clocks",
913 "" 911 ""
914 ); 912 );
915 #endif 913 #endif
916 914
configs/imx8mq_evk_defconfig
Diff comments   View file @ 369776e
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_IMX8M=y 2 CONFIG_ARCH_IMX8M=y
3 CONFIG_SYS_TEXT_BASE=0x40200000 3 CONFIG_SYS_TEXT_BASE=0x40200000
4 CONFIG_SYS_MALLOC_F_LEN=0x2000 4 CONFIG_SYS_MALLOC_F_LEN=0x2000
5 CONFIG_TARGET_IMX8MQ_EVK=y 5 CONFIG_TARGET_IMX8MQ_EVK=y
6 CONFIG_SPL_SERIAL_SUPPORT=y 6 CONFIG_SPL_SERIAL_SUPPORT=y
7 CONFIG_ARCH_MISC_INIT=y 7 CONFIG_ARCH_MISC_INIT=y
8 CONFIG_SPL=y 8 CONFIG_SPL=y
9 CONFIG_FIT=y 9 CONFIG_FIT=y
10 CONFIG_FIT_EXTERNAL_OFFSET=0x3000 10 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
11 CONFIG_SPL_LOAD_FIT=y 11 CONFIG_SPL_LOAD_FIT=y
12 CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" 12 CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
13 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" 13 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
14 CONFIG_SPL_BOARD_INIT=y 14 CONFIG_SPL_BOARD_INIT=y
15 CONFIG_HUSH_PARSER=y 15 CONFIG_HUSH_PARSER=y
16 CONFIG_CMD_GPIO=y 16 CONFIG_CMD_GPIO=y
17 CONFIG_CMD_I2C=y 17 CONFIG_CMD_I2C=y
18 CONFIG_CMD_CACHE=y 18 CONFIG_CMD_CACHE=y
19 CONFIG_CMD_REGULATOR=y 19 CONFIG_CMD_REGULATOR=y
20 CONFIG_CMD_EXT2=y 20 CONFIG_CMD_EXT2=y
21 CONFIG_CMD_EXT4=y 21 CONFIG_CMD_EXT4=y
22 CONFIG_CMD_EXT4_WRITE=y 22 CONFIG_CMD_EXT4_WRITE=y
23 CONFIG_CMD_FAT=y 23 CONFIG_CMD_FAT=y
24 CONFIG_CMD_MEMTEST=y 24 CONFIG_CMD_MEMTEST=y
25 CONFIG_OF_CONTROL=y 25 CONFIG_OF_CONTROL=y
26 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk" 26 CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk"
27 CONFIG_ENV_IS_IN_MMC=y 27 CONFIG_ENV_IS_IN_MMC=y
28 CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 28 CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
29 CONFIG_DM_GPIO=y 29 CONFIG_DM_GPIO=y
30 CONFIG_DM_I2C=y 30 CONFIG_DM_I2C=y
31 CONFIG_SYS_I2C_MXC=y 31 CONFIG_SYS_I2C_MXC=y
32 CONFIG_DM_MMC=y 32 CONFIG_DM_MMC=y
33 CONFIG_MMC_IO_VOLTAGE=y
34 CONFIG_MMC_UHS_SUPPORT=y
35 CONFIG_MMC_HS400_SUPPORT=y
33 CONFIG_DM_ETH=y 36 CONFIG_DM_ETH=y
34 CONFIG_PINCTRL=y 37 CONFIG_PINCTRL=y
35 CONFIG_PINCTRL_IMX8M=y 38 CONFIG_PINCTRL_IMX8M=y
36 CONFIG_DM_REGULATOR=y 39 CONFIG_DM_REGULATOR=y
37 CONFIG_DM_REGULATOR_FIXED=y 40 CONFIG_DM_REGULATOR_FIXED=y
38 CONFIG_DM_REGULATOR_GPIO=y 41 CONFIG_DM_REGULATOR_GPIO=y
39 CONFIG_DM_THERMAL=y 42 CONFIG_DM_THERMAL=y
40 CONFIG_NXP_TMU=y 43 CONFIG_NXP_TMU=y
41 CONFIG_USB_TCPC=y 44 CONFIG_USB_TCPC=y
42 CONFIG_USB=y 45 CONFIG_USB=y
43 CONFIG_DM_USB=y 46 CONFIG_DM_USB=y
44 47
45 CONFIG_SPI=y 48 CONFIG_SPI=y
46 CONFIG_DM_SPI=y 49 CONFIG_DM_SPI=y
47 CONFIG_DM_SPI_FLASH=y 50 CONFIG_DM_SPI_FLASH=y
48 CONFIG_FSL_QSPI=y 51 CONFIG_FSL_QSPI=y
49 CONFIG_CMD_SF=y 52 CONFIG_CMD_SF=y
50 CONFIG_SPI_FLASH=y 53 CONFIG_SPI_FLASH=y
51 CONFIG_SPI_FLASH_STMICRO=y 54 CONFIG_SPI_FLASH_STMICRO=y
52 CONFIG_SPI_FLASH_BAR=y 55 CONFIG_SPI_FLASH_BAR=y
53 CONFIG_SF_DEFAULT_BUS=0 56 CONFIG_SF_DEFAULT_BUS=0
54 CONFIG_SF_DEFAULT_CS=0 57 CONFIG_SF_DEFAULT_CS=0
55 CONFIG_SF_DEFAULT_SPEED=40000000 58 CONFIG_SF_DEFAULT_SPEED=40000000
56 CONFIG_SF_DEFAULT_MODE=0 59 CONFIG_SF_DEFAULT_MODE=0
57 60
58 CONFIG_VIDEO=y 61 CONFIG_VIDEO=y
59 CONFIG_VIDEO_IMX8_HDMI=y 62 CONFIG_VIDEO_IMX8_HDMI=y
60 CONFIG_USB_GADGET=y 63 CONFIG_USB_GADGET=y
61 CONFIG_FASTBOOT=y 64 CONFIG_FASTBOOT=y
62 CONFIG_USB_FUNCTION_FASTBOOT=y 65 CONFIG_USB_FUNCTION_FASTBOOT=y
63 CONFIG_CMD_FASTBOOT=y 66 CONFIG_CMD_FASTBOOT=y
64 CONFIG_ANDROID_BOOT_IMAGE=y 67 CONFIG_ANDROID_BOOT_IMAGE=y
65 CONFIG_FASTBOOT_UUU_SUPPORT=y 68 CONFIG_FASTBOOT_UUU_SUPPORT=y
66 CONFIG_FASTBOOT_BUF_ADDR=0x42800000 69 CONFIG_FASTBOOT_BUF_ADDR=0x42800000
67 CONFIG_FASTBOOT_BUF_SIZE=0x40000000 70 CONFIG_FASTBOOT_BUF_SIZE=0x40000000
68 CONFIG_FASTBOOT_FLASH=y 71 CONFIG_FASTBOOT_FLASH=y
69 CONFIG_EFI_PARTITION=y 72 CONFIG_EFI_PARTITION=y
70 CONFIG_SDP_LOADADDR=0x40400000 73 CONFIG_SDP_LOADADDR=0x40400000
71 CONFIG_USB_GADGET_VENDOR_NUM=0x0525 74 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
72 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 75 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
73 CONFIG_USB_GADGET_MANUFACTURER="FSL" 76 CONFIG_USB_GADGET_MANUFACTURER="FSL"
74 CONFIG_USB_GADGET_DOWNLOAD=y 77 CONFIG_USB_GADGET_DOWNLOAD=y
75 CONFIG_SPL_USB_GADGET=y 78 CONFIG_SPL_USB_GADGET=y
76 CONFIG_SPL_USB_SDP_SUPPORT=y 79 CONFIG_SPL_USB_SDP_SUPPORT=y
77 CONFIG_USB_XHCI_HCD=y 80 CONFIG_USB_XHCI_HCD=y
78 CONFIG_USB_XHCI_IMX8M=y 81 CONFIG_USB_XHCI_IMX8M=y
79 CONFIG_USB_XHCI_DWC3=y 82 CONFIG_USB_XHCI_DWC3=y
80 CONFIG_USB_DWC3=y 83 CONFIG_USB_DWC3=y
81 CONFIG_USB_DWC3_GADGET=y 84 CONFIG_USB_DWC3_GADGET=y
82 85