Commit 369776edfebf022130a2a8ed986e73ede62ec7cd

Authored by Ye Li
1 parent 5274ae1eb9

MLK-22851-3 imx8mq: Enable eMMC HS400 and SD UHS mode on EVK

iMX8MQ EVK board has a eMMC5.0 chip and supports SD3.0, so enable the UHS
and HS400 configs to enhance the eMMC/SD access.

The change also needs to set usdhc clock to 400Mhz, and add the off-on-delay-us
to SD reset pin, otherwise some SD cards will fail to select UHS mode in
re-initialization.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 57e1bc5f634be231b2bfd10cf0cbbff86dadd2e1)

Showing 3 changed files with 6 additions and 4 deletions Side-by-side Diff

arch/arm/dts/fsl-imx8mq-evk.dts
... ... @@ -37,6 +37,7 @@
37 37 regulator-min-microvolt = <3300000>;
38 38 regulator-max-microvolt = <3300000>;
39 39 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  40 + u-boot,off-on-delay-us = <20000>;
40 41 enable-active-high;
41 42 };
42 43 };
arch/arm/mach-imx/imx8m/clock_imx8mq.c
... ... @@ -471,15 +471,13 @@
471 471 case 0:
472 472 clock_enable(CCGR_USDHC1, 0);
473 473 clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON |
474   - CLK_ROOT_SOURCE_SEL(1) |
475   - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
  474 + CLK_ROOT_SOURCE_SEL(1));
476 475 clock_enable(CCGR_USDHC1, 1);
477 476 return;
478 477 case 1:
479 478 clock_enable(CCGR_USDHC2, 0);
480 479 clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON |
481   - CLK_ROOT_SOURCE_SEL(1) |
482   - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2));
  480 + CLK_ROOT_SOURCE_SEL(1));
483 481 clock_enable(CCGR_USDHC2, 1);
484 482 return;
485 483 default:
configs/imx8mq_evk_defconfig
... ... @@ -30,6 +30,9 @@
30 30 CONFIG_DM_I2C=y
31 31 CONFIG_SYS_I2C_MXC=y
32 32 CONFIG_DM_MMC=y
  33 +CONFIG_MMC_IO_VOLTAGE=y
  34 +CONFIG_MMC_UHS_SUPPORT=y
  35 +CONFIG_MMC_HS400_SUPPORT=y
33 36 CONFIG_DM_ETH=y
34 37 CONFIG_PINCTRL=y
35 38 CONFIG_PINCTRL_IMX8M=y