Eric Lee / smarc-uboot

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Commit 3afecc120b3079e26ce9afb1edf94f9db819802f

Authored by Peng Fan
1 parent 0abdd9a9bb
Exists in smarc_8mq-imx_v2020.04_5.4.24_2.1.0 and in 1 other branch smarc_8mm-imx_v2020.04_5.4.24_2.1.0

MLK-18577-5 imx8: update soc code to support uboot in XEN VM 

Update SOC code to support U-Boot in a XEN VM. Currently
we only support to boot android using uboot in a VM,
so there is hardcode that using MMC1_BOOT boot.

There are a few small fixes included.

For the mmu configuration, the mem map is used from xen
guest VM and our iomem space in vm cfg file.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 533087bc1bce0c35fead0956b0613971862c280f)
(cherry picked from commit c2ba2460d8985aa0b084f7beef2d0bc8773d90e3)
(cherry picked from commit 2b0a537f59646f3f222d60ebe46611160ba6bdc9)
(cherry picked from commit 179a0a6ff3eba16fcf8d5966904b810531fe8665)

Showing 1 changed file with 49 additions and 2 deletions Side-by-side Diff

arch/arm/mach-imx/imx8/cpu.c
Diff comments   View file @ 3afecc1
... ... @@ -91,6 +91,9 @@
91 91 return ret;
92 92 }
93 93  
  94 + if (IS_ENABLED(CONFIG_XEN))
  95 + return 0;
  96 +
94 97 struct pass_over_info_t *pass_over;
95 98  
96 99 if ((is_imx8qm() || is_imx8qxp()) && is_soc_rev(CHIP_REV_A)) {
... ... @@ -388,6 +391,10 @@
388 391  
389 392 sc_rsrc_t dev_rsrc;
390 393  
  394 + /* Note we only support android in EMMC SDHC0 */
  395 + if (IS_ENABLED(CONFIG_XEN))
  396 + return MMC1_BOOT;
  397 +
391 398 sc_misc_get_boot_dev(-1, &dev_rsrc);
392 399  
393 400 switch (dev_rsrc) {
394 401  
... ... @@ -537,8 +544,10 @@
537 544 sc_faddr_t start, end, end1, start_aligned;
538 545 int err;
539 546  
540   - end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
  547 + if (IS_ENABLED(CONFIG_XEN))
  548 + return PHYS_SDRAM_1_SIZE;
541 549  
  550 + end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
542 551 for (mr = 0; mr < 64; mr++) {
543 552 err = get_owned_memreg(mr, &start, &end);
544 553 if (!err) {
... ... @@ -569,6 +578,13 @@
569 578 sc_faddr_t start, end, end1, end2;
570 579 int err;
571 580  
  581 + if (IS_ENABLED(CONFIG_XEN)) {
  582 + gd->ram_size = PHYS_SDRAM_1_SIZE;
  583 + gd->ram_size += PHYS_SDRAM_2_SIZE;
  584 +
  585 + return 0;
  586 + }
  587 +
572 588 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
573 589 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
574 590 for (mr = 0; mr < 64; mr++) {
575 591  
... ... @@ -631,9 +647,17 @@
631 647 int i = 0;
632 648 int err;
633 649  
  650 + if (IS_ENABLED(CONFIG_XEN)) {
  651 + gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  652 + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  653 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  654 + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  655 +
  656 + return 0;
  657 + }
  658 +
634 659 end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
635 660 end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
636   -
637 661 for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
638 662 err = get_owned_memreg(mr, &start, &end);
639 663 if (!err) {
... ... @@ -725,6 +749,29 @@
725 749 sc_rm_mr_t mr;
726 750 sc_faddr_t start, end;
727 751 int err, i;
  752 +
  753 + if (IS_ENABLED(CONFIG_XEN)) {
  754 + imx8_mem_map[0].virt = 0x00000000UL;
  755 + imx8_mem_map[0].phys = 0x00000000UL;
  756 + imx8_mem_map[0].size = 0x40000000UL;
  757 + imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  758 + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
  759 + imx8_mem_map[1].virt = 0x40000000UL;
  760 + imx8_mem_map[1].phys = 0x40000000UL;
  761 + imx8_mem_map[1].size = 0xC0000000UL;
  762 + imx8_mem_map[1].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
  763 +
  764 + imx8_mem_map[2].virt = 0x100000000UL;
  765 + imx8_mem_map[2].phys = 0x100000000UL;
  766 + imx8_mem_map[2].size = 0x100000000UL;
  767 + imx8_mem_map[2].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  768 + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
  769 +
  770 + icache_enable();
  771 + dcache_enable();
  772 +
  773 + return;
  774 + }
728 775  
729 776 /* Create map for registers access from 0x1c000000 to 0x80000000*/
730 777 imx8_mem_map[0].virt = 0x1c000000UL;