Eric Lee / smarc-uboot

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Commit 40e1df5f6cba32dedb58a8009e121da6edbcc1e6

Authored by Roger Quadros
Committed by Lokesh Vutla
1 parent 98addfd487
Exists in v2016.05-smarct4x and in 3 other branches v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc

usb: phy: omap_usb_phy: Fix USB3_PHY DPLL configuration 

The index returned by get_sys_clk_index() is not exactly what we expect.
Let's not rely on that and use get_sys_clk_freq() instead.

This fixes missing USB3 devices in the Linux kernel when USB is started
in u-boot. It still doesn't fix missing USB3 devices in u-boot though.

Signed-off-by: Roger Quadros <rogerq@ti.com>

Showing 1 changed file with 41 additions and 15 deletions Side-by-side Diff

drivers/usb/phy/omap_usb_phy.c
Diff comments   View file @ 40e1df5
... ... @@ -23,7 +23,7 @@
23 23 #include "../host/xhci.h"
24 24  
25 25 #ifdef CONFIG_OMAP_USB3PHY1_HOST
26   -struct usb_dpll_params {
  26 +struct usb3_dpll_params {
27 27 u16 m;
28 28 u8 n;
29 29 u8 freq:3;
30 30  
31 31  
... ... @@ -31,17 +31,39 @@
31 31 u32 mf;
32 32 };
33 33  
34   -#define NUM_USB_CLKS 6
  34 +struct usb3_dpll_map {
  35 + unsigned long rate;
  36 + struct usb3_dpll_params params;
  37 + struct usb3_dpll_map *dpll_map;
  38 +};
35 39  
36   -static struct usb_dpll_params omap_usb3_dpll_params[NUM_USB_CLKS] = {
37   - {1250, 5, 4, 20, 0}, /* 12 MHz */
38   - {3125, 20, 4, 20, 0}, /* 16.8 MHz */
39   - {1172, 8, 4, 20, 65537}, /* 19.2 MHz */
40   - {1250, 12, 4, 20, 0}, /* 26 MHz */
41   - {3125, 47, 4, 20, 92843}, /* 38.4 MHz */
42   - {1000, 7, 4, 10, 0}, /* 20 MHz */
  40 +static struct usb3_dpll_map dpll_map_usb[] = {
  41 + {12000000, {1250, 5, 4, 20, 0} }, /* 12 MHz */
  42 + {16800000, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
  43 + {19200000, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
  44 + {20000000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
  45 + {26000000, {1250, 12, 4, 20, 0} }, /* 26 MHz */
  46 + {38400000, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
  47 + { }, /* Terminator */
43 48 };
44 49  
  50 +static struct usb3_dpll_params *omap_usb3_get_dpll_params(void)
  51 +{
  52 + unsigned long rate;
  53 + struct usb3_dpll_map *dpll_map = dpll_map_usb;
  54 +
  55 + rate = get_sys_clk_freq();
  56 +
  57 + for (; dpll_map->rate; dpll_map++) {
  58 + if (rate == dpll_map->rate)
  59 + return &dpll_map->params;
  60 + }
  61 +
  62 + dev_err(phy->dev, "No DPLL configuration for %lu Hz SYS CLK\n", rate);
  63 +
  64 + return NULL;
  65 +}
  66 +
45 67 static void omap_usb_dpll_relock(struct omap_usb3_phy *phy_regs)
46 68 {
47 69 u32 val;
48 70  
49 71  
50 72  
51 73  
52 74  
53 75  
... ... @@ -56,32 +78,36 @@
56 78  
57 79 static void omap_usb_dpll_lock(struct omap_usb3_phy *phy_regs)
58 80 {
59   - u32 clk_index = get_sys_clk_index();
  81 + struct usb3_dpll_params *dpll_params;
60 82 u32 val;
61 83  
  84 + dpll_params = omap_usb3_get_dpll_params();
  85 + if (!dpll_params)
  86 + return;
  87 +
62 88 val = readl(&phy_regs->pll_config_1);
63 89 val &= ~PLL_REGN_MASK;
64   - val |= omap_usb3_dpll_params[clk_index].n << PLL_REGN_SHIFT;
  90 + val |= dpll_params->n << PLL_REGN_SHIFT;
65 91 writel(val, &phy_regs->pll_config_1);
66 92  
67 93 val = readl(&phy_regs->pll_config_2);
68 94 val &= ~PLL_SELFREQDCO_MASK;
69   - val |= omap_usb3_dpll_params[clk_index].freq << PLL_SELFREQDCO_SHIFT;
  95 + val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
70 96 writel(val, &phy_regs->pll_config_2);
71 97  
72 98 val = readl(&phy_regs->pll_config_1);
73 99 val &= ~PLL_REGM_MASK;
74   - val |= omap_usb3_dpll_params[clk_index].m << PLL_REGM_SHIFT;
  100 + val |= dpll_params->m << PLL_REGM_SHIFT;
75 101 writel(val, &phy_regs->pll_config_1);
76 102  
77 103 val = readl(&phy_regs->pll_config_4);
78 104 val &= ~PLL_REGM_F_MASK;
79   - val |= omap_usb3_dpll_params[clk_index].mf << PLL_REGM_F_SHIFT;
  105 + val |= dpll_params->mf << PLL_REGM_F_SHIFT;
80 106 writel(val, &phy_regs->pll_config_4);
81 107  
82 108 val = readl(&phy_regs->pll_config_3);
83 109 val &= ~PLL_SD_MASK;
84   - val |= omap_usb3_dpll_params[clk_index].sd << PLL_SD_SHIFT;
  110 + val |= dpll_params->sd << PLL_SD_SHIFT;
85 111 writel(val, &phy_regs->pll_config_3);
86 112  
87 113 omap_usb_dpll_relock(phy_regs);