Eric Lee / smarc-uboot

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Commit 40e7bcdee72830fa51d9e98428f1a61f9126527e

Authored by Marek Vasut
1 parent 9ca2116ce4
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: socfpga: cache: Enable D-Cache 

The code is now fixed to the point where we can safely enable
the L1 data cache. Enable the D-Cache and set it as write-alloc.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

Showing 2 changed files with 2 additions and 1 deletions Side-by-side Diff

board/altera/socfpga/socfpga_cyclone5.c
Diff comments   View file @ 40e7bcd
... ... @@ -35,6 +35,7 @@
35 35 int board_init(void)
36 36 {
37 37 icache_enable();
  38 + dcache_enable();
38 39  
39 40 /* Address of boot parameters for ATAG (if ATAG is used) */
40 41 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
include/configs/socfpga_cyclone5.h
Diff comments   View file @ 40e7bcd
... ... @@ -18,7 +18,6 @@
18 18 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
19 19  
20 20 #define CONFIG_ARMV7
21   -#define CONFIG_SYS_DCACHE_OFF
22 21 #undef CONFIG_USE_IRQ
23 22  
24 23 #define CONFIG_MISC_INIT_R
... ... @@ -26,6 +25,7 @@
26 25 #define CONFIG_SOCFPGA
27 26 #define CONFIG_CLOCKS
28 27  
  28 +#define CONFIG_SYS_ARM_CACHE_WRITEALLOC
29 29 #define CONFIG_SYS_CACHELINE_SIZE 32
30 30  
31 31 /* base address for .text section */