Eric Lee / smarc-uboot

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Commit 41895cd598be6c4a64fc4fec521120e4962abc28

Authored by Ye Li
1 parent a4d958d120
Exists in smarc-n7.1.2_2.0.0-ga and in 4 other branches smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m

MLK-14445-2 mx7ulp_evk: Add QSPI flash support 

Porting the QSPI flash board support from v2016.03, and convert to use
DM QSPI driver.
Since we need to support QSPI at default in u-boot, change the default
DTS file to qspi enabled DTS.

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 7 changed files with 111 additions and 3 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ 41895cd
... ... @@ -375,7 +375,8 @@
375 375 imx7d-19x19-lpddr2-arm2.dtb \
376 376 imx7d-19x19-lpddr3-arm2.dtb
377 377  
378   -dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
  378 +dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb \
  379 + imx7ulp-evk-qspi.dtb
379 380  
380 381 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
381 382 keystone-k2l-evm.dtb \
arch/arm/dts/imx7ulp-evk-qspi.dts
Diff comments   View file @ 41895cd
  1 +/*
  2 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
  3 + * Copyright 2017 NXP
  4 + *
  5 + * This program is free software; you can redistribute it and/or modify
  6 + * it under the terms of the GNU General Public License version 2 as
  7 + * published by the Free Software Foundation.
  8 + */
  9 +
  10 +#include "imx7ulp-evk.dts"
  11 +
  12 +&qspi1 {
  13 + pinctrl-names = "default";
  14 + pinctrl-0 = <&pinctrl_qspi1_1>;
  15 + status = "okay";
  16 +
  17 + flash0: mx25r6435f@0 {
  18 + reg = <0>;
  19 + #address-cells = <1>;
  20 + #size-cells = <1>;
  21 + compatible = "macronix,mx25r6435f";
  22 + spi-max-frequency = <29000000>;
  23 + };
  24 +};
  25 +
  26 +&iomuxc {
  27 + status = "okay";
  28 +};
  29 +
  30 +&iomuxc {
  31 + imx7ulp-evk {
  32 + pinctrl_qspi1_1: qspi1grp_1 {
  33 + fsl,pins = <
  34 + ULP1_PAD_PTB7_LLWU0_P11__QSPIA_SS1_B 0x43 /* SS1 */
  35 + ULP1_PAD_PTB8__QSPIA_SS0_B 0x43 /* SS0 */
  36 + ULP1_PAD_PTB15__QSPIA_SCLK 0x43 /* SCLK */
  37 + ULP1_PAD_PTB9_LLWU0_P12__QSPIA_DQS 0x43 /* DQS */
  38 + ULP1_PAD_PTB16_LLWU0_P14__QSPIA_DATA3 0x43 /* D3 */
  39 + ULP1_PAD_PTB17__QSPIA_DATA2 0x43 /* D2 */
  40 + ULP1_PAD_PTB18__QSPIA_DATA1 0x43 /* D1 */
  41 + ULP1_PAD_PTB19_LLWU0_P15__QSPIA_DATA0 0x43 /* D0 */
  42 + >;
  43 + };
  44 + };
  45 +};
arch/arm/dts/imx7ulp.dtsi
Diff comments   View file @ 41895cd
... ... @@ -31,6 +31,7 @@
31 31 i2c1 = &lpi2c5;
32 32 i2c2 = &lpi2c6;
33 33 i2c3 = &lpi2c7;
  34 + spi0 = &qspi1;
34 35 };
35 36  
36 37 cpus {
board/freescale/mx7ulp_evk/mx7ulp_evk.c
Diff comments   View file @ 41895cd
... ... @@ -13,6 +13,7 @@
13 13 DECLARE_GLOBAL_DATA_PTR;
14 14  
15 15 #define UART_PAD_CTRL (PAD_CTL_PUS_UP)
  16 +#define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP | PAD_CTL_DSE)
16 17  
17 18 int dram_init(void)
18 19 {
... ... @@ -32,6 +33,36 @@
32 33 ARRAY_SIZE(lpuart4_pads));
33 34 }
34 35  
  36 +#ifdef CONFIG_FSL_QSPI
  37 +#ifndef CONFIG_DM_SPI
  38 +static iomux_cfg_t const quadspi_pads[] = {
  39 + MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  40 + MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  41 + MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  42 + MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  43 + MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  44 + MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
  45 +};
  46 +#endif
  47 +
  48 +int board_qspi_init(void)
  49 +{
  50 + u32 val;
  51 +#ifndef CONFIG_DM_SPI
  52 + mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
  53 +#endif
  54 +
  55 + /* enable clock */
  56 + val = readl(PCC1_RBASE + 0x94);
  57 +
  58 + if (!(val & 0x20000000)) {
  59 + writel(0x03000003, (PCC1_RBASE + 0x94));
  60 + writel(0x43000003, (PCC1_RBASE + 0x94));
  61 + }
  62 + return 0;
  63 +}
  64 +#endif
  65 +
35 66 int board_early_init_f(void)
36 67 {
37 68 setup_iomux_uart();
... ... @@ -43,6 +74,10 @@
43 74 {
44 75 /* address of boot parameters */
45 76 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  77 +
  78 +#ifdef CONFIG_FSL_QSPI
  79 + board_qspi_init();
  80 +#endif
46 81  
47 82 return 0;
48 83 }
configs/mx7ulp_evk_defconfig
Diff comments   View file @ 41895cd
1 1 CONFIG_ARM=y
2 2 CONFIG_ARCH_MX7ULP=y
3 3 CONFIG_TARGET_MX7ULP_EVK=y
4   -CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
  4 +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi"
5 5 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
6 6 CONFIG_HUSH_PARSER=y
7 7 CONFIG_CMD_I2C=y
... ... @@ -23,4 +23,10 @@
23 23 CONFIG_DM_REGULATOR_FIXED=y
24 24 CONFIG_DM_REGULATOR_GPIO=y
25 25 CONFIG_CMD_GPIO=y
  26 +CONFIG_CMD_SF=y
  27 +CONFIG_FSL_QSPI=y
  28 +CONFIG_DM_SPI=y
  29 +CONFIG_DM_SPI_FLASH=y
  30 +CONFIG_SPI_FLASH=y
  31 +CONFIG_SPI_FLASH_MACRONIX=y
configs/mx7ulp_evk_plugin_defconfig
Diff comments   View file @ 41895cd
... ... @@ -2,7 +2,7 @@
2 2 CONFIG_ARCH_MX7ULP=y
3 3 CONFIG_TARGET_MX7ULP_EVK=y
4 4 CONFIG_USE_IMXIMG_PLUGIN=y
5   -CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
  5 +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi"
6 6 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
7 7 CONFIG_HUSH_PARSER=y
8 8 CONFIG_CMD_I2C=y
... ... @@ -24,4 +24,10 @@
24 24 CONFIG_DM_REGULATOR_FIXED=y
25 25 CONFIG_DM_REGULATOR_GPIO=y
26 26 CONFIG_CMD_GPIO=y
  27 +CONFIG_CMD_SF=y
  28 +CONFIG_FSL_QSPI=y
  29 +CONFIG_DM_SPI=y
  30 +CONFIG_DM_SPI_FLASH=y
  31 +CONFIG_SPI_FLASH=y
  32 +CONFIG_SPI_FLASH_MACRONIX=y
include/configs/mx7ulp_evk.h
Diff comments   View file @ 41895cd
... ... @@ -195,6 +195,19 @@
195 195 #define CONFIG_CMD_CACHE
196 196 #endif
197 197  
  198 +/* QSPI configs */
  199 +#ifdef CONFIG_FSL_QSPI
  200 +#define CONFIG_SYS_FSL_QSPI_AHB
  201 +#define CONFIG_SF_DEFAULT_BUS 0
  202 +#define CONFIG_SF_DEFAULT_CS 0
  203 +#define CONFIG_SF_DEFAULT_SPEED 40000000
  204 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  205 +#define FSL_QSPI_FLASH_NUM 1
  206 +#define FSL_QSPI_FLASH_SIZE SZ_8M
  207 +#define QSPI0_BASE_ADDR 0x410A5000
  208 +#define QSPI0_AMBA_BASE 0xC0000000
  209 +#endif
  210 +
198 211 #define CONFIG_OF_SYSTEM_SETUP
199 212  
200 213 #endif /* __CONFIG_H */