MLK-14445-2 mx7ulp_evk: Add QSPI flash support

Porting the QSPI flash board support from v2016.03, and convert to use DM QSPI driver. Since we need to support QSPI at default in u-boot, change the default DTS file to qspi enabled DTS. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 41895cd598be6c4a64fc4fec521120e4962abc28)

MLK-14445-2 mx7ulp_evk: Add QSPI flash support
Porting the QSPI flash board support from v2016.03, and convert to use DM QSPI driver. Since we need to support QSPI at default in u-boot, change the default DTS file to qspi enabled DTS. Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 41895cd598be6c4a64fc4fec521120e4962abc28)
Ye Li · Eric Lee · Eric Lee · Eric Lee · Eric Lee · Eric Lee
1 parent ed4a4a9d1c
Showing 7 changed files with 112 additions and 3 deletions Side-by-side Diff
arch/arm/dts/Makefile
arch/arm/dts/imx7ulp-evk-qspi.dts
arch/arm/dts/imx7ulp.dtsi
board/freescale/mx7ulp_evk/mx7ulp_evk.c
configs/mx7ulp_evk_defconfig
configs/mx7ulp_evk_plugin_defconfig
include/configs/mx7ulp_evk.h
@@ -424,7 +424,8 @@
 	imx7d-sdb-qspi.dtb \
     imx7d-sdb-reva.dtb
  
-dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb \
+		imx7ulp-evk-qspi.dtb
  
 dtb-$(CONFIG_RCAR_GEN3) += \
 	r8a7795-h3ulcb.dtb \
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7ulp-evk.dts"
+
+&qspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi1_1>;
+	status = "okay";
+
+	flash0: mx25r6435f@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "macronix,mx25r6435f";
+		spi-max-frequency = <29000000>;
+	};
+};
+
+&iomuxc {
+	status = "okay";
+};
+
+&iomuxc {
+	imx7ulp-evk {
+		pinctrl_qspi1_1: qspi1grp_1 {
+			fsl,pins = <
+				ULP1_PAD_PTB7_LLWU0_P11__QSPIA_SS1_B    0x43 /* SS1 */
+				ULP1_PAD_PTB8__QSPIA_SS0_B              0x43 /* SS0 */
+				ULP1_PAD_PTB15__QSPIA_SCLK              0x43 /* SCLK */
+				ULP1_PAD_PTB9_LLWU0_P12__QSPIA_DQS      0x43 /* DQS */
+				ULP1_PAD_PTB16_LLWU0_P14__QSPIA_DATA3   0x43 /* D3 */
+				ULP1_PAD_PTB17__QSPIA_DATA2             0x43 /* D2 */
+				ULP1_PAD_PTB18__QSPIA_DATA1             0x43 /* D1 */
+				ULP1_PAD_PTB19_LLWU0_P15__QSPIA_DATA0   0x43 /* D0 */
+			>;
+		};
+	};
+};
@@ -31,6 +31,7 @@
 		i2c5 = &lpi2c5;
 		i2c6 = &lpi2c6;
 		i2c7 = &lpi2c7;
+		spi0 = &qspi1;
 	};
  
 	cpus {
@@ -13,6 +13,7 @@
 DECLARE_GLOBAL_DATA_PTR;
  
 #define UART_PAD_CTRL	(PAD_CTL_PUS_UP)
+#define QSPI_PAD_CTRL1	(PAD_CTL_PUS_UP | PAD_CTL_DSE)
  
 int dram_init(void)
 {
@@ -32,6 +33,36 @@
 					 ARRAY_SIZE(lpuart4_pads));
 }
  
+#ifdef CONFIG_FSL_QSPI
+#ifndef CONFIG_DM_SPI
+static iomux_cfg_t const quadspi_pads[] = {
+	MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB15__QSPIA_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+#endif
+
+int board_qspi_init(void)
+{
+	u32 val;
+#ifndef CONFIG_DM_SPI
+	mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
+#endif
+
+	/* enable clock */
+	val = readl(PCC1_RBASE + 0x94);
+
+	if (!(val & 0x20000000)) {
+		writel(0x03000003, (PCC1_RBASE + 0x94));
+		writel(0x43000003, (PCC1_RBASE + 0x94));
+	}
+	return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -43,6 +74,10 @@
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
  
 	return 0;
 }
@@ -2,7 +2,7 @@
 CONFIG_ARCH_MX7ULP=y
 CONFIG_SYS_TEXT_BASE=0x67800000
 CONFIG_TARGET_MX7ULP_EVK=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
@@ -25,4 +25,10 @@
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
@@ -2,7 +2,8 @@
 CONFIG_ARCH_MX7ULP=y
 CONFIG_SYS_TEXT_BASE=0x67800000
 CONFIG_TARGET_MX7ULP_EVK=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
+CONFIG_USE_IMXIMG_PLUGIN=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_GPIO=y
@@ -24,4 +25,10 @@
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
@@ -179,6 +179,19 @@
 #define CONFIG_CMD_CACHE
 #endif
  
+/* QSPI configs */
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_FSL_QSPI_AHB
+#define CONFIG_SF_DEFAULT_BUS           0
+#define CONFIG_SF_DEFAULT_CS            0
+#define CONFIG_SF_DEFAULT_SPEED         40000000
+#define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
+#define FSL_QSPI_FLASH_NUM              1
+#define FSL_QSPI_FLASH_SIZE             SZ_8M
+#define QSPI0_BASE_ADDR                 0x410A5000
+#define QSPI0_AMBA_BASE                 0xC0000000
+#endif
+
 #define CONFIG_OF_SYSTEM_SETUP
  
 #endif	/* __CONFIG_H */
...	...	@@ -424,7 +424,8 @@
424	424	imx7d-sdb-qspi.dtb \
425	425	imx7d-sdb-reva.dtb
426	426
427		-dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
	427	+dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb \
	428	+ imx7ulp-evk-qspi.dtb
428	429
429	430	dtb-$(CONFIG_RCAR_GEN3) += \
430	431	r8a7795-h3ulcb.dtb \
	1	+/*
	2	+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
	3	+ * Copyright 2017 NXP
	4	+ *
	5	+ * This program is free software; you can redistribute it and/or modify
	6	+ * it under the terms of the GNU General Public License version 2 as
	7	+ * published by the Free Software Foundation.
	8	+ */
	9	+
	10	+#include "imx7ulp-evk.dts"
	11	+
	12	+&qspi1 {
	13	+ pinctrl-names = "default";
	14	+ pinctrl-0 = <&pinctrl_qspi1_1>;
	15	+ status = "okay";
	16	+
	17	+ flash0: mx25r6435f@0 {
	18	+ reg = <0>;
	19	+ #address-cells = <1>;
	20	+ #size-cells = <1>;
	21	+ compatible = "macronix,mx25r6435f";
	22	+ spi-max-frequency = <29000000>;
	23	+ };
	24	+};
	25	+
	26	+&iomuxc {
	27	+ status = "okay";
	28	+};
	29	+
	30	+&iomuxc {
	31	+ imx7ulp-evk {
	32	+ pinctrl_qspi1_1: qspi1grp_1 {
	33	+ fsl,pins = <
	34	+ ULP1_PAD_PTB7_LLWU0_P11__QSPIA_SS1_B 0x43 /* SS1 */
	35	+ ULP1_PAD_PTB8__QSPIA_SS0_B 0x43 /* SS0 */
	36	+ ULP1_PAD_PTB15__QSPIA_SCLK 0x43 /* SCLK */
	37	+ ULP1_PAD_PTB9_LLWU0_P12__QSPIA_DQS 0x43 /* DQS */
	38	+ ULP1_PAD_PTB16_LLWU0_P14__QSPIA_DATA3 0x43 /* D3 */
	39	+ ULP1_PAD_PTB17__QSPIA_DATA2 0x43 /* D2 */
	40	+ ULP1_PAD_PTB18__QSPIA_DATA1 0x43 /* D1 */
	41	+ ULP1_PAD_PTB19_LLWU0_P15__QSPIA_DATA0 0x43 /* D0 */
	42	+ >;
	43	+ };
	44	+ };
	45	+};
...	...	@@ -31,6 +31,7 @@
31	31	i2c5 = &lpi2c5;
32	32	i2c6 = &lpi2c6;
33	33	i2c7 = &lpi2c7;
	34	+ spi0 = &qspi1;
34	35	};
35	36
36	37	cpus {
...	...	@@ -13,6 +13,7 @@
13	13	DECLARE_GLOBAL_DATA_PTR;
14	14
15	15	#define UART_PAD_CTRL (PAD_CTL_PUS_UP)
	16	+#define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP \| PAD_CTL_DSE)
16	17
17	18	int dram_init(void)
18	19	{
...	...	@@ -32,6 +33,36 @@
32	33	ARRAY_SIZE(lpuart4_pads));
33	34	}
34	35
	36	+#ifdef CONFIG_FSL_QSPI
	37	+#ifndef CONFIG_DM_SPI
	38	+static iomux_cfg_t const quadspi_pads[] = {
	39	+ MX7ULP_PAD_PTB8__QSPIA_SS0_B \| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	40	+ MX7ULP_PAD_PTB15__QSPIA_SCLK \| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	41	+ MX7ULP_PAD_PTB16__QSPIA_DATA3 \| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	42	+ MX7ULP_PAD_PTB17__QSPIA_DATA2 \| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	43	+ MX7ULP_PAD_PTB18__QSPIA_DATA1 \| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	44	+ MX7ULP_PAD_PTB19__QSPIA_DATA0 \| MUX_PAD_CTRL(QSPI_PAD_CTRL1),
	45	+};
	46	+#endif
	47	+
	48	+int board_qspi_init(void)
	49	+{
	50	+ u32 val;
	51	+#ifndef CONFIG_DM_SPI
	52	+ mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
	53	+#endif
	54	+
	55	+ /* enable clock */
	56	+ val = readl(PCC1_RBASE + 0x94);
	57	+
	58	+ if (!(val & 0x20000000)) {
	59	+ writel(0x03000003, (PCC1_RBASE + 0x94));
	60	+ writel(0x43000003, (PCC1_RBASE + 0x94));
	61	+ }
	62	+ return 0;
	63	+}
	64	+#endif
	65	+
35	66	int board_early_init_f(void)
36	67	{
37	68	setup_iomux_uart();
...	...	@@ -43,6 +74,10 @@
43	74	{
44	75	/* address of boot parameters */
45	76	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	77	+
	78	+#ifdef CONFIG_FSL_QSPI
	79	+ board_qspi_init();
	80	+#endif
46	81
47	82	return 0;
48	83	}
...	...	@@ -2,7 +2,7 @@
2	2	CONFIG_ARCH_MX7ULP=y
3	3	CONFIG_SYS_TEXT_BASE=0x67800000
4	4	CONFIG_TARGET_MX7ULP_EVK=y
5		-CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
	5	+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi"
6	6	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
7	7	CONFIG_HUSH_PARSER=y
8	8	CONFIG_CMD_BOOTZ=y
...	...	@@ -25,4 +25,10 @@
25	25	CONFIG_DM_REGULATOR_GPIO=y
26	26	CONFIG_DM_SERIAL=y
27	27	CONFIG_FSL_LPUART=y
	28	+CONFIG_CMD_SF=y
	29	+CONFIG_FSL_QSPI=y
	30	+CONFIG_DM_SPI=y
	31	+CONFIG_DM_SPI_FLASH=y
	32	+CONFIG_SPI_FLASH=y
	33	+CONFIG_SPI_FLASH_MACRONIX=y
...	...	@@ -2,7 +2,8 @@
2	2	CONFIG_ARCH_MX7ULP=y
3	3	CONFIG_SYS_TEXT_BASE=0x67800000
4	4	CONFIG_TARGET_MX7ULP_EVK=y
5		-CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
	5	+CONFIG_USE_IMXIMG_PLUGIN=y
	6	+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi"
6	7	CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
7	8	CONFIG_HUSH_PARSER=y
8	9	CONFIG_CMD_GPIO=y
...	...	@@ -24,4 +25,10 @@
24	25	CONFIG_DM_REGULATOR_GPIO=y
25	26	CONFIG_DM_SERIAL=y
26	27	CONFIG_FSL_LPUART=y
	28	+CONFIG_CMD_SF=y
	29	+CONFIG_FSL_QSPI=y
	30	+CONFIG_DM_SPI=y
	31	+CONFIG_DM_SPI_FLASH=y
	32	+CONFIG_SPI_FLASH=y
	33	+CONFIG_SPI_FLASH_MACRONIX=y
...	...	@@ -179,6 +179,19 @@
179	179	#define CONFIG_CMD_CACHE
180	180	#endif
181	181
	182	+/* QSPI configs */
	183	+#ifdef CONFIG_FSL_QSPI
	184	+#define CONFIG_SYS_FSL_QSPI_AHB
	185	+#define CONFIG_SF_DEFAULT_BUS 0
	186	+#define CONFIG_SF_DEFAULT_CS 0
	187	+#define CONFIG_SF_DEFAULT_SPEED 40000000
	188	+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
	189	+#define FSL_QSPI_FLASH_NUM 1
	190	+#define FSL_QSPI_FLASH_SIZE SZ_8M
	191	+#define QSPI0_BASE_ADDR 0x410A5000
	192	+#define QSPI0_AMBA_BASE 0xC0000000
	193	+#endif
	194	+
182	195	#define CONFIG_OF_SYSTEM_SETUP
183	196
184	197	#endif /* __CONFIG_H */