arm: socfpga: clock: Trim down code duplication

Pull out functions to read frequency of Main clock VCO and PLL clock VCO as the code is duplicated multiple times. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: clock: Trim down code duplication
Pull out functions to read frequency of Main clock VCO and PLL clock VCO as the code is duplicated multiple times. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
Marek Vasut
1 parent a832ddba55
Showing 1 changed file with 38 additions and 58 deletions Side-by-side Diff
arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -361,7 +361,7 @@
 	writel(~0, &clock_manager_base->sdr_pll.en);
 }
  
-unsigned long cm_get_mpu_clk_hz(void)
+static unsigned int cm_get_main_vco_clk_hz(void)
 {
 	uint32_t reg, clock;
  
@@ -371,6 +371,37 @@
 		(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
 	clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
  
+	return clock;
+}
+
+static unsigned int cm_get_per_vco_clk_hz(void)
+{
+	uint32_t reg, clock = 0;
+
+	/* identify PER PLL clock source */
+	reg = readl(&clock_manager_base->per_pll.vco);
+	reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
+	if (reg == CLKMGR_VCO_SSRC_EOSC1)
+		clock = CONFIG_HPS_CLK_OSC1_HZ;
+	else if (reg == CLKMGR_VCO_SSRC_EOSC2)
+		clock = CONFIG_HPS_CLK_OSC2_HZ;
+	else if (reg == CLKMGR_VCO_SSRC_F2S)
+		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+
+	/* get the PER VCO clock */
+	reg = readl(&clock_manager_base->per_pll.vco);
+	clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
+	clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+
+	return clock;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+	uint32_t reg, clock;
+
+	clock = cm_get_main_vco_clk_hz();
+
 	/* get the MPU clock */
 	reg = readl(&clock_manager_base->altera.mpuclk);
 	clock /= (reg + 1);
@@ -415,11 +446,7 @@
 	reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg);
  
 	if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
-		/* get the main VCO clock */
-		reg = readl(&clock_manager_base->main_pll.vco);
-		clock = CONFIG_HPS_CLK_OSC1_HZ /
-			(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
-		clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+		clock = cm_get_main_vco_clk_hz();
  
 		/* get the clock prior L4 SP divider (main clk) */
 		reg = readl(&clock_manager_base->altera.mainclk);
  
@@ -427,21 +454,8 @@
 		reg = readl(&clock_manager_base->main_pll.mainclk);
 		clock /= (reg + 1);
 	} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
-		/* identify PER PLL clock source */
-		reg = readl(&clock_manager_base->per_pll.vco);
-		reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
-		if (reg == CLKMGR_VCO_SSRC_EOSC1)
-			clock = CONFIG_HPS_CLK_OSC1_HZ;
-		else if (reg == CLKMGR_VCO_SSRC_EOSC2)
-			clock = CONFIG_HPS_CLK_OSC2_HZ;
-		else if (reg == CLKMGR_VCO_SSRC_F2S)
-			clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+		clock = cm_get_per_vco_clk_hz();
  
-		/* get the PER VCO clock */
-		reg = readl(&clock_manager_base->per_pll.vco);
-		clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
-		clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
-
 		/* get the clock prior L4 SP divider (periph_base_clk) */
 		reg = readl(&clock_manager_base->per_pll.perbaseclk);
 		clock /= (reg + 1);
  
  
@@ -466,31 +480,14 @@
 	if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
 		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
 	} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
-		/* get the main VCO clock */
-		reg = readl(&clock_manager_base->main_pll.vco);
-		clock = CONFIG_HPS_CLK_OSC1_HZ /
-			(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
-		clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+		clock = cm_get_main_vco_clk_hz();
  
 		/* get the SDMMC clock */
 		reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
 		clock /= (reg + 1);
 	} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
-		/* identify PER PLL clock source */
-		reg = readl(&clock_manager_base->per_pll.vco);
-		reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
-		if (reg == CLKMGR_VCO_SSRC_EOSC1)
-			clock = CONFIG_HPS_CLK_OSC1_HZ;
-		else if (reg == CLKMGR_VCO_SSRC_EOSC2)
-			clock = CONFIG_HPS_CLK_OSC2_HZ;
-		else if (reg == CLKMGR_VCO_SSRC_F2S)
-			clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
+		clock = cm_get_per_vco_clk_hz();
  
-		/* get the PER VCO clock */
-		reg = readl(&clock_manager_base->per_pll.vco);
-		clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
-		clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
-
 		/* get the SDMMC clock */
 		reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
 		clock /= (reg + 1);
  
@@ -512,30 +509,13 @@
 	if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
 		clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
 	} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
-		/* get the main VCO clock */
-		reg = readl(&clock_manager_base->main_pll.vco);
-		clock = CONFIG_HPS_CLK_OSC1_HZ /
-			(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
-		clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
+		clock = cm_get_main_vco_clk_hz();
  
 		/* get the qspi clock */
 		reg = readl(&clock_manager_base->main_pll.mainqspiclk);
 		clock /= (reg + 1);
 	} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
-		/* identify PER PLL clock source */
-		reg = readl(&clock_manager_base->per_pll.vco);
-		reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
-		if (reg == CLKMGR_VCO_SSRC_EOSC1)
-			clock = CONFIG_HPS_CLK_OSC1_HZ;
-		else if (reg == CLKMGR_VCO_SSRC_EOSC2)
-			clock = CONFIG_HPS_CLK_OSC2_HZ;
-		else if (reg == CLKMGR_VCO_SSRC_F2S)
-			clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
-
-		/* get the PER VCO clock */
-		reg = readl(&clock_manager_base->per_pll.vco);
-		clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
-		clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
+		clock = cm_get_per_vco_clk_hz();
  
 		/* get the qspi clock */
 		reg = readl(&clock_manager_base->per_pll.perqspiclk);
...	...	@@ -361,7 +361,7 @@
361	361	writel(~0, &clock_manager_base->sdr_pll.en);
362	362	}
363	363
364		-unsigned long cm_get_mpu_clk_hz(void)
	364	+static unsigned int cm_get_main_vco_clk_hz(void)
365	365	{
366	366	uint32_t reg, clock;
367	367
...	...	@@ -371,6 +371,37 @@
371	371	(CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
372	372	clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
373	373
	374	+ return clock;
	375	+}
	376	+
	377	+static unsigned int cm_get_per_vco_clk_hz(void)
	378	+{
	379	+ uint32_t reg, clock = 0;
	380	+
	381	+ /* identify PER PLL clock source */
	382	+ reg = readl(&clock_manager_base->per_pll.vco);
	383	+ reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
	384	+ if (reg == CLKMGR_VCO_SSRC_EOSC1)
	385	+ clock = CONFIG_HPS_CLK_OSC1_HZ;
	386	+ else if (reg == CLKMGR_VCO_SSRC_EOSC2)
	387	+ clock = CONFIG_HPS_CLK_OSC2_HZ;
	388	+ else if (reg == CLKMGR_VCO_SSRC_F2S)
	389	+ clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
	390	+
	391	+ /* get the PER VCO clock */
	392	+ reg = readl(&clock_manager_base->per_pll.vco);
	393	+ clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
	394	+ clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
	395	+
	396	+ return clock;
	397	+}
	398	+
	399	+unsigned long cm_get_mpu_clk_hz(void)
	400	+{
	401	+ uint32_t reg, clock;
	402	+
	403	+ clock = cm_get_main_vco_clk_hz();
	404	+
374	405	/* get the MPU clock */
375	406	reg = readl(&clock_manager_base->altera.mpuclk);
376	407	clock /= (reg + 1);
...	...	@@ -415,11 +446,7 @@
415	446	reg = CLKMGR_MAINPLLGRP_L4SRC_L4SP_GET(reg);
416	447
417	448	if (reg == CLKMGR_L4_SP_CLK_SRC_MAINPLL) {
418		- /* get the main VCO clock */
419		- reg = readl(&clock_manager_base->main_pll.vco);
420		- clock = CONFIG_HPS_CLK_OSC1_HZ /
421		- (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
422		- clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
	449	+ clock = cm_get_main_vco_clk_hz();
423	450
424	451	/* get the clock prior L4 SP divider (main clk) */
425	452	reg = readl(&clock_manager_base->altera.mainclk);
426	453
...	...	@@ -427,21 +454,8 @@
427	454	reg = readl(&clock_manager_base->main_pll.mainclk);
428	455	clock /= (reg + 1);
429	456	} else if (reg == CLKMGR_L4_SP_CLK_SRC_PERPLL) {
430		- /* identify PER PLL clock source */
431		- reg = readl(&clock_manager_base->per_pll.vco);
432		- reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
433		- if (reg == CLKMGR_VCO_SSRC_EOSC1)
434		- clock = CONFIG_HPS_CLK_OSC1_HZ;
435		- else if (reg == CLKMGR_VCO_SSRC_EOSC2)
436		- clock = CONFIG_HPS_CLK_OSC2_HZ;
437		- else if (reg == CLKMGR_VCO_SSRC_F2S)
438		- clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
	457	+ clock = cm_get_per_vco_clk_hz();
439	458
440		- /* get the PER VCO clock */
441		- reg = readl(&clock_manager_base->per_pll.vco);
442		- clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
443		- clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
444		-
445	459	/* get the clock prior L4 SP divider (periph_base_clk) */
446	460	reg = readl(&clock_manager_base->per_pll.perbaseclk);
447	461	clock /= (reg + 1);
448	462
449	463
...	...	@@ -466,31 +480,14 @@
466	480	if (reg == CLKMGR_SDMMC_CLK_SRC_F2S) {
467	481	clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
468	482	} else if (reg == CLKMGR_SDMMC_CLK_SRC_MAIN) {
469		- /* get the main VCO clock */
470		- reg = readl(&clock_manager_base->main_pll.vco);
471		- clock = CONFIG_HPS_CLK_OSC1_HZ /
472		- (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
473		- clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
	483	+ clock = cm_get_main_vco_clk_hz();
474	484
475	485	/* get the SDMMC clock */
476	486	reg = readl(&clock_manager_base->main_pll.mainnandsdmmcclk);
477	487	clock /= (reg + 1);
478	488	} else if (reg == CLKMGR_SDMMC_CLK_SRC_PER) {
479		- /* identify PER PLL clock source */
480		- reg = readl(&clock_manager_base->per_pll.vco);
481		- reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
482		- if (reg == CLKMGR_VCO_SSRC_EOSC1)
483		- clock = CONFIG_HPS_CLK_OSC1_HZ;
484		- else if (reg == CLKMGR_VCO_SSRC_EOSC2)
485		- clock = CONFIG_HPS_CLK_OSC2_HZ;
486		- else if (reg == CLKMGR_VCO_SSRC_F2S)
487		- clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
	489	+ clock = cm_get_per_vco_clk_hz();
488	490
489		- /* get the PER VCO clock */
490		- reg = readl(&clock_manager_base->per_pll.vco);
491		- clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
492		- clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
493		-
494	491	/* get the SDMMC clock */
495	492	reg = readl(&clock_manager_base->per_pll.pernandsdmmcclk);
496	493	clock /= (reg + 1);
497	494
...	...	@@ -512,30 +509,13 @@
512	509	if (reg == CLKMGR_QSPI_CLK_SRC_F2S) {
513	510	clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
514	511	} else if (reg == CLKMGR_QSPI_CLK_SRC_MAIN) {
515		- /* get the main VCO clock */
516		- reg = readl(&clock_manager_base->main_pll.vco);
517		- clock = CONFIG_HPS_CLK_OSC1_HZ /
518		- (CLKMGR_MAINPLLGRP_VCO_DENOM_GET(reg) + 1);
519		- clock *= (CLKMGR_MAINPLLGRP_VCO_NUMER_GET(reg) + 1);
	512	+ clock = cm_get_main_vco_clk_hz();
520	513
521	514	/* get the qspi clock */
522	515	reg = readl(&clock_manager_base->main_pll.mainqspiclk);
523	516	clock /= (reg + 1);
524	517	} else if (reg == CLKMGR_QSPI_CLK_SRC_PER) {
525		- /* identify PER PLL clock source */
526		- reg = readl(&clock_manager_base->per_pll.vco);
527		- reg = CLKMGR_PERPLLGRP_VCO_SSRC_GET(reg);
528		- if (reg == CLKMGR_VCO_SSRC_EOSC1)
529		- clock = CONFIG_HPS_CLK_OSC1_HZ;
530		- else if (reg == CLKMGR_VCO_SSRC_EOSC2)
531		- clock = CONFIG_HPS_CLK_OSC2_HZ;
532		- else if (reg == CLKMGR_VCO_SSRC_F2S)
533		- clock = CONFIG_HPS_CLK_F2S_PER_REF_HZ;
534		-
535		- /* get the PER VCO clock */
536		- reg = readl(&clock_manager_base->per_pll.vco);
537		- clock /= (CLKMGR_PERPLLGRP_VCO_DENOM_GET(reg) + 1);
538		- clock *= (CLKMGR_PERPLLGRP_VCO_NUMER_GET(reg) + 1);
	518	+ clock = cm_get_per_vco_clk_hz();
539	519
540	520	/* get the qspi clock */
541	521	reg = readl(&clock_manager_base->per_pll.perqspiclk);