Eric Lee / smarc-uboot

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Commit 462883d1a88e59fd2b854c3f751e75a329fad500

Authored by Ye Li
1 parent 6891e8b4a3
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

MLK-18152-2 mx6sxsabresd: Update board codes to align with v2019.04 

Add emmc support which needs board rework.
Add I2C2.
Update DM PMIC settings and LDO bypass support.
Add BMODE support.
Add LVDS and LCD splash screen support
Add PCI power and reset GPIO and disable PCI at default.
Update QSPI settings for QSPI boot and M4 fastup.
Update environment settings

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e74716b6e78f016226dc9f800b04574f545d9367)
(cherry picked from commit f3dd07286dc39d3028deaedf5dc1668929cbfd29)

Showing 6 changed files with 813 additions and 61 deletions Side-by-side Diff

board/freescale/mx6sxsabresd/Kconfig
Diff comments   View file @ 462883d
... ... @@ -9,5 +9,10 @@
9 9 config SYS_CONFIG_NAME
10 10 default "mx6sxsabresd"
11 11  
  12 +config MX6SXSABRESD_EMMC_REWORK
  13 + bool "Select for the board with eMMC rework"
  14 +
  15 +config SYS_TEXT_BASE
  16 + default 0x87800000
12 17 endif
board/freescale/mx6sxsabresd/imximage.cfg
Diff comments   View file @ 462883d
1 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 2 /*
3   - * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
4 4 */
5 5  
6 6 #define __ASSEMBLY__
7 7  
8 8  
... ... @@ -15,8 +15,17 @@
15 15 * spi/sd/nand/onenand, qspi/nor
16 16 */
17 17  
  18 +#ifdef CONFIG_QSPI_BOOT
  19 +BOOT_FROM qspi
  20 +#else
18 21 BOOT_FROM sd
  22 +#endif
19 23  
  24 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  25 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  26 +PLUGIN board/freescale/mx6sxsabresd/plugin.bin 0x00907000
  27 +#else
  28 +
20 29 /*
21 30 * Secure boot support
22 31 */
... ... @@ -136,4 +145,5 @@
136 145 DATA 4 0x021b0020 0x00000800
137 146 DATA 4 0x021b0818 0x00011117
138 147 DATA 4 0x021b001c 0x00000000
  148 +#endif
board/freescale/mx6sxsabresd/mx6sxsabresd.c
Diff comments   View file @ 462883d
1 1 // SPDX-License-Identifier: GPL-2.0+
2 2 /*
3   - * Copyright (C) 2014 Freescale Semiconductor, Inc.
  3 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  4 + * Copyright 2017 NXP
4 5 *
5 6 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 7 */
... ... @@ -14,6 +15,7 @@
14 15 #include <asm/arch/sys_proto.h>
15 16 #include <asm/gpio.h>
16 17 #include <asm/mach-imx/iomux-v3.h>
  18 +#include <asm/mach-imx/boot_mode.h>
17 19 #include <asm/io.h>
18 20 #include <asm/mach-imx/mxc_i2c.h>
19 21 #include <env.h>
20 22  
... ... @@ -27,7 +29,14 @@
27 29 #include <power/pmic.h>
28 30 #include <power/pfuze100_pmic.h>
29 31 #include "../common/pfuze.h"
  32 +#include <usb.h>
  33 +#include <usb/ehci-ci.h>
  34 +#include <asm/mach-imx/video.h>
30 35  
  36 +#ifdef CONFIG_IMX_RDC
  37 +#include <asm/mach-imx/rdc-sema.h>
  38 +#include <asm/arch/imx-rdc.h>
  39 +#endif
31 40 DECLARE_GLOBAL_DATA_PTR;
32 41  
33 42 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
... ... @@ -38,6 +47,11 @@
38 47 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
39 48 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40 49  
  50 +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  51 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  52 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  53 + PAD_CTL_ODE)
  54 +
41 55 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
42 56 PAD_CTL_SPEED_HIGH | \
43 57 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
44 58  
... ... @@ -48,12 +62,21 @@
48 62 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
49 63 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
50 64  
  65 +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  66 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  67 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  68 + PAD_CTL_ODE)
  69 +
51 70 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
52 71 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
53 72  
54 73 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
55 74 PAD_CTL_DSE_40ohm)
56 75  
  76 +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  77 + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  78 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  79 +
57 80 int dram_init(void)
58 81 {
59 82 gd->ram_size = imx_ddr_size();
60 83  
... ... @@ -66,25 +89,63 @@
66 89 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
67 90 };
68 91  
  92 +static iomux_v3_cfg_t const usdhc2_pads[] = {
  93 + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94 + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95 + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96 + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97 + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98 + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99 +};
  100 +
  101 +static iomux_v3_cfg_t const usdhc3_pads[] = {
  102 + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  103 + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  104 + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  105 + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  106 + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  107 + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  108 + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  109 + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  110 + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  111 + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  112 +
  113 + /* CD pin */
  114 + MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  115 +
  116 + /* RST_B, used for power reset cycle */
  117 + MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  118 +};
  119 +
  120 +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
  121 +static iomux_v3_cfg_t const usdhc4_emmc_pads[] = {
  122 + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  123 + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  124 + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  125 + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  126 + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  127 + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  128 + MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  129 + MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  130 + MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  131 + MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  132 + MX6_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  133 +};
  134 +#else
  135 +static iomux_v3_cfg_t const usdhc4_pads[] = {
  136 + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  137 + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  138 + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  139 + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  140 + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  141 + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  142 + MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
  143 +};
  144 +#endif
  145 +
69 146 static iomux_v3_cfg_t const wdog_b_pad = {
70 147 MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
71 148 };
72   -static iomux_v3_cfg_t const fec1_pads[] = {
73   - MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
74   - MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
75   - MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
76   - MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
77   - MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
78   - MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
79   - MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
80   - MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
81   - MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
82   - MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
83   - MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
84   - MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
85   - MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
86   - MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
87   -};
88 149  
89 150 static iomux_v3_cfg_t const peri_3v3_pads[] = {
90 151 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
... ... @@ -101,6 +162,20 @@
101 162 MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
102 163 };
103 164  
  165 +#ifdef CONFIG_PCIE_IMX
  166 +iomux_v3_cfg_t const pcie_pads[] = {
  167 + MX6_PAD_ENET1_COL__GPIO2_IO_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
  168 + MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
  169 +};
  170 +
  171 +static void setup_pcie(void)
  172 +{
  173 + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
  174 + gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "PCIE Power Enable");
  175 + gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "PCIE Reset");
  176 +}
  177 +#endif
  178 +
104 179 static void setup_iomux_uart(void)
105 180 {
106 181 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
107 182  
108 183  
109 184  
110 185  
111 186  
112 187  
... ... @@ -111,26 +186,57 @@
111 186 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
112 187 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
113 188 int reg, ret;
  189 + struct gpio_desc desc;
114 190  
115   - /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
  191 + /* Use 125M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
116 192 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
117 193  
  194 + /* Use 125M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/
  195 + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
  196 +
118 197 ret = enable_fec_anatop_clock(0, ENET_125MHZ);
119 198 if (ret)
120 199 return ret;
121 200  
  201 + ret = enable_fec_anatop_clock(1, ENET_125MHZ);
  202 + if (ret)
  203 + return ret;
  204 +
122 205 imx_iomux_v3_setup_multiple_pads(phy_control_pads,
123 206 ARRAY_SIZE(phy_control_pads));
124 207  
125 208 /* Enable the ENET power, active low */
126   - gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
127   - gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
  209 + ret = dm_gpio_lookup_name("GPIO2_6", &desc);
  210 + if (ret) {
  211 + printf("%s lookup GPIO2_6 failed ret = %d\n", __func__, ret);
  212 + return ret;
  213 + }
128 214  
129   - /* Reset AR8031 PHY */
130   - gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
131   - gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
  215 + ret = dm_gpio_request(&desc, "fec power en");
  216 + if (ret) {
  217 + printf("%s request fec power en failed ret = %d\n", __func__, ret);
  218 + return ret;
  219 + }
  220 +
  221 + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
  222 + dm_gpio_set_value(&desc, 0);
  223 +
  224 + ret = dm_gpio_lookup_name("GPIO2_7", &desc);
  225 + if (ret) {
  226 + printf("%s lookup GPIO2_7 failed ret = %d\n", __func__, ret);
  227 + return ret;
  228 + }
  229 +
  230 + ret = dm_gpio_request(&desc, "ar8031 reset");
  231 + if (ret) {
  232 + printf("%s request ar8031 reset failed ret = %d\n", __func__, ret);
  233 + return ret;
  234 + }
  235 +
  236 + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
  237 + dm_gpio_set_value(&desc, 0);
132 238 mdelay(10);
133   - gpio_set_value(IMX_GPIO_NR(2, 7), 1);
  239 + dm_gpio_set_value(&desc, 1);
134 240  
135 241 reg = readl(&anatop->pll_enet);
136 242 reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
137 243  
138 244  
139 245  
... ... @@ -139,14 +245,85 @@
139 245 return 0;
140 246 }
141 247  
142   -int board_eth_init(bd_t *bis)
  248 +#ifdef CONFIG_SYS_I2C
  249 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  250 +/* I2C1 for PMIC */
  251 +static struct i2c_pads_info i2c_pad_info1 = {
  252 + .scl = {
  253 + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
  254 + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
  255 + .gp = IMX_GPIO_NR(1, 0),
  256 + },
  257 + .sda = {
  258 + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
  259 + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
  260 + .gp = IMX_GPIO_NR(1, 1),
  261 + },
  262 +};
  263 +
  264 +/* I2C2 */
  265 +struct i2c_pads_info i2c_pad_info2 = {
  266 + .scl = {
  267 + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
  268 + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
  269 + .gp = IMX_GPIO_NR(1, 2),
  270 + },
  271 + .sda = {
  272 + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
  273 + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
  274 + .gp = IMX_GPIO_NR(1, 3),
  275 + },
  276 +};
  277 +#endif
  278 +
  279 +#ifdef CONFIG_POWER
  280 +int power_init_board(void)
143 281 {
144   - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
145   - setup_fec();
  282 + struct pmic *pfuze;
  283 + unsigned int reg;
  284 + int ret;
146 285  
147   - return cpu_eth_init(bis);
148   -}
  286 + pfuze = pfuze_common_init(I2C_PMIC);
  287 + if (!pfuze)
  288 + return -ENODEV;
149 289  
  290 + ret = pfuze_mode_init(pfuze, APS_PFM);
  291 + if (ret < 0)
  292 + return ret;
  293 +
  294 + /* set SW1AB standby volatage 1.10V */
  295 + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);
  296 + reg &= ~0x3f;
  297 + reg |= PFUZE100_SW1ABC_SETP(11000);
  298 + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
  299 +
  300 + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  301 + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);
  302 + reg &= ~0xc0;
  303 + reg |= 0x40;
  304 + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
  305 +
  306 + /* set SW1C standby volatage 1.10V */
  307 + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
  308 + reg &= ~0x3f;
  309 + reg |= PFUZE100_SW1ABC_SETP(11000);
  310 + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
  311 +
  312 + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
  313 + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
  314 + reg &= ~0xc0;
  315 + reg |= 0x40;
  316 + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
  317 +
  318 + /* Enable power of VGEN5 3V3, needed for SD3 */
  319 + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &reg);
  320 + reg &= ~LDO_VOL_MASK;
  321 + reg |= (LDOB_3_30V | (1 << LDO_EN));
  322 + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg);
  323 +
  324 + return 0;
  325 +}
  326 +#elif defined(CONFIG_DM_PMIC_PFUZE100)
150 327 int power_init_board(void)
151 328 {
152 329 struct udevice *dev;
153 330  
154 331  
155 332  
... ... @@ -161,14 +338,176 @@
161 338 if (ret < 0)
162 339 return ret;
163 340  
  341 + /* set SW1AB staby volatage 0.975V*/
  342 + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
  343 + reg &= ~0x3f;
  344 + reg |= PFUZE100_SW1ABC_SETP(11000);
  345 + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
  346 +
  347 + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  348 + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
  349 + reg &= ~0xc0;
  350 + reg |= 0x40;
  351 + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
  352 +
  353 + /* set SW1C staby volatage 0.975V*/
  354 + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
  355 + reg &= ~0x3f;
  356 + reg |= PFUZE100_SW1ABC_SETP(11000);
  357 + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
  358 +
  359 + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
  360 + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
  361 + reg &= ~0xc0;
  362 + reg |= 0x40;
  363 + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
  364 +
164 365 /* Enable power of VGEN5 3V3, needed for SD3 */
165 366 reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
166 367 reg &= ~LDO_VOL_MASK;
167 368 reg |= (LDOB_3_30V | (1 << LDO_EN));
168 369 pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
  370 + return 0;
  371 +}
  372 +#endif
169 373  
  374 +#ifdef CONFIG_LDO_BYPASS_CHECK
  375 +#ifdef CONFIG_POWER
  376 +void ldo_mode_set(int ldo_bypass)
  377 +{
  378 + unsigned int value;
  379 + int is_400M;
  380 + u32 vddarm;
  381 + struct pmic *p = pmic_get("PFUZE100");
  382 +
  383 + if (!p) {
  384 + printf("No PMIC found!\n");
  385 + return;
  386 + }
  387 +
  388 + /* switch to ldo_bypass mode */
  389 + if (ldo_bypass) {
  390 + prep_anatop_bypass();
  391 + /* decrease VDDARM to 1.275V */
  392 + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
  393 + value &= ~0x3f;
  394 + value |= PFUZE100_SW1ABC_SETP(12750);
  395 + pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
  396 +
  397 + /* decrease VDDSOC to 1.3V */
  398 + pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
  399 + value &= ~0x3f;
  400 + value |= PFUZE100_SW1ABC_SETP(13000);
  401 + pmic_reg_write(p, PFUZE100_SW1CVOL, value);
  402 +
  403 + is_400M = set_anatop_bypass(1);
  404 + if (is_400M)
  405 + vddarm = PFUZE100_SW1ABC_SETP(10750);
  406 + else
  407 + vddarm = PFUZE100_SW1ABC_SETP(11750);
  408 +
  409 + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
  410 + value &= ~0x3f;
  411 + value |= vddarm;
  412 + pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
  413 +
  414 + pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
  415 + value &= ~0x3f;
  416 + value |= PFUZE100_SW1ABC_SETP(11750);
  417 + pmic_reg_write(p, PFUZE100_SW1CVOL, value);
  418 +
  419 + finish_anatop_bypass();
  420 + printf("switch to ldo_bypass mode!\n");
  421 + }
  422 +
  423 +}
  424 +#elif defined(CONFIG_DM_PMIC_PFUZE100)
  425 +void ldo_mode_set(int ldo_bypass)
  426 +{
  427 + struct udevice *dev;
  428 + int ret;
  429 + int is_400M;
  430 + u32 vddarm;
  431 +
  432 + ret = pmic_get("pfuze100@8", &dev);
  433 + if (ret == -ENODEV) {
  434 + printf("No PMIC found!\n");
  435 + return;
  436 + }
  437 +
  438 + /* switch to ldo_bypass mode , boot on 800Mhz */
  439 + if (ldo_bypass) {
  440 + prep_anatop_bypass();
  441 +
  442 + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
  443 + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
  444 +
  445 + /* increase VDDSOC to 1.3V */
  446 + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000));
  447 +
  448 + is_400M = set_anatop_bypass(1);
  449 + if (is_400M)
  450 + vddarm = PFUZE100_SW1ABC_SETP(10750);
  451 + else
  452 + vddarm = PFUZE100_SW1ABC_SETP(11750);
  453 +
  454 + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
  455 +
  456 + /* decrease VDDSOC to 1.175V */
  457 + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750));
  458 +
  459 + finish_anatop_bypass();
  460 + printf("switch to ldo_bypass mode!\n");
  461 + }
  462 +}
  463 +#endif
  464 +#endif
  465 +
  466 +#ifdef CONFIG_USB_EHCI_MX6
  467 +#ifndef CONFIG_DM_USB
  468 +
  469 +#define USB_OTHERREGS_OFFSET 0x800
  470 +#define UCTRL_PWR_POL (1 << 9)
  471 +
  472 +static iomux_v3_cfg_t const usb_otg_pads[] = {
  473 + /* OGT1 */
  474 + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  475 + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
  476 + /* OTG2 */
  477 + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
  478 +};
  479 +
  480 +static void setup_usb(void)
  481 +{
  482 + imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
  483 + ARRAY_SIZE(usb_otg_pads));
  484 +}
  485 +
  486 +int board_usb_phy_mode(int port)
  487 +{
  488 + if (port == 1)
  489 + return USB_INIT_HOST;
  490 + else
  491 + return usb_phy_mode(port);
  492 +}
  493 +
  494 +int board_ehci_hcd_init(int port)
  495 +{
  496 + u32 *usbnc_usb_ctrl;
  497 +
  498 + if (port > 1)
  499 + return -EINVAL;
  500 +
  501 + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
  502 + port * 4);
  503 +
  504 + /* Set Power polarity */
  505 + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
  506 +
170 507 return 0;
171 508 }
  509 +#endif
  510 +#endif
172 511  
173 512 int board_phy_config(struct phy_device *phydev)
174 513 {
175 514  
... ... @@ -189,8 +528,22 @@
189 528 return 0;
190 529 }
191 530  
  531 +#ifdef CONFIG_IMX_RDC
  532 +static rdc_peri_cfg_t const shared_resources[] = {
  533 + (RDC_PER_GPIO1 | RDC_DOMAIN(0) | RDC_DOMAIN(1)),
  534 +};
  535 +#endif
  536 +
192 537 int board_early_init_f(void)
193 538 {
  539 +#ifdef CONFIG_IMX_RDC
  540 + imx_rdc_setup_peripherals(shared_resources, ARRAY_SIZE(shared_resources));
  541 +#endif
  542 +
  543 +#ifdef CONFIG_SYS_AUXCORE_FASTUP
  544 + arch_auxiliary_core_up(0, CONFIG_SYS_AUXCORE_BOOTDATA);
  545 +#endif
  546 +
194 547 setup_iomux_uart();
195 548  
196 549 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
197 550  
198 551  
... ... @@ -200,11 +553,99 @@
200 553 return 0;
201 554 }
202 555  
203   -int board_mmc_get_env_dev(int devno)
  556 +static struct fsl_esdhc_cfg usdhc_cfg[3] = {
  557 + {USDHC2_BASE_ADDR, 0, 4},
  558 + {USDHC3_BASE_ADDR},
  559 +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
  560 + {USDHC4_BASE_ADDR, 0, 8},
  561 +#else
  562 + {USDHC4_BASE_ADDR},
  563 +#endif
  564 +};
  565 +
  566 +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
  567 +#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
  568 +#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
  569 +
  570 +int board_mmc_getcd(struct mmc *mmc)
204 571 {
205   - return devno;
  572 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  573 + int ret = 0;
  574 +
  575 + switch (cfg->esdhc_base) {
  576 + case USDHC2_BASE_ADDR:
  577 + ret = 1; /* Assume uSDHC2 is always present */
  578 + break;
  579 + case USDHC3_BASE_ADDR:
  580 + ret = !gpio_get_value(USDHC3_CD_GPIO);
  581 + break;
  582 + case USDHC4_BASE_ADDR:
  583 +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
  584 + ret = 1;
  585 +#else
  586 + ret = !gpio_get_value(USDHC4_CD_GPIO);
  587 +#endif
  588 + break;
  589 + }
  590 +
  591 + return ret;
206 592 }
207 593  
  594 +int board_mmc_init(bd_t *bis)
  595 +{
  596 + int i, ret;
  597 +
  598 + /*
  599 + * According to the board_mmc_init() the following map is done:
  600 + * (U-Boot device node) (Physical Port)
  601 + * mmc0 USDHC2
  602 + * mmc1 USDHC3
  603 + * mmc2 USDHC4
  604 + */
  605 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  606 + switch (i) {
  607 + case 0:
  608 + imx_iomux_v3_setup_multiple_pads(
  609 + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  610 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  611 + break;
  612 + case 1:
  613 + imx_iomux_v3_setup_multiple_pads(
  614 + usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  615 + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
  616 + gpio_request(USDHC3_PWR_GPIO, "usdhc3 pwr");
  617 + gpio_direction_input(USDHC3_CD_GPIO);
  618 + gpio_direction_output(USDHC3_PWR_GPIO, 1);
  619 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  620 + break;
  621 + case 2:
  622 +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
  623 + imx_iomux_v3_setup_multiple_pads(
  624 + usdhc4_emmc_pads, ARRAY_SIZE(usdhc4_emmc_pads));
  625 +#else
  626 + imx_iomux_v3_setup_multiple_pads(
  627 + usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  628 + gpio_request(USDHC4_CD_GPIO, "usdhc4 cd");
  629 + gpio_direction_input(USDHC4_CD_GPIO);
  630 +#endif
  631 + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  632 + break;
  633 + default:
  634 + printf("Warning: you configured more USDHC controllers"
  635 + "(%d) than supported by the board\n", i + 1);
  636 + return -EINVAL;
  637 + }
  638 +
  639 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  640 + if (ret) {
  641 + printf("Warning: failed to initialize mmc dev %d\n", i);
  642 + return ret;
  643 + }
  644 + }
  645 +
  646 + return 0;
  647 +}
  648 +
208 649 #ifdef CONFIG_FSL_QSPI
209 650  
210 651 int board_qspi_init(void)
211 652  
... ... @@ -216,7 +657,25 @@
216 657 }
217 658 #endif
218 659  
  660 +#ifdef CONFIG_CMD_BMODE
  661 +static const struct boot_mode board_boot_modes[] = {
  662 + /* 4 bit bus width */
  663 + {"sd3", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
  664 + {"sd4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  665 + {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)},
  666 + {NULL, 0},
  667 +};
  668 +#endif
  669 +
219 670 #ifdef CONFIG_VIDEO_MXS
  671 +static iomux_v3_cfg_t const lvds_ctrl_pads[] = {
  672 + /* CABC enable */
  673 + MX6_PAD_QSPI1A_DATA2__GPIO4_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
  674 +
  675 + /* Use GPIO for Brightness adjustment, duty cycle = period */
  676 + MX6_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL),
  677 +};
  678 +
220 679 static iomux_v3_cfg_t const lcd_pads[] = {
221 680 MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
222 681 MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
223 682  
224 683  
... ... @@ -252,10 +711,44 @@
252 711 MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
253 712 };
254 713  
255   -static int setup_lcd(void)
  714 +void do_enable_lvds(struct display_info_t const *dev)
256 715 {
257   - enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
  716 + int ret;
258 717  
  718 + ret = enable_lcdif_clock(dev->bus, 1);
  719 + if (ret) {
  720 + printf("Enable LCDIF clock failed, %d\n", ret);
  721 + return;
  722 + }
  723 + ret = enable_lvds_bridge(dev->bus);
  724 + if (ret) {
  725 + printf("Enable LVDS bridge failed, %d\n", ret);
  726 + return;
  727 + }
  728 +
  729 + imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads,
  730 + ARRAY_SIZE(lvds_ctrl_pads));
  731 +
  732 + /* Enable CABC */
  733 + gpio_request(IMX_GPIO_NR(4, 18), "CABC enable");
  734 + gpio_direction_output(IMX_GPIO_NR(4, 18) , 1);
  735 +
  736 + /* Set Brightness to high */
  737 + gpio_request(IMX_GPIO_NR(6, 3), "lvds backlight");
  738 + gpio_direction_output(IMX_GPIO_NR(6, 3) , 1);
  739 +}
  740 +
  741 +void do_enable_parallel_lcd(struct display_info_t const *dev)
  742 +
  743 +{
  744 + int ret;
  745 +
  746 + ret = enable_lcdif_clock(dev->bus, 1);
  747 + if (ret) {
  748 + printf("Enable LCDIF clock failed, %d\n", ret);
  749 + return;
  750 + }
  751 +
259 752 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
260 753  
261 754 /* Reset the LCD */
262 755  
... ... @@ -267,9 +760,48 @@
267 760 /* Set Brightness to high */
268 761 gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
269 762 gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
270   -
271   - return 0;
272 763 }
  764 +
  765 +struct display_info_t const displays[] = {{
  766 + .bus = LCDIF2_BASE_ADDR,
  767 + .addr = 0,
  768 + .pixfmt = 18,
  769 + .detect = NULL,
  770 + .enable = do_enable_lvds,
  771 + .mode = {
  772 + .name = "Hannstar-XGA",
  773 + .xres = 1024,
  774 + .yres = 768,
  775 + .pixclock = 15385,
  776 + .left_margin = 220,
  777 + .right_margin = 40,
  778 + .upper_margin = 21,
  779 + .lower_margin = 7,
  780 + .hsync_len = 60,
  781 + .vsync_len = 10,
  782 + .sync = 0,
  783 + .vmode = FB_VMODE_NONINTERLACED
  784 +} }, {
  785 + .bus = MX6SX_LCDIF1_BASE_ADDR,
  786 + .addr = 0,
  787 + .pixfmt = 24,
  788 + .detect = NULL,
  789 + .enable = do_enable_parallel_lcd,
  790 + .mode = {
  791 + .name = "MCIMX28LCD",
  792 + .xres = 800,
  793 + .yres = 480,
  794 + .pixclock = 29850,
  795 + .left_margin = 89,
  796 + .right_margin = 164,
  797 + .upper_margin = 23,
  798 + .lower_margin = 10,
  799 + .hsync_len = 10,
  800 + .vsync_len = 10,
  801 + .sync = 0,
  802 + .vmode = FB_VMODE_NONINTERLACED
  803 +} } };
  804 +size_t display_count = ARRAY_SIZE(displays);
273 805 #endif
274 806  
275 807 int board_init(void)
276 808  
277 809  
... ... @@ -290,14 +822,30 @@
290 822 gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
291 823 gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
292 824  
  825 +#ifdef CONFIG_SYS_I2C
  826 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  827 + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  828 +#endif
  829 +
  830 +#ifdef CONFIG_USB_EHCI_MX6
  831 +#ifndef CONFIG_DM_USB
  832 + setup_usb();
  833 +#endif
  834 +#endif
  835 +
293 836 #ifdef CONFIG_FSL_QSPI
294 837 board_qspi_init();
295 838 #endif
296 839  
297   -#ifdef CONFIG_VIDEO_MXS
298   - setup_lcd();
  840 +#ifdef CONFIG_PCIE_IMX
  841 + setup_pcie();
299 842 #endif
300 843  
  844 + /* Also used for OF_CONTROL enabled */
  845 +#ifdef CONFIG_FEC_MXC
  846 + setup_fec();
  847 +#endif
  848 +
301 849 return 0;
302 850 }
303 851  
... ... @@ -311,6 +859,14 @@
311 859 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
312 860 if (is_reva())
313 861 env_set("board_rev", "REVA");
  862 +#endif
  863 +
  864 +#ifdef CONFIG_CMD_BMODE
  865 + add_board_boot_modes(board_boot_modes);
  866 +#endif
  867 +
  868 +#ifdef CONFIG_ENV_IS_IN_MMC
  869 + board_late_mmc_env_init();
314 870 #endif
315 871 return 0;
316 872 }
board/freescale/mx6sxsabresd/plugin.S
Diff comments   View file @ 462883d
  1 +/*
  2 + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <config.h>
  8 +
  9 +/* DDR script */
  10 +.macro imx6sx_sabresd_ddr_setting
  11 + ldr r0, =IOMUXC_BASE_ADDR
  12 + ldr r1, =0x000c0000
  13 + str r1, [r0, #0x618]
  14 + ldr r1, =0x00000000
  15 + str r1, [r0, #0x5fc]
  16 + ldr r1, =0x00000030
  17 + str r1, [r0, #0x32c]
  18 +
  19 + ldr r1, =0x00000020
  20 + str r1, [r0, #0x300]
  21 + str r1, [r0, #0x2fc]
  22 + str r1, [r0, #0x5f4]
  23 + str r1, [r0, #0x340]
  24 +
  25 + ldr r1, =0x00000000
  26 + str r1, [r0, #0x320]
  27 + ldr r1, =0x00000020
  28 + str r1, [r0, #0x310]
  29 + str r1, [r0, #0x314]
  30 + str r1, [r0, #0x614]
  31 +
  32 + ldr r1, =0x00020000
  33 + str r1, [r0, #0x5f8]
  34 + ldr r1, =0x00000028
  35 + str r1, [r0, #0x330]
  36 + str r1, [r0, #0x334]
  37 + str r1, [r0, #0x338]
  38 + str r1, [r0, #0x33c]
  39 + ldr r1, =0x00020000
  40 + str r1, [r0, #0x608]
  41 + ldr r1, =0x00000028
  42 + str r1, [r0, #0x60c]
  43 + str r1, [r0, #0x610]
  44 + str r1, [r0, #0x61c]
  45 + str r1, [r0, #0x620]
  46 + str r1, [r0, #0x2ec]
  47 + str r1, [r0, #0x2f0]
  48 + str r1, [r0, #0x2f4]
  49 + str r1, [r0, #0x2f8]
  50 +
  51 + ldr r0, =MMDC_P0_BASE_ADDR
  52 + ldr r2, =0xa1390003
  53 + str r2, [r0, #0x800]
  54 + ldr r2, =0x00290025
  55 + str r2, [r0, #0x80c]
  56 + ldr r2, =0x00220022
  57 + str r2, [r0, #0x810]
  58 + ldr r2, =0x41480144
  59 + str r2, [r0, #0x83c]
  60 + ldr r2, =0x01340130
  61 + str r2, [r0, #0x840]
  62 + ldr r2, =0x3C3E4244
  63 + str r2, [r0, #0x848]
  64 + ldr r2, =0x34363638
  65 + str r2, [r0, #0x850]
  66 +
  67 + ldr r2, =0x33333333
  68 + str r2, [r0, #0x81c]
  69 + str r2, [r0, #0x820]
  70 + str r2, [r0, #0x824]
  71 + str r2, [r0, #0x828]
  72 +
  73 + ldr r2, =0x00000800
  74 + str r2, [r0, #0x8b8]
  75 + ldr r2, =0x0002002d
  76 + str r2, [r0, #0x004]
  77 + ldr r2, =0x00333030
  78 + str r2, [r0, #0x008]
  79 + ldr r2, =0x676b52f3
  80 + str r2, [r0, #0x00c]
  81 + ldr r2, =0xb66d8b63
  82 + str r2, [r0, #0x010]
  83 + ldr r2, =0x01ff00db
  84 + str r2, [r0, #0x014]
  85 + ldr r2, =0x00011740
  86 + str r2, [r0, #0x018]
  87 + ldr r2, =0x00008000
  88 + str r2, [r0, #0x01c]
  89 + ldr r2, =0x000026d2
  90 + str r2, [r0, #0x02c]
  91 + ldr r2, =0x006b1023
  92 + str r2, [r0, #0x030]
  93 + ldr r2, =0x0000005f
  94 + str r2, [r0, #0x040]
  95 + ldr r2, =0x84190000
  96 + str r2, [r0, #0x000]
  97 + ldr r2, =0x04008032
  98 + str r2, [r0, #0x01c]
  99 + ldr r2, =0x00008033
  100 + str r2, [r0, #0x01c]
  101 + ldr r2, =0x00048031
  102 + str r2, [r0, #0x01c]
  103 + ldr r2, =0x05208030
  104 + str r2, [r0, #0x01c]
  105 + ldr r2, =0x04008040
  106 + str r2, [r0, #0x01c]
  107 + ldr r2, =0x00000800
  108 + str r2, [r0, #0x020]
  109 + ldr r2, =0x00011117
  110 + str r2, [r0, #0x818]
  111 + ldr r2, =0x00000000
  112 + str r2, [r0, #0x01c]
  113 +.endm
  114 +.macro imx6_clock_gating
  115 + ldr r0, =CCM_BASE_ADDR
  116 + ldr r1, =0xffffffff
  117 + str r1, [r0, #0x068]
  118 + str r1, [r0, #0x06c]
  119 + str r1, [r0, #0x070]
  120 + str r1, [r0, #0x074]
  121 + str r1, [r0, #0x078]
  122 + str r1, [r0, #0x07c]
  123 + str r1, [r0, #0x080]
  124 + str r1, [r0, #0x084]
  125 +.endm
  126 +
  127 +.macro imx6_qos_setting
  128 +.endm
  129 +
  130 +.macro imx6_ddr_setting
  131 + imx6sx_sabresd_ddr_setting
  132 +.endm
  133 +
  134 +/* include the common plugin code here */
  135 +#include <asm/arch/mx6_plugin.S>
include/configs/mx6sxsabresd.h
Diff comments   View file @ 462883d
1 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 2 /*
3 3 * Copyright 2014 Freescale Semiconductor, Inc.
  4 + * Copyright 2018 NXP
4 5 *
5 6 * Configuration settings for the Freescale i.MX6SX Sabresd board.
6 7 */
7 8  
8 9  
9 10  
10 11  
11 12  
... ... @@ -17,20 +18,32 @@
17 18 #endif
18 19  
19 20 /* Size of malloc() pool */
20   -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
  21 +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
21 22  
22 23 #define CONFIG_MXC_UART
23 24 #define CONFIG_MXC_UART_BASE UART1_BASE
24 25  
25 26 #ifdef CONFIG_IMX_BOOTAUX
26 27 /* Set to QSPI2 B flash at default */
  28 +#ifdef CONFIG_DM_SPI
27 29 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000
  30 +#define SF_QSPI2_B_CS_NUM 2
  31 +#elif defined(CONFIG_MX6SX_SABRESD_REVA)
  32 +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x71000000
  33 +#define SF_QSPI2_B_CS_NUM 1
  34 +#else
  35 +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x72000000
  36 +#define SF_QSPI2_B_CS_NUM 1
  37 +#endif
28 38  
  39 +/* When using M4 fastup demo, no need these M4 env, since QSPI is used by M4 */
  40 +#ifndef CONFIG_SYS_AUXCORE_FASTUP
29 41 #define UPDATE_M4_ENV \
30 42 "m4image=m4_qspi.bin\0" \
  43 + "m4_qspi_cs="__stringify(SF_QSPI2_B_CS_NUM)"\0" \
31 44 "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
32 45 "update_m4_from_sd=" \
33   - "if sf probe 1:0; then " \
  46 + "if sf probe 1:${m4_qspi_cs}; then " \
34 47 "if run loadm4image; then " \
35 48 "setexpr fw_sz ${filesize} + 0xffff; " \
36 49 "setexpr fw_sz ${fw_sz} / 0x10000; " \
37 50  
38 51  
39 52  
... ... @@ -39,12 +52,29 @@
39 52 "sf write ${loadaddr} 0x0 ${filesize}; " \
40 53 "fi; " \
41 54 "fi\0" \
42   - "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0""
  55 + "m4boot=sf probe 1:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0""
43 56 #else
44 57 #define UPDATE_M4_ENV ""
45   -#endif
  58 +#endif /* CONFIG_SYS_AUXCORE_FASTUP */
46 59  
  60 +#else
  61 +#define UPDATE_M4_ENV ""
  62 +#endif /* CONFIG_IMX_BOOTAUX */
  63 +
  64 +#define CONFIG_MFG_ENV_SETTINGS \
  65 + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  66 + "rdinit=/linuxrc " \
  67 + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  68 + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \
  69 + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  70 + "g_mass_storage.iSerialNumber=\"\" "\
  71 + "\0" \
  72 + "initrd_addr=0x83800000\0" \
  73 + "initrd_high=0xffffffff\0" \
  74 + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  75 +
47 76 #define CONFIG_EXTRA_ENV_SETTINGS \
  77 + CONFIG_MFG_ENV_SETTINGS \
48 78 UPDATE_M4_ENV \
49 79 "script=boot.scr\0" \
50 80 "image=zImage\0" \
51 81  
52 82  
53 83  
... ... @@ -52,15 +82,16 @@
52 82 "fdt_high=0xffffffff\0" \
53 83 "initrd_high=0xffffffff\0" \
54 84 "fdt_file=imx6sx-sdb.dtb\0" \
55   - "fdt_addr=0x88000000000000\0" \" \
  85 + "fdt_addr=0x83000000000000\0" \" \
56 86 "boot_fdt=try\0" \
57 87 "ip_dyn=yes\0" \
58   - "videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \
59   - "mmcdev=3\0" \
  88 + "panel=Hannstar-XGA\0" \
  89 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
60 90 "mmcpart=1\0" \
61   - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
  91 + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  92 + "mmcautodetect=yes\0" \
62 93 "mmcargs=setenv bootargs console=${console},${baudrate} " \
63   - "root=PARTUUID=${uuid} rootwait rw\0" \" \
  94 + "root=${mmcroot}\0" \" \
64 95 "loadbootscript=" \
65 96 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
66 97 "bootscript=echo Running bootscript from mmc ...; " \
... ... @@ -68,7 +99,6 @@
68 99 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
69 100 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
70 101 "mmcboot=echo Booting from mmc ...; " \
71   - "run finduuid; " \
72 102 "run mmcargs; " \
73 103 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
74 104 "if run loadfdt; then " \
75 105  
76 106  
77 107  
78 108  
79 109  
80 110  
... ... @@ -141,26 +171,33 @@
141 171 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
142 172  
143 173 /* MMC Configuration */
  174 +
144 175 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
145 176  
146 177 /* I2C Configs */
  178 +#ifndef CONFIG_DM_I2C
  179 +#define CONFIG_SYS_I2C
  180 +#endif
  181 +#ifdef CONFIG_CMD_I2C
147 182 #define CONFIG_SYS_I2C_MXC
148 183 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
149 184 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
150 185 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
151 186 #define CONFIG_SYS_I2C_SPEED 100000
  187 +#endif
152 188  
153   -/* Network */
154   -#define CONFIG_FEC_MXC
  189 +/* PMIC */
  190 +#ifndef CONFIG_DM_PMIC
  191 +#define CONFIG_POWER
  192 +#define CONFIG_POWER_I2C
  193 +#define CONFIG_POWER_PFUZE100
  194 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
  195 +#endif
155 196  
156   -#define IMX_FEC_BASE ENET_BASE_ADDR
157   -#define CONFIG_FEC_MXC_PHYADDR 0x1
158   -
  197 +/* Network */
  198 +#define CONFIG_ETHPRIME "eth0"
159 199 #define CONFIG_FEC_XCV_TYPE RGMII
160   -#define CONFIG_ETHPRIME "FEC"
161 200  
162   -#define CONFIG_PHY_ATHEROS
163   -
164 201 #ifdef CONFIG_CMD_USB
165 202 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
166 203 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
... ... @@ -178,7 +215,6 @@
178 215 #define CONFIG_IMX_THERMAL
179 216  
180 217 #ifdef CONFIG_FSL_QSPI
181   -#define CONFIG_SYS_FSL_QSPI_LE
182 218 #define CONFIG_SYS_FSL_QSPI_AHB
183 219 #ifdef CONFIG_MX6SX_SABRESD_REVA
184 220 #define FSL_QSPI_FLASH_SIZE SZ_16M
185 221  
186 222  
... ... @@ -197,14 +233,23 @@
197 233 #define CONFIG_BMP_16BPP
198 234 #define CONFIG_VIDEO_BMP_RLE8
199 235 #define CONFIG_VIDEO_BMP_LOGO
200   -#define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR
  236 +#define CONFIG_IMX_VIDEO_SKIP
  237 +#define CONFIG_SYS_CONSOLE_BG_COL 0x00
  238 +#define CONFIG_SYS_CONSOLE_FG_COL 0xa0
201 239 #endif
202 240 #endif
203 241  
204   -#define CONFIG_SYS_FSL_USDHC_NUM 3
205   -#if defined(CONFIG_ENV_IS_IN_MMC)
206   -#define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/
  242 +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  243 +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
  244 +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  245 +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
  246 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
207 247 #endif
  248 +
  249 +#define CONFIG_SYS_FSL_USDHC_NUM 3
  250 +#define CONFIG_MMCROOT "/dev/mmcblk3p2" /* USDHC4 */
  251 +#define CONFIG_SYS_MMC_ENV_DEV 3 /*USDHC4*/
  252 +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
208 253  
209 254 #endif /* __CONFIG_H */
scripts/config_whitelist.txt
Diff comments   View file @ 462883d
... ... @@ -1810,6 +1810,7 @@
1810 1810 CONFIG_SYS_AUTOLOAD
1811 1811 CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
1812 1812 CONFIG_SYS_AUXCORE_BOOTDATA
  1813 +CONFIG_SYS_AUXCORE_FASTUP
1813 1814 CONFIG_SYS_BARGSIZE
1814 1815 CONFIG_SYS_BAUDRATE_TABLE
1815 1816 CONFIG_SYS_BCSR