Eric Lee / smarc-uboot

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Commit e74716b6e78f016226dc9f800b04574f545d9367

Authored by Ye Li
1 parent 9d8838cb14
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-18152-2 mx6sxsabresd: Update board codes to align with v2017.03 

Add emmc support which needs board rework.
Add I2C2.
Update DM PMIC settings and LDO bypass support.
Add BMODE support.
Add LVDS and LCD splash screen support
Add PCI power and reset GPIO and disable PCI at default.
Update QSPI settings for QSPI boot and M4 fastup.
Update environment settings

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 6 changed files with 850 additions and 32 deletions Side-by-side Diff

board/freescale/mx6sxsabresd/Kconfig
Diff comments   View file @ e74716b
... ... @@ -9,5 +9,10 @@
9 9 config SYS_CONFIG_NAME
10 10 default "mx6sxsabresd"
11 11  
  12 +config MX6SXSABRESD_EMMC_REWORK
  13 + bool "Select for the board with eMMC rework"
  14 +
  15 +config SYS_TEXT_BASE
  16 + default 0x87800000
12 17 endif
board/freescale/mx6sxsabresd/imximage.cfg
Diff comments   View file @ e74716b
1 1 /*
2   - * Copyright (C) 2014 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3 3 *
4 4 * SPDX-License-Identifier: GPL-2.0+
5 5 */
6 6  
7 7  
... ... @@ -16,8 +16,21 @@
16 16 * spi/sd/nand/onenand, qspi/nor
17 17 */
18 18  
  19 +#ifdef CONFIG_QSPI_BOOT
  20 +BOOT_FROM qspi
  21 +#else
19 22 BOOT_FROM sd
  23 +#endif
20 24  
  25 +#ifdef CONFIG_USE_IMXIMG_PLUGIN
  26 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  27 +PLUGIN board/freescale/mx6sxsabresd/plugin.bin 0x00907000
  28 +#else
  29 +
  30 +#ifdef CONFIG_SECURE_BOOT
  31 +CSF CONFIG_CSF_SIZE
  32 +#endif
  33 +
21 34 /*
22 35 * Device Configuration Data (DCD)
23 36 *
... ... @@ -130,4 +143,5 @@
130 143 DATA 4 0x021b0020 0x00000800
131 144 DATA 4 0x021b0818 0x00011117
132 145 DATA 4 0x021b001c 0x00000000
  146 +#endif
board/freescale/mx6sxsabresd/mx6sxsabresd.c
Diff comments   View file @ e74716b
1 1 /*
2   - * Copyright (C) 2014 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
  3 + * Copyright 2017 NXP
3 4 *
4 5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 6 *
... ... @@ -14,6 +15,7 @@
14 15 #include <asm/arch/sys_proto.h>
15 16 #include <asm/gpio.h>
16 17 #include <asm/mach-imx/iomux-v3.h>
  18 +#include <asm/mach-imx/boot_mode.h>
17 19 #include <asm/io.h>
18 20 #include <asm/mach-imx/mxc_i2c.h>
19 21 #include <linux/sizes.h>
20 22  
... ... @@ -26,7 +28,14 @@
26 28 #include <power/pmic.h>
27 29 #include <power/pfuze100_pmic.h>
28 30 #include "../common/pfuze.h"
  31 +#include <usb.h>
  32 +#include <usb/ehci-ci.h>
  33 +#include <asm/mach-imx/video.h>
29 34  
  35 +#ifdef CONFIG_IMX_RDC
  36 +#include <asm/mach-imx/rdc-sema.h>
  37 +#include <asm/arch/imx-rdc.h>
  38 +#endif
30 39 DECLARE_GLOBAL_DATA_PTR;
31 40  
32 41 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
... ... @@ -37,6 +46,11 @@
37 46 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
38 47 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
39 48  
  49 +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  50 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  51 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  52 + PAD_CTL_ODE)
  53 +
40 54 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
41 55 PAD_CTL_SPEED_HIGH | \
42 56 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
43 57  
... ... @@ -47,12 +61,21 @@
47 61 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
48 62 PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
49 63  
  64 +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  65 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  66 + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  67 + PAD_CTL_ODE)
  68 +
50 69 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
51 70 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
52 71  
53 72 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
54 73 PAD_CTL_DSE_40ohm)
55 74  
  75 +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  76 + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  77 + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  78 +
56 79 int dram_init(void)
57 80 {
58 81 gd->ram_size = imx_ddr_size();
... ... @@ -65,6 +88,60 @@
65 88 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
66 89 };
67 90  
  91 +static iomux_v3_cfg_t const usdhc2_pads[] = {
  92 + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93 + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94 + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95 + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96 + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97 + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98 +};
  99 +
  100 +static iomux_v3_cfg_t const usdhc3_pads[] = {
  101 + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  102 + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  103 + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  104 + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  105 + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  106 + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  107 + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  108 + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  109 + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  110 + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  111 +
  112 + /* CD pin */
  113 + MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  114 +
  115 + /* RST_B, used for power reset cycle */
  116 + MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  117 +};
  118 +
  119 +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
  120 +static iomux_v3_cfg_t const usdhc4_emmc_pads[] = {
  121 + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  122 + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  123 + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  124 + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  125 + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  126 + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  127 + MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  128 + MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  129 + MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  130 + MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  131 + MX6_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  132 +};
  133 +#else
  134 +static iomux_v3_cfg_t const usdhc4_pads[] = {
  135 + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  136 + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  137 + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  138 + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  139 + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  140 + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  141 + MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
  142 +};
  143 +#endif
  144 +
68 145 static iomux_v3_cfg_t const wdog_b_pad = {
69 146 MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
70 147 };
... ... @@ -85,6 +162,23 @@
85 162 MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
86 163 };
87 164  
  165 +static iomux_v3_cfg_t const fec2_pads[] = {
  166 + MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  167 + MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  168 + MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  169 + MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  170 + MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  171 + MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  172 + MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  173 + MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  174 + MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  175 + MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  176 + MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  177 + MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  178 + MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  179 + MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  180 +};
  181 +
88 182 static iomux_v3_cfg_t const peri_3v3_pads[] = {
89 183 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
90 184 };
91 185  
92 186  
93 187  
... ... @@ -100,21 +194,39 @@
100 194 MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
101 195 };
102 196  
  197 +#ifdef CONFIG_PCIE_IMX
  198 +iomux_v3_cfg_t const pcie_pads[] = {
  199 + MX6_PAD_ENET1_COL__GPIO2_IO_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
  200 + MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
  201 +};
  202 +
  203 +static void setup_pcie(void)
  204 +{
  205 + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
  206 + gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "PCIE Power Enable");
  207 + gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "PCIE Reset");
  208 +}
  209 +#endif
  210 +
103 211 static void setup_iomux_uart(void)
104 212 {
105 213 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
106 214 }
107 215  
108   -static int setup_fec(void)
  216 +static int setup_fec(int fec_id)
109 217 {
110 218 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
111 219 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
112 220 int reg, ret;
113 221  
114   - /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
115   - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
  222 + if (0 == fec_id)
  223 + /* Use 125M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
  224 + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
  225 + else
  226 + /* Use 125M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/
  227 + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
116 228  
117   - ret = enable_fec_anatop_clock(0, ENET_125MHZ);
  229 + ret = enable_fec_anatop_clock(fec_id, ENET_125MHZ);
118 230 if (ret)
119 231 return ret;
120 232  
121 233  
... ... @@ -122,11 +234,11 @@
122 234 ARRAY_SIZE(phy_control_pads));
123 235  
124 236 /* Enable the ENET power, active low */
125   - gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
  237 + gpio_request(IMX_GPIO_NR(2, 6), "fec power en");
126 238 gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
127 239  
128 240 /* Reset AR8031 PHY */
129   - gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
  241 + gpio_request(IMX_GPIO_NR(2, 7), "ar8031 reset");
130 242 gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
131 243 mdelay(10);
132 244 gpio_set_value(IMX_GPIO_NR(2, 7), 1);
133 245  
134 246  
... ... @@ -140,14 +252,95 @@
140 252  
141 253 int board_eth_init(bd_t *bis)
142 254 {
143   - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
144   - setup_fec();
  255 + if (0 == CONFIG_FEC_ENET_DEV)
  256 + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
  257 + else
  258 + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
145 259  
146 260 return cpu_eth_init(bis);
147 261 }
148 262  
  263 +#ifdef CONFIG_SYS_I2C
  264 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  265 +/* I2C1 for PMIC */
  266 +static struct i2c_pads_info i2c_pad_info1 = {
  267 + .scl = {
  268 + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC,
  269 + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC,
  270 + .gp = IMX_GPIO_NR(1, 0),
  271 + },
  272 + .sda = {
  273 + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC,
  274 + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC,
  275 + .gp = IMX_GPIO_NR(1, 1),
  276 + },
  277 +};
  278 +
  279 +/* I2C2 */
  280 +struct i2c_pads_info i2c_pad_info2 = {
  281 + .scl = {
  282 + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC,
  283 + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC,
  284 + .gp = IMX_GPIO_NR(1, 2),
  285 + },
  286 + .sda = {
  287 + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC,
  288 + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC,
  289 + .gp = IMX_GPIO_NR(1, 3),
  290 + },
  291 +};
  292 +#endif
  293 +
  294 +#ifdef CONFIG_POWER
149 295 int power_init_board(void)
150 296 {
  297 + struct pmic *pfuze;
  298 + unsigned int reg;
  299 + int ret;
  300 +
  301 + pfuze = pfuze_common_init(I2C_PMIC);
  302 + if (!pfuze)
  303 + return -ENODEV;
  304 +
  305 + ret = pfuze_mode_init(pfuze, APS_PFM);
  306 + if (ret < 0)
  307 + return ret;
  308 +
  309 + /* set SW1AB standby volatage 1.10V */
  310 + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);
  311 + reg &= ~0x3f;
  312 + reg |= PFUZE100_SW1ABC_SETP(11000);
  313 + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
  314 +
  315 + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  316 + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);
  317 + reg &= ~0xc0;
  318 + reg |= 0x40;
  319 + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
  320 +
  321 + /* set SW1C standby volatage 1.10V */
  322 + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
  323 + reg &= ~0x3f;
  324 + reg |= PFUZE100_SW1ABC_SETP(11000);
  325 + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
  326 +
  327 + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
  328 + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
  329 + reg &= ~0xc0;
  330 + reg |= 0x40;
  331 + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
  332 +
  333 + /* Enable power of VGEN5 3V3, needed for SD3 */
  334 + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &reg);
  335 + reg &= ~LDO_VOL_MASK;
  336 + reg |= (LDOB_3_30V | (1 << LDO_EN));
  337 + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg);
  338 +
  339 + return 0;
  340 +}
  341 +#elif defined(CONFIG_DM_PMIC_PFUZE100)
  342 +int power_init_board(void)
  343 +{
151 344 struct udevice *dev;
152 345 unsigned int reg;
153 346 int ret;
154 347  
155 348  
156 349  
... ... @@ -160,14 +353,176 @@
160 353 if (ret < 0)
161 354 return ret;
162 355  
  356 + /* set SW1AB staby volatage 0.975V*/
  357 + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
  358 + reg &= ~0x3f;
  359 + reg |= PFUZE100_SW1ABC_SETP(11000);
  360 + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
  361 +
  362 + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  363 + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
  364 + reg &= ~0xc0;
  365 + reg |= 0x40;
  366 + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
  367 +
  368 + /* set SW1C staby volatage 0.975V*/
  369 + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
  370 + reg &= ~0x3f;
  371 + reg |= PFUZE100_SW1ABC_SETP(11000);
  372 + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
  373 +
  374 + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
  375 + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
  376 + reg &= ~0xc0;
  377 + reg |= 0x40;
  378 + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
  379 +
163 380 /* Enable power of VGEN5 3V3, needed for SD3 */
164 381 reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
165 382 reg &= ~LDO_VOL_MASK;
166 383 reg |= (LDOB_3_30V | (1 << LDO_EN));
167 384 pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
  385 + return 0;
  386 +}
  387 +#endif
168 388  
  389 +#ifdef CONFIG_LDO_BYPASS_CHECK
  390 +#ifdef CONFIG_POWER
  391 +void ldo_mode_set(int ldo_bypass)
  392 +{
  393 + unsigned int value;
  394 + int is_400M;
  395 + u32 vddarm;
  396 + struct pmic *p = pmic_get("PFUZE100");
  397 +
  398 + if (!p) {
  399 + printf("No PMIC found!\n");
  400 + return;
  401 + }
  402 +
  403 + /* switch to ldo_bypass mode */
  404 + if (ldo_bypass) {
  405 + prep_anatop_bypass();
  406 + /* decrease VDDARM to 1.275V */
  407 + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
  408 + value &= ~0x3f;
  409 + value |= PFUZE100_SW1ABC_SETP(12750);
  410 + pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
  411 +
  412 + /* decrease VDDSOC to 1.3V */
  413 + pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
  414 + value &= ~0x3f;
  415 + value |= PFUZE100_SW1ABC_SETP(13000);
  416 + pmic_reg_write(p, PFUZE100_SW1CVOL, value);
  417 +
  418 + is_400M = set_anatop_bypass(1);
  419 + if (is_400M)
  420 + vddarm = PFUZE100_SW1ABC_SETP(10750);
  421 + else
  422 + vddarm = PFUZE100_SW1ABC_SETP(11750);
  423 +
  424 + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
  425 + value &= ~0x3f;
  426 + value |= vddarm;
  427 + pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
  428 +
  429 + pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
  430 + value &= ~0x3f;
  431 + value |= PFUZE100_SW1ABC_SETP(11750);
  432 + pmic_reg_write(p, PFUZE100_SW1CVOL, value);
  433 +
  434 + finish_anatop_bypass();
  435 + printf("switch to ldo_bypass mode!\n");
  436 + }
  437 +
  438 +}
  439 +#elif defined(CONFIG_DM_PMIC_PFUZE100)
  440 +void ldo_mode_set(int ldo_bypass)
  441 +{
  442 + struct udevice *dev;
  443 + int ret;
  444 + int is_400M;
  445 + u32 vddarm;
  446 +
  447 + ret = pmic_get("pfuze100", &dev);
  448 + if (ret == -ENODEV) {
  449 + printf("No PMIC found!\n");
  450 + return;
  451 + }
  452 +
  453 + /* switch to ldo_bypass mode , boot on 800Mhz */
  454 + if (ldo_bypass) {
  455 + prep_anatop_bypass();
  456 +
  457 + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
  458 + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750));
  459 +
  460 + /* increase VDDSOC to 1.3V */
  461 + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000));
  462 +
  463 + is_400M = set_anatop_bypass(1);
  464 + if (is_400M)
  465 + vddarm = PFUZE100_SW1ABC_SETP(10750);
  466 + else
  467 + vddarm = PFUZE100_SW1ABC_SETP(11750);
  468 +
  469 + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
  470 +
  471 + /* decrease VDDSOC to 1.175V */
  472 + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750));
  473 +
  474 + finish_anatop_bypass();
  475 + printf("switch to ldo_bypass mode!\n");
  476 + }
  477 +}
  478 +#endif
  479 +#endif
  480 +
  481 +#ifdef CONFIG_USB_EHCI_MX6
  482 +#ifndef CONFIG_DM_USB
  483 +
  484 +#define USB_OTHERREGS_OFFSET 0x800
  485 +#define UCTRL_PWR_POL (1 << 9)
  486 +
  487 +static iomux_v3_cfg_t const usb_otg_pads[] = {
  488 + /* OGT1 */
  489 + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  490 + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
  491 + /* OTG2 */
  492 + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
  493 +};
  494 +
  495 +static void setup_usb(void)
  496 +{
  497 + imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
  498 + ARRAY_SIZE(usb_otg_pads));
  499 +}
  500 +
  501 +int board_usb_phy_mode(int port)
  502 +{
  503 + if (port == 1)
  504 + return USB_INIT_HOST;
  505 + else
  506 + return usb_phy_mode(port);
  507 +}
  508 +
  509 +int board_ehci_hcd_init(int port)
  510 +{
  511 + u32 *usbnc_usb_ctrl;
  512 +
  513 + if (port > 1)
  514 + return -EINVAL;
  515 +
  516 + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
  517 + port * 4);
  518 +
  519 + /* Set Power polarity */
  520 + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
  521 +
169 522 return 0;
170 523 }
  524 +#endif
  525 +#endif
171 526  
172 527 int board_phy_config(struct phy_device *phydev)
173 528 {
174 529  
... ... @@ -188,8 +543,22 @@
188 543 return 0;
189 544 }
190 545  
  546 +#ifdef CONFIG_IMX_RDC
  547 +static rdc_peri_cfg_t const shared_resources[] = {
  548 + (RDC_PER_GPIO1 | RDC_DOMAIN(0) | RDC_DOMAIN(1)),
  549 +};
  550 +#endif
  551 +
191 552 int board_early_init_f(void)
192 553 {
  554 +#ifdef CONFIG_IMX_RDC
  555 + imx_rdc_setup_peripherals(shared_resources, ARRAY_SIZE(shared_resources));
  556 +#endif
  557 +
  558 +#ifdef CONFIG_SYS_AUXCORE_FASTUP
  559 + arch_auxiliary_core_up(0, CONFIG_SYS_AUXCORE_BOOTDATA);
  560 +#endif
  561 +
193 562 setup_iomux_uart();
194 563  
195 564 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
196 565  
197 566  
198 567  
... ... @@ -199,13 +568,112 @@
199 568 return 0;
200 569 }
201 570  
  571 +static struct fsl_esdhc_cfg usdhc_cfg[3] = {
  572 + {USDHC2_BASE_ADDR, 0, 4},
  573 + {USDHC3_BASE_ADDR},
  574 +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
  575 + {USDHC4_BASE_ADDR, 0, 8},
  576 +#else
  577 + {USDHC4_BASE_ADDR},
  578 +#endif
  579 +};
  580 +
  581 +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
  582 +#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
  583 +#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
  584 +
202 585 int board_mmc_get_env_dev(int devno)
203 586 {
204   - return devno;
  587 + return devno - 1;
205 588 }
206 589  
  590 +int mmc_map_to_kernel_blk(int dev_no)
  591 +{
  592 + return dev_no + 1;
  593 +}
  594 +
  595 +int board_mmc_getcd(struct mmc *mmc)
  596 +{
  597 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  598 + int ret = 0;
  599 +
  600 + switch (cfg->esdhc_base) {
  601 + case USDHC2_BASE_ADDR:
  602 + ret = 1; /* Assume uSDHC2 is always present */
  603 + break;
  604 + case USDHC3_BASE_ADDR:
  605 + ret = !gpio_get_value(USDHC3_CD_GPIO);
  606 + break;
  607 + case USDHC4_BASE_ADDR:
  608 +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
  609 + ret = 1;
  610 +#else
  611 + ret = !gpio_get_value(USDHC4_CD_GPIO);
  612 +#endif
  613 + break;
  614 + }
  615 +
  616 + return ret;
  617 +}
  618 +
  619 +int board_mmc_init(bd_t *bis)
  620 +{
  621 + int i, ret;
  622 +
  623 + /*
  624 + * According to the board_mmc_init() the following map is done:
  625 + * (U-Boot device node) (Physical Port)
  626 + * mmc0 USDHC2
  627 + * mmc1 USDHC3
  628 + * mmc2 USDHC4
  629 + */
  630 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  631 + switch (i) {
  632 + case 0:
  633 + imx_iomux_v3_setup_multiple_pads(
  634 + usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  635 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  636 + break;
  637 + case 1:
  638 + imx_iomux_v3_setup_multiple_pads(
  639 + usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  640 + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
  641 + gpio_request(USDHC3_PWR_GPIO, "usdhc3 pwr");
  642 + gpio_direction_input(USDHC3_CD_GPIO);
  643 + gpio_direction_output(USDHC3_PWR_GPIO, 1);
  644 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  645 + break;
  646 + case 2:
  647 +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK
  648 + imx_iomux_v3_setup_multiple_pads(
  649 + usdhc4_emmc_pads, ARRAY_SIZE(usdhc4_emmc_pads));
  650 +#else
  651 + imx_iomux_v3_setup_multiple_pads(
  652 + usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  653 + gpio_request(USDHC4_CD_GPIO, "usdhc4 cd");
  654 + gpio_direction_input(USDHC4_CD_GPIO);
  655 +#endif
  656 + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  657 + break;
  658 + default:
  659 + printf("Warning: you configured more USDHC controllers"
  660 + "(%d) than supported by the board\n", i + 1);
  661 + return -EINVAL;
  662 + }
  663 +
  664 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  665 + if (ret) {
  666 + printf("Warning: failed to initialize mmc dev %d\n", i);
  667 + return ret;
  668 + }
  669 + }
  670 +
  671 + return 0;
  672 +}
  673 +
207 674 #ifdef CONFIG_FSL_QSPI
208 675  
  676 +#ifndef CONFIG_DM_SPI
209 677 #define QSPI_PAD_CTRL1 \
210 678 (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_HIGH | \
211 679 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
212 680  
213 681  
... ... @@ -226,13 +694,15 @@
226 694 MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
227 695 MX6_PAD_NAND_DATA05__QSPI2_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
228 696 };
  697 +#endif
229 698  
230 699 int board_qspi_init(void)
231 700 {
  701 +#ifndef CONFIG_DM_SPI
232 702 /* Set the iomux */
233 703 imx_iomux_v3_setup_multiple_pads(quadspi_pads,
234 704 ARRAY_SIZE(quadspi_pads));
235   -
  705 +#endif
236 706 /* Set the clock */
237 707 enable_qspi_clk(1);
238 708  
239 709  
... ... @@ -240,7 +710,25 @@
240 710 }
241 711 #endif
242 712  
  713 +#ifdef CONFIG_CMD_BMODE
  714 +static const struct boot_mode board_boot_modes[] = {
  715 + /* 4 bit bus width */
  716 + {"sd3", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
  717 + {"sd4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  718 + {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)},
  719 + {NULL, 0},
  720 +};
  721 +#endif
  722 +
243 723 #ifdef CONFIG_VIDEO_MXS
  724 +static iomux_v3_cfg_t const lvds_ctrl_pads[] = {
  725 + /* CABC enable */
  726 + MX6_PAD_QSPI1A_DATA2__GPIO4_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
  727 +
  728 + /* Use GPIO for Brightness adjustment, duty cycle = period */
  729 + MX6_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL),
  730 +};
  731 +
244 732 static iomux_v3_cfg_t const lcd_pads[] = {
245 733 MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
246 734 MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
247 735  
248 736  
... ... @@ -276,10 +764,44 @@
276 764 MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
277 765 };
278 766  
279   -static int setup_lcd(void)
  767 +void do_enable_lvds(struct display_info_t const *dev)
280 768 {
281   - enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
  769 + int ret;
282 770  
  771 + ret = enable_lcdif_clock(dev->bus, 1);
  772 + if (ret) {
  773 + printf("Enable LCDIF clock failed, %d\n", ret);
  774 + return;
  775 + }
  776 + ret = enable_lvds_bridge(dev->bus);
  777 + if (ret) {
  778 + printf("Enable LVDS bridge failed, %d\n", ret);
  779 + return;
  780 + }
  781 +
  782 + imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads,
  783 + ARRAY_SIZE(lvds_ctrl_pads));
  784 +
  785 + /* Enable CABC */
  786 + gpio_request(IMX_GPIO_NR(4, 18), "CABC enable");
  787 + gpio_direction_output(IMX_GPIO_NR(4, 18) , 1);
  788 +
  789 + /* Set Brightness to high */
  790 + gpio_request(IMX_GPIO_NR(6, 3), "lvds backlight");
  791 + gpio_direction_output(IMX_GPIO_NR(6, 3) , 1);
  792 +}
  793 +
  794 +void do_enable_parallel_lcd(struct display_info_t const *dev)
  795 +
  796 +{
  797 + int ret;
  798 +
  799 + ret = enable_lcdif_clock(dev->bus, 1);
  800 + if (ret) {
  801 + printf("Enable LCDIF clock failed, %d\n", ret);
  802 + return;
  803 + }
  804 +
283 805 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
284 806  
285 807 /* Reset the LCD */
286 808  
... ... @@ -291,9 +813,48 @@
291 813 /* Set Brightness to high */
292 814 gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
293 815 gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
294   -
295   - return 0;
296 816 }
  817 +
  818 +struct display_info_t const displays[] = {{
  819 + .bus = LCDIF2_BASE_ADDR,
  820 + .addr = 0,
  821 + .pixfmt = 18,
  822 + .detect = NULL,
  823 + .enable = do_enable_lvds,
  824 + .mode = {
  825 + .name = "Hannstar-XGA",
  826 + .xres = 1024,
  827 + .yres = 768,
  828 + .pixclock = 15385,
  829 + .left_margin = 220,
  830 + .right_margin = 40,
  831 + .upper_margin = 21,
  832 + .lower_margin = 7,
  833 + .hsync_len = 60,
  834 + .vsync_len = 10,
  835 + .sync = 0,
  836 + .vmode = FB_VMODE_NONINTERLACED
  837 +} }, {
  838 + .bus = MX6SX_LCDIF1_BASE_ADDR,
  839 + .addr = 0,
  840 + .pixfmt = 24,
  841 + .detect = NULL,
  842 + .enable = do_enable_parallel_lcd,
  843 + .mode = {
  844 + .name = "MCIMX28LCD",
  845 + .xres = 800,
  846 + .yres = 480,
  847 + .pixclock = 29850,
  848 + .left_margin = 89,
  849 + .right_margin = 164,
  850 + .upper_margin = 23,
  851 + .lower_margin = 10,
  852 + .hsync_len = 10,
  853 + .vsync_len = 10,
  854 + .sync = 0,
  855 + .vmode = FB_VMODE_NONINTERLACED
  856 +} } };
  857 +size_t display_count = ARRAY_SIZE(displays);
297 858 #endif
298 859  
299 860 int board_init(void)
300 861  
301 862  
... ... @@ -314,14 +875,30 @@
314 875 gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
315 876 gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
316 877  
  878 +#ifdef CONFIG_SYS_I2C
  879 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  880 + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  881 +#endif
  882 +
  883 +#ifdef CONFIG_USB_EHCI_MX6
  884 +#ifndef CONFIG_DM_USB
  885 + setup_usb();
  886 +#endif
  887 +#endif
  888 +
317 889 #ifdef CONFIG_FSL_QSPI
318 890 board_qspi_init();
319 891 #endif
320 892  
321   -#ifdef CONFIG_VIDEO_MXS
322   - setup_lcd();
  893 +#ifdef CONFIG_PCIE_IMX
  894 + setup_pcie();
323 895 #endif
324 896  
  897 + /* Also used for OF_CONTROL enabled */
  898 +#ifdef CONFIG_FEC_MXC
  899 + setup_fec(CONFIG_FEC_ENET_DEV);
  900 +#endif
  901 +
325 902 return 0;
326 903 }
327 904  
... ... @@ -335,6 +912,14 @@
335 912 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
336 913 if (is_reva())
337 914 env_set("board_rev", "REVA");
  915 +#endif
  916 +
  917 +#ifdef CONFIG_CMD_BMODE
  918 + add_board_boot_modes(board_boot_modes);
  919 +#endif
  920 +
  921 +#ifdef CONFIG_ENV_IS_IN_MMC
  922 + board_late_mmc_env_init();
338 923 #endif
339 924 return 0;
340 925 }
board/freescale/mx6sxsabresd/plugin.S
Diff comments   View file @ e74716b
  1 +/*
  2 + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <config.h>
  8 +
  9 +/* DDR script */
  10 +.macro imx6sx_sabresd_ddr_setting
  11 + ldr r0, =IOMUXC_BASE_ADDR
  12 + ldr r1, =0x000c0000
  13 + str r1, [r0, #0x618]
  14 + ldr r1, =0x00000000
  15 + str r1, [r0, #0x5fc]
  16 + ldr r1, =0x00000030
  17 + str r1, [r0, #0x32c]
  18 +
  19 + ldr r1, =0x00000020
  20 + str r1, [r0, #0x300]
  21 + str r1, [r0, #0x2fc]
  22 + str r1, [r0, #0x5f4]
  23 + str r1, [r0, #0x340]
  24 +
  25 + ldr r1, =0x00000000
  26 + str r1, [r0, #0x320]
  27 + ldr r1, =0x00000020
  28 + str r1, [r0, #0x310]
  29 + str r1, [r0, #0x314]
  30 + str r1, [r0, #0x614]
  31 +
  32 + ldr r1, =0x00020000
  33 + str r1, [r0, #0x5f8]
  34 + ldr r1, =0x00000028
  35 + str r1, [r0, #0x330]
  36 + str r1, [r0, #0x334]
  37 + str r1, [r0, #0x338]
  38 + str r1, [r0, #0x33c]
  39 + ldr r1, =0x00020000
  40 + str r1, [r0, #0x608]
  41 + ldr r1, =0x00000028
  42 + str r1, [r0, #0x60c]
  43 + str r1, [r0, #0x610]
  44 + str r1, [r0, #0x61c]
  45 + str r1, [r0, #0x620]
  46 + str r1, [r0, #0x2ec]
  47 + str r1, [r0, #0x2f0]
  48 + str r1, [r0, #0x2f4]
  49 + str r1, [r0, #0x2f8]
  50 +
  51 + ldr r0, =MMDC_P0_BASE_ADDR
  52 + ldr r2, =0xa1390003
  53 + str r2, [r0, #0x800]
  54 + ldr r2, =0x00290025
  55 + str r2, [r0, #0x80c]
  56 + ldr r2, =0x00220022
  57 + str r2, [r0, #0x810]
  58 + ldr r2, =0x41480144
  59 + str r2, [r0, #0x83c]
  60 + ldr r2, =0x01340130
  61 + str r2, [r0, #0x840]
  62 + ldr r2, =0x3C3E4244
  63 + str r2, [r0, #0x848]
  64 + ldr r2, =0x34363638
  65 + str r2, [r0, #0x850]
  66 +
  67 + ldr r2, =0x33333333
  68 + str r2, [r0, #0x81c]
  69 + str r2, [r0, #0x820]
  70 + str r2, [r0, #0x824]
  71 + str r2, [r0, #0x828]
  72 +
  73 + ldr r2, =0x00000800
  74 + str r2, [r0, #0x8b8]
  75 + ldr r2, =0x0002002d
  76 + str r2, [r0, #0x004]
  77 + ldr r2, =0x00333030
  78 + str r2, [r0, #0x008]
  79 + ldr r2, =0x676b52f3
  80 + str r2, [r0, #0x00c]
  81 + ldr r2, =0xb66d8b63
  82 + str r2, [r0, #0x010]
  83 + ldr r2, =0x01ff00db
  84 + str r2, [r0, #0x014]
  85 + ldr r2, =0x00011740
  86 + str r2, [r0, #0x018]
  87 + ldr r2, =0x00008000
  88 + str r2, [r0, #0x01c]
  89 + ldr r2, =0x000026d2
  90 + str r2, [r0, #0x02c]
  91 + ldr r2, =0x006b1023
  92 + str r2, [r0, #0x030]
  93 + ldr r2, =0x0000005f
  94 + str r2, [r0, #0x040]
  95 + ldr r2, =0x84190000
  96 + str r2, [r0, #0x000]
  97 + ldr r2, =0x04008032
  98 + str r2, [r0, #0x01c]
  99 + ldr r2, =0x00008033
  100 + str r2, [r0, #0x01c]
  101 + ldr r2, =0x00048031
  102 + str r2, [r0, #0x01c]
  103 + ldr r2, =0x05208030
  104 + str r2, [r0, #0x01c]
  105 + ldr r2, =0x04008040
  106 + str r2, [r0, #0x01c]
  107 + ldr r2, =0x00000800
  108 + str r2, [r0, #0x020]
  109 + ldr r2, =0x00011117
  110 + str r2, [r0, #0x818]
  111 + ldr r2, =0x00000000
  112 + str r2, [r0, #0x01c]
  113 +.endm
  114 +.macro imx6_clock_gating
  115 + ldr r0, =CCM_BASE_ADDR
  116 + ldr r1, =0xffffffff
  117 + str r1, [r0, #0x068]
  118 + str r1, [r0, #0x06c]
  119 + str r1, [r0, #0x070]
  120 + str r1, [r0, #0x074]
  121 + str r1, [r0, #0x078]
  122 + str r1, [r0, #0x07c]
  123 + str r1, [r0, #0x080]
  124 + str r1, [r0, #0x084]
  125 +.endm
  126 +
  127 +.macro imx6_qos_setting
  128 +.endm
  129 +
  130 +.macro imx6_ddr_setting
  131 + imx6sx_sabresd_ddr_setting
  132 +.endm
  133 +
  134 +/* include the common plugin code here */
  135 +#include <asm/arch/mx6_plugin.S>
include/configs/mx6sxsabresd.h
Diff comments   View file @ e74716b
1 1 /*
2 2 * Copyright 2014 Freescale Semiconductor, Inc.
  3 + * Copyright 2018 NXP
3 4 *
4 5 * Configuration settings for the Freescale i.MX6SX Sabresd board.
5 6 *
6 7  
7 8  
8 9  
9 10  
10 11  
... ... @@ -18,20 +19,32 @@
18 19 #endif
19 20  
20 21 /* Size of malloc() pool */
21   -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
  22 +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
22 23  
23 24 #define CONFIG_MXC_UART
24 25 #define CONFIG_MXC_UART_BASE UART1_BASE
25 26  
26 27 #ifdef CONFIG_IMX_BOOTAUX
27 28 /* Set to QSPI2 B flash at default */
  29 +#ifdef CONFIG_DM_SPI
28 30 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000
  31 +#define SF_QSPI2_B_CS_NUM 2
  32 +#elif defined(CONFIG_MX6SX_SABRESD_REVA)
  33 +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x71000000
  34 +#define SF_QSPI2_B_CS_NUM 1
  35 +#else
  36 +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x72000000
  37 +#define SF_QSPI2_B_CS_NUM 1
  38 +#endif
29 39  
  40 +/* When using M4 fastup demo, no need these M4 env, since QSPI is used by M4 */
  41 +#ifndef CONFIG_SYS_AUXCORE_FASTUP
30 42 #define UPDATE_M4_ENV \
31 43 "m4image=m4_qspi.bin\0" \
  44 + "m4_qspi_cs="__stringify(SF_QSPI2_B_CS_NUM)"\0" \
32 45 "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
33 46 "update_m4_from_sd=" \
34   - "if sf probe 1:0; then " \
  47 + "if sf probe 1:${m4_qspi_cs}; then " \
35 48 "if run loadm4image; then " \
36 49 "setexpr fw_sz ${filesize} + 0xffff; " \
37 50 "setexpr fw_sz ${fw_sz} / 0x10000; " \
38 51  
39 52  
40 53  
41 54  
... ... @@ -40,13 +53,31 @@
40 53 "sf write ${loadaddr} 0x0 ${filesize}; " \
41 54 "fi; " \
42 55 "fi\0" \
43   - "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0""
  56 + "m4boot=sf probe 1:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0""
44 57 #else
45 58 #define UPDATE_M4_ENV ""
46   -#endif
  59 +#endif /* CONFIG_SYS_AUXCORE_FASTUP */
47 60  
  61 +#else
  62 +#define UPDATE_M4_ENV ""
  63 +#endif /* CONFIG_IMX_BOOTAUX */
  64 +
48 65 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  66 +
  67 +#define CONFIG_MFG_ENV_SETTINGS \
  68 + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  69 + "rdinit=/linuxrc " \
  70 + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  71 + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \
  72 + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  73 + "g_mass_storage.iSerialNumber=\"\" "\
  74 + "\0" \
  75 + "initrd_addr=0x83800000\0" \
  76 + "initrd_high=0xffffffff\0" \
  77 + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  78 +
49 79 #define CONFIG_EXTRA_ENV_SETTINGS \
  80 + CONFIG_MFG_ENV_SETTINGS \
50 81 UPDATE_M4_ENV \
51 82 "script=boot.scr\0" \
52 83 "image=zImage\0" \
53 84  
54 85  
55 86  
... ... @@ -54,15 +85,16 @@
54 85 "fdt_high=0xffffffff\0" \
55 86 "initrd_high=0xffffffff\0" \
56 87 "fdt_file=imx6sx-sdb.dtb\0" \
57   - "fdt_addr=0x88000000000000\0" \" \
  88 + "fdt_addr=0x83000000000000\0" \" \
58 89 "boot_fdt=try\0" \
59 90 "ip_dyn=yes\0" \
60   - "videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \
61   - "mmcdev=2\0" \
  91 + "panel=Hannstar-XGA\0" \
  92 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
62 93 "mmcpart=1\0" \
63   - "finduuid=part uuid mmc 2:2 uuid\0" \
  94 + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  95 + "mmcautodetect=yes\0" \
64 96 "mmcargs=setenv bootargs console=${console},${baudrate} " \
65   - "root=PARTUUID=${uuid} rootwait rw\0" \" \
  97 + "root=${mmcroot}\0" \" \
66 98 "loadbootscript=" \
67 99 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
68 100 "bootscript=echo Running bootscript from mmc ...; " \
... ... @@ -70,7 +102,6 @@
70 102 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
71 103 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
72 104 "mmcboot=echo Booting from mmc ...; " \
73   - "run finduuid; " \
74 105 "run mmcargs; " \
75 106 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
76 107 "if run loadfdt; then " \
77 108  
78 109  
79 110  
80 111  
81 112  
82 113  
83 114  
... ... @@ -144,26 +175,57 @@
144 175 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
145 176  
146 177 /* MMC Configuration */
  178 +
147 179 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
148 180  
149 181 /* I2C Configs */
  182 +#ifndef CONFIG_DM_I2C
  183 +#define CONFIG_SYS_I2C
  184 +#endif
  185 +#ifdef CONFIG_CMD_I2C
150 186 #define CONFIG_SYS_I2C_MXC
151 187 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
152 188 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
153 189 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
154 190 #define CONFIG_SYS_I2C_SPEED 100000
  191 +#endif
155 192  
  193 +/* PMIC */
  194 +#ifndef CONFIG_DM_PMIC
  195 +#define CONFIG_POWER
  196 +#define CONFIG_POWER_I2C
  197 +#define CONFIG_POWER_PFUZE100
  198 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
  199 +#endif
  200 +
156 201 /* Network */
157 202 #define CONFIG_FEC_MXC
158 203 #define CONFIG_MII
159 204  
  205 +#define CONFIG_FEC_ENET_DEV 1
  206 +
  207 +#if (CONFIG_FEC_ENET_DEV == 0)
160 208 #define IMX_FEC_BASE ENET_BASE_ADDR
161 209 #define CONFIG_FEC_MXC_PHYADDR 0x1
  210 +#ifdef CONFIG_DM_ETH
  211 +#define CONFIG_ETHPRIME "eth0"
  212 +#else
  213 +#define CONFIG_ETHPRIME "FEC0"
  214 +#endif
  215 +#elif (CONFIG_FEC_ENET_DEV == 1)
  216 +#define IMX_FEC_BASE ENET2_BASE_ADDR
  217 +#define CONFIG_FEC_MXC_PHYADDR 0x2
  218 +#ifdef CONFIG_DM_ETH
  219 +#define CONFIG_ETHPRIME "eth1"
  220 +#else
  221 +#define CONFIG_ETHPRIME "FEC1"
  222 +#endif
  223 +#endif
162 224  
163 225 #define CONFIG_FEC_XCV_TYPE RGMII
164   -#define CONFIG_ETHPRIME "FEC"
165 226  
166 227 #define CONFIG_PHY_ATHEROS
  228 +#define CONFIG_FEC_MXC_MDIO_BASE ENET_BASE_ADDR
167 229  
168 230 #ifdef CONFIG_CMD_USB
169 231 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
... ... @@ -182,7 +244,6 @@
182 244 #define CONFIG_IMX_THERMAL
183 245  
184 246 #ifdef CONFIG_FSL_QSPI
185   -#define CONFIG_SYS_FSL_QSPI_LE
186 247 #define CONFIG_SYS_FSL_QSPI_AHB
187 248 #ifdef CONFIG_MX6SX_SABRESD_REVA
188 249 #define FSL_QSPI_FLASH_SIZE SZ_16M
... ... @@ -190,6 +251,10 @@
190 251 #define FSL_QSPI_FLASH_SIZE SZ_32M
191 252 #endif
192 253 #define FSL_QSPI_FLASH_NUM 2
  254 +#define CONFIG_SF_DEFAULT_BUS 1
  255 +#define CONFIG_SF_DEFAULT_CS 0
  256 +#define CONFIG_SF_DEFAULT_SPEED 40000000
  257 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
193 258 #endif
194 259  
195 260 #ifndef CONFIG_SPL_BUILD
196 261  
197 262  
198 263  
199 264  
... ... @@ -201,16 +266,29 @@
201 266 #define CONFIG_BMP_16BPP
202 267 #define CONFIG_VIDEO_BMP_RLE8
203 268 #define CONFIG_VIDEO_BMP_LOGO
204   -#define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR
  269 +#define CONFIG_IMX_VIDEO_SKIP
  270 +#define CONFIG_SYS_CONSOLE_BG_COL 0x00
  271 +#define CONFIG_SYS_CONSOLE_FG_COL 0xa0
205 272 #endif
206 273 #endif
207 274  
208   -#define CONFIG_ENV_OFFSET (14 * SZ_64K)
209 275 #define CONFIG_ENV_SIZE SZ_8K
  276 +#if defined(CONFIG_ENV_IS_IN_MMC)
  277 +#define CONFIG_ENV_OFFSET (14 * SZ_64K)
  278 +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
  279 +#define CONFIG_ENV_OFFSET (896 * 1024)
  280 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
  281 +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
  282 +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  283 +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
  284 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  285 +#endif
210 286  
211 287 #define CONFIG_SYS_FSL_USDHC_NUM 3
  288 +#define CONFIG_MMCROOT "/dev/mmcblk3p2" /* USDHC4 */
212 289 #if defined(CONFIG_ENV_IS_IN_MMC)
213 290 #define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/
  291 +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
214 292 #endif
215 293  
216 294 #endif /* __CONFIG_H */
scripts/config_whitelist.txt
Diff comments   View file @ e74716b
... ... @@ -2144,6 +2144,7 @@
2144 2144 CONFIG_SYS_AUTOLOAD
2145 2145 CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
2146 2146 CONFIG_SYS_AUXCORE_BOOTDATA
  2147 +CONFIG_SYS_AUXCORE_FASTUP
2147 2148 CONFIG_SYS_BARGSIZE
2148 2149 CONFIG_SYS_BAUDRATE_TABLE
2149 2150 CONFIG_SYS_BCSR