Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 48bb3bb5ac4dd21e931ae157caad6449bcb2d0d4

Authored by Jerry Huang
Committed by Kumar Gala
1 parent cc4d122658
Exists in master and in 56 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

fsl_esdhc: Add function to reset the eSDHC controller 

To support multiple block read command we must set abort or use auto
CMD12.  If we booted from eSDHC controller neither of these are used
and thus we need to reset the controller to allow multiple block read
to function.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Showing 2 changed files with 18 additions and 0 deletions Inline Diff

drivers/mmc/fsl_esdhc.c
Diff comments   View file @ 48bb3bb
1 /* 1 /*
2 * Copyright 2007,2010 Freescale Semiconductor, Inc 2 * Copyright 2007,2010 Freescale Semiconductor, Inc
3 * Andy Fleming 3 * Andy Fleming
4 * 4 *
5 * Based vaguely on the pxa mmc code: 5 * Based vaguely on the pxa mmc code:
6 * (C) Copyright 2003 6 * (C) Copyright 2003
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
8 * 8 *
9 * See file CREDITS for list of people who contributed to this 9 * See file CREDITS for list of people who contributed to this
10 * project. 10 * project.
11 * 11 *
12 * This program is free software; you can redistribute it and/or 12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as 13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of 14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version. 15 * the License, or (at your option) any later version.
16 * 16 *
17 * This program is distributed in the hope that it will be useful, 17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details. 20 * GNU General Public License for more details.
21 * 21 *
22 * You should have received a copy of the GNU General Public License 22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software 23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA 25 * MA 02111-1307 USA
26 */ 26 */
27 27
28 #include <config.h> 28 #include <config.h>
29 #include <common.h> 29 #include <common.h>
30 #include <command.h> 30 #include <command.h>
31 #include <hwconfig.h> 31 #include <hwconfig.h>
32 #include <mmc.h> 32 #include <mmc.h>
33 #include <part.h> 33 #include <part.h>
34 #include <malloc.h> 34 #include <malloc.h>
35 #include <mmc.h> 35 #include <mmc.h>
36 #include <fsl_esdhc.h> 36 #include <fsl_esdhc.h>
37 #include <fdt_support.h> 37 #include <fdt_support.h>
38 #include <asm/io.h> 38 #include <asm/io.h>
39 39
40 DECLARE_GLOBAL_DATA_PTR; 40 DECLARE_GLOBAL_DATA_PTR;
41 41
42 struct fsl_esdhc { 42 struct fsl_esdhc {
43 uint dsaddr; 43 uint dsaddr;
44 uint blkattr; 44 uint blkattr;
45 uint cmdarg; 45 uint cmdarg;
46 uint xfertyp; 46 uint xfertyp;
47 uint cmdrsp0; 47 uint cmdrsp0;
48 uint cmdrsp1; 48 uint cmdrsp1;
49 uint cmdrsp2; 49 uint cmdrsp2;
50 uint cmdrsp3; 50 uint cmdrsp3;
51 uint datport; 51 uint datport;
52 uint prsstat; 52 uint prsstat;
53 uint proctl; 53 uint proctl;
54 uint sysctl; 54 uint sysctl;
55 uint irqstat; 55 uint irqstat;
56 uint irqstaten; 56 uint irqstaten;
57 uint irqsigen; 57 uint irqsigen;
58 uint autoc12err; 58 uint autoc12err;
59 uint hostcapblt; 59 uint hostcapblt;
60 uint wml; 60 uint wml;
61 char reserved1[8]; 61 char reserved1[8];
62 uint fevt; 62 uint fevt;
63 char reserved2[168]; 63 char reserved2[168];
64 uint hostver; 64 uint hostver;
65 char reserved3[780]; 65 char reserved3[780];
66 uint scr; 66 uint scr;
67 }; 67 };
68 68
69 /* Return the XFERTYP flags for a given command and data packet */ 69 /* Return the XFERTYP flags for a given command and data packet */
70 uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) 70 uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
71 { 71 {
72 uint xfertyp = 0; 72 uint xfertyp = 0;
73 73
74 if (data) { 74 if (data) {
75 xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN; 75 xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN;
76 76
77 if (data->blocks > 1) { 77 if (data->blocks > 1) {
78 xfertyp |= XFERTYP_MSBSEL; 78 xfertyp |= XFERTYP_MSBSEL;
79 xfertyp |= XFERTYP_BCEN; 79 xfertyp |= XFERTYP_BCEN;
80 } 80 }
81 81
82 if (data->flags & MMC_DATA_READ) 82 if (data->flags & MMC_DATA_READ)
83 xfertyp |= XFERTYP_DTDSEL; 83 xfertyp |= XFERTYP_DTDSEL;
84 } 84 }
85 85
86 if (cmd->resp_type & MMC_RSP_CRC) 86 if (cmd->resp_type & MMC_RSP_CRC)
87 xfertyp |= XFERTYP_CCCEN; 87 xfertyp |= XFERTYP_CCCEN;
88 if (cmd->resp_type & MMC_RSP_OPCODE) 88 if (cmd->resp_type & MMC_RSP_OPCODE)
89 xfertyp |= XFERTYP_CICEN; 89 xfertyp |= XFERTYP_CICEN;
90 if (cmd->resp_type & MMC_RSP_136) 90 if (cmd->resp_type & MMC_RSP_136)
91 xfertyp |= XFERTYP_RSPTYP_136; 91 xfertyp |= XFERTYP_RSPTYP_136;
92 else if (cmd->resp_type & MMC_RSP_BUSY) 92 else if (cmd->resp_type & MMC_RSP_BUSY)
93 xfertyp |= XFERTYP_RSPTYP_48_BUSY; 93 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
94 else if (cmd->resp_type & MMC_RSP_PRESENT) 94 else if (cmd->resp_type & MMC_RSP_PRESENT)
95 xfertyp |= XFERTYP_RSPTYP_48; 95 xfertyp |= XFERTYP_RSPTYP_48;
96 96
97 return XFERTYP_CMD(cmd->cmdidx) | xfertyp; 97 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
98 } 98 }
99 99
100 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) 100 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
101 { 101 {
102 uint wml_value; 102 uint wml_value;
103 int timeout; 103 int timeout;
104 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 104 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
105 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 105 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
106 106
107 wml_value = data->blocksize/4; 107 wml_value = data->blocksize/4;
108 108
109 if (data->flags & MMC_DATA_READ) { 109 if (data->flags & MMC_DATA_READ) {
110 if (wml_value > 0x10) 110 if (wml_value > 0x10)
111 wml_value = 0x10; 111 wml_value = 0x10;
112 112
113 wml_value = 0x100000 | wml_value; 113 wml_value = 0x100000 | wml_value;
114 114
115 esdhc_write32(&regs->dsaddr, (u32)data->dest); 115 esdhc_write32(&regs->dsaddr, (u32)data->dest);
116 } else { 116 } else {
117 if (wml_value > 0x80) 117 if (wml_value > 0x80)
118 wml_value = 0x80; 118 wml_value = 0x80;
119 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) { 119 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
120 printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); 120 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
121 return TIMEOUT; 121 return TIMEOUT;
122 } 122 }
123 wml_value = wml_value << 16 | 0x10; 123 wml_value = wml_value << 16 | 0x10;
124 esdhc_write32(&regs->dsaddr, (u32)data->src); 124 esdhc_write32(&regs->dsaddr, (u32)data->src);
125 } 125 }
126 126
127 esdhc_write32(&regs->wml, wml_value); 127 esdhc_write32(&regs->wml, wml_value);
128 128
129 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize); 129 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
130 130
131 /* Calculate the timeout period for data transactions */ 131 /* Calculate the timeout period for data transactions */
132 timeout = fls(mmc->tran_speed/10) - 1; 132 timeout = fls(mmc->tran_speed/10) - 1;
133 timeout -= 13; 133 timeout -= 13;
134 134
135 if (timeout > 14) 135 if (timeout > 14)
136 timeout = 14; 136 timeout = 14;
137 137
138 if (timeout < 0) 138 if (timeout < 0)
139 timeout = 0; 139 timeout = 0;
140 140
141 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); 141 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
142 142
143 return 0; 143 return 0;
144 } 144 }
145 145
146 146
147 /* 147 /*
148 * Sends a command out on the bus. Takes the mmc pointer, 148 * Sends a command out on the bus. Takes the mmc pointer,
149 * a command pointer, and an optional data pointer. 149 * a command pointer, and an optional data pointer.
150 */ 150 */
151 static int 151 static int
152 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 152 esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
153 { 153 {
154 uint xfertyp; 154 uint xfertyp;
155 uint irqstat; 155 uint irqstat;
156 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 156 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
157 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 157 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
158 158
159 esdhc_write32(&regs->irqstat, -1); 159 esdhc_write32(&regs->irqstat, -1);
160 160
161 sync(); 161 sync();
162 162
163 /* Wait for the bus to be idle */ 163 /* Wait for the bus to be idle */
164 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) || 164 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
165 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB)) 165 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
166 ; 166 ;
167 167
168 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA) 168 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
169 ; 169 ;
170 170
171 /* Wait at least 8 SD clock cycles before the next command */ 171 /* Wait at least 8 SD clock cycles before the next command */
172 /* 172 /*
173 * Note: This is way more than 8 cycles, but 1ms seems to 173 * Note: This is way more than 8 cycles, but 1ms seems to
174 * resolve timing issues with some cards 174 * resolve timing issues with some cards
175 */ 175 */
176 udelay(1000); 176 udelay(1000);
177 177
178 /* Set up for a data transfer if we have one */ 178 /* Set up for a data transfer if we have one */
179 if (data) { 179 if (data) {
180 int err; 180 int err;
181 181
182 err = esdhc_setup_data(mmc, data); 182 err = esdhc_setup_data(mmc, data);
183 if(err) 183 if(err)
184 return err; 184 return err;
185 } 185 }
186 186
187 /* Figure out the transfer arguments */ 187 /* Figure out the transfer arguments */
188 xfertyp = esdhc_xfertyp(cmd, data); 188 xfertyp = esdhc_xfertyp(cmd, data);
189 189
190 /* Send the command */ 190 /* Send the command */
191 esdhc_write32(&regs->cmdarg, cmd->cmdarg); 191 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
192 esdhc_write32(&regs->xfertyp, xfertyp); 192 esdhc_write32(&regs->xfertyp, xfertyp);
193 193
194 /* Wait for the command to complete */ 194 /* Wait for the command to complete */
195 while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC)) 195 while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
196 ; 196 ;
197 197
198 irqstat = esdhc_read32(&regs->irqstat); 198 irqstat = esdhc_read32(&regs->irqstat);
199 esdhc_write32(&regs->irqstat, irqstat); 199 esdhc_write32(&regs->irqstat, irqstat);
200 200
201 if (irqstat & CMD_ERR) 201 if (irqstat & CMD_ERR)
202 return COMM_ERR; 202 return COMM_ERR;
203 203
204 if (irqstat & IRQSTAT_CTOE) 204 if (irqstat & IRQSTAT_CTOE)
205 return TIMEOUT; 205 return TIMEOUT;
206 206
207 /* Copy the response to the response buffer */ 207 /* Copy the response to the response buffer */
208 if (cmd->resp_type & MMC_RSP_136) { 208 if (cmd->resp_type & MMC_RSP_136) {
209 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; 209 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
210 210
211 cmdrsp3 = esdhc_read32(&regs->cmdrsp3); 211 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
212 cmdrsp2 = esdhc_read32(&regs->cmdrsp2); 212 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
213 cmdrsp1 = esdhc_read32(&regs->cmdrsp1); 213 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
214 cmdrsp0 = esdhc_read32(&regs->cmdrsp0); 214 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
215 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); 215 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
216 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); 216 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
217 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); 217 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
218 cmd->response[3] = (cmdrsp0 << 8); 218 cmd->response[3] = (cmdrsp0 << 8);
219 } else 219 } else
220 cmd->response[0] = esdhc_read32(&regs->cmdrsp0); 220 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
221 221
222 /* Wait until all of the blocks are transferred */ 222 /* Wait until all of the blocks are transferred */
223 if (data) { 223 if (data) {
224 do { 224 do {
225 irqstat = esdhc_read32(&regs->irqstat); 225 irqstat = esdhc_read32(&regs->irqstat);
226 226
227 if (irqstat & DATA_ERR) 227 if (irqstat & DATA_ERR)
228 return COMM_ERR; 228 return COMM_ERR;
229 229
230 if (irqstat & IRQSTAT_DTOE) 230 if (irqstat & IRQSTAT_DTOE)
231 return TIMEOUT; 231 return TIMEOUT;
232 } while (!(irqstat & IRQSTAT_TC) && 232 } while (!(irqstat & IRQSTAT_TC) &&
233 (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)); 233 (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
234 } 234 }
235 235
236 esdhc_write32(&regs->irqstat, -1); 236 esdhc_write32(&regs->irqstat, -1);
237 237
238 return 0; 238 return 0;
239 } 239 }
240 240
241 void set_sysctl(struct mmc *mmc, uint clock) 241 void set_sysctl(struct mmc *mmc, uint clock)
242 { 242 {
243 int sdhc_clk = gd->sdhc_clk; 243 int sdhc_clk = gd->sdhc_clk;
244 int div, pre_div; 244 int div, pre_div;
245 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 245 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
246 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 246 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
247 uint clk; 247 uint clk;
248 248
249 if (clock < mmc->f_min) 249 if (clock < mmc->f_min)
250 clock = mmc->f_min; 250 clock = mmc->f_min;
251 251
252 if (sdhc_clk / 16 > clock) { 252 if (sdhc_clk / 16 > clock) {
253 for (pre_div = 2; pre_div < 256; pre_div *= 2) 253 for (pre_div = 2; pre_div < 256; pre_div *= 2)
254 if ((sdhc_clk / pre_div) <= (clock * 16)) 254 if ((sdhc_clk / pre_div) <= (clock * 16))
255 break; 255 break;
256 } else 256 } else
257 pre_div = 2; 257 pre_div = 2;
258 258
259 for (div = 1; div <= 16; div++) 259 for (div = 1; div <= 16; div++)
260 if ((sdhc_clk / (div * pre_div)) <= clock) 260 if ((sdhc_clk / (div * pre_div)) <= clock)
261 break; 261 break;
262 262
263 pre_div >>= 1; 263 pre_div >>= 1;
264 div -= 1; 264 div -= 1;
265 265
266 clk = (pre_div << 8) | (div << 4); 266 clk = (pre_div << 8) | (div << 4);
267 267
268 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); 268 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
269 269
270 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk); 270 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
271 271
272 udelay(10000); 272 udelay(10000);
273 273
274 clk = SYSCTL_PEREN | SYSCTL_CKEN; 274 clk = SYSCTL_PEREN | SYSCTL_CKEN;
275 275
276 esdhc_setbits32(&regs->sysctl, clk); 276 esdhc_setbits32(&regs->sysctl, clk);
277 } 277 }
278 278
279 static void esdhc_set_ios(struct mmc *mmc) 279 static void esdhc_set_ios(struct mmc *mmc)
280 { 280 {
281 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 281 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
282 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 282 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
283 283
284 /* Set the clock speed */ 284 /* Set the clock speed */
285 set_sysctl(mmc, mmc->clock); 285 set_sysctl(mmc, mmc->clock);
286 286
287 /* Set the bus width */ 287 /* Set the bus width */
288 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); 288 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
289 289
290 if (mmc->bus_width == 4) 290 if (mmc->bus_width == 4)
291 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4); 291 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
292 else if (mmc->bus_width == 8) 292 else if (mmc->bus_width == 8)
293 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8); 293 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
294 294
295 } 295 }
296 296
297 static int esdhc_init(struct mmc *mmc) 297 static int esdhc_init(struct mmc *mmc)
298 { 298 {
299 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 299 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
300 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; 300 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
301 int timeout = 1000; 301 int timeout = 1000;
302 int ret = 0; 302 int ret = 0;
303 u8 card_absent; 303 u8 card_absent;
304 304
305 /* Enable cache snooping */ 305 /* Enable cache snooping */
306 if (cfg && !cfg->no_snoop) 306 if (cfg && !cfg->no_snoop)
307 esdhc_write32(&regs->scr, 0x00000040); 307 esdhc_write32(&regs->scr, 0x00000040);
308 308
309 /* Reset the entire host controller */ 309 /* Reset the entire host controller */
310 esdhc_write32(&regs->sysctl, SYSCTL_RSTA); 310 esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
311 311
312 /* Wait until the controller is available */ 312 /* Wait until the controller is available */
313 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout) 313 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
314 udelay(1000); 314 udelay(1000);
315 315
316 esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); 316 esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
317 317
318 /* Set the initial clock speed */ 318 /* Set the initial clock speed */
319 set_sysctl(mmc, 400000); 319 set_sysctl(mmc, 400000);
320 320
321 /* Disable the BRR and BWR bits in IRQSTAT */ 321 /* Disable the BRR and BWR bits in IRQSTAT */
322 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); 322 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
323 323
324 /* Put the PROCTL reg back to the default */ 324 /* Put the PROCTL reg back to the default */
325 esdhc_write32(&regs->proctl, PROCTL_INIT); 325 esdhc_write32(&regs->proctl, PROCTL_INIT);
326 326
327 /* Set timout to the maximum value */ 327 /* Set timout to the maximum value */
328 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); 328 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
329 329
330 /* Check if there is a callback for detecting the card */ 330 /* Check if there is a callback for detecting the card */
331 if (board_mmc_getcd(&card_absent, mmc)) { 331 if (board_mmc_getcd(&card_absent, mmc)) {
332 timeout = 1000; 332 timeout = 1000;
333 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && 333 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) &&
334 --timeout) 334 --timeout)
335 udelay(1000); 335 udelay(1000);
336 336
337 if (timeout <= 0) 337 if (timeout <= 0)
338 ret = NO_CARD_ERR; 338 ret = NO_CARD_ERR;
339 } else { 339 } else {
340 if (card_absent) 340 if (card_absent)
341 ret = NO_CARD_ERR; 341 ret = NO_CARD_ERR;
342 } 342 }
343 343
344 return ret; 344 return ret;
345 } 345 }
346 346
347 static void esdhc_reset(struct fsl_esdhc *regs)
348 {
349 unsigned long timeout = 100; /* wait max 100 ms */
350
351 /* reset the controller */
352 esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
353
354 /* hardware clears the bit when it is done */
355 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
356 udelay(1000);
357 if (!timeout)
358 printf("MMC/SD: Reset never completed.\n");
359 }
360
347 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) 361 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
348 { 362 {
349 struct fsl_esdhc *regs; 363 struct fsl_esdhc *regs;
350 struct mmc *mmc; 364 struct mmc *mmc;
351 u32 caps; 365 u32 caps;
352 366
353 if (!cfg) 367 if (!cfg)
354 return -1; 368 return -1;
355 369
356 mmc = malloc(sizeof(struct mmc)); 370 mmc = malloc(sizeof(struct mmc));
357 371
358 sprintf(mmc->name, "FSL_ESDHC"); 372 sprintf(mmc->name, "FSL_ESDHC");
359 regs = (struct fsl_esdhc *)cfg->esdhc_base; 373 regs = (struct fsl_esdhc *)cfg->esdhc_base;
374
375 /* First reset the eSDHC controller */
376 esdhc_reset(regs);
360 377
361 mmc->priv = cfg; 378 mmc->priv = cfg;
362 mmc->send_cmd = esdhc_send_cmd; 379 mmc->send_cmd = esdhc_send_cmd;
363 mmc->set_ios = esdhc_set_ios; 380 mmc->set_ios = esdhc_set_ios;
364 mmc->init = esdhc_init; 381 mmc->init = esdhc_init;
365 382
366 caps = regs->hostcapblt; 383 caps = regs->hostcapblt;
367 384
368 if (caps & ESDHC_HOSTCAPBLT_VS18) 385 if (caps & ESDHC_HOSTCAPBLT_VS18)
369 mmc->voltages |= MMC_VDD_165_195; 386 mmc->voltages |= MMC_VDD_165_195;
370 if (caps & ESDHC_HOSTCAPBLT_VS30) 387 if (caps & ESDHC_HOSTCAPBLT_VS30)
371 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; 388 mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
372 if (caps & ESDHC_HOSTCAPBLT_VS33) 389 if (caps & ESDHC_HOSTCAPBLT_VS33)
373 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; 390 mmc->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
374 391
375 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; 392 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
376 393
377 if (caps & ESDHC_HOSTCAPBLT_HSS) 394 if (caps & ESDHC_HOSTCAPBLT_HSS)
378 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; 395 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
379 396
380 mmc->f_min = 400000; 397 mmc->f_min = 400000;
381 mmc->f_max = MIN(gd->sdhc_clk, 50000000); 398 mmc->f_max = MIN(gd->sdhc_clk, 50000000);
382 399
383 mmc_register(mmc); 400 mmc_register(mmc);
384 401
385 return 0; 402 return 0;
386 } 403 }
387 404
388 int fsl_esdhc_mmc_init(bd_t *bis) 405 int fsl_esdhc_mmc_init(bd_t *bis)
389 { 406 {
390 struct fsl_esdhc_cfg *cfg; 407 struct fsl_esdhc_cfg *cfg;
391 408
392 cfg = malloc(sizeof(struct fsl_esdhc_cfg)); 409 cfg = malloc(sizeof(struct fsl_esdhc_cfg));
393 memset(cfg, 0, sizeof(struct fsl_esdhc_cfg)); 410 memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
394 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; 411 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
395 return fsl_esdhc_initialize(bis, cfg); 412 return fsl_esdhc_initialize(bis, cfg);
396 } 413 }
397 414
398 #ifdef CONFIG_OF_LIBFDT 415 #ifdef CONFIG_OF_LIBFDT
399 void fdt_fixup_esdhc(void *blob, bd_t *bd) 416 void fdt_fixup_esdhc(void *blob, bd_t *bd)
400 { 417 {
401 const char *compat = "fsl,esdhc"; 418 const char *compat = "fsl,esdhc";
402 const char *status = "okay"; 419 const char *status = "okay";
403 420
404 if (!hwconfig("esdhc")) { 421 if (!hwconfig("esdhc")) {
405 status = "disabled"; 422 status = "disabled";
406 goto out; 423 goto out;
407 } 424 }
408 425
409 do_fixup_by_compat_u32(blob, compat, "clock-frequency", 426 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
410 gd->sdhc_clk, 1); 427 gd->sdhc_clk, 1);
411 out: 428 out:
412 do_fixup_by_compat(blob, compat, "status", status, 429 do_fixup_by_compat(blob, compat, "status", status,
413 strlen(status) + 1, 1); 430 strlen(status) + 1, 1);
414 } 431 }
415 #endif 432 #endif
416 433
1 /* 1 /*
2 * FSL SD/MMC Defines 2 * FSL SD/MMC Defines
3 *------------------------------------------------------------------- 3 *-------------------------------------------------------------------
4 * 4 *
5 * Copyright 2007-2008,2010 Freescale Semiconductor, Inc 5 * Copyright 2007-2008,2010 Freescale Semiconductor, Inc
6 * 6 *
7 * This program is free software; you can redistribute it and/or 7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as 8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of 9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version. 10 * the License, or (at your option) any later version.
11 * 11 *
12 * This program is distributed in the hope that it will be useful, 12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 * 16 *
17 * You should have received a copy of the GNU General Public License 17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA 20 * MA 02111-1307 USA
21 * 21 *
22 *------------------------------------------------------------------- 22 *-------------------------------------------------------------------
23 * 23 *
24 */ 24 */
25 25
26 #ifndef __FSL_ESDHC_H__ 26 #ifndef __FSL_ESDHC_H__
27 #define __FSL_ESDHC_H__ 27 #define __FSL_ESDHC_H__
28 28
29 #include <asm/errno.h> 29 #include <asm/errno.h>
30 #include <asm/byteorder.h> 30 #include <asm/byteorder.h>
31 31
32 /* FSL eSDHC-specific constants */ 32 /* FSL eSDHC-specific constants */
33 #define SYSCTL 0x0002e02c 33 #define SYSCTL 0x0002e02c
34 #define SYSCTL_INITA 0x08000000 34 #define SYSCTL_INITA 0x08000000
35 #define SYSCTL_TIMEOUT_MASK 0x000f0000 35 #define SYSCTL_TIMEOUT_MASK 0x000f0000
36 #define SYSCTL_CLOCK_MASK 0x0000fff0 36 #define SYSCTL_CLOCK_MASK 0x0000fff0
37 #define SYSCTL_RSTA 0x01000000 37 #define SYSCTL_RSTA 0x01000000
38 #define SYSCTL_CKEN 0x00000008 38 #define SYSCTL_CKEN 0x00000008
39 #define SYSCTL_PEREN 0x00000004 39 #define SYSCTL_PEREN 0x00000004
40 #define SYSCTL_HCKEN 0x00000002 40 #define SYSCTL_HCKEN 0x00000002
41 #define SYSCTL_IPGEN 0x00000001 41 #define SYSCTL_IPGEN 0x00000001
42 #define SYSCTL_RSTA 0x01000000
42 43
43 #define IRQSTAT 0x0002e030 44 #define IRQSTAT 0x0002e030
44 #define IRQSTAT_DMAE (0x10000000) 45 #define IRQSTAT_DMAE (0x10000000)
45 #define IRQSTAT_AC12E (0x01000000) 46 #define IRQSTAT_AC12E (0x01000000)
46 #define IRQSTAT_DEBE (0x00400000) 47 #define IRQSTAT_DEBE (0x00400000)
47 #define IRQSTAT_DCE (0x00200000) 48 #define IRQSTAT_DCE (0x00200000)
48 #define IRQSTAT_DTOE (0x00100000) 49 #define IRQSTAT_DTOE (0x00100000)
49 #define IRQSTAT_CIE (0x00080000) 50 #define IRQSTAT_CIE (0x00080000)
50 #define IRQSTAT_CEBE (0x00040000) 51 #define IRQSTAT_CEBE (0x00040000)
51 #define IRQSTAT_CCE (0x00020000) 52 #define IRQSTAT_CCE (0x00020000)
52 #define IRQSTAT_CTOE (0x00010000) 53 #define IRQSTAT_CTOE (0x00010000)
53 #define IRQSTAT_CINT (0x00000100) 54 #define IRQSTAT_CINT (0x00000100)
54 #define IRQSTAT_CRM (0x00000080) 55 #define IRQSTAT_CRM (0x00000080)
55 #define IRQSTAT_CINS (0x00000040) 56 #define IRQSTAT_CINS (0x00000040)
56 #define IRQSTAT_BRR (0x00000020) 57 #define IRQSTAT_BRR (0x00000020)
57 #define IRQSTAT_BWR (0x00000010) 58 #define IRQSTAT_BWR (0x00000010)
58 #define IRQSTAT_DINT (0x00000008) 59 #define IRQSTAT_DINT (0x00000008)
59 #define IRQSTAT_BGE (0x00000004) 60 #define IRQSTAT_BGE (0x00000004)
60 #define IRQSTAT_TC (0x00000002) 61 #define IRQSTAT_TC (0x00000002)
61 #define IRQSTAT_CC (0x00000001) 62 #define IRQSTAT_CC (0x00000001)
62 63
63 #define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE) 64 #define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
64 #define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE) 65 #define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE)
65 66
66 #define IRQSTATEN 0x0002e034 67 #define IRQSTATEN 0x0002e034
67 #define IRQSTATEN_DMAE (0x10000000) 68 #define IRQSTATEN_DMAE (0x10000000)
68 #define IRQSTATEN_AC12E (0x01000000) 69 #define IRQSTATEN_AC12E (0x01000000)
69 #define IRQSTATEN_DEBE (0x00400000) 70 #define IRQSTATEN_DEBE (0x00400000)
70 #define IRQSTATEN_DCE (0x00200000) 71 #define IRQSTATEN_DCE (0x00200000)
71 #define IRQSTATEN_DTOE (0x00100000) 72 #define IRQSTATEN_DTOE (0x00100000)
72 #define IRQSTATEN_CIE (0x00080000) 73 #define IRQSTATEN_CIE (0x00080000)
73 #define IRQSTATEN_CEBE (0x00040000) 74 #define IRQSTATEN_CEBE (0x00040000)
74 #define IRQSTATEN_CCE (0x00020000) 75 #define IRQSTATEN_CCE (0x00020000)
75 #define IRQSTATEN_CTOE (0x00010000) 76 #define IRQSTATEN_CTOE (0x00010000)
76 #define IRQSTATEN_CINT (0x00000100) 77 #define IRQSTATEN_CINT (0x00000100)
77 #define IRQSTATEN_CRM (0x00000080) 78 #define IRQSTATEN_CRM (0x00000080)
78 #define IRQSTATEN_CINS (0x00000040) 79 #define IRQSTATEN_CINS (0x00000040)
79 #define IRQSTATEN_BRR (0x00000020) 80 #define IRQSTATEN_BRR (0x00000020)
80 #define IRQSTATEN_BWR (0x00000010) 81 #define IRQSTATEN_BWR (0x00000010)
81 #define IRQSTATEN_DINT (0x00000008) 82 #define IRQSTATEN_DINT (0x00000008)
82 #define IRQSTATEN_BGE (0x00000004) 83 #define IRQSTATEN_BGE (0x00000004)
83 #define IRQSTATEN_TC (0x00000002) 84 #define IRQSTATEN_TC (0x00000002)
84 #define IRQSTATEN_CC (0x00000001) 85 #define IRQSTATEN_CC (0x00000001)
85 86
86 #define PRSSTAT 0x0002e024 87 #define PRSSTAT 0x0002e024
87 #define PRSSTAT_CLSL (0x00800000) 88 #define PRSSTAT_CLSL (0x00800000)
88 #define PRSSTAT_WPSPL (0x00080000) 89 #define PRSSTAT_WPSPL (0x00080000)
89 #define PRSSTAT_CDPL (0x00040000) 90 #define PRSSTAT_CDPL (0x00040000)
90 #define PRSSTAT_CINS (0x00010000) 91 #define PRSSTAT_CINS (0x00010000)
91 #define PRSSTAT_BREN (0x00000800) 92 #define PRSSTAT_BREN (0x00000800)
92 #define PRSSTAT_DLA (0x00000004) 93 #define PRSSTAT_DLA (0x00000004)
93 #define PRSSTAT_CICHB (0x00000002) 94 #define PRSSTAT_CICHB (0x00000002)
94 #define PRSSTAT_CIDHB (0x00000001) 95 #define PRSSTAT_CIDHB (0x00000001)
95 96
96 #define PROCTL 0x0002e028 97 #define PROCTL 0x0002e028
97 #define PROCTL_INIT 0x00000020 98 #define PROCTL_INIT 0x00000020
98 #define PROCTL_DTW_4 0x00000002 99 #define PROCTL_DTW_4 0x00000002
99 #define PROCTL_DTW_8 0x00000004 100 #define PROCTL_DTW_8 0x00000004
100 101
101 #define CMDARG 0x0002e008 102 #define CMDARG 0x0002e008
102 103
103 #define XFERTYP 0x0002e00c 104 #define XFERTYP 0x0002e00c
104 #define XFERTYP_CMD(x) ((x & 0x3f) << 24) 105 #define XFERTYP_CMD(x) ((x & 0x3f) << 24)
105 #define XFERTYP_CMDTYP_NORMAL 0x0 106 #define XFERTYP_CMDTYP_NORMAL 0x0
106 #define XFERTYP_CMDTYP_SUSPEND 0x00400000 107 #define XFERTYP_CMDTYP_SUSPEND 0x00400000
107 #define XFERTYP_CMDTYP_RESUME 0x00800000 108 #define XFERTYP_CMDTYP_RESUME 0x00800000
108 #define XFERTYP_CMDTYP_ABORT 0x00c00000 109 #define XFERTYP_CMDTYP_ABORT 0x00c00000
109 #define XFERTYP_DPSEL 0x00200000 110 #define XFERTYP_DPSEL 0x00200000
110 #define XFERTYP_CICEN 0x00100000 111 #define XFERTYP_CICEN 0x00100000
111 #define XFERTYP_CCCEN 0x00080000 112 #define XFERTYP_CCCEN 0x00080000
112 #define XFERTYP_RSPTYP_NONE 0 113 #define XFERTYP_RSPTYP_NONE 0
113 #define XFERTYP_RSPTYP_136 0x00010000 114 #define XFERTYP_RSPTYP_136 0x00010000
114 #define XFERTYP_RSPTYP_48 0x00020000 115 #define XFERTYP_RSPTYP_48 0x00020000
115 #define XFERTYP_RSPTYP_48_BUSY 0x00030000 116 #define XFERTYP_RSPTYP_48_BUSY 0x00030000
116 #define XFERTYP_MSBSEL 0x00000020 117 #define XFERTYP_MSBSEL 0x00000020
117 #define XFERTYP_DTDSEL 0x00000010 118 #define XFERTYP_DTDSEL 0x00000010
118 #define XFERTYP_AC12EN 0x00000004 119 #define XFERTYP_AC12EN 0x00000004
119 #define XFERTYP_BCEN 0x00000002 120 #define XFERTYP_BCEN 0x00000002
120 #define XFERTYP_DMAEN 0x00000001 121 #define XFERTYP_DMAEN 0x00000001
121 122
122 #define CINS_TIMEOUT 1000 123 #define CINS_TIMEOUT 1000
123 124
124 #define DSADDR 0x2e004 125 #define DSADDR 0x2e004
125 126
126 #define CMDRSP0 0x2e010 127 #define CMDRSP0 0x2e010
127 #define CMDRSP1 0x2e014 128 #define CMDRSP1 0x2e014
128 #define CMDRSP2 0x2e018 129 #define CMDRSP2 0x2e018
129 #define CMDRSP3 0x2e01c 130 #define CMDRSP3 0x2e01c
130 131
131 #define DATPORT 0x2e020 132 #define DATPORT 0x2e020
132 133
133 #define WML 0x2e044 134 #define WML 0x2e044
134 #define WML_WRITE 0x00010000 135 #define WML_WRITE 0x00010000
135 136
136 #define BLKATTR 0x2e004 137 #define BLKATTR 0x2e004
137 #define BLKATTR_CNT(x) ((x & 0xffff) << 16) 138 #define BLKATTR_CNT(x) ((x & 0xffff) << 16)
138 #define BLKATTR_SIZE(x) (x & 0x1fff) 139 #define BLKATTR_SIZE(x) (x & 0x1fff)
139 #define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */ 140 #define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
140 141
141 #define ESDHC_HOSTCAPBLT_VS18 0x04000000 142 #define ESDHC_HOSTCAPBLT_VS18 0x04000000
142 #define ESDHC_HOSTCAPBLT_VS30 0x02000000 143 #define ESDHC_HOSTCAPBLT_VS30 0x02000000
143 #define ESDHC_HOSTCAPBLT_VS33 0x01000000 144 #define ESDHC_HOSTCAPBLT_VS33 0x01000000
144 #define ESDHC_HOSTCAPBLT_SRS 0x00800000 145 #define ESDHC_HOSTCAPBLT_SRS 0x00800000
145 #define ESDHC_HOSTCAPBLT_DMAS 0x00400000 146 #define ESDHC_HOSTCAPBLT_DMAS 0x00400000
146 #define ESDHC_HOSTCAPBLT_HSS 0x00200000 147 #define ESDHC_HOSTCAPBLT_HSS 0x00200000
147 148
148 struct fsl_esdhc_cfg { 149 struct fsl_esdhc_cfg {
149 u32 esdhc_base; 150 u32 esdhc_base;
150 u32 no_snoop; 151 u32 no_snoop;
151 }; 152 };
152 153
153 /* Select the correct accessors depending on endianess */ 154 /* Select the correct accessors depending on endianess */
154 #if __BYTE_ORDER == __LITTLE_ENDIAN 155 #if __BYTE_ORDER == __LITTLE_ENDIAN
155 #define esdhc_read32 in_le32 156 #define esdhc_read32 in_le32
156 #define esdhc_write32 out_le32 157 #define esdhc_write32 out_le32
157 #define esdhc_clrsetbits32 clrsetbits_le32 158 #define esdhc_clrsetbits32 clrsetbits_le32
158 #define esdhc_clrbits32 clrbits_le32 159 #define esdhc_clrbits32 clrbits_le32
159 #define esdhc_setbits32 setbits_le32 160 #define esdhc_setbits32 setbits_le32
160 #elif __BYTE_ORDER == __BIG_ENDIAN 161 #elif __BYTE_ORDER == __BIG_ENDIAN
161 #define esdhc_read32 in_be32 162 #define esdhc_read32 in_be32
162 #define esdhc_write32 out_be32 163 #define esdhc_write32 out_be32
163 #define esdhc_clrsetbits32 clrsetbits_be32 164 #define esdhc_clrsetbits32 clrsetbits_be32
164 #define esdhc_clrbits32 clrbits_be32 165 #define esdhc_clrbits32 clrbits_be32
165 #define esdhc_setbits32 setbits_be32 166 #define esdhc_setbits32 setbits_be32
166 #else 167 #else
167 #error "Endianess is not defined: please fix to continue" 168 #error "Endianess is not defined: please fix to continue"
168 #endif 169 #endif
169 170
170 #ifdef CONFIG_FSL_ESDHC 171 #ifdef CONFIG_FSL_ESDHC
171 int fsl_esdhc_mmc_init(bd_t *bis); 172 int fsl_esdhc_mmc_init(bd_t *bis);
172 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg); 173 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
173 void fdt_fixup_esdhc(void *blob, bd_t *bd); 174 void fdt_fixup_esdhc(void *blob, bd_t *bd);
174 #else 175 #else
175 static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; } 176 static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
176 static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {} 177 static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
177 #endif /* CONFIG_FSL_ESDHC */ 178 #endif /* CONFIG_FSL_ESDHC */
178 179
179 #endif /* __FSL_ESDHC_H__ */ 180 #endif /* __FSL_ESDHC_H__ */
180 181