fsl_esdhc: Add function to reset the eSDHC controller

To support multiple block read command we must set abort or use auto CMD12. If we booted from eSDHC controller neither of these are used and thus we need to reset the controller to allow multiple block read to function. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

fsl_esdhc: Add function to reset the eSDHC controller
To support multiple block read command we must set abort or use auto CMD12. If we booted from eSDHC controller neither of these are used and thus we need to reset the controller to allow multiple block read to function. Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Jerry Huang · Kumar Gala
1 parent cc4d122658
Showing 2 changed files with 18 additions and 0 deletions Side-by-side Diff
drivers/mmc/fsl_esdhc.c
include/fsl_esdhc.h
@@ -344,6 +344,20 @@
 	return ret;
 }
  
+static void esdhc_reset(struct fsl_esdhc *regs)
+{
+	unsigned long timeout = 100; /* wait max 100 ms */
+
+	/* reset the controller */
+	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
+
+	/* hardware clears the bit when it is done */
+	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
+		udelay(1000);
+	if (!timeout)
+		printf("MMC/SD: Reset never completed.\n");
+}
+
 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 {
 	struct fsl_esdhc *regs;
@@ -357,6 +371,9 @@
  
 	sprintf(mmc->name, "FSL_ESDHC");
 	regs = (struct fsl_esdhc *)cfg->esdhc_base;
+
+	/* First reset the eSDHC controller */
+	esdhc_reset(regs);
  
 	mmc->priv = cfg;
 	mmc->send_cmd = esdhc_send_cmd;
@@ -39,6 +39,7 @@
 #define SYSCTL_PEREN		0x00000004
 #define SYSCTL_HCKEN		0x00000002
 #define SYSCTL_IPGEN		0x00000001
+#define SYSCTL_RSTA		0x01000000
  
 #define IRQSTAT			0x0002e030
 #define IRQSTAT_DMAE		(0x10000000)
...	...	@@ -344,6 +344,20 @@
344	344	return ret;
345	345	}
346	346
	347	+static void esdhc_reset(struct fsl_esdhc *regs)
	348	+{
	349	+ unsigned long timeout = 100; /* wait max 100 ms */
	350	+
	351	+ /* reset the controller */
	352	+ esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
	353	+
	354	+ /* hardware clears the bit when it is done */
	355	+ while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
	356	+ udelay(1000);
	357	+ if (!timeout)
	358	+ printf("MMC/SD: Reset never completed.\n");
	359	+}
	360	+
347	361	int fsl_esdhc_initialize(bd_t bis, struct fsl_esdhc_cfg cfg)
348	362	{
349	363	struct fsl_esdhc *regs;
...	...	@@ -357,6 +371,9 @@
357	371
358	372	sprintf(mmc->name, "FSL_ESDHC");
359	373	regs = (struct fsl_esdhc *)cfg->esdhc_base;
	374	+
	375	+ /* First reset the eSDHC controller */
	376	+ esdhc_reset(regs);
360	377
361	378	mmc->priv = cfg;
362	379	mmc->send_cmd = esdhc_send_cmd;
...	...	@@ -39,6 +39,7 @@
39	39	#define SYSCTL_PEREN 0x00000004
40	40	#define SYSCTL_HCKEN 0x00000002
41	41	#define SYSCTL_IPGEN 0x00000001
	42	+#define SYSCTL_RSTA 0x01000000
42	43
43	44	#define IRQSTAT 0x0002e030
44	45	#define IRQSTAT_DMAE (0x10000000)