Eric Lee / smarc-uboot

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Commit 49413ea3f5b05079c11d284a8520da2bc421442e

Authored by Luka Perkov
Committed by Luka Perkov
1 parent 37b608a52d
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

cosmetic: kirkwood: style fixes in kwbimage.cfg files 

When diffing through the changes only the relevant changes
should be displayed.

Signed-off-by: Luka Perkov <luka@openwrt.org>
Acked-by: Stefan Roese <sr@denx.de>

Showing 2 changed files with 13 additions and 13 deletions Side-by-side Diff

board/iomega/iconnect/kwbimage.cfg
Diff comments   View file @ 49413ea
... ... @@ -20,7 +20,7 @@
20 20 # Configure RGMII-0 interface pad voltage to 1.8V
21 21 DATA 0xffd100e0 0x1b1b1b9b
22 22  
23   -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
  23 +# Dram initalization for SINGLE x16 CL=5 @ 400MHz
24 24 DATA 0xffd01400 0x43000c30 # DDR Configuration register
25 25 # bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
26 26 # bit23-14: 0x0,
... ... @@ -87,7 +87,7 @@
87 87 # bit6-4: 0x4, CL=5
88 88 # bit7: 0x0, TestMode=0 normal
89 89 # bit8: 0x0, DLL reset=0 normal
90   -# bit11-9: 0x6, auto-precharge write recovery ????????????
  90 +# bit11-9: 0x6, auto-precharge write recovery
91 91 # bit12: 0x0, PD must be zero
92 92 # bit31-13: 0x0, required
93 93  
board/raidsonic/ib62x0/kwbimage.cfg
Diff comments   View file @ 49413ea
... ... @@ -11,7 +11,7 @@
11 11 #
12 12  
13 13 # Boot Media configurations
14   -BOOT_FROM nand # change from nand to uart if building UART image
  14 +BOOT_FROM nand
15 15 NAND_ECC_MODE default
16 16 NAND_PAGE_SIZE 0x0800
17 17  
18 18  
... ... @@ -21,12 +21,12 @@
21 21 # Configure RGMII-0 interface pad voltage to 1.8V
22 22 DATA 0xffd100e0 0x1b1b1b9b
23 23  
24   -#Dram initalization for SINGLE x16 CL=5 @ 400MHz
  24 +# Dram initalization for SINGLE x16 CL=5 @ 400MHz
25 25 DATA 0xffd01400 0x43000c30 # DDR Configuration register
26 26 # bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
27 27 # bit23-14: 0x0,
28   -# bit24: 0x1, enable exit self refresh mode on DDR access
29   -# bit25: 0x1, required
  28 +# bit24: 0x1, enable exit self refresh mode on DDR access
  29 +# bit25: 0x1, required
30 30 # bit29-26: 0x0,
31 31 # bit31-30: 0x1,
32 32  
... ... @@ -64,10 +64,10 @@
64 64 # bit3-2: 11, Cs0size (1Gb)
65 65 # bit5-4: 00, Cs1width (x8)
66 66 # bit7-6: 11, Cs1size (1Gb)
67   -# bit9-8: 00, Cs2width (nonexistent
68   -# bit11-10: 00, Cs2size (nonexistent
69   -# bit13-12: 00, Cs3width (nonexistent
70   -# bit15-14: 00, Cs3size (nonexistent
  67 +# bit9-8: 00, Cs2width (nonexistent)
  68 +# bit11-10: 00, Cs2size (nonexistent)
  69 +# bit13-12: 00, Cs3width (nonexistent)
  70 +# bit15-14: 00, Cs3size (nonexistent)
71 71 # bit16: 0, Cs0AddrSel
72 72 # bit17: 0, Cs1AddrSel
73 73 # bit18: 0, Cs2AddrSel
... ... @@ -88,7 +88,7 @@
88 88 # bit6-4: 0x4, CL=5
89 89 # bit7: 0x0, TestMode=0 normal
90 90 # bit8: 0x0, DLL reset=0 normal
91   -# bit11-9: 0x6, auto-precharge write recovery ????????????
  91 +# bit11-9: 0x6, auto-precharge write recovery
92 92 # bit12: 0x0, PD must be zero
93 93 # bit31-13: 0x0, required
94 94  
... ... @@ -148,8 +148,8 @@
148 148 DATA 0xffd01480 0x00000001 # DDR Initialization Control
149 149 # bit0: 0x1, enable DDR init upon this register write
150 150  
151   -DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
152   -DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
  151 +DATA 0xffd20134 0x66666666 # L2 RAM Timing 0 Register
  152 +DATA 0xffd20138 0x66666666 # L2 RAM Timing 1 Register
153 153  
154 154 # End of Header extension
155 155 DATA 0x0 0x0