Eric Lee / smarc-uboot

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Commit 4c95f3389019ae1cf87f78057d4f8071c43e20c3

Authored by Marek Vasut
Committed by Haibo Chen
1 parent 128b1aaf8d
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 4 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

mmc: Add support for downgrading HS200/HS400 to HS mode 

The mmc_select_mode_and_width() function can be called while the card
is in HS200/HS400 mode and can be used to downgrade the card to lower
mode, e.g. HS. This is used for example by mmc_boot_part_access_chk()
which cannot access the card in HS200/HS400 mode and which is in turn
called by saveenv if env is in the MMC.

In such case, forcing the card clock to legacy frequency cannot work.
Instead, the card must be switched to HS mode first, from which it can
then be reprogrammed as needed.

However, this procedure needs additional code changes, since the current
implementation checks whether the card correctly switched to HS mode in
mmc_set_card_speed(). The check only expects that the card will be going
to HS mode from lower modes, not from higher modes, hence add a parameter
which indicates that the HS200/HS400 to HS downgrade is happening. This
makes the code send the switch command first, reconfigure the controller
next and finally perform the EXT_CSD readback check. The last two steps
cannot be done in reverse order as the card is already in HS mode when
the clock are being switched on the controller side.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
(cherry picked from commit 523f613609545252f08f01f346ba4b0403f78b7c)
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>

Showing 1 changed file with 33 additions and 6 deletions Inline Diff

1 /* 1 /*
2 * Copyright 2008, Freescale Semiconductor, Inc 2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming 3 * Andy Fleming
4 * 4 *
5 * Based vaguely on the Linux code 5 * Based vaguely on the Linux code
6 * 6 *
7 * SPDX-License-Identifier: GPL-2.0+ 7 * SPDX-License-Identifier: GPL-2.0+
8 */ 8 */
9 9
10 #include <config.h> 10 #include <config.h>
11 #include <common.h> 11 #include <common.h>
12 #include <command.h> 12 #include <command.h>
13 #include <dm.h> 13 #include <dm.h>
14 #include <dm/device-internal.h> 14 #include <dm/device-internal.h>
15 #include <errno.h> 15 #include <errno.h>
16 #include <mmc.h> 16 #include <mmc.h>
17 #include <part.h> 17 #include <part.h>
18 #include <power/regulator.h> 18 #include <power/regulator.h>
19 #include <malloc.h> 19 #include <malloc.h>
20 #include <memalign.h> 20 #include <memalign.h>
21 #include <linux/list.h> 21 #include <linux/list.h>
22 #include <div64.h> 22 #include <div64.h>
23 #include "mmc_private.h" 23 #include "mmc_private.h"
24 24
25 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage); 25 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
26 static int mmc_power_cycle(struct mmc *mmc); 26 static int mmc_power_cycle(struct mmc *mmc);
27 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps); 27 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps);
28 28
29 #if CONFIG_IS_ENABLED(MMC_TINY) 29 #if CONFIG_IS_ENABLED(MMC_TINY)
30 static struct mmc mmc_static; 30 static struct mmc mmc_static;
31 struct mmc *find_mmc_device(int dev_num) 31 struct mmc *find_mmc_device(int dev_num)
32 { 32 {
33 return &mmc_static; 33 return &mmc_static;
34 } 34 }
35 35
36 void mmc_do_preinit(void) 36 void mmc_do_preinit(void)
37 { 37 {
38 struct mmc *m = &mmc_static; 38 struct mmc *m = &mmc_static;
39 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 39 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
40 mmc_set_preinit(m, 1); 40 mmc_set_preinit(m, 1);
41 #endif 41 #endif
42 if (m->preinit) 42 if (m->preinit)
43 mmc_start_init(m); 43 mmc_start_init(m);
44 } 44 }
45 45
46 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) 46 struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
47 { 47 {
48 return &mmc->block_dev; 48 return &mmc->block_dev;
49 } 49 }
50 #endif 50 #endif
51 51
52 #if !CONFIG_IS_ENABLED(DM_MMC) 52 #if !CONFIG_IS_ENABLED(DM_MMC)
53 53
54 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 54 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
55 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout) 55 static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
56 { 56 {
57 return -ENOSYS; 57 return -ENOSYS;
58 } 58 }
59 #endif 59 #endif
60 60
61 __weak int board_mmc_getwp(struct mmc *mmc) 61 __weak int board_mmc_getwp(struct mmc *mmc)
62 { 62 {
63 return -1; 63 return -1;
64 } 64 }
65 65
66 int mmc_getwp(struct mmc *mmc) 66 int mmc_getwp(struct mmc *mmc)
67 { 67 {
68 int wp; 68 int wp;
69 69
70 wp = board_mmc_getwp(mmc); 70 wp = board_mmc_getwp(mmc);
71 71
72 if (wp < 0) { 72 if (wp < 0) {
73 if (mmc->cfg->ops->getwp) 73 if (mmc->cfg->ops->getwp)
74 wp = mmc->cfg->ops->getwp(mmc); 74 wp = mmc->cfg->ops->getwp(mmc);
75 else 75 else
76 wp = 0; 76 wp = 0;
77 } 77 }
78 78
79 return wp; 79 return wp;
80 } 80 }
81 81
82 __weak int board_mmc_getcd(struct mmc *mmc) 82 __weak int board_mmc_getcd(struct mmc *mmc)
83 { 83 {
84 return -1; 84 return -1;
85 } 85 }
86 #endif 86 #endif
87 87
88 #ifdef CONFIG_MMC_TRACE 88 #ifdef CONFIG_MMC_TRACE
89 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd) 89 void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
90 { 90 {
91 printf("CMD_SEND:%d\n", cmd->cmdidx); 91 printf("CMD_SEND:%d\n", cmd->cmdidx);
92 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); 92 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
93 } 93 }
94 94
95 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret) 95 void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
96 { 96 {
97 int i; 97 int i;
98 u8 *ptr; 98 u8 *ptr;
99 99
100 if (ret) { 100 if (ret) {
101 printf("\t\tRET\t\t\t %d\n", ret); 101 printf("\t\tRET\t\t\t %d\n", ret);
102 } else { 102 } else {
103 switch (cmd->resp_type) { 103 switch (cmd->resp_type) {
104 case MMC_RSP_NONE: 104 case MMC_RSP_NONE:
105 printf("\t\tMMC_RSP_NONE\n"); 105 printf("\t\tMMC_RSP_NONE\n");
106 break; 106 break;
107 case MMC_RSP_R1: 107 case MMC_RSP_R1:
108 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", 108 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
109 cmd->response[0]); 109 cmd->response[0]);
110 break; 110 break;
111 case MMC_RSP_R1b: 111 case MMC_RSP_R1b:
112 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", 112 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
113 cmd->response[0]); 113 cmd->response[0]);
114 break; 114 break;
115 case MMC_RSP_R2: 115 case MMC_RSP_R2:
116 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", 116 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
117 cmd->response[0]); 117 cmd->response[0]);
118 printf("\t\t \t\t 0x%08X \n", 118 printf("\t\t \t\t 0x%08X \n",
119 cmd->response[1]); 119 cmd->response[1]);
120 printf("\t\t \t\t 0x%08X \n", 120 printf("\t\t \t\t 0x%08X \n",
121 cmd->response[2]); 121 cmd->response[2]);
122 printf("\t\t \t\t 0x%08X \n", 122 printf("\t\t \t\t 0x%08X \n",
123 cmd->response[3]); 123 cmd->response[3]);
124 printf("\n"); 124 printf("\n");
125 printf("\t\t\t\t\tDUMPING DATA\n"); 125 printf("\t\t\t\t\tDUMPING DATA\n");
126 for (i = 0; i < 4; i++) { 126 for (i = 0; i < 4; i++) {
127 int j; 127 int j;
128 printf("\t\t\t\t\t%03d - ", i*4); 128 printf("\t\t\t\t\t%03d - ", i*4);
129 ptr = (u8 *)&cmd->response[i]; 129 ptr = (u8 *)&cmd->response[i];
130 ptr += 3; 130 ptr += 3;
131 for (j = 0; j < 4; j++) 131 for (j = 0; j < 4; j++)
132 printf("%02X ", *ptr--); 132 printf("%02X ", *ptr--);
133 printf("\n"); 133 printf("\n");
134 } 134 }
135 break; 135 break;
136 case MMC_RSP_R3: 136 case MMC_RSP_R3:
137 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", 137 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
138 cmd->response[0]); 138 cmd->response[0]);
139 break; 139 break;
140 default: 140 default:
141 printf("\t\tERROR MMC rsp not supported\n"); 141 printf("\t\tERROR MMC rsp not supported\n");
142 break; 142 break;
143 } 143 }
144 } 144 }
145 } 145 }
146 146
147 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd) 147 void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
148 { 148 {
149 int status; 149 int status;
150 150
151 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9; 151 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
152 printf("CURR STATE:%d\n", status); 152 printf("CURR STATE:%d\n", status);
153 } 153 }
154 #endif 154 #endif
155 155
156 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) 156 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
157 const char *mmc_mode_name(enum bus_mode mode) 157 const char *mmc_mode_name(enum bus_mode mode)
158 { 158 {
159 static const char *const names[] = { 159 static const char *const names[] = {
160 [MMC_LEGACY] = "MMC legacy", 160 [MMC_LEGACY] = "MMC legacy",
161 [SD_LEGACY] = "SD Legacy", 161 [SD_LEGACY] = "SD Legacy",
162 [MMC_HS] = "MMC High Speed (26MHz)", 162 [MMC_HS] = "MMC High Speed (26MHz)",
163 [SD_HS] = "SD High Speed (50MHz)", 163 [SD_HS] = "SD High Speed (50MHz)",
164 [UHS_SDR12] = "UHS SDR12 (25MHz)", 164 [UHS_SDR12] = "UHS SDR12 (25MHz)",
165 [UHS_SDR25] = "UHS SDR25 (50MHz)", 165 [UHS_SDR25] = "UHS SDR25 (50MHz)",
166 [UHS_SDR50] = "UHS SDR50 (100MHz)", 166 [UHS_SDR50] = "UHS SDR50 (100MHz)",
167 [UHS_SDR104] = "UHS SDR104 (208MHz)", 167 [UHS_SDR104] = "UHS SDR104 (208MHz)",
168 [UHS_DDR50] = "UHS DDR50 (50MHz)", 168 [UHS_DDR50] = "UHS DDR50 (50MHz)",
169 [MMC_HS_52] = "MMC High Speed (52MHz)", 169 [MMC_HS_52] = "MMC High Speed (52MHz)",
170 [MMC_DDR_52] = "MMC DDR52 (52MHz)", 170 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
171 [MMC_HS_200] = "HS200 (200MHz)", 171 [MMC_HS_200] = "HS200 (200MHz)",
172 [MMC_HS_400] = "HS400 (200MHz)", 172 [MMC_HS_400] = "HS400 (200MHz)",
173 [MMC_HS_400_ES] = "HS400ES (200MHz)", 173 [MMC_HS_400_ES] = "HS400ES (200MHz)",
174 }; 174 };
175 175
176 if (mode >= MMC_MODES_END) 176 if (mode >= MMC_MODES_END)
177 return "Unknown mode"; 177 return "Unknown mode";
178 else 178 else
179 return names[mode]; 179 return names[mode];
180 } 180 }
181 #endif 181 #endif
182 182
183 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode) 183 static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
184 { 184 {
185 static const int freqs[] = { 185 static const int freqs[] = {
186 [MMC_LEGACY] = 25000000, 186 [MMC_LEGACY] = 25000000,
187 [SD_LEGACY] = 25000000, 187 [SD_LEGACY] = 25000000,
188 [MMC_HS] = 26000000, 188 [MMC_HS] = 26000000,
189 [SD_HS] = 50000000, 189 [SD_HS] = 50000000,
190 [MMC_HS_52] = 52000000, 190 [MMC_HS_52] = 52000000,
191 [MMC_DDR_52] = 52000000, 191 [MMC_DDR_52] = 52000000,
192 [UHS_SDR12] = 25000000, 192 [UHS_SDR12] = 25000000,
193 [UHS_SDR25] = 50000000, 193 [UHS_SDR25] = 50000000,
194 [UHS_SDR50] = 100000000, 194 [UHS_SDR50] = 100000000,
195 [UHS_DDR50] = 50000000, 195 [UHS_DDR50] = 50000000,
196 [UHS_SDR104] = 208000000, 196 [UHS_SDR104] = 208000000,
197 [MMC_HS_200] = 200000000, 197 [MMC_HS_200] = 200000000,
198 [MMC_HS_400] = 200000000, 198 [MMC_HS_400] = 200000000,
199 [MMC_HS_400_ES] = 200000000, 199 [MMC_HS_400_ES] = 200000000,
200 }; 200 };
201 201
202 if (mode == MMC_LEGACY) 202 if (mode == MMC_LEGACY)
203 return mmc->legacy_speed; 203 return mmc->legacy_speed;
204 else if (mode >= MMC_MODES_END) 204 else if (mode >= MMC_MODES_END)
205 return 0; 205 return 0;
206 else 206 else
207 return freqs[mode]; 207 return freqs[mode];
208 } 208 }
209 209
210 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode) 210 static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
211 { 211 {
212 mmc->selected_mode = mode; 212 mmc->selected_mode = mode;
213 mmc->tran_speed = mmc_mode2freq(mmc, mode); 213 mmc->tran_speed = mmc_mode2freq(mmc, mode);
214 mmc->ddr_mode = mmc_is_mode_ddr(mode); 214 mmc->ddr_mode = mmc_is_mode_ddr(mode);
215 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode), 215 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
216 mmc->tran_speed / 1000000); 216 mmc->tran_speed / 1000000);
217 return 0; 217 return 0;
218 } 218 }
219 219
220 #if !CONFIG_IS_ENABLED(DM_MMC) 220 #if !CONFIG_IS_ENABLED(DM_MMC)
221 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) 221 int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
222 { 222 {
223 int ret; 223 int ret;
224 224
225 mmmc_trace_before_send(mmc, cmd); 225 mmmc_trace_before_send(mmc, cmd);
226 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); 226 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
227 mmmc_trace_after_send(mmc, cmd, ret); 227 mmmc_trace_after_send(mmc, cmd, ret);
228 228
229 return ret; 229 return ret;
230 } 230 }
231 #endif 231 #endif
232 232
233 int mmc_send_status(struct mmc *mmc, int timeout) 233 int mmc_send_status(struct mmc *mmc, int timeout)
234 { 234 {
235 struct mmc_cmd cmd; 235 struct mmc_cmd cmd;
236 int err, retries = 5; 236 int err, retries = 5;
237 237
238 cmd.cmdidx = MMC_CMD_SEND_STATUS; 238 cmd.cmdidx = MMC_CMD_SEND_STATUS;
239 cmd.resp_type = MMC_RSP_R1; 239 cmd.resp_type = MMC_RSP_R1;
240 if (!mmc_host_is_spi(mmc)) 240 if (!mmc_host_is_spi(mmc))
241 cmd.cmdarg = mmc->rca << 16; 241 cmd.cmdarg = mmc->rca << 16;
242 242
243 while (1) { 243 while (1) {
244 err = mmc_send_cmd(mmc, &cmd, NULL); 244 err = mmc_send_cmd(mmc, &cmd, NULL);
245 if (!err) { 245 if (!err) {
246 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && 246 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
247 (cmd.response[0] & MMC_STATUS_CURR_STATE) != 247 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
248 MMC_STATE_PRG) 248 MMC_STATE_PRG)
249 break; 249 break;
250 250
251 if (cmd.response[0] & MMC_STATUS_MASK) { 251 if (cmd.response[0] & MMC_STATUS_MASK) {
252 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 252 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
253 pr_err("Status Error: 0x%08X\n", 253 pr_err("Status Error: 0x%08X\n",
254 cmd.response[0]); 254 cmd.response[0]);
255 #endif 255 #endif
256 return -ECOMM; 256 return -ECOMM;
257 } 257 }
258 } else if (--retries < 0) 258 } else if (--retries < 0)
259 return err; 259 return err;
260 260
261 if (timeout-- <= 0) 261 if (timeout-- <= 0)
262 break; 262 break;
263 263
264 udelay(1000); 264 udelay(1000);
265 } 265 }
266 266
267 mmc_trace_state(mmc, &cmd); 267 mmc_trace_state(mmc, &cmd);
268 if (timeout <= 0) { 268 if (timeout <= 0) {
269 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 269 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
270 pr_err("Timeout waiting card ready\n"); 270 pr_err("Timeout waiting card ready\n");
271 #endif 271 #endif
272 return -ETIMEDOUT; 272 return -ETIMEDOUT;
273 } 273 }
274 274
275 return 0; 275 return 0;
276 } 276 }
277 277
278 int mmc_set_blocklen(struct mmc *mmc, int len) 278 int mmc_set_blocklen(struct mmc *mmc, int len)
279 { 279 {
280 struct mmc_cmd cmd; 280 struct mmc_cmd cmd;
281 int err; 281 int err;
282 282
283 if (mmc->ddr_mode) 283 if (mmc->ddr_mode)
284 return 0; 284 return 0;
285 285
286 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; 286 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
287 cmd.resp_type = MMC_RSP_R1; 287 cmd.resp_type = MMC_RSP_R1;
288 cmd.cmdarg = len; 288 cmd.cmdarg = len;
289 289
290 err = mmc_send_cmd(mmc, &cmd, NULL); 290 err = mmc_send_cmd(mmc, &cmd, NULL);
291 291
292 #ifdef CONFIG_MMC_QUIRKS 292 #ifdef CONFIG_MMC_QUIRKS
293 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) { 293 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
294 int retries = 4; 294 int retries = 4;
295 /* 295 /*
296 * It has been seen that SET_BLOCKLEN may fail on the first 296 * It has been seen that SET_BLOCKLEN may fail on the first
297 * attempt, let's try a few more time 297 * attempt, let's try a few more time
298 */ 298 */
299 do { 299 do {
300 err = mmc_send_cmd(mmc, &cmd, NULL); 300 err = mmc_send_cmd(mmc, &cmd, NULL);
301 if (!err) 301 if (!err)
302 break; 302 break;
303 } while (retries--); 303 } while (retries--);
304 } 304 }
305 #endif 305 #endif
306 306
307 return err; 307 return err;
308 } 308 }
309 309
310 #ifdef MMC_SUPPORTS_TUNING 310 #ifdef MMC_SUPPORTS_TUNING
311 static const u8 tuning_blk_pattern_4bit[] = { 311 static const u8 tuning_blk_pattern_4bit[] = {
312 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc, 312 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
313 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef, 313 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
314 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb, 314 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
315 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef, 315 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
316 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c, 316 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
317 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee, 317 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
318 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff, 318 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
319 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde, 319 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
320 }; 320 };
321 321
322 static const u8 tuning_blk_pattern_8bit[] = { 322 static const u8 tuning_blk_pattern_8bit[] = {
323 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00, 323 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
324 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc, 324 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
325 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff, 325 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
326 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff, 326 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
327 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd, 327 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
328 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb, 328 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
329 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff, 329 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
330 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff, 330 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
331 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 331 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
332 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 332 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
333 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 333 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
334 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 334 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
335 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 335 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
336 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 336 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
337 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 337 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
338 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 338 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
339 }; 339 };
340 340
341 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error) 341 int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
342 { 342 {
343 struct mmc_cmd cmd; 343 struct mmc_cmd cmd;
344 struct mmc_data data; 344 struct mmc_data data;
345 const u8 *tuning_block_pattern; 345 const u8 *tuning_block_pattern;
346 int size, err; 346 int size, err;
347 347
348 if (mmc->bus_width == 8) { 348 if (mmc->bus_width == 8) {
349 tuning_block_pattern = tuning_blk_pattern_8bit; 349 tuning_block_pattern = tuning_blk_pattern_8bit;
350 size = sizeof(tuning_blk_pattern_8bit); 350 size = sizeof(tuning_blk_pattern_8bit);
351 } else if (mmc->bus_width == 4) { 351 } else if (mmc->bus_width == 4) {
352 tuning_block_pattern = tuning_blk_pattern_4bit; 352 tuning_block_pattern = tuning_blk_pattern_4bit;
353 size = sizeof(tuning_blk_pattern_4bit); 353 size = sizeof(tuning_blk_pattern_4bit);
354 } else { 354 } else {
355 return -EINVAL; 355 return -EINVAL;
356 } 356 }
357 357
358 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size); 358 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
359 359
360 cmd.cmdidx = opcode; 360 cmd.cmdidx = opcode;
361 cmd.cmdarg = 0; 361 cmd.cmdarg = 0;
362 cmd.resp_type = MMC_RSP_R1; 362 cmd.resp_type = MMC_RSP_R1;
363 363
364 data.dest = (void *)data_buf; 364 data.dest = (void *)data_buf;
365 data.blocks = 1; 365 data.blocks = 1;
366 data.blocksize = size; 366 data.blocksize = size;
367 data.flags = MMC_DATA_READ; 367 data.flags = MMC_DATA_READ;
368 368
369 err = mmc_send_cmd(mmc, &cmd, &data); 369 err = mmc_send_cmd(mmc, &cmd, &data);
370 if (err) 370 if (err)
371 return err; 371 return err;
372 372
373 if (memcmp(data_buf, tuning_block_pattern, size)) 373 if (memcmp(data_buf, tuning_block_pattern, size))
374 return -EIO; 374 return -EIO;
375 375
376 return 0; 376 return 0;
377 } 377 }
378 #endif 378 #endif
379 379
380 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, 380 static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
381 lbaint_t blkcnt) 381 lbaint_t blkcnt)
382 { 382 {
383 struct mmc_cmd cmd; 383 struct mmc_cmd cmd;
384 struct mmc_data data; 384 struct mmc_data data;
385 385
386 if (blkcnt > 1) 386 if (blkcnt > 1)
387 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; 387 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
388 else 388 else
389 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; 389 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
390 390
391 if (mmc->high_capacity) 391 if (mmc->high_capacity)
392 cmd.cmdarg = start; 392 cmd.cmdarg = start;
393 else 393 else
394 cmd.cmdarg = start * mmc->read_bl_len; 394 cmd.cmdarg = start * mmc->read_bl_len;
395 395
396 cmd.resp_type = MMC_RSP_R1; 396 cmd.resp_type = MMC_RSP_R1;
397 397
398 data.dest = dst; 398 data.dest = dst;
399 data.blocks = blkcnt; 399 data.blocks = blkcnt;
400 data.blocksize = mmc->read_bl_len; 400 data.blocksize = mmc->read_bl_len;
401 data.flags = MMC_DATA_READ; 401 data.flags = MMC_DATA_READ;
402 402
403 if (mmc_send_cmd(mmc, &cmd, &data)) 403 if (mmc_send_cmd(mmc, &cmd, &data))
404 return 0; 404 return 0;
405 405
406 if (blkcnt > 1) { 406 if (blkcnt > 1) {
407 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; 407 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
408 cmd.cmdarg = 0; 408 cmd.cmdarg = 0;
409 cmd.resp_type = MMC_RSP_R1b; 409 cmd.resp_type = MMC_RSP_R1b;
410 if (mmc_send_cmd(mmc, &cmd, NULL)) { 410 if (mmc_send_cmd(mmc, &cmd, NULL)) {
411 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 411 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
412 pr_err("mmc fail to send stop cmd\n"); 412 pr_err("mmc fail to send stop cmd\n");
413 #endif 413 #endif
414 return 0; 414 return 0;
415 } 415 }
416 } 416 }
417 417
418 return blkcnt; 418 return blkcnt;
419 } 419 }
420 420
421 #if CONFIG_IS_ENABLED(BLK) 421 #if CONFIG_IS_ENABLED(BLK)
422 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst) 422 ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
423 #else 423 #else
424 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, 424 ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
425 void *dst) 425 void *dst)
426 #endif 426 #endif
427 { 427 {
428 #if CONFIG_IS_ENABLED(BLK) 428 #if CONFIG_IS_ENABLED(BLK)
429 struct blk_desc *block_dev = dev_get_uclass_platdata(dev); 429 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
430 #endif 430 #endif
431 int dev_num = block_dev->devnum; 431 int dev_num = block_dev->devnum;
432 int err; 432 int err;
433 lbaint_t cur, blocks_todo = blkcnt; 433 lbaint_t cur, blocks_todo = blkcnt;
434 434
435 if (blkcnt == 0) 435 if (blkcnt == 0)
436 return 0; 436 return 0;
437 437
438 struct mmc *mmc = find_mmc_device(dev_num); 438 struct mmc *mmc = find_mmc_device(dev_num);
439 if (!mmc) 439 if (!mmc)
440 return 0; 440 return 0;
441 441
442 if (CONFIG_IS_ENABLED(MMC_TINY)) 442 if (CONFIG_IS_ENABLED(MMC_TINY))
443 err = mmc_switch_part(mmc, block_dev->hwpart); 443 err = mmc_switch_part(mmc, block_dev->hwpart);
444 else 444 else
445 err = blk_dselect_hwpart(block_dev, block_dev->hwpart); 445 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
446 446
447 if (err < 0) 447 if (err < 0)
448 return 0; 448 return 0;
449 449
450 if ((start + blkcnt) > block_dev->lba) { 450 if ((start + blkcnt) > block_dev->lba) {
451 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 451 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
452 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", 452 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
453 start + blkcnt, block_dev->lba); 453 start + blkcnt, block_dev->lba);
454 #endif 454 #endif
455 return 0; 455 return 0;
456 } 456 }
457 457
458 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { 458 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
459 pr_debug("%s: Failed to set blocklen\n", __func__); 459 pr_debug("%s: Failed to set blocklen\n", __func__);
460 return 0; 460 return 0;
461 } 461 }
462 462
463 do { 463 do {
464 cur = (blocks_todo > mmc->cfg->b_max) ? 464 cur = (blocks_todo > mmc->cfg->b_max) ?
465 mmc->cfg->b_max : blocks_todo; 465 mmc->cfg->b_max : blocks_todo;
466 if (mmc_read_blocks(mmc, dst, start, cur) != cur) { 466 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
467 pr_debug("%s: Failed to read blocks\n", __func__); 467 pr_debug("%s: Failed to read blocks\n", __func__);
468 return 0; 468 return 0;
469 } 469 }
470 blocks_todo -= cur; 470 blocks_todo -= cur;
471 start += cur; 471 start += cur;
472 dst += cur * mmc->read_bl_len; 472 dst += cur * mmc->read_bl_len;
473 } while (blocks_todo > 0); 473 } while (blocks_todo > 0);
474 474
475 return blkcnt; 475 return blkcnt;
476 } 476 }
477 477
478 static int mmc_go_idle(struct mmc *mmc) 478 static int mmc_go_idle(struct mmc *mmc)
479 { 479 {
480 struct mmc_cmd cmd; 480 struct mmc_cmd cmd;
481 int err; 481 int err;
482 482
483 udelay(1000); 483 udelay(1000);
484 484
485 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; 485 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
486 cmd.cmdarg = 0; 486 cmd.cmdarg = 0;
487 cmd.resp_type = MMC_RSP_NONE; 487 cmd.resp_type = MMC_RSP_NONE;
488 488
489 err = mmc_send_cmd(mmc, &cmd, NULL); 489 err = mmc_send_cmd(mmc, &cmd, NULL);
490 490
491 if (err) 491 if (err)
492 return err; 492 return err;
493 493
494 udelay(2000); 494 udelay(2000);
495 495
496 return 0; 496 return 0;
497 } 497 }
498 498
499 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 499 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
500 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage) 500 static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
501 { 501 {
502 struct mmc_cmd cmd; 502 struct mmc_cmd cmd;
503 int err = 0; 503 int err = 0;
504 504
505 /* 505 /*
506 * Send CMD11 only if the request is to switch the card to 506 * Send CMD11 only if the request is to switch the card to
507 * 1.8V signalling. 507 * 1.8V signalling.
508 */ 508 */
509 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330) 509 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
510 return mmc_set_signal_voltage(mmc, signal_voltage); 510 return mmc_set_signal_voltage(mmc, signal_voltage);
511 511
512 cmd.cmdidx = SD_CMD_SWITCH_UHS18V; 512 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
513 cmd.cmdarg = 0; 513 cmd.cmdarg = 0;
514 cmd.resp_type = MMC_RSP_R1; 514 cmd.resp_type = MMC_RSP_R1;
515 515
516 err = mmc_send_cmd(mmc, &cmd, NULL); 516 err = mmc_send_cmd(mmc, &cmd, NULL);
517 if (err) 517 if (err)
518 return err; 518 return err;
519 519
520 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR)) 520 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
521 return -EIO; 521 return -EIO;
522 522
523 /* 523 /*
524 * The card should drive cmd and dat[0:3] low immediately 524 * The card should drive cmd and dat[0:3] low immediately
525 * after the response of cmd11, but wait 100 us to be sure 525 * after the response of cmd11, but wait 100 us to be sure
526 */ 526 */
527 err = mmc_wait_dat0(mmc, 0, 100); 527 err = mmc_wait_dat0(mmc, 0, 100);
528 if (err == -ENOSYS) 528 if (err == -ENOSYS)
529 udelay(100); 529 udelay(100);
530 else if (err) 530 else if (err)
531 return -ETIMEDOUT; 531 return -ETIMEDOUT;
532 532
533 /* 533 /*
534 * During a signal voltage level switch, the clock must be gated 534 * During a signal voltage level switch, the clock must be gated
535 * for 5 ms according to the SD spec 535 * for 5 ms according to the SD spec
536 */ 536 */
537 mmc_set_clock(mmc, mmc->clock, true); 537 mmc_set_clock(mmc, mmc->clock, true);
538 538
539 err = mmc_set_signal_voltage(mmc, signal_voltage); 539 err = mmc_set_signal_voltage(mmc, signal_voltage);
540 if (err) 540 if (err)
541 return err; 541 return err;
542 542
543 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */ 543 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
544 mdelay(10); 544 mdelay(10);
545 mmc_set_clock(mmc, mmc->clock, false); 545 mmc_set_clock(mmc, mmc->clock, false);
546 546
547 /* 547 /*
548 * Failure to switch is indicated by the card holding 548 * Failure to switch is indicated by the card holding
549 * dat[0:3] low. Wait for at least 1 ms according to spec 549 * dat[0:3] low. Wait for at least 1 ms according to spec
550 */ 550 */
551 err = mmc_wait_dat0(mmc, 1, 1000); 551 err = mmc_wait_dat0(mmc, 1, 1000);
552 if (err == -ENOSYS) 552 if (err == -ENOSYS)
553 udelay(1000); 553 udelay(1000);
554 else if (err) 554 else if (err)
555 return -ETIMEDOUT; 555 return -ETIMEDOUT;
556 556
557 return 0; 557 return 0;
558 } 558 }
559 #endif 559 #endif
560 560
561 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en) 561 static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
562 { 562 {
563 int timeout = 1000; 563 int timeout = 1000;
564 int err; 564 int err;
565 struct mmc_cmd cmd; 565 struct mmc_cmd cmd;
566 566
567 while (1) { 567 while (1) {
568 cmd.cmdidx = MMC_CMD_APP_CMD; 568 cmd.cmdidx = MMC_CMD_APP_CMD;
569 cmd.resp_type = MMC_RSP_R1; 569 cmd.resp_type = MMC_RSP_R1;
570 cmd.cmdarg = 0; 570 cmd.cmdarg = 0;
571 571
572 err = mmc_send_cmd(mmc, &cmd, NULL); 572 err = mmc_send_cmd(mmc, &cmd, NULL);
573 573
574 if (err) 574 if (err)
575 return err; 575 return err;
576 576
577 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; 577 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
578 cmd.resp_type = MMC_RSP_R3; 578 cmd.resp_type = MMC_RSP_R3;
579 579
580 /* 580 /*
581 * Most cards do not answer if some reserved bits 581 * Most cards do not answer if some reserved bits
582 * in the ocr are set. However, Some controller 582 * in the ocr are set. However, Some controller
583 * can set bit 7 (reserved for low voltages), but 583 * can set bit 7 (reserved for low voltages), but
584 * how to manage low voltages SD card is not yet 584 * how to manage low voltages SD card is not yet
585 * specified. 585 * specified.
586 */ 586 */
587 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : 587 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
588 (mmc->cfg->voltages & 0xff8000); 588 (mmc->cfg->voltages & 0xff8000);
589 589
590 if (mmc->version == SD_VERSION_2) 590 if (mmc->version == SD_VERSION_2)
591 cmd.cmdarg |= OCR_HCS; 591 cmd.cmdarg |= OCR_HCS;
592 592
593 if (uhs_en) 593 if (uhs_en)
594 cmd.cmdarg |= OCR_S18R; 594 cmd.cmdarg |= OCR_S18R;
595 595
596 err = mmc_send_cmd(mmc, &cmd, NULL); 596 err = mmc_send_cmd(mmc, &cmd, NULL);
597 597
598 if (err) 598 if (err)
599 return err; 599 return err;
600 600
601 if (cmd.response[0] & OCR_BUSY) 601 if (cmd.response[0] & OCR_BUSY)
602 break; 602 break;
603 603
604 if (timeout-- <= 0) 604 if (timeout-- <= 0)
605 return -EOPNOTSUPP; 605 return -EOPNOTSUPP;
606 606
607 udelay(1000); 607 udelay(1000);
608 } 608 }
609 609
610 if (mmc->version != SD_VERSION_2) 610 if (mmc->version != SD_VERSION_2)
611 mmc->version = SD_VERSION_1_0; 611 mmc->version = SD_VERSION_1_0;
612 612
613 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 613 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
614 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 614 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
615 cmd.resp_type = MMC_RSP_R3; 615 cmd.resp_type = MMC_RSP_R3;
616 cmd.cmdarg = 0; 616 cmd.cmdarg = 0;
617 617
618 err = mmc_send_cmd(mmc, &cmd, NULL); 618 err = mmc_send_cmd(mmc, &cmd, NULL);
619 619
620 if (err) 620 if (err)
621 return err; 621 return err;
622 } 622 }
623 623
624 mmc->ocr = cmd.response[0]; 624 mmc->ocr = cmd.response[0];
625 625
626 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 626 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
627 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000) 627 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
628 == 0x41000000) { 628 == 0x41000000) {
629 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180); 629 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
630 if (err) 630 if (err)
631 return err; 631 return err;
632 } 632 }
633 #endif 633 #endif
634 634
635 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 635 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
636 mmc->rca = 0; 636 mmc->rca = 0;
637 637
638 return 0; 638 return 0;
639 } 639 }
640 640
641 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) 641 static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
642 { 642 {
643 struct mmc_cmd cmd; 643 struct mmc_cmd cmd;
644 int err; 644 int err;
645 645
646 cmd.cmdidx = MMC_CMD_SEND_OP_COND; 646 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
647 cmd.resp_type = MMC_RSP_R3; 647 cmd.resp_type = MMC_RSP_R3;
648 cmd.cmdarg = 0; 648 cmd.cmdarg = 0;
649 if (use_arg && !mmc_host_is_spi(mmc)) 649 if (use_arg && !mmc_host_is_spi(mmc))
650 cmd.cmdarg = OCR_HCS | 650 cmd.cmdarg = OCR_HCS |
651 (mmc->cfg->voltages & 651 (mmc->cfg->voltages &
652 (mmc->ocr & OCR_VOLTAGE_MASK)) | 652 (mmc->ocr & OCR_VOLTAGE_MASK)) |
653 (mmc->ocr & OCR_ACCESS_MODE); 653 (mmc->ocr & OCR_ACCESS_MODE);
654 654
655 err = mmc_send_cmd(mmc, &cmd, NULL); 655 err = mmc_send_cmd(mmc, &cmd, NULL);
656 if (err) 656 if (err)
657 return err; 657 return err;
658 mmc->ocr = cmd.response[0]; 658 mmc->ocr = cmd.response[0];
659 return 0; 659 return 0;
660 } 660 }
661 661
662 static int mmc_send_op_cond(struct mmc *mmc) 662 static int mmc_send_op_cond(struct mmc *mmc)
663 { 663 {
664 int err, i; 664 int err, i;
665 665
666 /* Some cards seem to need this */ 666 /* Some cards seem to need this */
667 mmc_go_idle(mmc); 667 mmc_go_idle(mmc);
668 668
669 /* Asking to the card its capabilities */ 669 /* Asking to the card its capabilities */
670 for (i = 0; i < 2; i++) { 670 for (i = 0; i < 2; i++) {
671 err = mmc_send_op_cond_iter(mmc, i != 0); 671 err = mmc_send_op_cond_iter(mmc, i != 0);
672 if (err) 672 if (err)
673 return err; 673 return err;
674 674
675 /* exit if not busy (flag seems to be inverted) */ 675 /* exit if not busy (flag seems to be inverted) */
676 if (mmc->ocr & OCR_BUSY) 676 if (mmc->ocr & OCR_BUSY)
677 break; 677 break;
678 } 678 }
679 mmc->op_cond_pending = 1; 679 mmc->op_cond_pending = 1;
680 return 0; 680 return 0;
681 } 681 }
682 682
683 static int mmc_complete_op_cond(struct mmc *mmc) 683 static int mmc_complete_op_cond(struct mmc *mmc)
684 { 684 {
685 struct mmc_cmd cmd; 685 struct mmc_cmd cmd;
686 int timeout = 1000; 686 int timeout = 1000;
687 uint start; 687 uint start;
688 int err; 688 int err;
689 689
690 mmc->op_cond_pending = 0; 690 mmc->op_cond_pending = 0;
691 if (!(mmc->ocr & OCR_BUSY)) { 691 if (!(mmc->ocr & OCR_BUSY)) {
692 /* Some cards seem to need this */ 692 /* Some cards seem to need this */
693 mmc_go_idle(mmc); 693 mmc_go_idle(mmc);
694 694
695 start = get_timer(0); 695 start = get_timer(0);
696 while (1) { 696 while (1) {
697 err = mmc_send_op_cond_iter(mmc, 1); 697 err = mmc_send_op_cond_iter(mmc, 1);
698 if (err) 698 if (err)
699 return err; 699 return err;
700 if (mmc->ocr & OCR_BUSY) 700 if (mmc->ocr & OCR_BUSY)
701 break; 701 break;
702 if (get_timer(start) > timeout) 702 if (get_timer(start) > timeout)
703 return -EOPNOTSUPP; 703 return -EOPNOTSUPP;
704 udelay(100); 704 udelay(100);
705 } 705 }
706 } 706 }
707 707
708 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ 708 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
709 cmd.cmdidx = MMC_CMD_SPI_READ_OCR; 709 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
710 cmd.resp_type = MMC_RSP_R3; 710 cmd.resp_type = MMC_RSP_R3;
711 cmd.cmdarg = 0; 711 cmd.cmdarg = 0;
712 712
713 err = mmc_send_cmd(mmc, &cmd, NULL); 713 err = mmc_send_cmd(mmc, &cmd, NULL);
714 714
715 if (err) 715 if (err)
716 return err; 716 return err;
717 717
718 mmc->ocr = cmd.response[0]; 718 mmc->ocr = cmd.response[0];
719 } 719 }
720 720
721 mmc->version = MMC_VERSION_UNKNOWN; 721 mmc->version = MMC_VERSION_UNKNOWN;
722 722
723 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); 723 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
724 mmc->rca = 1; 724 mmc->rca = 1;
725 725
726 return 0; 726 return 0;
727 } 727 }
728 728
729 729
730 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) 730 static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
731 { 731 {
732 struct mmc_cmd cmd; 732 struct mmc_cmd cmd;
733 struct mmc_data data; 733 struct mmc_data data;
734 int err; 734 int err;
735 735
736 /* Get the Card Status Register */ 736 /* Get the Card Status Register */
737 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; 737 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
738 cmd.resp_type = MMC_RSP_R1; 738 cmd.resp_type = MMC_RSP_R1;
739 cmd.cmdarg = 0; 739 cmd.cmdarg = 0;
740 740
741 data.dest = (char *)ext_csd; 741 data.dest = (char *)ext_csd;
742 data.blocks = 1; 742 data.blocks = 1;
743 data.blocksize = MMC_MAX_BLOCK_LEN; 743 data.blocksize = MMC_MAX_BLOCK_LEN;
744 data.flags = MMC_DATA_READ; 744 data.flags = MMC_DATA_READ;
745 745
746 err = mmc_send_cmd(mmc, &cmd, &data); 746 err = mmc_send_cmd(mmc, &cmd, &data);
747 747
748 return err; 748 return err;
749 } 749 }
750 750
751 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) 751 int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
752 { 752 {
753 struct mmc_cmd cmd; 753 struct mmc_cmd cmd;
754 int timeout = 1000; 754 int timeout = 1000;
755 int retries = 3; 755 int retries = 3;
756 int ret; 756 int ret;
757 757
758 cmd.cmdidx = MMC_CMD_SWITCH; 758 cmd.cmdidx = MMC_CMD_SWITCH;
759 cmd.resp_type = MMC_RSP_R1b; 759 cmd.resp_type = MMC_RSP_R1b;
760 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | 760 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
761 (index << 16) | 761 (index << 16) |
762 (value << 8); 762 (value << 8);
763 763
764 while (retries > 0) { 764 while (retries > 0) {
765 ret = mmc_send_cmd(mmc, &cmd, NULL); 765 ret = mmc_send_cmd(mmc, &cmd, NULL);
766 766
767 /* Waiting for the ready status */ 767 /* Waiting for the ready status */
768 if (!ret) { 768 if (!ret) {
769 ret = mmc_send_status(mmc, timeout); 769 ret = mmc_send_status(mmc, timeout);
770 return ret; 770 return ret;
771 } 771 }
772 772
773 retries--; 773 retries--;
774 } 774 }
775 775
776 return ret; 776 return ret;
777 777
778 } 778 }
779 779
780 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode) 780 static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
781 bool hsdowngrade)
781 { 782 {
782 int err; 783 int err;
783 int speed_bits; 784 int speed_bits;
784 785
785 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 786 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
786 787
787 switch (mode) { 788 switch (mode) {
788 case MMC_HS: 789 case MMC_HS:
789 case MMC_HS_52: 790 case MMC_HS_52:
790 case MMC_DDR_52: 791 case MMC_DDR_52:
791 speed_bits = EXT_CSD_TIMING_HS; 792 speed_bits = EXT_CSD_TIMING_HS;
792 break; 793 break;
793 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) 794 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
794 case MMC_HS_200: 795 case MMC_HS_200:
795 speed_bits = EXT_CSD_TIMING_HS200; 796 speed_bits = EXT_CSD_TIMING_HS200;
796 break; 797 break;
797 #endif 798 #endif
798 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) 799 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
799 case MMC_HS_400: 800 case MMC_HS_400:
800 speed_bits = EXT_CSD_TIMING_HS400; 801 speed_bits = EXT_CSD_TIMING_HS400;
801 break; 802 break;
802 #endif 803 #endif
803 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) 804 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
804 case MMC_HS_400_ES: 805 case MMC_HS_400_ES:
805 speed_bits = EXT_CSD_TIMING_HS400; 806 speed_bits = EXT_CSD_TIMING_HS400;
806 break; 807 break;
807 #endif 808 #endif
808 case MMC_LEGACY: 809 case MMC_LEGACY:
809 speed_bits = EXT_CSD_TIMING_LEGACY; 810 speed_bits = EXT_CSD_TIMING_LEGACY;
810 break; 811 break;
811 default: 812 default:
812 return -EINVAL; 813 return -EINVAL;
813 } 814 }
814 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 815 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
815 speed_bits); 816 speed_bits);
816 if (err) 817 if (err)
817 return err; 818 return err;
818 819
820 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
821 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
822 /*
823 * In case the eMMC is in HS200/HS400 mode and we are downgrading
824 * to HS mode, the card clock are still running much faster than
825 * the supported HS mode clock, so we can not reliably read out
826 * Extended CSD. Reconfigure the controller to run at HS mode.
827 */
828 if (hsdowngrade) {
829 mmc_select_mode(mmc, MMC_HS);
830 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
831 }
832 #endif
833
819 if ((mode == MMC_HS) || (mode == MMC_HS_52)) { 834 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
820 /* Now check to see that it worked */ 835 /* Now check to see that it worked */
821 err = mmc_send_ext_csd(mmc, test_csd); 836 err = mmc_send_ext_csd(mmc, test_csd);
822 if (err) 837 if (err)
823 return err; 838 return err;
824 839
825 /* No high-speed support */ 840 /* No high-speed support */
826 if (!test_csd[EXT_CSD_HS_TIMING]) 841 if (!test_csd[EXT_CSD_HS_TIMING])
827 return -ENOTSUPP; 842 return -ENOTSUPP;
828 } 843 }
829 844
830 return 0; 845 return 0;
831 } 846 }
832 847
833 static int mmc_get_capabilities(struct mmc *mmc) 848 static int mmc_get_capabilities(struct mmc *mmc)
834 { 849 {
835 u8 *ext_csd = mmc->ext_csd; 850 u8 *ext_csd = mmc->ext_csd;
836 char cardtype; 851 char cardtype;
837 852
838 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY); 853 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
839 854
840 if (mmc_host_is_spi(mmc)) 855 if (mmc_host_is_spi(mmc))
841 return 0; 856 return 0;
842 857
843 /* Only version 4 supports high-speed */ 858 /* Only version 4 supports high-speed */
844 if (mmc->version < MMC_VERSION_4) 859 if (mmc->version < MMC_VERSION_4)
845 return 0; 860 return 0;
846 861
847 if (!ext_csd) { 862 if (!ext_csd) {
848 pr_err("No ext_csd found!\n"); /* this should enver happen */ 863 pr_err("No ext_csd found!\n"); /* this should enver happen */
849 return -ENOTSUPP; 864 return -ENOTSUPP;
850 } 865 }
851 866
852 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; 867 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
853 868
854 cardtype = ext_csd[EXT_CSD_CARD_TYPE]; 869 cardtype = ext_csd[EXT_CSD_CARD_TYPE];
855 mmc->cardtype = cardtype; 870 mmc->cardtype = cardtype;
856 871
857 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) 872 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
858 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V | 873 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
859 EXT_CSD_CARD_TYPE_HS200_1_8V)) { 874 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
860 mmc->card_caps |= MMC_MODE_HS200; 875 mmc->card_caps |= MMC_MODE_HS200;
861 } 876 }
862 #endif 877 #endif
863 #if (CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)) 878 #if (CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT))
864 if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V | 879 if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
865 EXT_CSD_CARD_TYPE_HS400_1_8V)) { 880 EXT_CSD_CARD_TYPE_HS400_1_8V)) {
866 mmc->card_caps |= MMC_MODE_HS400; 881 mmc->card_caps |= MMC_MODE_HS400;
867 } 882 }
868 #endif 883 #endif
869 if (cardtype & EXT_CSD_CARD_TYPE_52) { 884 if (cardtype & EXT_CSD_CARD_TYPE_52) {
870 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52) 885 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
871 mmc->card_caps |= MMC_MODE_DDR_52MHz; 886 mmc->card_caps |= MMC_MODE_DDR_52MHz;
872 mmc->card_caps |= MMC_MODE_HS_52MHz; 887 mmc->card_caps |= MMC_MODE_HS_52MHz;
873 } 888 }
874 if (cardtype & EXT_CSD_CARD_TYPE_26) 889 if (cardtype & EXT_CSD_CARD_TYPE_26)
875 mmc->card_caps |= MMC_MODE_HS; 890 mmc->card_caps |= MMC_MODE_HS;
876 891
877 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) 892 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
878 if (ext_csd[EXT_CSD_STROBE_SUPPORT] && (mmc->card_caps & MMC_MODE_HS400)) 893 if (ext_csd[EXT_CSD_STROBE_SUPPORT] && (mmc->card_caps & MMC_MODE_HS400))
879 mmc->card_caps |= MMC_MODE_HS400_ES; 894 mmc->card_caps |= MMC_MODE_HS400_ES;
880 #endif 895 #endif
881 896
882 return 0; 897 return 0;
883 } 898 }
884 899
885 static int mmc_set_capacity(struct mmc *mmc, int part_num) 900 static int mmc_set_capacity(struct mmc *mmc, int part_num)
886 { 901 {
887 switch (part_num) { 902 switch (part_num) {
888 case 0: 903 case 0:
889 mmc->capacity = mmc->capacity_user; 904 mmc->capacity = mmc->capacity_user;
890 break; 905 break;
891 case 1: 906 case 1:
892 case 2: 907 case 2:
893 mmc->capacity = mmc->capacity_boot; 908 mmc->capacity = mmc->capacity_boot;
894 break; 909 break;
895 case 3: 910 case 3:
896 mmc->capacity = mmc->capacity_rpmb; 911 mmc->capacity = mmc->capacity_rpmb;
897 break; 912 break;
898 case 4: 913 case 4:
899 case 5: 914 case 5:
900 case 6: 915 case 6:
901 case 7: 916 case 7:
902 mmc->capacity = mmc->capacity_gp[part_num - 4]; 917 mmc->capacity = mmc->capacity_gp[part_num - 4];
903 break; 918 break;
904 default: 919 default:
905 return -1; 920 return -1;
906 } 921 }
907 922
908 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len); 923 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
909 924
910 return 0; 925 return 0;
911 } 926 }
912 927
913 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) 928 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
914 static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num) 929 static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
915 { 930 {
916 int forbidden = 0; 931 int forbidden = 0;
917 bool change = false; 932 bool change = false;
918 933
919 if (part_num & PART_ACCESS_MASK) 934 if (part_num & PART_ACCESS_MASK)
920 forbidden = MMC_CAP(MMC_HS_200); 935 forbidden = MMC_CAP(MMC_HS_200);
921 936
922 if (MMC_CAP(mmc->selected_mode) & forbidden) { 937 if (MMC_CAP(mmc->selected_mode) & forbidden) {
923 pr_debug("selected mode (%s) is forbidden for part %d\n", 938 pr_debug("selected mode (%s) is forbidden for part %d\n",
924 mmc_mode_name(mmc->selected_mode), part_num); 939 mmc_mode_name(mmc->selected_mode), part_num);
925 change = true; 940 change = true;
926 } else if (mmc->selected_mode != mmc->best_mode) { 941 } else if (mmc->selected_mode != mmc->best_mode) {
927 pr_debug("selected mode is not optimal\n"); 942 pr_debug("selected mode is not optimal\n");
928 change = true; 943 change = true;
929 } 944 }
930 945
931 if (change) 946 if (change)
932 return mmc_select_mode_and_width(mmc, 947 return mmc_select_mode_and_width(mmc,
933 mmc->card_caps & ~forbidden); 948 mmc->card_caps & ~forbidden);
934 949
935 return 0; 950 return 0;
936 } 951 }
937 #else 952 #else
938 static inline int mmc_boot_part_access_chk(struct mmc *mmc, 953 static inline int mmc_boot_part_access_chk(struct mmc *mmc,
939 unsigned int part_num) 954 unsigned int part_num)
940 { 955 {
941 return 0; 956 return 0;
942 } 957 }
943 #endif 958 #endif
944 959
945 int mmc_switch_part(struct mmc *mmc, unsigned int part_num) 960 int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
946 { 961 {
947 int ret; 962 int ret;
948 963
949 ret = mmc_boot_part_access_chk(mmc, part_num); 964 ret = mmc_boot_part_access_chk(mmc, part_num);
950 if (ret) 965 if (ret)
951 return ret; 966 return ret;
952 967
953 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, 968 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
954 (mmc->part_config & ~PART_ACCESS_MASK) 969 (mmc->part_config & ~PART_ACCESS_MASK)
955 | (part_num & PART_ACCESS_MASK)); 970 | (part_num & PART_ACCESS_MASK));
956 971
957 /* 972 /*
958 * Set the capacity if the switch succeeded or was intended 973 * Set the capacity if the switch succeeded or was intended
959 * to return to representing the raw device. 974 * to return to representing the raw device.
960 */ 975 */
961 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { 976 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
962 ret = mmc_set_capacity(mmc, part_num); 977 ret = mmc_set_capacity(mmc, part_num);
963 mmc_get_blk_desc(mmc)->hwpart = part_num; 978 mmc_get_blk_desc(mmc)->hwpart = part_num;
964 } 979 }
965 980
966 return ret; 981 return ret;
967 } 982 }
968 983
969 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) 984 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
970 int mmc_hwpart_config(struct mmc *mmc, 985 int mmc_hwpart_config(struct mmc *mmc,
971 const struct mmc_hwpart_conf *conf, 986 const struct mmc_hwpart_conf *conf,
972 enum mmc_hwpart_conf_mode mode) 987 enum mmc_hwpart_conf_mode mode)
973 { 988 {
974 u8 part_attrs = 0; 989 u8 part_attrs = 0;
975 u32 enh_size_mult; 990 u32 enh_size_mult;
976 u32 enh_start_addr; 991 u32 enh_start_addr;
977 u32 gp_size_mult[4]; 992 u32 gp_size_mult[4];
978 u32 max_enh_size_mult; 993 u32 max_enh_size_mult;
979 u32 tot_enh_size_mult = 0; 994 u32 tot_enh_size_mult = 0;
980 u8 wr_rel_set; 995 u8 wr_rel_set;
981 int i, pidx, err; 996 int i, pidx, err;
982 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 997 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
983 998
984 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) 999 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
985 return -EINVAL; 1000 return -EINVAL;
986 1001
987 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { 1002 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
988 pr_err("eMMC >= 4.4 required for enhanced user data area\n"); 1003 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
989 return -EMEDIUMTYPE; 1004 return -EMEDIUMTYPE;
990 } 1005 }
991 1006
992 if (!(mmc->part_support & PART_SUPPORT)) { 1007 if (!(mmc->part_support & PART_SUPPORT)) {
993 pr_err("Card does not support partitioning\n"); 1008 pr_err("Card does not support partitioning\n");
994 return -EMEDIUMTYPE; 1009 return -EMEDIUMTYPE;
995 } 1010 }
996 1011
997 if (!mmc->hc_wp_grp_size) { 1012 if (!mmc->hc_wp_grp_size) {
998 pr_err("Card does not define HC WP group size\n"); 1013 pr_err("Card does not define HC WP group size\n");
999 return -EMEDIUMTYPE; 1014 return -EMEDIUMTYPE;
1000 } 1015 }
1001 1016
1002 /* check partition alignment and total enhanced size */ 1017 /* check partition alignment and total enhanced size */
1003 if (conf->user.enh_size) { 1018 if (conf->user.enh_size) {
1004 if (conf->user.enh_size % mmc->hc_wp_grp_size || 1019 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1005 conf->user.enh_start % mmc->hc_wp_grp_size) { 1020 conf->user.enh_start % mmc->hc_wp_grp_size) {
1006 pr_err("User data enhanced area not HC WP group " 1021 pr_err("User data enhanced area not HC WP group "
1007 "size aligned\n"); 1022 "size aligned\n");
1008 return -EINVAL; 1023 return -EINVAL;
1009 } 1024 }
1010 part_attrs |= EXT_CSD_ENH_USR; 1025 part_attrs |= EXT_CSD_ENH_USR;
1011 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; 1026 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1012 if (mmc->high_capacity) { 1027 if (mmc->high_capacity) {
1013 enh_start_addr = conf->user.enh_start; 1028 enh_start_addr = conf->user.enh_start;
1014 } else { 1029 } else {
1015 enh_start_addr = (conf->user.enh_start << 9); 1030 enh_start_addr = (conf->user.enh_start << 9);
1016 } 1031 }
1017 } else { 1032 } else {
1018 enh_size_mult = 0; 1033 enh_size_mult = 0;
1019 enh_start_addr = 0; 1034 enh_start_addr = 0;
1020 } 1035 }
1021 tot_enh_size_mult += enh_size_mult; 1036 tot_enh_size_mult += enh_size_mult;
1022 1037
1023 for (pidx = 0; pidx < 4; pidx++) { 1038 for (pidx = 0; pidx < 4; pidx++) {
1024 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { 1039 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
1025 pr_err("GP%i partition not HC WP group size " 1040 pr_err("GP%i partition not HC WP group size "
1026 "aligned\n", pidx+1); 1041 "aligned\n", pidx+1);
1027 return -EINVAL; 1042 return -EINVAL;
1028 } 1043 }
1029 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; 1044 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1030 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { 1045 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1031 part_attrs |= EXT_CSD_ENH_GP(pidx); 1046 part_attrs |= EXT_CSD_ENH_GP(pidx);
1032 tot_enh_size_mult += gp_size_mult[pidx]; 1047 tot_enh_size_mult += gp_size_mult[pidx];
1033 } 1048 }
1034 } 1049 }
1035 1050
1036 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { 1051 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
1037 pr_err("Card does not support enhanced attribute\n"); 1052 pr_err("Card does not support enhanced attribute\n");
1038 return -EMEDIUMTYPE; 1053 return -EMEDIUMTYPE;
1039 } 1054 }
1040 1055
1041 err = mmc_send_ext_csd(mmc, ext_csd); 1056 err = mmc_send_ext_csd(mmc, ext_csd);
1042 if (err) 1057 if (err)
1043 return err; 1058 return err;
1044 1059
1045 max_enh_size_mult = 1060 max_enh_size_mult =
1046 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + 1061 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1047 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + 1062 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1048 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; 1063 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1049 if (tot_enh_size_mult > max_enh_size_mult) { 1064 if (tot_enh_size_mult > max_enh_size_mult) {
1050 pr_err("Total enhanced size exceeds maximum (%u > %u)\n", 1065 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
1051 tot_enh_size_mult, max_enh_size_mult); 1066 tot_enh_size_mult, max_enh_size_mult);
1052 return -EMEDIUMTYPE; 1067 return -EMEDIUMTYPE;
1053 } 1068 }
1054 1069
1055 /* The default value of EXT_CSD_WR_REL_SET is device 1070 /* The default value of EXT_CSD_WR_REL_SET is device
1056 * dependent, the values can only be changed if the 1071 * dependent, the values can only be changed if the
1057 * EXT_CSD_HS_CTRL_REL bit is set. The values can be 1072 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1058 * changed only once and before partitioning is completed. */ 1073 * changed only once and before partitioning is completed. */
1059 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 1074 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1060 if (conf->user.wr_rel_change) { 1075 if (conf->user.wr_rel_change) {
1061 if (conf->user.wr_rel_set) 1076 if (conf->user.wr_rel_set)
1062 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; 1077 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1063 else 1078 else
1064 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; 1079 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1065 } 1080 }
1066 for (pidx = 0; pidx < 4; pidx++) { 1081 for (pidx = 0; pidx < 4; pidx++) {
1067 if (conf->gp_part[pidx].wr_rel_change) { 1082 if (conf->gp_part[pidx].wr_rel_change) {
1068 if (conf->gp_part[pidx].wr_rel_set) 1083 if (conf->gp_part[pidx].wr_rel_set)
1069 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); 1084 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1070 else 1085 else
1071 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); 1086 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1072 } 1087 }
1073 } 1088 }
1074 1089
1075 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && 1090 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1076 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { 1091 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1077 puts("Card does not support host controlled partition write " 1092 puts("Card does not support host controlled partition write "
1078 "reliability settings\n"); 1093 "reliability settings\n");
1079 return -EMEDIUMTYPE; 1094 return -EMEDIUMTYPE;
1080 } 1095 }
1081 1096
1082 if (ext_csd[EXT_CSD_PARTITION_SETTING] & 1097 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1083 EXT_CSD_PARTITION_SETTING_COMPLETED) { 1098 EXT_CSD_PARTITION_SETTING_COMPLETED) {
1084 pr_err("Card already partitioned\n"); 1099 pr_err("Card already partitioned\n");
1085 return -EPERM; 1100 return -EPERM;
1086 } 1101 }
1087 1102
1088 if (mode == MMC_HWPART_CONF_CHECK) 1103 if (mode == MMC_HWPART_CONF_CHECK)
1089 return 0; 1104 return 0;
1090 1105
1091 /* Partitioning requires high-capacity size definitions */ 1106 /* Partitioning requires high-capacity size definitions */
1092 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { 1107 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1093 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1108 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1094 EXT_CSD_ERASE_GROUP_DEF, 1); 1109 EXT_CSD_ERASE_GROUP_DEF, 1);
1095 1110
1096 if (err) 1111 if (err)
1097 return err; 1112 return err;
1098 1113
1099 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 1114 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1100 1115
1101 /* update erase group size to be high-capacity */ 1116 /* update erase group size to be high-capacity */
1102 mmc->erase_grp_size = 1117 mmc->erase_grp_size =
1103 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 1118 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1104 1119
1105 } 1120 }
1106 1121
1107 /* all OK, write the configuration */ 1122 /* all OK, write the configuration */
1108 for (i = 0; i < 4; i++) { 1123 for (i = 0; i < 4; i++) {
1109 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1124 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1110 EXT_CSD_ENH_START_ADDR+i, 1125 EXT_CSD_ENH_START_ADDR+i,
1111 (enh_start_addr >> (i*8)) & 0xFF); 1126 (enh_start_addr >> (i*8)) & 0xFF);
1112 if (err) 1127 if (err)
1113 return err; 1128 return err;
1114 } 1129 }
1115 for (i = 0; i < 3; i++) { 1130 for (i = 0; i < 3; i++) {
1116 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1131 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1117 EXT_CSD_ENH_SIZE_MULT+i, 1132 EXT_CSD_ENH_SIZE_MULT+i,
1118 (enh_size_mult >> (i*8)) & 0xFF); 1133 (enh_size_mult >> (i*8)) & 0xFF);
1119 if (err) 1134 if (err)
1120 return err; 1135 return err;
1121 } 1136 }
1122 for (pidx = 0; pidx < 4; pidx++) { 1137 for (pidx = 0; pidx < 4; pidx++) {
1123 for (i = 0; i < 3; i++) { 1138 for (i = 0; i < 3; i++) {
1124 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1139 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1125 EXT_CSD_GP_SIZE_MULT+pidx*3+i, 1140 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1126 (gp_size_mult[pidx] >> (i*8)) & 0xFF); 1141 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1127 if (err) 1142 if (err)
1128 return err; 1143 return err;
1129 } 1144 }
1130 } 1145 }
1131 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1146 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1132 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); 1147 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1133 if (err) 1148 if (err)
1134 return err; 1149 return err;
1135 1150
1136 if (mode == MMC_HWPART_CONF_SET) 1151 if (mode == MMC_HWPART_CONF_SET)
1137 return 0; 1152 return 0;
1138 1153
1139 /* The WR_REL_SET is a write-once register but shall be 1154 /* The WR_REL_SET is a write-once register but shall be
1140 * written before setting PART_SETTING_COMPLETED. As it is 1155 * written before setting PART_SETTING_COMPLETED. As it is
1141 * write-once we can only write it when completing the 1156 * write-once we can only write it when completing the
1142 * partitioning. */ 1157 * partitioning. */
1143 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { 1158 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1144 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1159 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1145 EXT_CSD_WR_REL_SET, wr_rel_set); 1160 EXT_CSD_WR_REL_SET, wr_rel_set);
1146 if (err) 1161 if (err)
1147 return err; 1162 return err;
1148 } 1163 }
1149 1164
1150 /* Setting PART_SETTING_COMPLETED confirms the partition 1165 /* Setting PART_SETTING_COMPLETED confirms the partition
1151 * configuration but it only becomes effective after power 1166 * configuration but it only becomes effective after power
1152 * cycle, so we do not adjust the partition related settings 1167 * cycle, so we do not adjust the partition related settings
1153 * in the mmc struct. */ 1168 * in the mmc struct. */
1154 1169
1155 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1170 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1156 EXT_CSD_PARTITION_SETTING, 1171 EXT_CSD_PARTITION_SETTING,
1157 EXT_CSD_PARTITION_SETTING_COMPLETED); 1172 EXT_CSD_PARTITION_SETTING_COMPLETED);
1158 if (err) 1173 if (err)
1159 return err; 1174 return err;
1160 1175
1161 return 0; 1176 return 0;
1162 } 1177 }
1163 #endif 1178 #endif
1164 1179
1165 #if !CONFIG_IS_ENABLED(DM_MMC) 1180 #if !CONFIG_IS_ENABLED(DM_MMC)
1166 int mmc_getcd(struct mmc *mmc) 1181 int mmc_getcd(struct mmc *mmc)
1167 { 1182 {
1168 int cd; 1183 int cd;
1169 1184
1170 cd = board_mmc_getcd(mmc); 1185 cd = board_mmc_getcd(mmc);
1171 1186
1172 if (cd < 0) { 1187 if (cd < 0) {
1173 if (mmc->cfg->ops->getcd) 1188 if (mmc->cfg->ops->getcd)
1174 cd = mmc->cfg->ops->getcd(mmc); 1189 cd = mmc->cfg->ops->getcd(mmc);
1175 else 1190 else
1176 cd = 1; 1191 cd = 1;
1177 } 1192 }
1178 1193
1179 return cd; 1194 return cd;
1180 } 1195 }
1181 #endif 1196 #endif
1182 1197
1183 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) 1198 static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
1184 { 1199 {
1185 struct mmc_cmd cmd; 1200 struct mmc_cmd cmd;
1186 struct mmc_data data; 1201 struct mmc_data data;
1187 1202
1188 /* Switch the frequency */ 1203 /* Switch the frequency */
1189 cmd.cmdidx = SD_CMD_SWITCH_FUNC; 1204 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1190 cmd.resp_type = MMC_RSP_R1; 1205 cmd.resp_type = MMC_RSP_R1;
1191 cmd.cmdarg = (mode << 31) | 0xffffff; 1206 cmd.cmdarg = (mode << 31) | 0xffffff;
1192 cmd.cmdarg &= ~(0xf << (group * 4)); 1207 cmd.cmdarg &= ~(0xf << (group * 4));
1193 cmd.cmdarg |= value << (group * 4); 1208 cmd.cmdarg |= value << (group * 4);
1194 1209
1195 data.dest = (char *)resp; 1210 data.dest = (char *)resp;
1196 data.blocksize = 64; 1211 data.blocksize = 64;
1197 data.blocks = 1; 1212 data.blocks = 1;
1198 data.flags = MMC_DATA_READ; 1213 data.flags = MMC_DATA_READ;
1199 1214
1200 return mmc_send_cmd(mmc, &cmd, &data); 1215 return mmc_send_cmd(mmc, &cmd, &data);
1201 } 1216 }
1202 1217
1203 1218
1204 static int sd_get_capabilities(struct mmc *mmc) 1219 static int sd_get_capabilities(struct mmc *mmc)
1205 { 1220 {
1206 int err; 1221 int err;
1207 struct mmc_cmd cmd; 1222 struct mmc_cmd cmd;
1208 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2); 1223 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1209 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16); 1224 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
1210 struct mmc_data data; 1225 struct mmc_data data;
1211 int timeout; 1226 int timeout;
1212 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 1227 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1213 u32 sd3_bus_mode; 1228 u32 sd3_bus_mode;
1214 #endif 1229 #endif
1215 1230
1216 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY); 1231 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(SD_LEGACY);
1217 1232
1218 if (mmc_host_is_spi(mmc)) 1233 if (mmc_host_is_spi(mmc))
1219 return 0; 1234 return 0;
1220 1235
1221 /* Read the SCR to find out if this card supports higher speeds */ 1236 /* Read the SCR to find out if this card supports higher speeds */
1222 cmd.cmdidx = MMC_CMD_APP_CMD; 1237 cmd.cmdidx = MMC_CMD_APP_CMD;
1223 cmd.resp_type = MMC_RSP_R1; 1238 cmd.resp_type = MMC_RSP_R1;
1224 cmd.cmdarg = mmc->rca << 16; 1239 cmd.cmdarg = mmc->rca << 16;
1225 1240
1226 err = mmc_send_cmd(mmc, &cmd, NULL); 1241 err = mmc_send_cmd(mmc, &cmd, NULL);
1227 1242
1228 if (err) 1243 if (err)
1229 return err; 1244 return err;
1230 1245
1231 cmd.cmdidx = SD_CMD_APP_SEND_SCR; 1246 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1232 cmd.resp_type = MMC_RSP_R1; 1247 cmd.resp_type = MMC_RSP_R1;
1233 cmd.cmdarg = 0; 1248 cmd.cmdarg = 0;
1234 1249
1235 timeout = 3; 1250 timeout = 3;
1236 1251
1237 retry_scr: 1252 retry_scr:
1238 data.dest = (char *)scr; 1253 data.dest = (char *)scr;
1239 data.blocksize = 8; 1254 data.blocksize = 8;
1240 data.blocks = 1; 1255 data.blocks = 1;
1241 data.flags = MMC_DATA_READ; 1256 data.flags = MMC_DATA_READ;
1242 1257
1243 err = mmc_send_cmd(mmc, &cmd, &data); 1258 err = mmc_send_cmd(mmc, &cmd, &data);
1244 1259
1245 if (err) { 1260 if (err) {
1246 if (timeout--) 1261 if (timeout--)
1247 goto retry_scr; 1262 goto retry_scr;
1248 1263
1249 return err; 1264 return err;
1250 } 1265 }
1251 1266
1252 mmc->scr[0] = __be32_to_cpu(scr[0]); 1267 mmc->scr[0] = __be32_to_cpu(scr[0]);
1253 mmc->scr[1] = __be32_to_cpu(scr[1]); 1268 mmc->scr[1] = __be32_to_cpu(scr[1]);
1254 1269
1255 switch ((mmc->scr[0] >> 24) & 0xf) { 1270 switch ((mmc->scr[0] >> 24) & 0xf) {
1256 case 0: 1271 case 0:
1257 mmc->version = SD_VERSION_1_0; 1272 mmc->version = SD_VERSION_1_0;
1258 break; 1273 break;
1259 case 1: 1274 case 1:
1260 mmc->version = SD_VERSION_1_10; 1275 mmc->version = SD_VERSION_1_10;
1261 break; 1276 break;
1262 case 2: 1277 case 2:
1263 mmc->version = SD_VERSION_2; 1278 mmc->version = SD_VERSION_2;
1264 if ((mmc->scr[0] >> 15) & 0x1) 1279 if ((mmc->scr[0] >> 15) & 0x1)
1265 mmc->version = SD_VERSION_3; 1280 mmc->version = SD_VERSION_3;
1266 break; 1281 break;
1267 default: 1282 default:
1268 mmc->version = SD_VERSION_1_0; 1283 mmc->version = SD_VERSION_1_0;
1269 break; 1284 break;
1270 } 1285 }
1271 1286
1272 if (mmc->scr[0] & SD_DATA_4BIT) 1287 if (mmc->scr[0] & SD_DATA_4BIT)
1273 mmc->card_caps |= MMC_MODE_4BIT; 1288 mmc->card_caps |= MMC_MODE_4BIT;
1274 1289
1275 /* Version 1.0 doesn't support switching */ 1290 /* Version 1.0 doesn't support switching */
1276 if (mmc->version == SD_VERSION_1_0) 1291 if (mmc->version == SD_VERSION_1_0)
1277 return 0; 1292 return 0;
1278 1293
1279 timeout = 4; 1294 timeout = 4;
1280 while (timeout--) { 1295 while (timeout--) {
1281 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, 1296 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
1282 (u8 *)switch_status); 1297 (u8 *)switch_status);
1283 1298
1284 if (err) 1299 if (err)
1285 return err; 1300 return err;
1286 1301
1287 /* The high-speed function is busy. Try again */ 1302 /* The high-speed function is busy. Try again */
1288 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) 1303 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
1289 break; 1304 break;
1290 } 1305 }
1291 1306
1292 /* If high-speed isn't supported, we return */ 1307 /* If high-speed isn't supported, we return */
1293 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED) 1308 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1294 mmc->card_caps |= MMC_CAP(SD_HS); 1309 mmc->card_caps |= MMC_CAP(SD_HS);
1295 1310
1296 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 1311 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1297 /* Version before 3.0 don't support UHS modes */ 1312 /* Version before 3.0 don't support UHS modes */
1298 if (mmc->version < SD_VERSION_3) 1313 if (mmc->version < SD_VERSION_3)
1299 return 0; 1314 return 0;
1300 1315
1301 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f; 1316 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1302 if (sd3_bus_mode & SD_MODE_UHS_SDR104) 1317 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1303 mmc->card_caps |= MMC_CAP(UHS_SDR104); 1318 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1304 if (sd3_bus_mode & SD_MODE_UHS_SDR50) 1319 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1305 mmc->card_caps |= MMC_CAP(UHS_SDR50); 1320 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1306 if (sd3_bus_mode & SD_MODE_UHS_SDR25) 1321 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1307 mmc->card_caps |= MMC_CAP(UHS_SDR25); 1322 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1308 if (sd3_bus_mode & SD_MODE_UHS_SDR12) 1323 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1309 mmc->card_caps |= MMC_CAP(UHS_SDR12); 1324 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1310 if (sd3_bus_mode & SD_MODE_UHS_DDR50) 1325 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1311 mmc->card_caps |= MMC_CAP(UHS_DDR50); 1326 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1312 #endif 1327 #endif
1313 1328
1314 return 0; 1329 return 0;
1315 } 1330 }
1316 1331
1317 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode) 1332 static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1318 { 1333 {
1319 int err; 1334 int err;
1320 1335
1321 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); 1336 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
1322 int speed; 1337 int speed;
1323 1338
1324 switch (mode) { 1339 switch (mode) {
1325 case SD_LEGACY: 1340 case SD_LEGACY:
1326 speed = UHS_SDR12_BUS_SPEED; 1341 speed = UHS_SDR12_BUS_SPEED;
1327 break; 1342 break;
1328 case SD_HS: 1343 case SD_HS:
1329 speed = HIGH_SPEED_BUS_SPEED; 1344 speed = HIGH_SPEED_BUS_SPEED;
1330 break; 1345 break;
1331 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 1346 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1332 case UHS_SDR12: 1347 case UHS_SDR12:
1333 speed = UHS_SDR12_BUS_SPEED; 1348 speed = UHS_SDR12_BUS_SPEED;
1334 break; 1349 break;
1335 case UHS_SDR25: 1350 case UHS_SDR25:
1336 speed = UHS_SDR25_BUS_SPEED; 1351 speed = UHS_SDR25_BUS_SPEED;
1337 break; 1352 break;
1338 case UHS_SDR50: 1353 case UHS_SDR50:
1339 speed = UHS_SDR50_BUS_SPEED; 1354 speed = UHS_SDR50_BUS_SPEED;
1340 break; 1355 break;
1341 case UHS_DDR50: 1356 case UHS_DDR50:
1342 speed = UHS_DDR50_BUS_SPEED; 1357 speed = UHS_DDR50_BUS_SPEED;
1343 break; 1358 break;
1344 case UHS_SDR104: 1359 case UHS_SDR104:
1345 speed = UHS_SDR104_BUS_SPEED; 1360 speed = UHS_SDR104_BUS_SPEED;
1346 break; 1361 break;
1347 #endif 1362 #endif
1348 default: 1363 default:
1349 return -EINVAL; 1364 return -EINVAL;
1350 } 1365 }
1351 1366
1352 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status); 1367 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
1353 if (err) 1368 if (err)
1354 return err; 1369 return err;
1355 1370
1356 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed) 1371 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
1357 return -ENOTSUPP; 1372 return -ENOTSUPP;
1358 1373
1359 return 0; 1374 return 0;
1360 } 1375 }
1361 1376
1362 int sd_select_bus_width(struct mmc *mmc, int w) 1377 int sd_select_bus_width(struct mmc *mmc, int w)
1363 { 1378 {
1364 int err; 1379 int err;
1365 struct mmc_cmd cmd; 1380 struct mmc_cmd cmd;
1366 1381
1367 if ((w != 4) && (w != 1)) 1382 if ((w != 4) && (w != 1))
1368 return -EINVAL; 1383 return -EINVAL;
1369 1384
1370 cmd.cmdidx = MMC_CMD_APP_CMD; 1385 cmd.cmdidx = MMC_CMD_APP_CMD;
1371 cmd.resp_type = MMC_RSP_R1; 1386 cmd.resp_type = MMC_RSP_R1;
1372 cmd.cmdarg = mmc->rca << 16; 1387 cmd.cmdarg = mmc->rca << 16;
1373 1388
1374 err = mmc_send_cmd(mmc, &cmd, NULL); 1389 err = mmc_send_cmd(mmc, &cmd, NULL);
1375 if (err) 1390 if (err)
1376 return err; 1391 return err;
1377 1392
1378 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; 1393 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1379 cmd.resp_type = MMC_RSP_R1; 1394 cmd.resp_type = MMC_RSP_R1;
1380 if (w == 4) 1395 if (w == 4)
1381 cmd.cmdarg = 2; 1396 cmd.cmdarg = 2;
1382 else if (w == 1) 1397 else if (w == 1)
1383 cmd.cmdarg = 0; 1398 cmd.cmdarg = 0;
1384 err = mmc_send_cmd(mmc, &cmd, NULL); 1399 err = mmc_send_cmd(mmc, &cmd, NULL);
1385 if (err) 1400 if (err)
1386 return err; 1401 return err;
1387 1402
1388 return 0; 1403 return 0;
1389 } 1404 }
1390 1405
1391 #if CONFIG_IS_ENABLED(MMC_WRITE) 1406 #if CONFIG_IS_ENABLED(MMC_WRITE)
1392 static int sd_read_ssr(struct mmc *mmc) 1407 static int sd_read_ssr(struct mmc *mmc)
1393 { 1408 {
1394 static const unsigned int sd_au_size[] = { 1409 static const unsigned int sd_au_size[] = {
1395 0, SZ_16K / 512, SZ_32K / 512, 1410 0, SZ_16K / 512, SZ_32K / 512,
1396 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512, 1411 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
1397 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512, 1412 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
1398 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512, 1413 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
1399 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, 1414 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1400 SZ_64M / 512, 1415 SZ_64M / 512,
1401 }; 1416 };
1402 int err, i; 1417 int err, i;
1403 struct mmc_cmd cmd; 1418 struct mmc_cmd cmd;
1404 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16); 1419 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1405 struct mmc_data data; 1420 struct mmc_data data;
1406 int timeout = 3; 1421 int timeout = 3;
1407 unsigned int au, eo, et, es; 1422 unsigned int au, eo, et, es;
1408 1423
1409 cmd.cmdidx = MMC_CMD_APP_CMD; 1424 cmd.cmdidx = MMC_CMD_APP_CMD;
1410 cmd.resp_type = MMC_RSP_R1; 1425 cmd.resp_type = MMC_RSP_R1;
1411 cmd.cmdarg = mmc->rca << 16; 1426 cmd.cmdarg = mmc->rca << 16;
1412 1427
1413 err = mmc_send_cmd(mmc, &cmd, NULL); 1428 err = mmc_send_cmd(mmc, &cmd, NULL);
1414 if (err) 1429 if (err)
1415 return err; 1430 return err;
1416 1431
1417 cmd.cmdidx = SD_CMD_APP_SD_STATUS; 1432 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1418 cmd.resp_type = MMC_RSP_R1; 1433 cmd.resp_type = MMC_RSP_R1;
1419 cmd.cmdarg = 0; 1434 cmd.cmdarg = 0;
1420 1435
1421 retry_ssr: 1436 retry_ssr:
1422 data.dest = (char *)ssr; 1437 data.dest = (char *)ssr;
1423 data.blocksize = 64; 1438 data.blocksize = 64;
1424 data.blocks = 1; 1439 data.blocks = 1;
1425 data.flags = MMC_DATA_READ; 1440 data.flags = MMC_DATA_READ;
1426 1441
1427 err = mmc_send_cmd(mmc, &cmd, &data); 1442 err = mmc_send_cmd(mmc, &cmd, &data);
1428 if (err) { 1443 if (err) {
1429 if (timeout--) 1444 if (timeout--)
1430 goto retry_ssr; 1445 goto retry_ssr;
1431 1446
1432 return err; 1447 return err;
1433 } 1448 }
1434 1449
1435 for (i = 0; i < 16; i++) 1450 for (i = 0; i < 16; i++)
1436 ssr[i] = be32_to_cpu(ssr[i]); 1451 ssr[i] = be32_to_cpu(ssr[i]);
1437 1452
1438 au = (ssr[2] >> 12) & 0xF; 1453 au = (ssr[2] >> 12) & 0xF;
1439 if ((au <= 9) || (mmc->version == SD_VERSION_3)) { 1454 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1440 mmc->ssr.au = sd_au_size[au]; 1455 mmc->ssr.au = sd_au_size[au];
1441 es = (ssr[3] >> 24) & 0xFF; 1456 es = (ssr[3] >> 24) & 0xFF;
1442 es |= (ssr[2] & 0xFF) << 8; 1457 es |= (ssr[2] & 0xFF) << 8;
1443 et = (ssr[3] >> 18) & 0x3F; 1458 et = (ssr[3] >> 18) & 0x3F;
1444 if (es && et) { 1459 if (es && et) {
1445 eo = (ssr[3] >> 16) & 0x3; 1460 eo = (ssr[3] >> 16) & 0x3;
1446 mmc->ssr.erase_timeout = (et * 1000) / es; 1461 mmc->ssr.erase_timeout = (et * 1000) / es;
1447 mmc->ssr.erase_offset = eo * 1000; 1462 mmc->ssr.erase_offset = eo * 1000;
1448 } 1463 }
1449 } else { 1464 } else {
1450 pr_debug("Invalid Allocation Unit Size.\n"); 1465 pr_debug("Invalid Allocation Unit Size.\n");
1451 } 1466 }
1452 1467
1453 return 0; 1468 return 0;
1454 } 1469 }
1455 #endif 1470 #endif
1456 /* frequency bases */ 1471 /* frequency bases */
1457 /* divided by 10 to be nice to platforms without floating point */ 1472 /* divided by 10 to be nice to platforms without floating point */
1458 static const int fbase[] = { 1473 static const int fbase[] = {
1459 10000, 1474 10000,
1460 100000, 1475 100000,
1461 1000000, 1476 1000000,
1462 10000000, 1477 10000000,
1463 }; 1478 };
1464 1479
1465 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice 1480 /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1466 * to platforms without floating point. 1481 * to platforms without floating point.
1467 */ 1482 */
1468 static const u8 multipliers[] = { 1483 static const u8 multipliers[] = {
1469 0, /* reserved */ 1484 0, /* reserved */
1470 10, 1485 10,
1471 12, 1486 12,
1472 13, 1487 13,
1473 15, 1488 15,
1474 20, 1489 20,
1475 25, 1490 25,
1476 30, 1491 30,
1477 35, 1492 35,
1478 40, 1493 40,
1479 45, 1494 45,
1480 50, 1495 50,
1481 55, 1496 55,
1482 60, 1497 60,
1483 70, 1498 70,
1484 80, 1499 80,
1485 }; 1500 };
1486 1501
1487 static inline int bus_width(uint cap) 1502 static inline int bus_width(uint cap)
1488 { 1503 {
1489 if (cap == MMC_MODE_8BIT) 1504 if (cap == MMC_MODE_8BIT)
1490 return 8; 1505 return 8;
1491 if (cap == MMC_MODE_4BIT) 1506 if (cap == MMC_MODE_4BIT)
1492 return 4; 1507 return 4;
1493 if (cap == MMC_MODE_1BIT) 1508 if (cap == MMC_MODE_1BIT)
1494 return 1; 1509 return 1;
1495 pr_warn("invalid bus witdh capability 0x%x\n", cap); 1510 pr_warn("invalid bus witdh capability 0x%x\n", cap);
1496 return 0; 1511 return 0;
1497 } 1512 }
1498 1513
1499 #if !CONFIG_IS_ENABLED(DM_MMC) 1514 #if !CONFIG_IS_ENABLED(DM_MMC)
1500 #ifdef MMC_SUPPORTS_TUNING 1515 #ifdef MMC_SUPPORTS_TUNING
1501 static int mmc_execute_tuning(struct mmc *mmc, uint opcode) 1516 static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1502 { 1517 {
1503 return -ENOTSUPP; 1518 return -ENOTSUPP;
1504 } 1519 }
1505 #endif 1520 #endif
1506 1521
1507 static void mmc_send_init_stream(struct mmc *mmc) 1522 static void mmc_send_init_stream(struct mmc *mmc)
1508 { 1523 {
1509 } 1524 }
1510 1525
1511 static int mmc_set_ios(struct mmc *mmc) 1526 static int mmc_set_ios(struct mmc *mmc)
1512 { 1527 {
1513 int ret = 0; 1528 int ret = 0;
1514 1529
1515 if (mmc->cfg->ops->set_ios) 1530 if (mmc->cfg->ops->set_ios)
1516 ret = mmc->cfg->ops->set_ios(mmc); 1531 ret = mmc->cfg->ops->set_ios(mmc);
1517 1532
1518 return ret; 1533 return ret;
1519 } 1534 }
1520 #endif 1535 #endif
1521 1536
1522 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable) 1537 int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
1523 { 1538 {
1524 if (!disable) { 1539 if (!disable) {
1525 if (clock > mmc->cfg->f_max) 1540 if (clock > mmc->cfg->f_max)
1526 clock = mmc->cfg->f_max; 1541 clock = mmc->cfg->f_max;
1527 1542
1528 if (clock < mmc->cfg->f_min) 1543 if (clock < mmc->cfg->f_min)
1529 clock = mmc->cfg->f_min; 1544 clock = mmc->cfg->f_min;
1530 } 1545 }
1531 1546
1532 mmc->clock = clock; 1547 mmc->clock = clock;
1533 mmc->clk_disable = disable; 1548 mmc->clk_disable = disable;
1534 1549
1535 return mmc_set_ios(mmc); 1550 return mmc_set_ios(mmc);
1536 } 1551 }
1537 1552
1538 static int mmc_set_bus_width(struct mmc *mmc, uint width) 1553 static int mmc_set_bus_width(struct mmc *mmc, uint width)
1539 { 1554 {
1540 mmc->bus_width = width; 1555 mmc->bus_width = width;
1541 1556
1542 return mmc_set_ios(mmc); 1557 return mmc_set_ios(mmc);
1543 } 1558 }
1544 1559
1545 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) 1560 #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1546 /* 1561 /*
1547 * helper function to display the capabilities in a human 1562 * helper function to display the capabilities in a human
1548 * friendly manner. The capabilities include bus width and 1563 * friendly manner. The capabilities include bus width and
1549 * supported modes. 1564 * supported modes.
1550 */ 1565 */
1551 void mmc_dump_capabilities(const char *text, uint caps) 1566 void mmc_dump_capabilities(const char *text, uint caps)
1552 { 1567 {
1553 enum bus_mode mode; 1568 enum bus_mode mode;
1554 1569
1555 pr_debug("%s: widths [", text); 1570 pr_debug("%s: widths [", text);
1556 if (caps & MMC_MODE_8BIT) 1571 if (caps & MMC_MODE_8BIT)
1557 pr_debug("8, "); 1572 pr_debug("8, ");
1558 if (caps & MMC_MODE_4BIT) 1573 if (caps & MMC_MODE_4BIT)
1559 pr_debug("4, "); 1574 pr_debug("4, ");
1560 if (caps & MMC_MODE_1BIT) 1575 if (caps & MMC_MODE_1BIT)
1561 pr_debug("1, "); 1576 pr_debug("1, ");
1562 pr_debug("\b\b] modes ["); 1577 pr_debug("\b\b] modes [");
1563 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++) 1578 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1564 if (MMC_CAP(mode) & caps) 1579 if (MMC_CAP(mode) & caps)
1565 pr_debug("%s, ", mmc_mode_name(mode)); 1580 pr_debug("%s, ", mmc_mode_name(mode));
1566 pr_debug("\b\b]\n"); 1581 pr_debug("\b\b]\n");
1567 } 1582 }
1568 #endif 1583 #endif
1569 1584
1570 struct mode_width_tuning { 1585 struct mode_width_tuning {
1571 enum bus_mode mode; 1586 enum bus_mode mode;
1572 uint widths; 1587 uint widths;
1573 #ifdef MMC_SUPPORTS_TUNING 1588 #ifdef MMC_SUPPORTS_TUNING
1574 uint tuning; 1589 uint tuning;
1575 #endif 1590 #endif
1576 }; 1591 };
1577 1592
1578 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE) 1593 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1579 int mmc_voltage_to_mv(enum mmc_voltage voltage) 1594 int mmc_voltage_to_mv(enum mmc_voltage voltage)
1580 { 1595 {
1581 switch (voltage) { 1596 switch (voltage) {
1582 case MMC_SIGNAL_VOLTAGE_000: return 0; 1597 case MMC_SIGNAL_VOLTAGE_000: return 0;
1583 case MMC_SIGNAL_VOLTAGE_330: return 3300; 1598 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1584 case MMC_SIGNAL_VOLTAGE_180: return 1800; 1599 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1585 case MMC_SIGNAL_VOLTAGE_120: return 1200; 1600 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1586 } 1601 }
1587 return -EINVAL; 1602 return -EINVAL;
1588 } 1603 }
1589 1604
1590 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage) 1605 static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1591 { 1606 {
1592 int err; 1607 int err;
1593 1608
1594 if (mmc->signal_voltage == signal_voltage) 1609 if (mmc->signal_voltage == signal_voltage)
1595 return 0; 1610 return 0;
1596 1611
1597 mmc->signal_voltage = signal_voltage; 1612 mmc->signal_voltage = signal_voltage;
1598 err = mmc_set_ios(mmc); 1613 err = mmc_set_ios(mmc);
1599 if (err) 1614 if (err)
1600 pr_debug("unable to set voltage (err %d)\n", err); 1615 pr_debug("unable to set voltage (err %d)\n", err);
1601 1616
1602 return err; 1617 return err;
1603 } 1618 }
1604 #else 1619 #else
1605 static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage) 1620 static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1606 { 1621 {
1607 return 0; 1622 return 0;
1608 } 1623 }
1609 #endif 1624 #endif
1610 1625
1611 static const struct mode_width_tuning sd_modes_by_pref[] = { 1626 static const struct mode_width_tuning sd_modes_by_pref[] = {
1612 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 1627 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1613 #ifdef MMC_SUPPORTS_TUNING 1628 #ifdef MMC_SUPPORTS_TUNING
1614 { 1629 {
1615 .mode = UHS_SDR104, 1630 .mode = UHS_SDR104,
1616 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, 1631 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1617 .tuning = MMC_CMD_SEND_TUNING_BLOCK 1632 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1618 }, 1633 },
1619 #endif 1634 #endif
1620 { 1635 {
1621 .mode = UHS_SDR50, 1636 .mode = UHS_SDR50,
1622 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, 1637 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1623 }, 1638 },
1624 { 1639 {
1625 .mode = UHS_DDR50, 1640 .mode = UHS_DDR50,
1626 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, 1641 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1627 }, 1642 },
1628 { 1643 {
1629 .mode = UHS_SDR25, 1644 .mode = UHS_SDR25,
1630 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, 1645 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1631 }, 1646 },
1632 #endif 1647 #endif
1633 { 1648 {
1634 .mode = SD_HS, 1649 .mode = SD_HS,
1635 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, 1650 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1636 }, 1651 },
1637 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 1652 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1638 { 1653 {
1639 .mode = UHS_SDR12, 1654 .mode = UHS_SDR12,
1640 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, 1655 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1641 }, 1656 },
1642 #endif 1657 #endif
1643 { 1658 {
1644 .mode = SD_LEGACY, 1659 .mode = SD_LEGACY,
1645 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT, 1660 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1646 } 1661 }
1647 }; 1662 };
1648 1663
1649 #define for_each_sd_mode_by_pref(caps, mwt) \ 1664 #define for_each_sd_mode_by_pref(caps, mwt) \
1650 for (mwt = sd_modes_by_pref;\ 1665 for (mwt = sd_modes_by_pref;\
1651 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\ 1666 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1652 mwt++) \ 1667 mwt++) \
1653 if (caps & MMC_CAP(mwt->mode)) 1668 if (caps & MMC_CAP(mwt->mode))
1654 1669
1655 static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps) 1670 static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
1656 { 1671 {
1657 int err; 1672 int err;
1658 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT}; 1673 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1659 const struct mode_width_tuning *mwt; 1674 const struct mode_width_tuning *mwt;
1660 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) 1675 #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1661 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false; 1676 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1662 #else 1677 #else
1663 bool uhs_en = false; 1678 bool uhs_en = false;
1664 #endif 1679 #endif
1665 uint caps; 1680 uint caps;
1666 1681
1667 #ifdef DEBUG 1682 #ifdef DEBUG
1668 mmc_dump_capabilities("sd card", card_caps); 1683 mmc_dump_capabilities("sd card", card_caps);
1669 mmc_dump_capabilities("host", mmc->host_caps); 1684 mmc_dump_capabilities("host", mmc->host_caps);
1670 #endif 1685 #endif
1671 1686
1672 /* Restrict card's capabilities by what the host can do */ 1687 /* Restrict card's capabilities by what the host can do */
1673 caps = card_caps & mmc->host_caps; 1688 caps = card_caps & mmc->host_caps;
1674 1689
1675 if (!uhs_en) 1690 if (!uhs_en)
1676 caps &= ~UHS_CAPS; 1691 caps &= ~UHS_CAPS;
1677 1692
1678 for_each_sd_mode_by_pref(caps, mwt) { 1693 for_each_sd_mode_by_pref(caps, mwt) {
1679 uint *w; 1694 uint *w;
1680 1695
1681 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) { 1696 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
1682 if (*w & caps & mwt->widths) { 1697 if (*w & caps & mwt->widths) {
1683 pr_debug("trying mode %s width %d (at %d MHz)\n", 1698 pr_debug("trying mode %s width %d (at %d MHz)\n",
1684 mmc_mode_name(mwt->mode), 1699 mmc_mode_name(mwt->mode),
1685 bus_width(*w), 1700 bus_width(*w),
1686 mmc_mode2freq(mmc, mwt->mode) / 1000000); 1701 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1687 1702
1688 /* configure the bus width (card + host) */ 1703 /* configure the bus width (card + host) */
1689 err = sd_select_bus_width(mmc, bus_width(*w)); 1704 err = sd_select_bus_width(mmc, bus_width(*w));
1690 if (err) 1705 if (err)
1691 goto error; 1706 goto error;
1692 mmc_set_bus_width(mmc, bus_width(*w)); 1707 mmc_set_bus_width(mmc, bus_width(*w));
1693 1708
1694 /* configure the bus mode (card) */ 1709 /* configure the bus mode (card) */
1695 err = sd_set_card_speed(mmc, mwt->mode); 1710 err = sd_set_card_speed(mmc, mwt->mode);
1696 if (err) 1711 if (err)
1697 goto error; 1712 goto error;
1698 1713
1699 /* configure the bus mode (host) */ 1714 /* configure the bus mode (host) */
1700 mmc_select_mode(mmc, mwt->mode); 1715 mmc_select_mode(mmc, mwt->mode);
1701 mmc_set_clock(mmc, mmc->tran_speed, false); 1716 mmc_set_clock(mmc, mmc->tran_speed, false);
1702 1717
1703 #ifdef MMC_SUPPORTS_TUNING 1718 #ifdef MMC_SUPPORTS_TUNING
1704 /* execute tuning if needed */ 1719 /* execute tuning if needed */
1705 if (mwt->tuning && !mmc_host_is_spi(mmc)) { 1720 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1706 err = mmc_execute_tuning(mmc, 1721 err = mmc_execute_tuning(mmc,
1707 mwt->tuning); 1722 mwt->tuning);
1708 if (err) { 1723 if (err) {
1709 pr_debug("tuning failed\n"); 1724 pr_debug("tuning failed\n");
1710 goto error; 1725 goto error;
1711 } 1726 }
1712 } 1727 }
1713 #endif 1728 #endif
1714 1729
1715 #if CONFIG_IS_ENABLED(MMC_WRITE) 1730 #if CONFIG_IS_ENABLED(MMC_WRITE)
1716 err = sd_read_ssr(mmc); 1731 err = sd_read_ssr(mmc);
1717 if (err) 1732 if (err)
1718 pr_warn("unable to read ssr\n"); 1733 pr_warn("unable to read ssr\n");
1719 #endif 1734 #endif
1720 if (!err) 1735 if (!err)
1721 return 0; 1736 return 0;
1722 1737
1723 error: 1738 error:
1724 /* revert to a safer bus speed */ 1739 /* revert to a safer bus speed */
1725 mmc_select_mode(mmc, SD_LEGACY); 1740 mmc_select_mode(mmc, SD_LEGACY);
1726 mmc_set_clock(mmc, mmc->tran_speed, false); 1741 mmc_set_clock(mmc, mmc->tran_speed, false);
1727 } 1742 }
1728 } 1743 }
1729 } 1744 }
1730 1745
1731 pr_err("unable to select a mode\n"); 1746 pr_err("unable to select a mode\n");
1732 return -ENOTSUPP; 1747 return -ENOTSUPP;
1733 } 1748 }
1734 1749
1735 /* 1750 /*
1736 * read the compare the part of ext csd that is constant. 1751 * read the compare the part of ext csd that is constant.
1737 * This can be used to check that the transfer is working 1752 * This can be used to check that the transfer is working
1738 * as expected. 1753 * as expected.
1739 */ 1754 */
1740 static int mmc_read_and_compare_ext_csd(struct mmc *mmc) 1755 static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
1741 { 1756 {
1742 int err; 1757 int err;
1743 const u8 *ext_csd = mmc->ext_csd; 1758 const u8 *ext_csd = mmc->ext_csd;
1744 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); 1759 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1745 1760
1746 if (mmc->version < MMC_VERSION_4) 1761 if (mmc->version < MMC_VERSION_4)
1747 return 0; 1762 return 0;
1748 1763
1749 err = mmc_send_ext_csd(mmc, test_csd); 1764 err = mmc_send_ext_csd(mmc, test_csd);
1750 if (err) 1765 if (err)
1751 return err; 1766 return err;
1752 1767
1753 /* Only compare read only fields */ 1768 /* Only compare read only fields */
1754 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] 1769 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1755 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && 1770 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1756 ext_csd[EXT_CSD_HC_WP_GRP_SIZE] 1771 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1757 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && 1772 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1758 ext_csd[EXT_CSD_REV] 1773 ext_csd[EXT_CSD_REV]
1759 == test_csd[EXT_CSD_REV] && 1774 == test_csd[EXT_CSD_REV] &&
1760 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 1775 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1761 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && 1776 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1762 memcmp(&ext_csd[EXT_CSD_SEC_CNT], 1777 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1763 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) 1778 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1764 return 0; 1779 return 0;
1765 1780
1766 return -EBADMSG; 1781 return -EBADMSG;
1767 } 1782 }
1768 1783
1769 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE) 1784 #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
1770 static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode, 1785 static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1771 uint32_t allowed_mask) 1786 uint32_t allowed_mask)
1772 { 1787 {
1773 u32 card_mask = 0; 1788 u32 card_mask = 0;
1774 1789
1775 switch (mode) { 1790 switch (mode) {
1776 case MMC_HS_400_ES: 1791 case MMC_HS_400_ES:
1777 case MMC_HS_400: 1792 case MMC_HS_400:
1778 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS400_1_8V) 1793 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS400_1_8V)
1779 card_mask |= MMC_SIGNAL_VOLTAGE_180; 1794 card_mask |= MMC_SIGNAL_VOLTAGE_180;
1780 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS400_1_2V) 1795 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS400_1_2V)
1781 card_mask |= MMC_SIGNAL_VOLTAGE_120; 1796 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1782 break; 1797 break;
1783 case MMC_HS_200: 1798 case MMC_HS_200:
1784 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V) 1799 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_8V)
1785 card_mask |= MMC_SIGNAL_VOLTAGE_180; 1800 card_mask |= MMC_SIGNAL_VOLTAGE_180;
1786 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V) 1801 if (mmc->cardtype & EXT_CSD_CARD_TYPE_HS200_1_2V)
1787 card_mask |= MMC_SIGNAL_VOLTAGE_120; 1802 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1788 break; 1803 break;
1789 case MMC_DDR_52: 1804 case MMC_DDR_52:
1790 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) 1805 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1791 card_mask |= MMC_SIGNAL_VOLTAGE_330 | 1806 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1792 MMC_SIGNAL_VOLTAGE_180; 1807 MMC_SIGNAL_VOLTAGE_180;
1793 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V) 1808 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1794 card_mask |= MMC_SIGNAL_VOLTAGE_120; 1809 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1795 break; 1810 break;
1796 default: 1811 default:
1797 card_mask |= MMC_SIGNAL_VOLTAGE_330; 1812 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1798 break; 1813 break;
1799 } 1814 }
1800 1815
1801 while (card_mask & allowed_mask) { 1816 while (card_mask & allowed_mask) {
1802 enum mmc_voltage best_match; 1817 enum mmc_voltage best_match;
1803 1818
1804 best_match = 1 << (ffs(card_mask & allowed_mask) - 1); 1819 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1805 if (!mmc_set_signal_voltage(mmc, best_match)) 1820 if (!mmc_set_signal_voltage(mmc, best_match))
1806 return 0; 1821 return 0;
1807 1822
1808 allowed_mask &= ~best_match; 1823 allowed_mask &= ~best_match;
1809 } 1824 }
1810 1825
1811 return -ENOTSUPP; 1826 return -ENOTSUPP;
1812 } 1827 }
1813 #else 1828 #else
1814 static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode, 1829 static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1815 uint32_t allowed_mask) 1830 uint32_t allowed_mask)
1816 { 1831 {
1817 return 0; 1832 return 0;
1818 } 1833 }
1819 #endif 1834 #endif
1820 1835
1821 static const struct mode_width_tuning mmc_modes_by_pref[] = { 1836 static const struct mode_width_tuning mmc_modes_by_pref[] = {
1822 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) 1837 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1823 { 1838 {
1824 .mode = MMC_HS_400_ES, 1839 .mode = MMC_HS_400_ES,
1825 .widths = MMC_MODE_8BIT, 1840 .widths = MMC_MODE_8BIT,
1826 }, 1841 },
1827 #endif 1842 #endif
1828 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) 1843 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1829 { 1844 {
1830 .mode = MMC_HS_400, 1845 .mode = MMC_HS_400,
1831 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT, 1846 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1832 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200 1847 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1833 }, 1848 },
1834 #endif 1849 #endif
1835 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) 1850 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
1836 { 1851 {
1837 .mode = MMC_HS_200, 1852 .mode = MMC_HS_200,
1838 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT, 1853 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1839 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200 1854 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1840 }, 1855 },
1841 #endif 1856 #endif
1842 { 1857 {
1843 .mode = MMC_DDR_52, 1858 .mode = MMC_DDR_52,
1844 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT, 1859 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1845 }, 1860 },
1846 { 1861 {
1847 .mode = MMC_HS_52, 1862 .mode = MMC_HS_52,
1848 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT, 1863 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1849 }, 1864 },
1850 { 1865 {
1851 .mode = MMC_HS, 1866 .mode = MMC_HS,
1852 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT, 1867 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1853 }, 1868 },
1854 { 1869 {
1855 .mode = MMC_LEGACY, 1870 .mode = MMC_LEGACY,
1856 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT, 1871 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1857 } 1872 }
1858 }; 1873 };
1859 1874
1860 #define for_each_mmc_mode_by_pref(caps, mwt) \ 1875 #define for_each_mmc_mode_by_pref(caps, mwt) \
1861 for (mwt = mmc_modes_by_pref;\ 1876 for (mwt = mmc_modes_by_pref;\
1862 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\ 1877 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1863 mwt++) \ 1878 mwt++) \
1864 if (caps & MMC_CAP(mwt->mode)) 1879 if (caps & MMC_CAP(mwt->mode))
1865 1880
1866 static const struct ext_csd_bus_width { 1881 static const struct ext_csd_bus_width {
1867 uint cap; 1882 uint cap;
1868 bool is_ddr; 1883 bool is_ddr;
1869 uint ext_csd_bits; 1884 uint ext_csd_bits;
1870 } ext_csd_bus_width[] = { 1885 } ext_csd_bus_width[] = {
1871 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8}, 1886 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1872 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4}, 1887 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1873 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8}, 1888 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1874 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4}, 1889 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1875 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1}, 1890 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1876 }; 1891 };
1877 1892
1878 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) 1893 #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1879 static int mmc_select_hs400(struct mmc *mmc) 1894 static int mmc_select_hs400(struct mmc *mmc)
1880 { 1895 {
1881 int err; 1896 int err;
1882 1897
1883 /* Set timing to HS200 for tuning */ 1898 /* Set timing to HS200 for tuning */
1884 err = mmc_set_card_speed(mmc, MMC_HS_200); 1899 err = mmc_set_card_speed(mmc, MMC_HS_200, false);
1885 if (err) 1900 if (err)
1886 return err; 1901 return err;
1887 1902
1888 /* configure the bus mode (host) */ 1903 /* configure the bus mode (host) */
1889 mmc_select_mode(mmc, MMC_HS_200); 1904 mmc_select_mode(mmc, MMC_HS_200);
1890 mmc_set_clock(mmc, mmc->tran_speed, false); 1905 mmc_set_clock(mmc, mmc->tran_speed, false);
1891 1906
1892 /* execute tuning if needed */ 1907 /* execute tuning if needed */
1893 err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200); 1908 err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
1894 if (err) { 1909 if (err) {
1895 debug("tuning failed\n"); 1910 debug("tuning failed\n");
1896 return err; 1911 return err;
1897 } 1912 }
1898 1913
1899 /* Set back to HS */ 1914 /* Set back to HS */
1900 mmc_set_card_speed(mmc, MMC_HS); 1915 mmc_set_card_speed(mmc, MMC_HS, false);
1901 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false); 1916 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
1902 1917
1903 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, 1918 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
1904 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG); 1919 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
1905 if (err) 1920 if (err)
1906 return err; 1921 return err;
1907 1922
1908 err = mmc_set_card_speed(mmc, MMC_HS_400); 1923 err = mmc_set_card_speed(mmc, MMC_HS_400, false);
1909 if (err) 1924 if (err)
1910 return err; 1925 return err;
1911 1926
1912 mmc_select_mode(mmc, MMC_HS_400); 1927 mmc_select_mode(mmc, MMC_HS_400);
1913 err = mmc_set_clock(mmc, mmc->tran_speed, false); 1928 err = mmc_set_clock(mmc, mmc->tran_speed, false);
1914 if (err) 1929 if (err)
1915 return err; 1930 return err;
1916 1931
1917 return 0; 1932 return 0;
1918 } 1933 }
1919 #else 1934 #else
1920 static int mmc_select_hs400(struct mmc *mmc) 1935 static int mmc_select_hs400(struct mmc *mmc)
1921 { 1936 {
1922 return -ENOTSUPP; 1937 return -ENOTSUPP;
1923 } 1938 }
1924 #endif 1939 #endif
1925 1940
1926 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) 1941 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1927 #if !CONFIG_IS_ENABLED(DM_MMC) 1942 #if !CONFIG_IS_ENABLED(DM_MMC)
1928 static void mmc_set_enhanced_strobe(struct mmc *mmc) 1943 static void mmc_set_enhanced_strobe(struct mmc *mmc)
1929 { 1944 {
1930 return; 1945 return;
1931 } 1946 }
1932 #endif 1947 #endif
1933 1948
1934 static int mmc_select_hs400es(struct mmc *mmc) 1949 static int mmc_select_hs400es(struct mmc *mmc)
1935 { 1950 {
1936 int err; 1951 int err;
1937 1952
1938 err = mmc_set_card_speed(mmc, MMC_HS); 1953 err = mmc_set_card_speed(mmc, MMC_HS, false);
1939 if (err) 1954 if (err)
1940 return err; 1955 return err;
1941 1956
1942 /* configure the bus mode (host) */ 1957 /* configure the bus mode (host) */
1943 mmc_select_mode(mmc, MMC_HS); 1958 mmc_select_mode(mmc, MMC_HS);
1944 mmc_set_clock(mmc, mmc->tran_speed, false); 1959 mmc_set_clock(mmc, mmc->tran_speed, false);
1945 1960
1946 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1961 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1947 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8 | 1962 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_8 |
1948 EXT_CSD_DDR_FLAG | EXT_CSD_BUS_WIDTH_STROBE); 1963 EXT_CSD_DDR_FLAG | EXT_CSD_BUS_WIDTH_STROBE);
1949 if (err) { 1964 if (err) {
1950 printf("switch to bus width for hs400 failed\n"); 1965 printf("switch to bus width for hs400 failed\n");
1951 return err; 1966 return err;
1952 } 1967 }
1953 /* TODO: driver strength */ 1968 /* TODO: driver strength */
1954 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 1969 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1955 EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS400 | (0 << EXT_CSD_DRV_STR_SHIFT)); 1970 EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS400 | (0 << EXT_CSD_DRV_STR_SHIFT));
1956 if (err) { 1971 if (err) {
1957 printf("switch to hs400 failed\n"); 1972 printf("switch to hs400 failed\n");
1958 return err; 1973 return err;
1959 } 1974 }
1960 1975
1961 mmc_select_mode(mmc, MMC_HS_400_ES); 1976 mmc_select_mode(mmc, MMC_HS_400_ES);
1962 mmc_set_clock(mmc, mmc->tran_speed, false); 1977 mmc_set_clock(mmc, mmc->tran_speed, false);
1963 mmc_set_enhanced_strobe(mmc); 1978 mmc_set_enhanced_strobe(mmc);
1964 1979
1965 return 0; 1980 return 0;
1966 } 1981 }
1967 1982
1968 #else 1983 #else
1969 static int mmc_select_hs400es(struct mmc *mmc) 1984 static int mmc_select_hs400es(struct mmc *mmc)
1970 { 1985 {
1971 return -ENOTSUPP; 1986 return -ENOTSUPP;
1972 } 1987 }
1973 #endif 1988 #endif
1974 1989
1975 #define for_each_supported_width(caps, ddr, ecbv) \ 1990 #define for_each_supported_width(caps, ddr, ecbv) \
1976 for (ecbv = ext_csd_bus_width;\ 1991 for (ecbv = ext_csd_bus_width;\
1977 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\ 1992 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1978 ecbv++) \ 1993 ecbv++) \
1979 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap)) 1994 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1980 1995
1981 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) 1996 static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
1982 { 1997 {
1983 int err; 1998 int err;
1984 const struct mode_width_tuning *mwt; 1999 const struct mode_width_tuning *mwt;
1985 const struct ext_csd_bus_width *ecbw; 2000 const struct ext_csd_bus_width *ecbw;
1986 2001
1987 #ifdef DEBUG 2002 #ifdef DEBUG
1988 mmc_dump_capabilities("mmc", card_caps); 2003 mmc_dump_capabilities("mmc", card_caps);
1989 mmc_dump_capabilities("host", mmc->host_caps); 2004 mmc_dump_capabilities("host", mmc->host_caps);
1990 #endif 2005 #endif
1991 2006
1992 /* Restrict card's capabilities by what the host can do */ 2007 /* Restrict card's capabilities by what the host can do */
1993 card_caps &= mmc->host_caps; 2008 card_caps &= mmc->host_caps;
1994 2009
1995 /* Only version 4 of MMC supports wider bus widths */ 2010 /* Only version 4 of MMC supports wider bus widths */
1996 if (mmc->version < MMC_VERSION_4) 2011 if (mmc->version < MMC_VERSION_4)
1997 return 0; 2012 return 0;
1998 2013
1999 if (!mmc->ext_csd) { 2014 if (!mmc->ext_csd) {
2000 pr_debug("No ext_csd found!\n"); /* this should enver happen */ 2015 pr_debug("No ext_csd found!\n"); /* this should enver happen */
2001 return -ENOTSUPP; 2016 return -ENOTSUPP;
2002 } 2017 }
2003 2018
2019 #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2020 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2021 /*
2022 * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
2023 * before doing anything else, since a transition from either of
2024 * the HS200/HS400 mode directly to legacy mode is not supported.
2025 */
2026 if (mmc->selected_mode == MMC_HS_200 ||
2027 mmc->selected_mode == MMC_HS_400)
2028 mmc_set_card_speed(mmc, MMC_HS, true);
2029 else
2030 #endif
2004 mmc_set_clock(mmc, mmc->legacy_speed, false); 2031 mmc_set_clock(mmc, mmc->legacy_speed, false);
2005 2032
2006 for_each_mmc_mode_by_pref(card_caps, mwt) { 2033 for_each_mmc_mode_by_pref(card_caps, mwt) {
2007 for_each_supported_width(card_caps & mwt->widths, 2034 for_each_supported_width(card_caps & mwt->widths,
2008 mmc_is_mode_ddr(mwt->mode), ecbw) { 2035 mmc_is_mode_ddr(mwt->mode), ecbw) {
2009 enum mmc_voltage old_voltage; 2036 enum mmc_voltage old_voltage;
2010 pr_debug("trying mode %s width %d (at %d MHz)\n", 2037 pr_debug("trying mode %s width %d (at %d MHz)\n",
2011 mmc_mode_name(mwt->mode), 2038 mmc_mode_name(mwt->mode),
2012 bus_width(ecbw->cap), 2039 bus_width(ecbw->cap),
2013 mmc_mode2freq(mmc, mwt->mode) / 1000000); 2040 mmc_mode2freq(mmc, mwt->mode) / 1000000);
2014 old_voltage = mmc->signal_voltage; 2041 old_voltage = mmc->signal_voltage;
2015 err = mmc_set_lowest_voltage(mmc, mwt->mode, 2042 err = mmc_set_lowest_voltage(mmc, mwt->mode,
2016 MMC_ALL_SIGNAL_VOLTAGE); 2043 MMC_ALL_SIGNAL_VOLTAGE);
2017 if (err) 2044 if (err)
2018 continue; 2045 continue;
2019 2046
2020 /* configure the bus width (card + host) */ 2047 /* configure the bus width (card + host) */
2021 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 2048 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2022 EXT_CSD_BUS_WIDTH, 2049 EXT_CSD_BUS_WIDTH,
2023 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG); 2050 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
2024 if (err) 2051 if (err)
2025 goto error; 2052 goto error;
2026 mmc_set_bus_width(mmc, bus_width(ecbw->cap)); 2053 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
2027 2054
2028 if (mwt->mode == MMC_HS_400) { 2055 if (mwt->mode == MMC_HS_400) {
2029 err = mmc_select_hs400(mmc); 2056 err = mmc_select_hs400(mmc);
2030 if (err) 2057 if (err)
2031 goto error; 2058 goto error;
2032 } else if (mwt->mode == MMC_HS_400_ES) { 2059 } else if (mwt->mode == MMC_HS_400_ES) {
2033 err = mmc_select_hs400es(mmc); 2060 err = mmc_select_hs400es(mmc);
2034 if (err) 2061 if (err)
2035 goto error; 2062 goto error;
2036 } else { 2063 } else {
2037 /* configure the bus speed (card) */ 2064 /* configure the bus speed (card) */
2038 err = mmc_set_card_speed(mmc, mwt->mode); 2065 err = mmc_set_card_speed(mmc, mwt->mode, false);
2039 if (err) 2066 if (err)
2040 goto error; 2067 goto error;
2041 2068
2042 /* 2069 /*
2043 * configure the bus width AND the ddr mode 2070 * configure the bus width AND the ddr mode
2044 * (card). The host side will be taken care 2071 * (card). The host side will be taken care
2045 * of in the next step 2072 * of in the next step
2046 */ 2073 */
2047 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) { 2074 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2048 err = mmc_switch(mmc, 2075 err = mmc_switch(mmc,
2049 EXT_CSD_CMD_SET_NORMAL, 2076 EXT_CSD_CMD_SET_NORMAL,
2050 EXT_CSD_BUS_WIDTH, 2077 EXT_CSD_BUS_WIDTH,
2051 ecbw->ext_csd_bits); 2078 ecbw->ext_csd_bits);
2052 if (err) 2079 if (err)
2053 goto error; 2080 goto error;
2054 } 2081 }
2055 2082
2056 /* configure the bus mode (host) */ 2083 /* configure the bus mode (host) */
2057 mmc_select_mode(mmc, mwt->mode); 2084 mmc_select_mode(mmc, mwt->mode);
2058 mmc_set_clock(mmc, mmc->tran_speed, false); 2085 mmc_set_clock(mmc, mmc->tran_speed, false);
2059 #ifdef MMC_SUPPORTS_TUNING 2086 #ifdef MMC_SUPPORTS_TUNING
2060 2087
2061 /* execute tuning if needed */ 2088 /* execute tuning if needed */
2062 if (mwt->tuning) { 2089 if (mwt->tuning) {
2063 err = mmc_execute_tuning(mmc, 2090 err = mmc_execute_tuning(mmc,
2064 mwt->tuning); 2091 mwt->tuning);
2065 if (err) { 2092 if (err) {
2066 pr_debug("tuning failed\n"); 2093 pr_debug("tuning failed\n");
2067 goto error; 2094 goto error;
2068 } 2095 }
2069 } 2096 }
2070 #endif 2097 #endif
2071 } 2098 }
2072 2099
2073 /* do a transfer to check the configuration */ 2100 /* do a transfer to check the configuration */
2074 err = mmc_read_and_compare_ext_csd(mmc); 2101 err = mmc_read_and_compare_ext_csd(mmc);
2075 if (!err) 2102 if (!err)
2076 return 0; 2103 return 0;
2077 error: 2104 error:
2078 mmc_set_signal_voltage(mmc, old_voltage); 2105 mmc_set_signal_voltage(mmc, old_voltage);
2079 /* if an error occured, revert to a safer bus mode */ 2106 /* if an error occured, revert to a safer bus mode */
2080 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 2107 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2081 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1); 2108 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2082 mmc_select_mode(mmc, MMC_LEGACY); 2109 mmc_select_mode(mmc, MMC_LEGACY);
2083 mmc_set_bus_width(mmc, 1); 2110 mmc_set_bus_width(mmc, 1);
2084 } 2111 }
2085 } 2112 }
2086 2113
2087 pr_err("unable to select a mode\n"); 2114 pr_err("unable to select a mode\n");
2088 2115
2089 return -ENOTSUPP; 2116 return -ENOTSUPP;
2090 } 2117 }
2091 2118
2092 static int mmc_startup_v4(struct mmc *mmc) 2119 static int mmc_startup_v4(struct mmc *mmc)
2093 { 2120 {
2094 int err, i; 2121 int err, i;
2095 u64 capacity; 2122 u64 capacity;
2096 bool has_parts = false; 2123 bool has_parts = false;
2097 bool part_completed; 2124 bool part_completed;
2098 static const u32 mmc_versions[] = { 2125 static const u32 mmc_versions[] = {
2099 MMC_VERSION_4, 2126 MMC_VERSION_4,
2100 MMC_VERSION_4_1, 2127 MMC_VERSION_4_1,
2101 MMC_VERSION_4_2, 2128 MMC_VERSION_4_2,
2102 MMC_VERSION_4_3, 2129 MMC_VERSION_4_3,
2103 MMC_VERSION_4_4, 2130 MMC_VERSION_4_4,
2104 MMC_VERSION_4_41, 2131 MMC_VERSION_4_41,
2105 MMC_VERSION_4_5, 2132 MMC_VERSION_4_5,
2106 MMC_VERSION_5_0, 2133 MMC_VERSION_5_0,
2107 MMC_VERSION_5_1 2134 MMC_VERSION_5_1
2108 }; 2135 };
2109 2136
2110 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 2137 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2111 2138
2112 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4)) 2139 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2113 return 0; 2140 return 0;
2114 2141
2115 /* check ext_csd version and capacity */ 2142 /* check ext_csd version and capacity */
2116 err = mmc_send_ext_csd(mmc, ext_csd); 2143 err = mmc_send_ext_csd(mmc, ext_csd);
2117 if (err) 2144 if (err)
2118 goto error; 2145 goto error;
2119 2146
2120 /* store the ext csd for future reference */ 2147 /* store the ext csd for future reference */
2121 if (!mmc->ext_csd) 2148 if (!mmc->ext_csd)
2122 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN); 2149 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2123 if (!mmc->ext_csd) 2150 if (!mmc->ext_csd)
2124 return -ENOMEM; 2151 return -ENOMEM;
2125 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN); 2152 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
2126 2153
2127 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions)) 2154 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
2128 return -EINVAL; 2155 return -EINVAL;
2129 2156
2130 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]]; 2157 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2131 2158
2132 if (mmc->version >= MMC_VERSION_4_2) { 2159 if (mmc->version >= MMC_VERSION_4_2) {
2133 /* 2160 /*
2134 * According to the JEDEC Standard, the value of 2161 * According to the JEDEC Standard, the value of
2135 * ext_csd's capacity is valid if the value is more 2162 * ext_csd's capacity is valid if the value is more
2136 * than 2GB 2163 * than 2GB
2137 */ 2164 */
2138 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 2165 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2139 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 2166 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2140 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 2167 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2141 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; 2168 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2142 capacity *= MMC_MAX_BLOCK_LEN; 2169 capacity *= MMC_MAX_BLOCK_LEN;
2143 if ((capacity >> 20) > 2 * 1024) 2170 if ((capacity >> 20) > 2 * 1024)
2144 mmc->capacity_user = capacity; 2171 mmc->capacity_user = capacity;
2145 } 2172 }
2146 2173
2147 /* The partition data may be non-zero but it is only 2174 /* The partition data may be non-zero but it is only
2148 * effective if PARTITION_SETTING_COMPLETED is set in 2175 * effective if PARTITION_SETTING_COMPLETED is set in
2149 * EXT_CSD, so ignore any data if this bit is not set, 2176 * EXT_CSD, so ignore any data if this bit is not set,
2150 * except for enabling the high-capacity group size 2177 * except for enabling the high-capacity group size
2151 * definition (see below). 2178 * definition (see below).
2152 */ 2179 */
2153 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & 2180 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2154 EXT_CSD_PARTITION_SETTING_COMPLETED); 2181 EXT_CSD_PARTITION_SETTING_COMPLETED);
2155 2182
2156 /* store the partition info of emmc */ 2183 /* store the partition info of emmc */
2157 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; 2184 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2158 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || 2185 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2159 ext_csd[EXT_CSD_BOOT_MULT]) 2186 ext_csd[EXT_CSD_BOOT_MULT])
2160 mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; 2187 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2161 if (part_completed && 2188 if (part_completed &&
2162 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) 2189 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2163 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; 2190 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2164 2191
2165 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; 2192 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2166 2193
2167 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; 2194 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2168 2195
2169 for (i = 0; i < 4; i++) { 2196 for (i = 0; i < 4; i++) {
2170 int idx = EXT_CSD_GP_SIZE_MULT + i * 3; 2197 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2171 uint mult = (ext_csd[idx + 2] << 16) + 2198 uint mult = (ext_csd[idx + 2] << 16) +
2172 (ext_csd[idx + 1] << 8) + ext_csd[idx]; 2199 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2173 if (mult) 2200 if (mult)
2174 has_parts = true; 2201 has_parts = true;
2175 if (!part_completed) 2202 if (!part_completed)
2176 continue; 2203 continue;
2177 mmc->capacity_gp[i] = mult; 2204 mmc->capacity_gp[i] = mult;
2178 mmc->capacity_gp[i] *= 2205 mmc->capacity_gp[i] *=
2179 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 2206 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2180 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 2207 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2181 mmc->capacity_gp[i] <<= 19; 2208 mmc->capacity_gp[i] <<= 19;
2182 } 2209 }
2183 2210
2184 #ifndef CONFIG_SPL_BUILD 2211 #ifndef CONFIG_SPL_BUILD
2185 if (part_completed) { 2212 if (part_completed) {
2186 mmc->enh_user_size = 2213 mmc->enh_user_size =
2187 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) + 2214 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2188 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) + 2215 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2189 ext_csd[EXT_CSD_ENH_SIZE_MULT]; 2216 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2190 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; 2217 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2191 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 2218 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2192 mmc->enh_user_size <<= 19; 2219 mmc->enh_user_size <<= 19;
2193 mmc->enh_user_start = 2220 mmc->enh_user_start =
2194 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) + 2221 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2195 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) + 2222 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2196 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) + 2223 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2197 ext_csd[EXT_CSD_ENH_START_ADDR]; 2224 ext_csd[EXT_CSD_ENH_START_ADDR];
2198 if (mmc->high_capacity) 2225 if (mmc->high_capacity)
2199 mmc->enh_user_start <<= 9; 2226 mmc->enh_user_start <<= 9;
2200 } 2227 }
2201 #endif 2228 #endif
2202 2229
2203 /* 2230 /*
2204 * Host needs to enable ERASE_GRP_DEF bit if device is 2231 * Host needs to enable ERASE_GRP_DEF bit if device is
2205 * partitioned. This bit will be lost every time after a reset 2232 * partitioned. This bit will be lost every time after a reset
2206 * or power off. This will affect erase size. 2233 * or power off. This will affect erase size.
2207 */ 2234 */
2208 if (part_completed) 2235 if (part_completed)
2209 has_parts = true; 2236 has_parts = true;
2210 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && 2237 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2211 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) 2238 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2212 has_parts = true; 2239 has_parts = true;
2213 if (has_parts) { 2240 if (has_parts) {
2214 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, 2241 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2215 EXT_CSD_ERASE_GROUP_DEF, 1); 2242 EXT_CSD_ERASE_GROUP_DEF, 1);
2216 2243
2217 if (err) 2244 if (err)
2218 goto error; 2245 goto error;
2219 2246
2220 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; 2247 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2221 } 2248 }
2222 2249
2223 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { 2250 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
2224 #if CONFIG_IS_ENABLED(MMC_WRITE) 2251 #if CONFIG_IS_ENABLED(MMC_WRITE)
2225 /* Read out group size from ext_csd */ 2252 /* Read out group size from ext_csd */
2226 mmc->erase_grp_size = 2253 mmc->erase_grp_size =
2227 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; 2254 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
2228 #endif 2255 #endif
2229 /* 2256 /*
2230 * if high capacity and partition setting completed 2257 * if high capacity and partition setting completed
2231 * SEC_COUNT is valid even if it is smaller than 2 GiB 2258 * SEC_COUNT is valid even if it is smaller than 2 GiB
2232 * JEDEC Standard JESD84-B45, 6.2.4 2259 * JEDEC Standard JESD84-B45, 6.2.4
2233 */ 2260 */
2234 if (mmc->high_capacity && part_completed) { 2261 if (mmc->high_capacity && part_completed) {
2235 capacity = (ext_csd[EXT_CSD_SEC_CNT]) | 2262 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2236 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | 2263 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2237 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | 2264 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2238 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); 2265 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2239 capacity *= MMC_MAX_BLOCK_LEN; 2266 capacity *= MMC_MAX_BLOCK_LEN;
2240 mmc->capacity_user = capacity; 2267 mmc->capacity_user = capacity;
2241 } 2268 }
2242 } 2269 }
2243 #if CONFIG_IS_ENABLED(MMC_WRITE) 2270 #if CONFIG_IS_ENABLED(MMC_WRITE)
2244 else { 2271 else {
2245 /* Calculate the group size from the csd value. */ 2272 /* Calculate the group size from the csd value. */
2246 int erase_gsz, erase_gmul; 2273 int erase_gsz, erase_gmul;
2247 2274
2248 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; 2275 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2249 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; 2276 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2250 mmc->erase_grp_size = (erase_gsz + 1) 2277 mmc->erase_grp_size = (erase_gsz + 1)
2251 * (erase_gmul + 1); 2278 * (erase_gmul + 1);
2252 } 2279 }
2253 #endif 2280 #endif
2254 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING) 2281 #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
2255 mmc->hc_wp_grp_size = 1024 2282 mmc->hc_wp_grp_size = 1024
2256 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] 2283 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2257 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; 2284 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2258 #endif 2285 #endif
2259 2286
2260 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; 2287 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2261 2288
2262 return 0; 2289 return 0;
2263 error: 2290 error:
2264 if (mmc->ext_csd) { 2291 if (mmc->ext_csd) {
2265 free(mmc->ext_csd); 2292 free(mmc->ext_csd);
2266 mmc->ext_csd = NULL; 2293 mmc->ext_csd = NULL;
2267 } 2294 }
2268 return err; 2295 return err;
2269 } 2296 }
2270 2297
2271 static int mmc_startup(struct mmc *mmc) 2298 static int mmc_startup(struct mmc *mmc)
2272 { 2299 {
2273 int err, i; 2300 int err, i;
2274 uint mult, freq; 2301 uint mult, freq;
2275 u64 cmult, csize; 2302 u64 cmult, csize;
2276 struct mmc_cmd cmd; 2303 struct mmc_cmd cmd;
2277 struct blk_desc *bdesc; 2304 struct blk_desc *bdesc;
2278 2305
2279 #ifdef CONFIG_MMC_SPI_CRC_ON 2306 #ifdef CONFIG_MMC_SPI_CRC_ON
2280 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ 2307 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2281 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; 2308 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2282 cmd.resp_type = MMC_RSP_R1; 2309 cmd.resp_type = MMC_RSP_R1;
2283 cmd.cmdarg = 1; 2310 cmd.cmdarg = 1;
2284 err = mmc_send_cmd(mmc, &cmd, NULL); 2311 err = mmc_send_cmd(mmc, &cmd, NULL);
2285 if (err) 2312 if (err)
2286 return err; 2313 return err;
2287 } 2314 }
2288 #endif 2315 #endif
2289 2316
2290 /* Put the Card in Identify Mode */ 2317 /* Put the Card in Identify Mode */
2291 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : 2318 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2292 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ 2319 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
2293 cmd.resp_type = MMC_RSP_R2; 2320 cmd.resp_type = MMC_RSP_R2;
2294 cmd.cmdarg = 0; 2321 cmd.cmdarg = 0;
2295 2322
2296 err = mmc_send_cmd(mmc, &cmd, NULL); 2323 err = mmc_send_cmd(mmc, &cmd, NULL);
2297 2324
2298 #ifdef CONFIG_MMC_QUIRKS 2325 #ifdef CONFIG_MMC_QUIRKS
2299 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) { 2326 if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
2300 int retries = 4; 2327 int retries = 4;
2301 /* 2328 /*
2302 * It has been seen that SEND_CID may fail on the first 2329 * It has been seen that SEND_CID may fail on the first
2303 * attempt, let's try a few more time 2330 * attempt, let's try a few more time
2304 */ 2331 */
2305 do { 2332 do {
2306 err = mmc_send_cmd(mmc, &cmd, NULL); 2333 err = mmc_send_cmd(mmc, &cmd, NULL);
2307 if (!err) 2334 if (!err)
2308 break; 2335 break;
2309 } while (retries--); 2336 } while (retries--);
2310 } 2337 }
2311 #endif 2338 #endif
2312 2339
2313 if (err) 2340 if (err)
2314 return err; 2341 return err;
2315 2342
2316 memcpy(mmc->cid, cmd.response, 16); 2343 memcpy(mmc->cid, cmd.response, 16);
2317 2344
2318 /* 2345 /*
2319 * For MMC cards, set the Relative Address. 2346 * For MMC cards, set the Relative Address.
2320 * For SD cards, get the Relatvie Address. 2347 * For SD cards, get the Relatvie Address.
2321 * This also puts the cards into Standby State 2348 * This also puts the cards into Standby State
2322 */ 2349 */
2323 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 2350 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2324 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; 2351 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2325 cmd.cmdarg = mmc->rca << 16; 2352 cmd.cmdarg = mmc->rca << 16;
2326 cmd.resp_type = MMC_RSP_R6; 2353 cmd.resp_type = MMC_RSP_R6;
2327 2354
2328 err = mmc_send_cmd(mmc, &cmd, NULL); 2355 err = mmc_send_cmd(mmc, &cmd, NULL);
2329 2356
2330 if (err) 2357 if (err)
2331 return err; 2358 return err;
2332 2359
2333 if (IS_SD(mmc)) 2360 if (IS_SD(mmc))
2334 mmc->rca = (cmd.response[0] >> 16) & 0xffff; 2361 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2335 } 2362 }
2336 2363
2337 /* Get the Card-Specific Data */ 2364 /* Get the Card-Specific Data */
2338 cmd.cmdidx = MMC_CMD_SEND_CSD; 2365 cmd.cmdidx = MMC_CMD_SEND_CSD;
2339 cmd.resp_type = MMC_RSP_R2; 2366 cmd.resp_type = MMC_RSP_R2;
2340 cmd.cmdarg = mmc->rca << 16; 2367 cmd.cmdarg = mmc->rca << 16;
2341 2368
2342 err = mmc_send_cmd(mmc, &cmd, NULL); 2369 err = mmc_send_cmd(mmc, &cmd, NULL);
2343 2370
2344 if (err) 2371 if (err)
2345 return err; 2372 return err;
2346 2373
2347 mmc->csd[0] = cmd.response[0]; 2374 mmc->csd[0] = cmd.response[0];
2348 mmc->csd[1] = cmd.response[1]; 2375 mmc->csd[1] = cmd.response[1];
2349 mmc->csd[2] = cmd.response[2]; 2376 mmc->csd[2] = cmd.response[2];
2350 mmc->csd[3] = cmd.response[3]; 2377 mmc->csd[3] = cmd.response[3];
2351 2378
2352 if (mmc->version == MMC_VERSION_UNKNOWN) { 2379 if (mmc->version == MMC_VERSION_UNKNOWN) {
2353 int version = (cmd.response[0] >> 26) & 0xf; 2380 int version = (cmd.response[0] >> 26) & 0xf;
2354 2381
2355 switch (version) { 2382 switch (version) {
2356 case 0: 2383 case 0:
2357 mmc->version = MMC_VERSION_1_2; 2384 mmc->version = MMC_VERSION_1_2;
2358 break; 2385 break;
2359 case 1: 2386 case 1:
2360 mmc->version = MMC_VERSION_1_4; 2387 mmc->version = MMC_VERSION_1_4;
2361 break; 2388 break;
2362 case 2: 2389 case 2:
2363 mmc->version = MMC_VERSION_2_2; 2390 mmc->version = MMC_VERSION_2_2;
2364 break; 2391 break;
2365 case 3: 2392 case 3:
2366 mmc->version = MMC_VERSION_3; 2393 mmc->version = MMC_VERSION_3;
2367 break; 2394 break;
2368 case 4: 2395 case 4:
2369 mmc->version = MMC_VERSION_4; 2396 mmc->version = MMC_VERSION_4;
2370 break; 2397 break;
2371 default: 2398 default:
2372 mmc->version = MMC_VERSION_1_2; 2399 mmc->version = MMC_VERSION_1_2;
2373 break; 2400 break;
2374 } 2401 }
2375 } 2402 }
2376 2403
2377 /* divide frequency by 10, since the mults are 10x bigger */ 2404 /* divide frequency by 10, since the mults are 10x bigger */
2378 freq = fbase[(cmd.response[0] & 0x7)]; 2405 freq = fbase[(cmd.response[0] & 0x7)];
2379 mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; 2406 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
2380 2407
2381 mmc->legacy_speed = freq * mult; 2408 mmc->legacy_speed = freq * mult;
2382 mmc_select_mode(mmc, MMC_LEGACY); 2409 mmc_select_mode(mmc, MMC_LEGACY);
2383 2410
2384 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); 2411 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
2385 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); 2412 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
2386 #if CONFIG_IS_ENABLED(MMC_WRITE) 2413 #if CONFIG_IS_ENABLED(MMC_WRITE)
2387 2414
2388 if (IS_SD(mmc)) 2415 if (IS_SD(mmc))
2389 mmc->write_bl_len = mmc->read_bl_len; 2416 mmc->write_bl_len = mmc->read_bl_len;
2390 else 2417 else
2391 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); 2418 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
2392 #endif 2419 #endif
2393 2420
2394 if (mmc->high_capacity) { 2421 if (mmc->high_capacity) {
2395 csize = (mmc->csd[1] & 0x3f) << 16 2422 csize = (mmc->csd[1] & 0x3f) << 16
2396 | (mmc->csd[2] & 0xffff0000) >> 16; 2423 | (mmc->csd[2] & 0xffff0000) >> 16;
2397 cmult = 8; 2424 cmult = 8;
2398 } else { 2425 } else {
2399 csize = (mmc->csd[1] & 0x3ff) << 2 2426 csize = (mmc->csd[1] & 0x3ff) << 2
2400 | (mmc->csd[2] & 0xc0000000) >> 30; 2427 | (mmc->csd[2] & 0xc0000000) >> 30;
2401 cmult = (mmc->csd[2] & 0x00038000) >> 15; 2428 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2402 } 2429 }
2403 2430
2404 mmc->capacity_user = (csize + 1) << (cmult + 2); 2431 mmc->capacity_user = (csize + 1) << (cmult + 2);
2405 mmc->capacity_user *= mmc->read_bl_len; 2432 mmc->capacity_user *= mmc->read_bl_len;
2406 mmc->capacity_boot = 0; 2433 mmc->capacity_boot = 0;
2407 mmc->capacity_rpmb = 0; 2434 mmc->capacity_rpmb = 0;
2408 for (i = 0; i < 4; i++) 2435 for (i = 0; i < 4; i++)
2409 mmc->capacity_gp[i] = 0; 2436 mmc->capacity_gp[i] = 0;
2410 2437
2411 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) 2438 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2412 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 2439 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2413 2440
2414 #if CONFIG_IS_ENABLED(MMC_WRITE) 2441 #if CONFIG_IS_ENABLED(MMC_WRITE)
2415 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) 2442 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2416 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 2443 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2417 #endif 2444 #endif
2418 2445
2419 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { 2446 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2420 cmd.cmdidx = MMC_CMD_SET_DSR; 2447 cmd.cmdidx = MMC_CMD_SET_DSR;
2421 cmd.cmdarg = (mmc->dsr & 0xffff) << 16; 2448 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2422 cmd.resp_type = MMC_RSP_NONE; 2449 cmd.resp_type = MMC_RSP_NONE;
2423 if (mmc_send_cmd(mmc, &cmd, NULL)) 2450 if (mmc_send_cmd(mmc, &cmd, NULL))
2424 pr_warn("MMC: SET_DSR failed\n"); 2451 pr_warn("MMC: SET_DSR failed\n");
2425 } 2452 }
2426 2453
2427 /* Select the card, and put it into Transfer Mode */ 2454 /* Select the card, and put it into Transfer Mode */
2428 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ 2455 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2429 cmd.cmdidx = MMC_CMD_SELECT_CARD; 2456 cmd.cmdidx = MMC_CMD_SELECT_CARD;
2430 cmd.resp_type = MMC_RSP_R1; 2457 cmd.resp_type = MMC_RSP_R1;
2431 cmd.cmdarg = mmc->rca << 16; 2458 cmd.cmdarg = mmc->rca << 16;
2432 err = mmc_send_cmd(mmc, &cmd, NULL); 2459 err = mmc_send_cmd(mmc, &cmd, NULL);
2433 2460
2434 if (err) 2461 if (err)
2435 return err; 2462 return err;
2436 } 2463 }
2437 2464
2438 /* 2465 /*
2439 * For SD, its erase group is always one sector 2466 * For SD, its erase group is always one sector
2440 */ 2467 */
2441 #if CONFIG_IS_ENABLED(MMC_WRITE) 2468 #if CONFIG_IS_ENABLED(MMC_WRITE)
2442 mmc->erase_grp_size = 1; 2469 mmc->erase_grp_size = 1;
2443 #endif 2470 #endif
2444 mmc->part_config = MMCPART_NOAVAILABLE; 2471 mmc->part_config = MMCPART_NOAVAILABLE;
2445 2472
2446 err = mmc_startup_v4(mmc); 2473 err = mmc_startup_v4(mmc);
2447 if (err) 2474 if (err)
2448 return err; 2475 return err;
2449 2476
2450 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart); 2477 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
2451 if (err) 2478 if (err)
2452 return err; 2479 return err;
2453 2480
2454 if (IS_SD(mmc)) { 2481 if (IS_SD(mmc)) {
2455 err = sd_get_capabilities(mmc); 2482 err = sd_get_capabilities(mmc);
2456 if (err) 2483 if (err)
2457 return err; 2484 return err;
2458 err = sd_select_mode_and_width(mmc, mmc->card_caps); 2485 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2459 } else { 2486 } else {
2460 err = mmc_get_capabilities(mmc); 2487 err = mmc_get_capabilities(mmc);
2461 if (err) 2488 if (err)
2462 return err; 2489 return err;
2463 mmc_select_mode_and_width(mmc, mmc->card_caps); 2490 mmc_select_mode_and_width(mmc, mmc->card_caps);
2464 } 2491 }
2465 2492
2466 if (err) 2493 if (err)
2467 return err; 2494 return err;
2468 2495
2469 mmc->best_mode = mmc->selected_mode; 2496 mmc->best_mode = mmc->selected_mode;
2470 2497
2471 /* Fix the block length for DDR mode */ 2498 /* Fix the block length for DDR mode */
2472 if (mmc->ddr_mode) { 2499 if (mmc->ddr_mode) {
2473 mmc->read_bl_len = MMC_MAX_BLOCK_LEN; 2500 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2474 #if CONFIG_IS_ENABLED(MMC_WRITE) 2501 #if CONFIG_IS_ENABLED(MMC_WRITE)
2475 mmc->write_bl_len = MMC_MAX_BLOCK_LEN; 2502 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2476 #endif 2503 #endif
2477 } 2504 }
2478 2505
2479 /* fill in device description */ 2506 /* fill in device description */
2480 bdesc = mmc_get_blk_desc(mmc); 2507 bdesc = mmc_get_blk_desc(mmc);
2481 bdesc->lun = 0; 2508 bdesc->lun = 0;
2482 bdesc->hwpart = 0; 2509 bdesc->hwpart = 0;
2483 bdesc->type = 0; 2510 bdesc->type = 0;
2484 bdesc->blksz = mmc->read_bl_len; 2511 bdesc->blksz = mmc->read_bl_len;
2485 bdesc->log2blksz = LOG2(bdesc->blksz); 2512 bdesc->log2blksz = LOG2(bdesc->blksz);
2486 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); 2513 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
2487 #if !defined(CONFIG_SPL_BUILD) || \ 2514 #if !defined(CONFIG_SPL_BUILD) || \
2488 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ 2515 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2489 !defined(CONFIG_USE_TINY_PRINTF)) 2516 !defined(CONFIG_USE_TINY_PRINTF))
2490 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x", 2517 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
2491 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), 2518 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2492 (mmc->cid[3] >> 16) & 0xffff); 2519 (mmc->cid[3] >> 16) & 0xffff);
2493 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, 2520 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
2494 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, 2521 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2495 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, 2522 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2496 (mmc->cid[2] >> 24) & 0xff); 2523 (mmc->cid[2] >> 24) & 0xff);
2497 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, 2524 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
2498 (mmc->cid[2] >> 16) & 0xf); 2525 (mmc->cid[2] >> 16) & 0xf);
2499 #else 2526 #else
2500 bdesc->vendor[0] = 0; 2527 bdesc->vendor[0] = 0;
2501 bdesc->product[0] = 0; 2528 bdesc->product[0] = 0;
2502 bdesc->revision[0] = 0; 2529 bdesc->revision[0] = 0;
2503 #endif 2530 #endif
2504 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) 2531 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
2505 part_init(bdesc); 2532 part_init(bdesc);
2506 #endif 2533 #endif
2507 2534
2508 return 0; 2535 return 0;
2509 } 2536 }
2510 2537
2511 static int mmc_send_if_cond(struct mmc *mmc) 2538 static int mmc_send_if_cond(struct mmc *mmc)
2512 { 2539 {
2513 struct mmc_cmd cmd; 2540 struct mmc_cmd cmd;
2514 int err; 2541 int err;
2515 2542
2516 cmd.cmdidx = SD_CMD_SEND_IF_COND; 2543 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2517 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ 2544 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
2518 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; 2545 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
2519 cmd.resp_type = MMC_RSP_R7; 2546 cmd.resp_type = MMC_RSP_R7;
2520 2547
2521 err = mmc_send_cmd(mmc, &cmd, NULL); 2548 err = mmc_send_cmd(mmc, &cmd, NULL);
2522 2549
2523 if (err) 2550 if (err)
2524 return err; 2551 return err;
2525 2552
2526 if ((cmd.response[0] & 0xff) != 0xaa) 2553 if ((cmd.response[0] & 0xff) != 0xaa)
2527 return -EOPNOTSUPP; 2554 return -EOPNOTSUPP;
2528 else 2555 else
2529 mmc->version = SD_VERSION_2; 2556 mmc->version = SD_VERSION_2;
2530 2557
2531 return 0; 2558 return 0;
2532 } 2559 }
2533 2560
2534 #if !CONFIG_IS_ENABLED(DM_MMC) 2561 #if !CONFIG_IS_ENABLED(DM_MMC)
2535 /* board-specific MMC power initializations. */ 2562 /* board-specific MMC power initializations. */
2536 __weak void board_mmc_power_init(void) 2563 __weak void board_mmc_power_init(void)
2537 { 2564 {
2538 } 2565 }
2539 #endif 2566 #endif
2540 2567
2541 static int mmc_power_init(struct mmc *mmc) 2568 static int mmc_power_init(struct mmc *mmc)
2542 { 2569 {
2543 #if CONFIG_IS_ENABLED(DM_MMC) 2570 #if CONFIG_IS_ENABLED(DM_MMC)
2544 #if CONFIG_IS_ENABLED(DM_REGULATOR) 2571 #if CONFIG_IS_ENABLED(DM_REGULATOR)
2545 int ret; 2572 int ret;
2546 2573
2547 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply", 2574 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
2548 &mmc->vmmc_supply); 2575 &mmc->vmmc_supply);
2549 if (ret) 2576 if (ret)
2550 pr_debug("%s: No vmmc supply\n", mmc->dev->name); 2577 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2551 2578
2552 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply", 2579 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2553 &mmc->vqmmc_supply); 2580 &mmc->vqmmc_supply);
2554 if (ret) 2581 if (ret)
2555 pr_debug("%s: No vqmmc supply\n", mmc->dev->name); 2582 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
2556 #endif 2583 #endif
2557 #else /* !CONFIG_DM_MMC */ 2584 #else /* !CONFIG_DM_MMC */
2558 /* 2585 /*
2559 * Driver model should use a regulator, as above, rather than calling 2586 * Driver model should use a regulator, as above, rather than calling
2560 * out to board code. 2587 * out to board code.
2561 */ 2588 */
2562 board_mmc_power_init(); 2589 board_mmc_power_init();
2563 #endif 2590 #endif
2564 return 0; 2591 return 0;
2565 } 2592 }
2566 2593
2567 /* 2594 /*
2568 * put the host in the initial state: 2595 * put the host in the initial state:
2569 * - turn on Vdd (card power supply) 2596 * - turn on Vdd (card power supply)
2570 * - configure the bus width and clock to minimal values 2597 * - configure the bus width and clock to minimal values
2571 */ 2598 */
2572 static void mmc_set_initial_state(struct mmc *mmc) 2599 static void mmc_set_initial_state(struct mmc *mmc)
2573 { 2600 {
2574 int err; 2601 int err;
2575 2602
2576 /* First try to set 3.3V. If it fails set to 1.8V */ 2603 /* First try to set 3.3V. If it fails set to 1.8V */
2577 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330); 2604 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2578 if (err != 0) 2605 if (err != 0)
2579 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180); 2606 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2580 if (err != 0) 2607 if (err != 0)
2581 pr_warn("mmc: failed to set signal voltage\n"); 2608 pr_warn("mmc: failed to set signal voltage\n");
2582 2609
2583 mmc_select_mode(mmc, MMC_LEGACY); 2610 mmc_select_mode(mmc, MMC_LEGACY);
2584 mmc_set_bus_width(mmc, 1); 2611 mmc_set_bus_width(mmc, 1);
2585 mmc_set_clock(mmc, 0, false); 2612 mmc_set_clock(mmc, 0, false);
2586 } 2613 }
2587 2614
2588 static int mmc_power_on(struct mmc *mmc) 2615 static int mmc_power_on(struct mmc *mmc)
2589 { 2616 {
2590 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR) 2617 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2591 if (mmc->vmmc_supply) { 2618 if (mmc->vmmc_supply) {
2592 int ret = regulator_set_enable(mmc->vmmc_supply, true); 2619 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2593 2620
2594 if (ret) { 2621 if (ret) {
2595 puts("Error enabling VMMC supply\n"); 2622 puts("Error enabling VMMC supply\n");
2596 return ret; 2623 return ret;
2597 } 2624 }
2598 } 2625 }
2599 #endif 2626 #endif
2600 return 0; 2627 return 0;
2601 } 2628 }
2602 2629
2603 static int mmc_power_off(struct mmc *mmc) 2630 static int mmc_power_off(struct mmc *mmc)
2604 { 2631 {
2605 mmc_set_clock(mmc, 0, true); 2632 mmc_set_clock(mmc, 0, true);
2606 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR) 2633 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2607 if (mmc->vmmc_supply) { 2634 if (mmc->vmmc_supply) {
2608 int ret = regulator_set_enable(mmc->vmmc_supply, false); 2635 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2609 2636
2610 if (ret) { 2637 if (ret) {
2611 pr_debug("Error disabling VMMC supply\n"); 2638 pr_debug("Error disabling VMMC supply\n");
2612 return ret; 2639 return ret;
2613 } 2640 }
2614 } 2641 }
2615 #endif 2642 #endif
2616 return 0; 2643 return 0;
2617 } 2644 }
2618 2645
2619 static int mmc_power_cycle(struct mmc *mmc) 2646 static int mmc_power_cycle(struct mmc *mmc)
2620 { 2647 {
2621 int ret; 2648 int ret;
2622 2649
2623 ret = mmc_power_off(mmc); 2650 ret = mmc_power_off(mmc);
2624 if (ret) 2651 if (ret)
2625 return ret; 2652 return ret;
2626 /* 2653 /*
2627 * SD spec recommends at least 1ms of delay. Let's wait for 2ms 2654 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2628 * to be on the safer side. 2655 * to be on the safer side.
2629 */ 2656 */
2630 udelay(2000); 2657 udelay(2000);
2631 return mmc_power_on(mmc); 2658 return mmc_power_on(mmc);
2632 } 2659 }
2633 2660
2634 int mmc_start_init(struct mmc *mmc) 2661 int mmc_start_init(struct mmc *mmc)
2635 { 2662 {
2636 bool no_card; 2663 bool no_card;
2637 bool uhs_en = supports_uhs(mmc->cfg->host_caps); 2664 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
2638 int err; 2665 int err;
2639 2666
2640 /* 2667 /*
2641 * all hosts are capable of 1 bit bus-width and able to use the legacy 2668 * all hosts are capable of 1 bit bus-width and able to use the legacy
2642 * timings. 2669 * timings.
2643 */ 2670 */
2644 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) | 2671 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(SD_LEGACY) |
2645 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT; 2672 MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
2646 2673
2647 #if !defined(CONFIG_MMC_BROKEN_CD) 2674 #if !defined(CONFIG_MMC_BROKEN_CD)
2648 /* we pretend there's no card when init is NULL */ 2675 /* we pretend there's no card when init is NULL */
2649 no_card = mmc_getcd(mmc) == 0; 2676 no_card = mmc_getcd(mmc) == 0;
2650 #else 2677 #else
2651 no_card = 0; 2678 no_card = 0;
2652 #endif 2679 #endif
2653 #if !CONFIG_IS_ENABLED(DM_MMC) 2680 #if !CONFIG_IS_ENABLED(DM_MMC)
2654 no_card = no_card || (mmc->cfg->ops->init == NULL); 2681 no_card = no_card || (mmc->cfg->ops->init == NULL);
2655 #endif 2682 #endif
2656 if (no_card) { 2683 if (no_card) {
2657 mmc->has_init = 0; 2684 mmc->has_init = 0;
2658 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 2685 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2659 pr_err("MMC: no card present\n"); 2686 pr_err("MMC: no card present\n");
2660 #endif 2687 #endif
2661 return -ENOMEDIUM; 2688 return -ENOMEDIUM;
2662 } 2689 }
2663 2690
2664 if (mmc->has_init) 2691 if (mmc->has_init)
2665 return 0; 2692 return 0;
2666 2693
2667 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 2694 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2668 mmc_adapter_card_type_ident(); 2695 mmc_adapter_card_type_ident();
2669 #endif 2696 #endif
2670 err = mmc_power_init(mmc); 2697 err = mmc_power_init(mmc);
2671 if (err) 2698 if (err)
2672 return err; 2699 return err;
2673 2700
2674 #ifdef CONFIG_MMC_QUIRKS 2701 #ifdef CONFIG_MMC_QUIRKS
2675 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN | 2702 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
2676 MMC_QUIRK_RETRY_SEND_CID; 2703 MMC_QUIRK_RETRY_SEND_CID;
2677 #endif 2704 #endif
2678 2705
2679 err = mmc_power_cycle(mmc); 2706 err = mmc_power_cycle(mmc);
2680 if (err) { 2707 if (err) {
2681 /* 2708 /*
2682 * if power cycling is not supported, we should not try 2709 * if power cycling is not supported, we should not try
2683 * to use the UHS modes, because we wouldn't be able to 2710 * to use the UHS modes, because we wouldn't be able to
2684 * recover from an error during the UHS initialization. 2711 * recover from an error during the UHS initialization.
2685 */ 2712 */
2686 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n"); 2713 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2687 uhs_en = false; 2714 uhs_en = false;
2688 mmc->host_caps &= ~UHS_CAPS; 2715 mmc->host_caps &= ~UHS_CAPS;
2689 err = mmc_power_on(mmc); 2716 err = mmc_power_on(mmc);
2690 } 2717 }
2691 if (err) 2718 if (err)
2692 return err; 2719 return err;
2693 2720
2694 #if CONFIG_IS_ENABLED(DM_MMC) 2721 #if CONFIG_IS_ENABLED(DM_MMC)
2695 /* The device has already been probed ready for use */ 2722 /* The device has already been probed ready for use */
2696 #else 2723 #else
2697 /* made sure it's not NULL earlier */ 2724 /* made sure it's not NULL earlier */
2698 err = mmc->cfg->ops->init(mmc); 2725 err = mmc->cfg->ops->init(mmc);
2699 if (err) 2726 if (err)
2700 return err; 2727 return err;
2701 #endif 2728 #endif
2702 mmc->ddr_mode = 0; 2729 mmc->ddr_mode = 0;
2703 2730
2704 retry: 2731 retry:
2705 mmc_set_initial_state(mmc); 2732 mmc_set_initial_state(mmc);
2706 mmc_send_init_stream(mmc); 2733 mmc_send_init_stream(mmc);
2707 2734
2708 /* Reset the Card */ 2735 /* Reset the Card */
2709 err = mmc_go_idle(mmc); 2736 err = mmc_go_idle(mmc);
2710 2737
2711 if (err) 2738 if (err)
2712 return err; 2739 return err;
2713 2740
2714 /* The internal partition reset to user partition(0) at every CMD0*/ 2741 /* The internal partition reset to user partition(0) at every CMD0*/
2715 mmc_get_blk_desc(mmc)->hwpart = 0; 2742 mmc_get_blk_desc(mmc)->hwpart = 0;
2716 2743
2717 /* Test for SD version 2 */ 2744 /* Test for SD version 2 */
2718 err = mmc_send_if_cond(mmc); 2745 err = mmc_send_if_cond(mmc);
2719 2746
2720 /* Now try to get the SD card's operating condition */ 2747 /* Now try to get the SD card's operating condition */
2721 err = sd_send_op_cond(mmc, uhs_en); 2748 err = sd_send_op_cond(mmc, uhs_en);
2722 if (err && uhs_en) { 2749 if (err && uhs_en) {
2723 uhs_en = false; 2750 uhs_en = false;
2724 mmc_power_cycle(mmc); 2751 mmc_power_cycle(mmc);
2725 goto retry; 2752 goto retry;
2726 } 2753 }
2727 2754
2728 /* If the command timed out, we check for an MMC card */ 2755 /* If the command timed out, we check for an MMC card */
2729 if (err == -ETIMEDOUT) { 2756 if (err == -ETIMEDOUT) {
2730 err = mmc_send_op_cond(mmc); 2757 err = mmc_send_op_cond(mmc);
2731 2758
2732 if (err) { 2759 if (err) {
2733 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) 2760 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2734 pr_err("Card did not respond to voltage select!\n"); 2761 pr_err("Card did not respond to voltage select!\n");
2735 #endif 2762 #endif
2736 return -EOPNOTSUPP; 2763 return -EOPNOTSUPP;
2737 } 2764 }
2738 } 2765 }
2739 2766
2740 if (!err) 2767 if (!err)
2741 mmc->init_in_progress = 1; 2768 mmc->init_in_progress = 1;
2742 2769
2743 return err; 2770 return err;
2744 } 2771 }
2745 2772
2746 static int mmc_complete_init(struct mmc *mmc) 2773 static int mmc_complete_init(struct mmc *mmc)
2747 { 2774 {
2748 int err = 0; 2775 int err = 0;
2749 2776
2750 mmc->init_in_progress = 0; 2777 mmc->init_in_progress = 0;
2751 if (mmc->op_cond_pending) 2778 if (mmc->op_cond_pending)
2752 err = mmc_complete_op_cond(mmc); 2779 err = mmc_complete_op_cond(mmc);
2753 2780
2754 if (!err) 2781 if (!err)
2755 err = mmc_startup(mmc); 2782 err = mmc_startup(mmc);
2756 if (err) 2783 if (err)
2757 mmc->has_init = 0; 2784 mmc->has_init = 0;
2758 else 2785 else
2759 mmc->has_init = 1; 2786 mmc->has_init = 1;
2760 return err; 2787 return err;
2761 } 2788 }
2762 2789
2763 int mmc_init(struct mmc *mmc) 2790 int mmc_init(struct mmc *mmc)
2764 { 2791 {
2765 int err = 0; 2792 int err = 0;
2766 __maybe_unused unsigned start; 2793 __maybe_unused unsigned start;
2767 #if CONFIG_IS_ENABLED(DM_MMC) 2794 #if CONFIG_IS_ENABLED(DM_MMC)
2768 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev); 2795 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
2769 2796
2770 upriv->mmc = mmc; 2797 upriv->mmc = mmc;
2771 #endif 2798 #endif
2772 if (mmc->has_init) 2799 if (mmc->has_init)
2773 return 0; 2800 return 0;
2774 2801
2775 start = get_timer(0); 2802 start = get_timer(0);
2776 2803
2777 if (!mmc->init_in_progress) 2804 if (!mmc->init_in_progress)
2778 err = mmc_start_init(mmc); 2805 err = mmc_start_init(mmc);
2779 2806
2780 if (!err) 2807 if (!err)
2781 err = mmc_complete_init(mmc); 2808 err = mmc_complete_init(mmc);
2782 if (err) 2809 if (err)
2783 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start)); 2810 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
2784 2811
2785 return err; 2812 return err;
2786 } 2813 }
2787 2814
2788 int mmc_set_dsr(struct mmc *mmc, u16 val) 2815 int mmc_set_dsr(struct mmc *mmc, u16 val)
2789 { 2816 {
2790 mmc->dsr = val; 2817 mmc->dsr = val;
2791 return 0; 2818 return 0;
2792 } 2819 }
2793 2820
2794 /* CPU-specific MMC initializations */ 2821 /* CPU-specific MMC initializations */
2795 __weak int cpu_mmc_init(bd_t *bis) 2822 __weak int cpu_mmc_init(bd_t *bis)
2796 { 2823 {
2797 return -1; 2824 return -1;
2798 } 2825 }
2799 2826
2800 /* board-specific MMC initializations. */ 2827 /* board-specific MMC initializations. */
2801 __weak int board_mmc_init(bd_t *bis) 2828 __weak int board_mmc_init(bd_t *bis)
2802 { 2829 {
2803 return -1; 2830 return -1;
2804 } 2831 }
2805 2832
2806 void mmc_set_preinit(struct mmc *mmc, int preinit) 2833 void mmc_set_preinit(struct mmc *mmc, int preinit)
2807 { 2834 {
2808 mmc->preinit = preinit; 2835 mmc->preinit = preinit;
2809 } 2836 }
2810 2837
2811 #if CONFIG_IS_ENABLED(DM_MMC) 2838 #if CONFIG_IS_ENABLED(DM_MMC)
2812 static int mmc_probe(bd_t *bis) 2839 static int mmc_probe(bd_t *bis)
2813 { 2840 {
2814 int ret, i; 2841 int ret, i;
2815 struct uclass *uc; 2842 struct uclass *uc;
2816 struct udevice *dev; 2843 struct udevice *dev;
2817 2844
2818 ret = uclass_get(UCLASS_MMC, &uc); 2845 ret = uclass_get(UCLASS_MMC, &uc);
2819 if (ret) 2846 if (ret)
2820 return ret; 2847 return ret;
2821 2848
2822 /* 2849 /*
2823 * Try to add them in sequence order. Really with driver model we 2850 * Try to add them in sequence order. Really with driver model we
2824 * should allow holes, but the current MMC list does not allow that. 2851 * should allow holes, but the current MMC list does not allow that.
2825 * So if we request 0, 1, 3 we will get 0, 1, 2. 2852 * So if we request 0, 1, 3 we will get 0, 1, 2.
2826 */ 2853 */
2827 for (i = 0; ; i++) { 2854 for (i = 0; ; i++) {
2828 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev); 2855 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2829 if (ret == -ENODEV) 2856 if (ret == -ENODEV)
2830 break; 2857 break;
2831 } 2858 }
2832 uclass_foreach_dev(dev, uc) { 2859 uclass_foreach_dev(dev, uc) {
2833 ret = device_probe(dev); 2860 ret = device_probe(dev);
2834 if (ret) 2861 if (ret)
2835 pr_err("%s - probe failed: %d\n", dev->name, ret); 2862 pr_err("%s - probe failed: %d\n", dev->name, ret);
2836 } 2863 }
2837 2864
2838 return 0; 2865 return 0;
2839 } 2866 }
2840 #else 2867 #else
2841 static int mmc_probe(bd_t *bis) 2868 static int mmc_probe(bd_t *bis)
2842 { 2869 {
2843 if (board_mmc_init(bis) < 0) 2870 if (board_mmc_init(bis) < 0)
2844 cpu_mmc_init(bis); 2871 cpu_mmc_init(bis);
2845 2872
2846 return 0; 2873 return 0;
2847 } 2874 }
2848 #endif 2875 #endif
2849 2876
2850 int mmc_initialize(bd_t *bis) 2877 int mmc_initialize(bd_t *bis)
2851 { 2878 {
2852 static int initialized = 0; 2879 static int initialized = 0;
2853 int ret; 2880 int ret;
2854 if (initialized) /* Avoid initializing mmc multiple times */ 2881 if (initialized) /* Avoid initializing mmc multiple times */
2855 return 0; 2882 return 0;
2856 initialized = 1; 2883 initialized = 1;
2857 2884
2858 #if !CONFIG_IS_ENABLED(BLK) 2885 #if !CONFIG_IS_ENABLED(BLK)
2859 #if !CONFIG_IS_ENABLED(MMC_TINY) 2886 #if !CONFIG_IS_ENABLED(MMC_TINY)
2860 mmc_list_init(); 2887 mmc_list_init();
2861 #endif 2888 #endif
2862 #endif 2889 #endif
2863 ret = mmc_probe(bis); 2890 ret = mmc_probe(bis);
2864 if (ret) 2891 if (ret)
2865 return ret; 2892 return ret;
2866 2893
2867 #ifndef CONFIG_SPL_BUILD 2894 #ifndef CONFIG_SPL_BUILD
2868 print_mmc_devices(','); 2895 print_mmc_devices(',');
2869 #endif 2896 #endif
2870 2897
2871 mmc_do_preinit(); 2898 mmc_do_preinit();
2872 return 0; 2899 return 0;
2873 } 2900 }
2874 2901
2875 #ifdef CONFIG_CMD_BKOPS_ENABLE 2902 #ifdef CONFIG_CMD_BKOPS_ENABLE
2876 int mmc_set_bkops_enable(struct mmc *mmc) 2903 int mmc_set_bkops_enable(struct mmc *mmc)
2877 { 2904 {
2878 int err; 2905 int err;
2879 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); 2906 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2880 2907
2881 err = mmc_send_ext_csd(mmc, ext_csd); 2908 err = mmc_send_ext_csd(mmc, ext_csd);
2882 if (err) { 2909 if (err) {
2883 puts("Could not get ext_csd register values\n"); 2910 puts("Could not get ext_csd register values\n");
2884 return err; 2911 return err;
2885 } 2912 }
2886 2913
2887 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) { 2914 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2888 puts("Background operations not supported on device\n"); 2915 puts("Background operations not supported on device\n");
2889 return -EMEDIUMTYPE; 2916 return -EMEDIUMTYPE;
2890 } 2917 }
2891 2918
2892 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) { 2919 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2893 puts("Background operations already enabled\n"); 2920 puts("Background operations already enabled\n");
2894 return 0; 2921 return 0;
2895 } 2922 }
2896 2923
2897 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1); 2924 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2898 if (err) { 2925 if (err) {
2899 puts("Failed to enable manual background operations\n"); 2926 puts("Failed to enable manual background operations\n");
2900 return err; 2927 return err;
2901 } 2928 }
2902 2929
2903 puts("Enabled manual background operations\n"); 2930 puts("Enabled manual background operations\n");
2904 2931
2905 return 0; 2932 return 0;
2906 } 2933 }
2907 #endif 2934 #endif
2908 2935