board/t208xrdb: Add support of 2-stage NAND/SPI/SD boot

Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>

board/t208xrdb: Add support of 2-stage NAND/SPI/SD boot
Add support of 2-stage NAND/SPI/SD boot loader using SPL framework. PBL initializes the internal CPC-SRAM and copy SPL(160K) to it, SPL further initializes DDR using SPD and environment and copy u-boot(768K) from SPI/SD/NAND to DDR, finally SPL transfers control to u-boot. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Shengzhou Liu · York Sun
1 parent b19e288f47
Showing 7 changed files with 282 additions and 36 deletions Side-by-side Diff
board/freescale/t208xrdb/Makefile
board/freescale/t208xrdb/README
board/freescale/t208xrdb/ddr.c
board/freescale/t208xrdb/spl.c
board/freescale/t208xrdb/tlb.c
boards.cfg
include/configs/T208xRDB.h
@@ -4,10 +4,15 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
  
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
 obj-$(CONFIG_T2080RDB) += t208xrdb.o
 obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
 obj-$(CONFIG_T2080RDB) += cpld.o
 obj-$(CONFIG_PCI)      += pci.o
+endif
+
 obj-y   += ddr.o
 obj-y   += law.o
 obj-y   += tlb.o
@@ -120,7 +120,7 @@
 0xEBF00000	0xEBF1FFFF	FMAN ucode (alt bank)		128KB
 0xEBE00000	0xEBE3FFFF	PHY CS4315 firmware (alt bank)	256KB
 0xE9300000	0xEBEFFFFF	rootfs (current bank)		44MB
-0xE8800000	0xE88FFFFF	Hardware device tree (cur bank)	11MB + 512KB
+0xE8800000	0xE88FFFFF	Hardware device tree (cur bank)	1MB
 0xE8020000	0xE86FFFFF	Linux.uImage (current bank)	7MB + 875KB
 0xE8000000	0xE801FFFF	RCW (current bank)		128KB
  
@@ -146,7 +146,8 @@
 ------------------------------------------
 1. NOR boot:
    a. build NOR boot image
-	$ make T2080RDB
+	$ make T2080RDB_config
+	$ make
    b. program u-boot.bin image to NOR flash
 	=> tftp 1000000 u-boot.bin
 	=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
@@ -164,9 +165,9 @@
 2. NAND Boot:
    a. build PBL image for NAND boot
 	$ make T2080RDB_NAND_config
-	$ make u-boot.pbl
-   b. program u-boot.pbl to NAND flash
-	=> tftp 1000000 u-boot.pbl
+	$ make
+   b. program u-boot-with-spl-pbl.bin to NAND flash
+	=> tftp 1000000 u-boot-with-spl-pbl.bin
 	=> nand erase 0 d0000
 	=> nand write 1000000 0 $filesize
 	set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
@@ -174,9 +175,9 @@
 3. SPI Boot:
    a. build PBL image for SPI boot
 	$ make T2080RDB_SPIFLASH_config
-	$ make u-boot.pbl
-   b. program u-boot.pbl to SPI flash
-	=> tftp 1000000 u-boot.pbl
+	$ make
+   b. program u-boot-with-spl-pbl.bin to SPI flash
+	=> tftp 1000000 u-boot-with-spl-pbl.bin
 	=> sf probe 0
 	=> sf erase 0 d0000
 	=> sf write 1000000 0 $filesize
  
@@ -185,11 +186,66 @@
 4. SD Boot:
    a. build PBL image for SD boot
 	$ make T2080RDB_SDCARD_config
-	$ make u-boot.pbl
-   b. program u-boot.pbl to TF card
-	=> tftp 1000000 u-boot.pbl
-	=> mmc write 1000000 8 1650
+	$ make
+   b. program u-boot-with-spl-pbl.bin to micro-SD/TF card
+	=> tftp 1000000 u-boot-with-spl-pbl.bin
+	=> mmc write 1000000 8 0x800
 	set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
+
+
+2-stage NAND/SPI/SD boot loader
+-------------------------------
+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
+SPL further initializes DDR using SPD and environment variables
+and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
+Finally SPL transers control to u-boot for futher booting.
+
+SPL has following features:
+ - Executes within 256K
+ - No relocation required
+
+Run time view of SPL framework
+-------------------------------------------------
+|Area		   | Address			|
+-------------------------------------------------
+|SecureBoot header | 0xFFFC0000 (32KB)		|
+-------------------------------------------------
+|GD, BD		   | 0xFFFC8000 (4KB)		|
+-------------------------------------------------
+|ENV		   | 0xFFFC9000 (8KB)		|
+-------------------------------------------------
+|HEAP		   | 0xFFFCB000 (50KB)		|
+-------------------------------------------------
+|STACK		   | 0xFFFD8000 (22KB)		|
+-------------------------------------------------
+|U-boot SPL	   | 0xFFFD8000 (160KB)		|
+-------------------------------------------------
+
+NAND Flash memory Map on T2080RDB
+--------------------------------------------------------------
+Start		End		Definition	Size
+0x000000	0x0FFFFF	u-boot img	1MB  (2 blocks)
+0x100000	0x17FFFF	u-boot env	512KB (1 block)
+0x180000	0x1FFFFF	FMAN ucode	512KB (1 block)
+0x200000	0x27FFFF	CS4315 ucode	512KB (1 block)
+
+
+Micro SD Card memory Map on T2080RDB
+----------------------------------------------------
+Block		#blocks		Definition	Size
+0x008		2048		u-boot img	1MB
+0x800		0016		u-boot env	8KB
+0x820		0128		FMAN ucode	64KB
+0x8a0		0512		CS4315 ucode	256KB
+
+
+SPI Flash memory Map on T2080RDB
+----------------------------------------------------
+Start		End		Definition	Size
+0x000000	0x0FFFFF	u-boot img	1MB
+0x100000	0x101FFF	u-boot env	8KB
+0x110000	0x11FFFF	FMAN ucode	64KB
+0x120000        0x15FFFF        CS4315 ucode	256KB
  
  
 How to update the ucode of Cortina CS4315/CS4340 10G PHY
@@ -100,14 +100,16 @@
 {
 	phys_size_t dram_size;
  
+#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
 	puts("Initializing....using SPD\n");
-
 	dram_size = fsl_ddr_sdram();
  
 	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 	dram_size *= 0x100000;
-
-	puts("    DDR: ");
+#else
+	/* DDR has been initialised by first stage boot loader */
+	dram_size = fsl_ddr_sdram_size();
+#endif
 	return dram_size;
 }
+/* Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <i2c.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <spi_flash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t get_effective_memsize(void)
+{
+	return CONFIG_SYS_L3_SIZE;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	return CONFIG_SYS_CLK_FREQ;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	return CONFIG_DDR_CLK_FREQ;
+}
+
+void board_init_f(ulong bootflag)
+{
+	u32 plat_ratio, sys_clk, ccb_clk;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+	/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
+	memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
+
+	/* Update GD pointer */
+	gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
+
+	console_init_f();
+
+	/* initialize selected port with appropriate baud rate */
+	sys_clk = get_board_sys_clk();
+	plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
+	ccb_clk = sys_clk * plat_ratio / 2;
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+		     ccb_clk / 16 / CONFIG_BAUDRATE);
+
+#if defined(CONFIG_SPL_MMC_BOOT)
+	puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	puts("\nSPI boot...\n");
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	puts("\nNAND boot...\n");
+#endif
+
+	relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	bd_t *bd;
+
+	bd = (bd_t *)(gd + sizeof(gd_t));
+	memset(bd, 0, sizeof(bd_t));
+	gd->bd = bd;
+	bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
+	bd->bi_memsize = CONFIG_SYS_L3_SIZE;
+
+	probecpu();
+	get_clocks();
+	mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
+			CONFIG_SPL_RELOC_MALLOC_SIZE);
+
+#ifdef CONFIG_SPL_NAND_BOOT
+	nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			    (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_initialize(bd);
+	mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)CONFIG_ENV_ADDR);
+#endif
+#ifdef CONFIG_SPL_SPI_BOOT
+	spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+			   (uchar *)CONFIG_ENV_ADDR);
+#endif
+
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+
+	i2c_init_all();
+
+	gd->ram_size = initdram(0);
+
+#ifdef CONFIG_SPL_MMC_BOOT
+	mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+	spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+	nand_boot();
+#endif
+}
@@ -65,6 +65,7 @@
 		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
  
+#ifndef CONFIG_SPL_BUILD
 	/* *I*G* - PCIe 1, 0x80000000 */
 	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -110,6 +111,7 @@
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 12, BOOKE_PAGESZ_16M, 1),
 #endif
+#endif
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -140,7 +142,7 @@
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 		      0, 18, BOOKE_PAGESZ_1M, 1),
 #endif
-#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
 	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 19, BOOKE_PAGESZ_2G, 1)
@@ -965,9 +965,9 @@
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SPIFLASH                    T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH                                                                                           -
 Active  powerpc     mpc85xx        -           freescale       t208xqds            T2081QDS_SRIO_PCIE_BOOT              T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB                             T208xRDB:PPC_T2080                                                                                                                -
-Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_NAND                        T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
-Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SDCARD                      T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000                                                                    -
-Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SPIFLASH                    T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_NAND                        T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SDCARD                      T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
+Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SPIFLASH                    T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH
 Active  powerpc     mpc85xx        -           freescale       t208xrdb            T2080RDB_SRIO_PCIE_BOOT              T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS                             T4240QDS:PPC_T4160                                                                                                                -
 Active  powerpc     mpc85xx        -           freescale       t4qds               T4160QDS_SECURE_BOOT                 T4240QDS:PPC_T4160,SECURE_BOOT                                                                                                    Aneesh Bansal <aneesh.bansal@freescale.com>
@@ -39,12 +39,76 @@
 #define CONFIG_ENV_OVERWRITE
  
 #ifdef CONFIG_RAMBOOT_PBL
-#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
-#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
+
+#define CONFIG_SPL
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_FLUSH_IMAGE
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+#define CONFIG_SYS_TEXT_BASE		0x00201000
+#define CONFIG_SPL_TEXT_BASE		0xFFFD8000
+#define CONFIG_SPL_PAD_TO		0x40000
+#define CONFIG_SPL_MAX_SIZE		0x28000
+#define RESET_VECTOR_OFFSET		0x27FFC
+#define BOOT_PAGE_OFFSET		0x27000
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_SKIP_RELOCATE
+#define CONFIG_SPL_COMMON_INIT_DDR
+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
+#define CONFIG_SYS_NO_FLASH
 #endif
  
+#ifdef CONFIG_NAND
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(768 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_START	0x00200000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(256 << 10)
+#define CONFIG_SYS_LDSCRIPT  "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
+#define CONFIG_SPL_NAND_BOOT
+#endif
+
+#ifdef CONFIG_SPIFLASH
+#define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_MINIMAL
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE       (768 << 10)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST                (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START      (0x00200000)
+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS       (256 << 10)
+#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_SPI_BOOT
+#endif
+
+#ifdef CONFIG_SDCARD
+#define        CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_MMC_MINIMAL
+#define CONFIG_SYS_MMC_U_BOOT_SIZE     (768 << 10)
+#define CONFIG_SYS_MMC_U_BOOT_DST      (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_START    (0x00200000)
+#define CONFIG_SYS_MMC_U_BOOT_OFFS     (260 << 10)
+#define CONFIG_SYS_LDSCRIPT    "arch/powerpc/cpu/mpc85xx/u-boot.lds"
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
+#endif
+#define CONFIG_SPL_MMC_BOOT
+#endif
+
+#endif /* CONFIG_RAMBOOT_PBL */
+
 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 /* Set 1M boot space */
@@ -74,11 +138,7 @@
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif
  
-#ifdef CONFIG_SYS_NO_FLASH
-#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
-#define CONFIG_ENV_IS_NOWHERE
-#endif
-#else
+#ifndef CONFIG_SYS_NO_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  
@@ -99,11 +159,11 @@
 #define CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV	0
 #define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_OFFSET	(512 * 1658)
+#define CONFIG_ENV_OFFSET	(512 * 0x800)
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_EXTRA_ENV_RELOC
 #define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_SIZE		0x2000
 #define CONFIG_ENV_OFFSET	(2 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 #define CONFIG_ENV_IS_IN_REMOTE
@@ -129,7 +189,16 @@
 /*
  * Config the L3 Cache as L3 SRAM
  */
-#define CONFIG_SYS_INIT_L3_ADDR	 CONFIG_RAMBOOT_TEXT_BASE
+#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
+#define CONFIG_SYS_L3_SIZE		(512 << 10)
+#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
+#endif
+#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
+#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
+#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
+#define CONFIG_SPL_RELOC_STACK_SIZE	(22 << 10)
  
 #define CONFIG_SYS_DCSRBAR	0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS	0xf00000000ull
@@ -301,7 +370,12 @@
 #define CONFIG_SYS_RAMBOOT
 #endif
  
-#define CONFIG_SYS_MONITOR_BASE	 CONFIG_SYS_TEXT_BASE
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE  CONFIG_SPL_TEXT_BASE
+#else
+#define CONFIG_SYS_MONITOR_BASE  CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
+
 #define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
 #define CONFIG_MISC_INIT_R
 #define CONFIG_HWCONFIG
  
  
@@ -516,17 +590,17 @@
 #elif defined(CONFIG_SDCARD)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
-#define CONFIG_SYS_FMAN_FW_ADDR	(512 * 1680)
-#define CONFIG_CORTINA_FW_ADDR		(512 * 1808)
+#define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x820)
+#define CONFIG_CORTINA_FW_ADDR		(512 * 0x8a0)
  
 #elif defined(CONFIG_NAND)
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_CORTINA_FW_ADDR		(7 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_FMAN_FW_ADDR		(3 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_CORTINA_FW_ADDR		(4 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 /*
  * Slave has no ucode locally, it can fetch this from remote. When implementing
...	...	@@ -4,10 +4,15 @@
4	4	# SPDX-License-Identifier: GPL-2.0+
5	5	#
6	6
	7	+ifdef CONFIG_SPL_BUILD
	8	+obj-y += spl.o
	9	+else
7	10	obj-$(CONFIG_T2080RDB) += t208xrdb.o
8	11	obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o
9	12	obj-$(CONFIG_T2080RDB) += cpld.o
10	13	obj-$(CONFIG_PCI) += pci.o
	14	+endif
	15	+
11	16	obj-y += ddr.o
12	17	obj-y += law.o
13	18	obj-y += tlb.o
...	...	@@ -120,7 +120,7 @@
120	120	0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
121	121	0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alt bank) 256KB
122	122	0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
123		-0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
	123	+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
124	124	0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
125	125	0xE8000000 0xE801FFFF RCW (current bank) 128KB
126	126
...	...	@@ -146,7 +146,8 @@
146	146	------------------------------------------
147	147	1. NOR boot:
148	148	a. build NOR boot image
149		- $ make T2080RDB
	149	+ $ make T2080RDB_config
	150	+ $ make
150	151	b. program u-boot.bin image to NOR flash
151	152	=> tftp 1000000 u-boot.bin
152	153	=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
...	...	@@ -164,9 +165,9 @@
164	165	2. NAND Boot:
165	166	a. build PBL image for NAND boot
166	167	$ make T2080RDB_NAND_config
167		- $ make u-boot.pbl
168		- b. program u-boot.pbl to NAND flash
169		- => tftp 1000000 u-boot.pbl
	168	+ $ make
	169	+ b. program u-boot-with-spl-pbl.bin to NAND flash
	170	+ => tftp 1000000 u-boot-with-spl-pbl.bin
170	171	=> nand erase 0 d0000
171	172	=> nand write 1000000 0 $filesize
172	173	set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
...	...	@@ -174,9 +175,9 @@
174	175	3. SPI Boot:
175	176	a. build PBL image for SPI boot
176	177	$ make T2080RDB_SPIFLASH_config
177		- $ make u-boot.pbl
178		- b. program u-boot.pbl to SPI flash
179		- => tftp 1000000 u-boot.pbl
	178	+ $ make
	179	+ b. program u-boot-with-spl-pbl.bin to SPI flash
	180	+ => tftp 1000000 u-boot-with-spl-pbl.bin
180	181	=> sf probe 0
181	182	=> sf erase 0 d0000
182	183	=> sf write 1000000 0 $filesize
183	184
...	...	@@ -185,11 +186,66 @@
185	186	4. SD Boot:
186	187	a. build PBL image for SD boot
187	188	$ make T2080RDB_SDCARD_config
188		- $ make u-boot.pbl
189		- b. program u-boot.pbl to TF card
190		- => tftp 1000000 u-boot.pbl
191		- => mmc write 1000000 8 1650
	189	+ $ make
	190	+ b. program u-boot-with-spl-pbl.bin to micro-SD/TF card
	191	+ => tftp 1000000 u-boot-with-spl-pbl.bin
	192	+ => mmc write 1000000 8 0x800
192	193	set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
	194	+
	195	+
	196	+2-stage NAND/SPI/SD boot loader
	197	+-------------------------------
	198	+PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
	199	+SPL further initializes DDR using SPD and environment variables
	200	+and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
	201	+Finally SPL transers control to u-boot for futher booting.
	202	+
	203	+SPL has following features:
	204	+ - Executes within 256K
	205	+ - No relocation required
	206	+
	207	+Run time view of SPL framework
	208	+-------------------------------------------------
	209	+\|Area \| Address \|
	210	+-------------------------------------------------
	211	+\|SecureBoot header \| 0xFFFC0000 (32KB) \|
	212	+-------------------------------------------------
	213	+\|GD, BD \| 0xFFFC8000 (4KB) \|
	214	+-------------------------------------------------
	215	+\|ENV \| 0xFFFC9000 (8KB) \|
	216	+-------------------------------------------------
	217	+\|HEAP \| 0xFFFCB000 (50KB) \|
	218	+-------------------------------------------------
	219	+\|STACK \| 0xFFFD8000 (22KB) \|
	220	+-------------------------------------------------
	221	+\|U-boot SPL \| 0xFFFD8000 (160KB) \|
	222	+-------------------------------------------------
	223	+
	224	+NAND Flash memory Map on T2080RDB
	225	+--------------------------------------------------------------
	226	+Start End Definition Size
	227	+0x000000 0x0FFFFF u-boot img 1MB (2 blocks)
	228	+0x100000 0x17FFFF u-boot env 512KB (1 block)
	229	+0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
	230	+0x200000 0x27FFFF CS4315 ucode 512KB (1 block)
	231	+
	232	+
	233	+Micro SD Card memory Map on T2080RDB
	234	+----------------------------------------------------
	235	+Block #blocks Definition Size
	236	+0x008 2048 u-boot img 1MB
	237	+0x800 0016 u-boot env 8KB
	238	+0x820 0128 FMAN ucode 64KB
	239	+0x8a0 0512 CS4315 ucode 256KB
	240	+
	241	+
	242	+SPI Flash memory Map on T2080RDB
	243	+----------------------------------------------------
	244	+Start End Definition Size
	245	+0x000000 0x0FFFFF u-boot img 1MB
	246	+0x100000 0x101FFF u-boot env 8KB
	247	+0x110000 0x11FFFF FMAN ucode 64KB
	248	+0x120000 0x15FFFF CS4315 ucode 256KB
193	249
194	250
195	251	How to update the ucode of Cortina CS4315/CS4340 10G PHY
...	...	@@ -100,14 +100,16 @@
100	100	{
101	101	phys_size_t dram_size;
102	102
	103	+#if defined(CONFIG_SPL_BUILD) \|\| !defined(CONFIG_RAMBOOT_PBL)
103	104	puts("Initializing....using SPD\n");
104		-
105	105	dram_size = fsl_ddr_sdram();
106	106
107	107	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
108	108	dram_size *= 0x100000;
109		-
110		- puts(" DDR: ");
	109	+#else
	110	+ /* DDR has been initialised by first stage boot loader */
	111	+ dram_size = fsl_ddr_sdram_size();
	112	+#endif
111	113	return dram_size;
112	114	}
	1	+/* Copyright 2013 Freescale Semiconductor, Inc.
	2	+ *
	3	+ * SPDX-License-Identifier: GPL-2.0+
	4	+ */
	5	+
	6	+#include <common.h>
	7	+#include <malloc.h>
	8	+#include <ns16550.h>
	9	+#include <nand.h>
	10	+#include <i2c.h>
	11	+#include <mmc.h>
	12	+#include <fsl_esdhc.h>
	13	+#include <spi_flash.h>
	14	+
	15	+DECLARE_GLOBAL_DATA_PTR;
	16	+
	17	+phys_size_t get_effective_memsize(void)
	18	+{
	19	+ return CONFIG_SYS_L3_SIZE;
	20	+}
	21	+
	22	+unsigned long get_board_sys_clk(void)
	23	+{
	24	+ return CONFIG_SYS_CLK_FREQ;
	25	+}
	26	+
	27	+unsigned long get_board_ddr_clk(void)
	28	+{
	29	+ return CONFIG_DDR_CLK_FREQ;
	30	+}
	31	+
	32	+void board_init_f(ulong bootflag)
	33	+{
	34	+ u32 plat_ratio, sys_clk, ccb_clk;
	35	+ ccsr_gur_t gur = (void )CONFIG_SYS_MPC85xx_GUTS_ADDR;
	36	+
	37	+ /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
	38	+ memcpy((void )CONFIG_SPL_GD_ADDR, (void )gd, sizeof(gd_t));
	39	+
	40	+ /* Update GD pointer */
	41	+ gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
	42	+
	43	+ console_init_f();
	44	+
	45	+ /* initialize selected port with appropriate baud rate */
	46	+ sys_clk = get_board_sys_clk();
	47	+ plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
	48	+ ccb_clk = sys_clk * plat_ratio / 2;
	49	+
	50	+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
	51	+ ccb_clk / 16 / CONFIG_BAUDRATE);
	52	+
	53	+#if defined(CONFIG_SPL_MMC_BOOT)
	54	+ puts("\nSD boot...\n");
	55	+#elif defined(CONFIG_SPL_SPI_BOOT)
	56	+ puts("\nSPI boot...\n");
	57	+#elif defined(CONFIG_SPL_NAND_BOOT)
	58	+ puts("\nNAND boot...\n");
	59	+#endif
	60	+
	61	+ relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
	62	+}
	63	+
	64	+void board_init_r(gd_t *gd, ulong dest_addr)
	65	+{
	66	+ bd_t *bd;
	67	+
	68	+ bd = (bd_t *)(gd + sizeof(gd_t));
	69	+ memset(bd, 0, sizeof(bd_t));
	70	+ gd->bd = bd;
	71	+ bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
	72	+ bd->bi_memsize = CONFIG_SYS_L3_SIZE;
	73	+
	74	+ probecpu();
	75	+ get_clocks();
	76	+ mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
	77	+ CONFIG_SPL_RELOC_MALLOC_SIZE);
	78	+
	79	+#ifdef CONFIG_SPL_NAND_BOOT
	80	+ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	81	+ (uchar *)CONFIG_ENV_ADDR);
	82	+#endif
	83	+#ifdef CONFIG_SPL_MMC_BOOT
	84	+ mmc_initialize(bd);
	85	+ mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	86	+ (uchar *)CONFIG_ENV_ADDR);
	87	+#endif
	88	+#ifdef CONFIG_SPL_SPI_BOOT
	89	+ spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
	90	+ (uchar *)CONFIG_ENV_ADDR);
	91	+#endif
	92	+
	93	+ gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
	94	+ gd->env_valid = 1;
	95	+
	96	+ i2c_init_all();
	97	+
	98	+ gd->ram_size = initdram(0);
	99	+
	100	+#ifdef CONFIG_SPL_MMC_BOOT
	101	+ mmc_boot();
	102	+#elif defined(CONFIG_SPL_SPI_BOOT)
	103	+ spi_boot();
	104	+#elif defined(CONFIG_SPL_NAND_BOOT)
	105	+ nand_boot();
	106	+#endif
	107	+}
...	...	@@ -65,6 +65,7 @@
65	65	MAS3_SX\|MAS3_SR, MAS2_W\|MAS2_G,
66	66	0, 2, BOOKE_PAGESZ_256M, 1),
67	67
	68	+#ifndef CONFIG_SPL_BUILD
68	69	/* IG* - PCIe 1, 0x80000000 */
69	70	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
70	71	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
...	...	@@ -110,6 +111,7 @@
110	111	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
111	112	0, 12, BOOKE_PAGESZ_16M, 1),
112	113	#endif
	114	+#endif
113	115	#ifdef CONFIG_SYS_DCSRBAR_PHYS
114	116	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
115	117	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
...	...	@@ -140,7 +142,7 @@
140	142	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_G,
141	143	0, 18, BOOKE_PAGESZ_1M, 1),
142	144	#endif
143		-#if defined(CONFIG_SYS_RAMBOOT)
	145	+#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
144	146	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
145	147	MAS3_SX\|MAS3_SW\|MAS3_SR, 0,
146	148	0, 19, BOOKE_PAGESZ_2G, 1)
...	...	@@ -965,9 +965,9 @@
965	965	Active powerpc mpc85xx - freescale t208xqds T2081QDS_SPIFLASH T208xQDS:PPC_T2081,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH -
966	966	Active powerpc mpc85xx - freescale t208xqds T2081QDS_SRIO_PCIE_BOOT T208xQDS:PPC_T2081,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
967	967	Active powerpc mpc85xx - freescale t208xrdb T2080RDB T208xRDB:PPC_T2080 -
968		-Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 -
969		-Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
970		-Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
	968	+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_NAND T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,NAND
	969	+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SDCARD T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD
	970	+Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SPIFLASH T208xRDB:PPC_T2080,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH
971	971	Active powerpc mpc85xx - freescale t208xrdb T2080RDB_SRIO_PCIE_BOOT T208xRDB:PPC_T2080,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 -
972	972	Active powerpc mpc85xx - freescale t4qds T4160QDS T4240QDS:PPC_T4160 -
973	973	Active powerpc mpc85xx - freescale t4qds T4160QDS_SECURE_BOOT T4240QDS:PPC_T4160,SECURE_BOOT Aneesh Bansal <aneesh.bansal@freescale.com>
...	...	@@ -39,12 +39,76 @@
39	39	#define CONFIG_ENV_OVERWRITE
40	40
41	41	#ifdef CONFIG_RAMBOOT_PBL
42		-#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
43		-#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
44	42	#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
45	43	#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_rcw.cfg
	44	+
	45	+#define CONFIG_SPL
	46	+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
	47	+#define CONFIG_SPL_ENV_SUPPORT
	48	+#define CONFIG_SPL_SERIAL_SUPPORT
	49	+#define CONFIG_SPL_FLUSH_IMAGE
	50	+#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
	51	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	52	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	53	+#define CONFIG_SPL_I2C_SUPPORT
	54	+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
	55	+#define CONFIG_FSL_LAW /* Use common FSL init code */
	56	+#define CONFIG_SYS_TEXT_BASE 0x00201000
	57	+#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
	58	+#define CONFIG_SPL_PAD_TO 0x40000
	59	+#define CONFIG_SPL_MAX_SIZE 0x28000
	60	+#define RESET_VECTOR_OFFSET 0x27FFC
	61	+#define BOOT_PAGE_OFFSET 0x27000
	62	+#ifdef CONFIG_SPL_BUILD
	63	+#define CONFIG_SPL_SKIP_RELOCATE
	64	+#define CONFIG_SPL_COMMON_INIT_DDR
	65	+#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
	66	+#define CONFIG_SYS_NO_FLASH
46	67	#endif
47	68
	69	+#ifdef CONFIG_NAND
	70	+#define CONFIG_SPL_NAND_SUPPORT
	71	+#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
	72	+#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
	73	+#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
	74	+#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
	75	+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
	76	+#define CONFIG_SPL_NAND_BOOT
	77	+#endif
	78	+
	79	+#ifdef CONFIG_SPIFLASH
	80	+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
	81	+#define CONFIG_SPL_SPI_SUPPORT
	82	+#define CONFIG_SPL_SPI_FLASH_SUPPORT
	83	+#define CONFIG_SPL_SPI_FLASH_MINIMAL
	84	+#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
	85	+#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
	86	+#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
	87	+#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
	88	+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
	89	+#ifndef CONFIG_SPL_BUILD
	90	+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	91	+#endif
	92	+#define CONFIG_SPL_SPI_BOOT
	93	+#endif
	94	+
	95	+#ifdef CONFIG_SDCARD
	96	+#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
	97	+#define CONFIG_SPL_MMC_SUPPORT
	98	+#define CONFIG_SPL_MMC_MINIMAL
	99	+#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
	100	+#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
	101	+#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
	102	+#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
	103	+#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
	104	+#ifndef CONFIG_SPL_BUILD
	105	+#define CONFIG_SYS_MPC85XX_NO_RESETVEC
	106	+#endif
	107	+#define CONFIG_SPL_MMC_BOOT
	108	+#endif
	109	+
	110	+#endif /* CONFIG_RAMBOOT_PBL */
	111	+
48	112	#define CONFIG_SRIO_PCIE_BOOT_MASTER
49	113	#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
50	114	/* Set 1M boot space */
...	...	@@ -74,11 +138,7 @@
74	138	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
75	139	#endif
76	140
77		-#ifdef CONFIG_SYS_NO_FLASH
78		-#if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
79		-#define CONFIG_ENV_IS_NOWHERE
80		-#endif
81		-#else
	141	+#ifndef CONFIG_SYS_NO_FLASH
82	142	#define CONFIG_FLASH_CFI_DRIVER
83	143	#define CONFIG_SYS_FLASH_CFI
84	144	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
85	145
...	...	@@ -99,11 +159,11 @@
99	159	#define CONFIG_ENV_IS_IN_MMC
100	160	#define CONFIG_SYS_MMC_ENV_DEV 0
101	161	#define CONFIG_ENV_SIZE 0x2000
102		-#define CONFIG_ENV_OFFSET (512 * 1658)
	162	+#define CONFIG_ENV_OFFSET (512 * 0x800)
103	163	#elif defined(CONFIG_NAND)
104	164	#define CONFIG_SYS_EXTRA_ENV_RELOC
105	165	#define CONFIG_ENV_IS_IN_NAND
106		-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
	166	+#define CONFIG_ENV_SIZE 0x2000
107	167	#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
108	168	#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
109	169	#define CONFIG_ENV_IS_IN_REMOTE
...	...	@@ -129,7 +189,16 @@
129	189	/*
130	190	* Config the L3 Cache as L3 SRAM
131	191	*/
132		-#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
	192	+#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
	193	+#define CONFIG_SYS_L3_SIZE (512 << 10)
	194	+#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
	195	+#ifdef CONFIG_RAMBOOT_PBL
	196	+#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
	197	+#endif
	198	+#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
	199	+#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
	200	+#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
	201	+#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
133	202
134	203	#define CONFIG_SYS_DCSRBAR 0xf0000000
135	204	#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
...	...	@@ -301,7 +370,12 @@
301	370	#define CONFIG_SYS_RAMBOOT
302	371	#endif
303	372
304		-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	373	+#ifdef CONFIG_SPL_BUILD
	374	+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	375	+#else
	376	+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	377	+#endif
	378	+
305	379	#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
306	380	#define CONFIG_MISC_INIT_R
307	381	#define CONFIG_HWCONFIG
308	382
309	383
...	...	@@ -516,17 +590,17 @@
516	590	#elif defined(CONFIG_SDCARD)
517	591	/*
518	592	* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
519		- * about 825KB (1650 blocks), Env is stored after the image, and the env size is
520		- * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
	593	+ * about 1MB (2048 blocks), Env is stored after the image, and the env size is
	594	+ * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
521	595	*/
522	596	#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
523		-#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
524		-#define CONFIG_CORTINA_FW_ADDR (512 * 1808)
	597	+#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
	598	+#define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
525	599
526	600	#elif defined(CONFIG_NAND)
527	601	#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
528		-#define CONFIG_SYS_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
529		-#define CONFIG_CORTINA_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
	602	+#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
	603	+#define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
530	604	#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
531	605	/*
532	606	* Slave has no ucode locally, it can fetch this from remote. When implementing