Commit 4dfff1b1666b8b1d589b2aebb356cc61bd335c62
1 parent
0044258713
Make changes for hw revision 00D0 of SMARC-iMX8M
Showing 2 changed files with 15 additions and 8 deletions Inline Diff
arch/arm/dts/fsl-smarcimx8mq.dts
| 1 | /* | 1 | /* |
| 2 | * Copyright (C) 2016 Freescale Semiconductor, Inc. | 2 | * Copyright (C) 2016 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2017 NXP | 3 | * Copyright 2017 NXP |
| 4 | * | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or | 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License | 6 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version 2 | 7 | * as published by the Free Software Foundation; either version 2 |
| 8 | * of the License, or (at your option) any later version. | 8 | * of the License, or (at your option) any later version. |
| 9 | * | 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, | 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. | 13 | * GNU General Public License for more details. |
| 14 | */ | 14 | */ |
| 15 | 15 | ||
| 16 | /dts-v1/; | 16 | /dts-v1/; |
| 17 | 17 | ||
| 18 | /* First 128KB is for PSCI ATF. */ | 18 | /* First 128KB is for PSCI ATF. */ |
| 19 | /memreserve/ 0x40000000 0x00020000; | 19 | /memreserve/ 0x40000000 0x00020000; |
| 20 | 20 | ||
| 21 | #include "fsl-imx8mq.dtsi" | 21 | #include "fsl-imx8mq.dtsi" |
| 22 | 22 | ||
| 23 | / { | 23 | / { |
| 24 | model = "Embedian SMARC-iMX8M Computer on Module"; | 24 | model = "Embedian SMARC-iMX8M Computer on Module"; |
| 25 | compatible = "embedian,imx8mq-smarcimx8m", "fsl,imx8mq"; | 25 | compatible = "embedian,imx8mq-smarcimx8m", "fsl,imx8mq"; |
| 26 | 26 | ||
| 27 | regulators { | 27 | regulators { |
| 28 | compatible = "simple-bus"; | 28 | compatible = "simple-bus"; |
| 29 | #address-cells = <1>; | 29 | #address-cells = <1>; |
| 30 | #size-cells = <0>; | 30 | #size-cells = <0>; |
| 31 | 31 | ||
| 32 | reg_usdhc2_vmmc: usdhc2_vmmc { | 32 | reg_usdhc2_vmmc: usdhc2_vmmc { |
| 33 | compatible = "regulator-fixed"; | 33 | compatible = "regulator-fixed"; |
| 34 | regulator-name = "VSD_3V3"; | 34 | regulator-name = "VSD_3V3"; |
| 35 | regulator-min-microvolt = <3300000>; | 35 | regulator-min-microvolt = <3300000>; |
| 36 | regulator-max-microvolt = <3300000>; | 36 | regulator-max-microvolt = <3300000>; |
| 37 | gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; | 37 | gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; |
| 38 | enable-active-high; | 38 | enable-active-high; |
| 39 | }; | 39 | }; |
| 40 | }; | 40 | }; |
| 41 | 41 | ||
| 42 | backlight: backlight { | 42 | backlight: backlight { |
| 43 | compatible = "pwm-backlight"; | 43 | compatible = "pwm-backlight"; |
| 44 | pwms = <&pwm1 0 1000000 0>; | 44 | pwms = <&pwm1 0 1000000 0>; |
| 45 | brightness-levels = < 0 1 2 3 4 5 6 7 8 9 | 45 | brightness-levels = < 0 1 2 3 4 5 6 7 8 9 |
| 46 | 10 11 12 13 14 15 16 17 18 19 | 46 | 10 11 12 13 14 15 16 17 18 19 |
| 47 | 20 21 22 23 24 25 26 27 28 29 | 47 | 20 21 22 23 24 25 26 27 28 29 |
| 48 | 30 31 32 33 34 35 36 37 38 39 | 48 | 30 31 32 33 34 35 36 37 38 39 |
| 49 | 40 41 42 43 44 45 46 47 48 49 | 49 | 40 41 42 43 44 45 46 47 48 49 |
| 50 | 50 51 52 53 54 55 56 57 58 59 | 50 | 50 51 52 53 54 55 56 57 58 59 |
| 51 | 60 61 62 63 64 65 66 67 68 69 | 51 | 60 61 62 63 64 65 66 67 68 69 |
| 52 | 70 71 72 73 74 75 76 77 78 79 | 52 | 70 71 72 73 74 75 76 77 78 79 |
| 53 | 80 81 82 83 84 85 86 87 88 89 | 53 | 80 81 82 83 84 85 86 87 88 89 |
| 54 | 90 91 92 93 94 95 96 97 98 99 | 54 | 90 91 92 93 94 95 96 97 98 99 |
| 55 | 100>; | 55 | 100>; |
| 56 | default-brightness-level = <80>; | 56 | default-brightness-level = <80>; |
| 57 | status = "disabled"; | 57 | status = "disabled"; |
| 58 | }; | 58 | }; |
| 59 | }; | 59 | }; |
| 60 | 60 | ||
| 61 | &iomuxc { | 61 | &iomuxc { |
| 62 | pinctrl-names = "default"; | 62 | pinctrl-names = "default"; |
| 63 | 63 | ||
| 64 | smarc-imx8mq { | 64 | smarc-imx8mq { |
| 65 | pinctrl_fec1: fec1grp { | 65 | pinctrl_fec1: fec1grp { |
| 66 | fsl,pins = < | 66 | fsl,pins = < |
| 67 | MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 | 67 | MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 |
| 68 | MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 | 68 | MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 |
| 69 | MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f | 69 | MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f |
| 70 | MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f | 70 | MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f |
| 71 | MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f | 71 | MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f |
| 72 | MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f | 72 | MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f |
| 73 | MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 | 73 | MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 |
| 74 | MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 | 74 | MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 |
| 75 | MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 | 75 | MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 |
| 76 | MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 | 76 | MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 |
| 77 | MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f | 77 | MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f |
| 78 | MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 | 78 | MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 |
| 79 | MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 | 79 | MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 |
| 80 | MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f | 80 | MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f |
| 81 | >; | 81 | >; |
| 82 | }; | 82 | }; |
| 83 | 83 | ||
| 84 | pinctrl_i2c1: i2c1grp { | 84 | pinctrl_i2c1: i2c1grp { |
| 85 | fsl,pins = < | 85 | fsl,pins = < |
| 86 | MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f | 86 | MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f |
| 87 | MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f | 87 | MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f |
| 88 | >; | 88 | >; |
| 89 | }; | 89 | }; |
| 90 | 90 | ||
| 91 | pinctrl_i2c2: i2c2grp { | 91 | pinctrl_i2c2: i2c2grp { |
| 92 | fsl,pins = < | 92 | fsl,pins = < |
| 93 | MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f | 93 | MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f |
| 94 | MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f | 94 | MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f |
| 95 | >; | 95 | >; |
| 96 | }; | 96 | }; |
| 97 | 97 | ||
| 98 | pinctrl_i2c3: i2c3grp { | 98 | pinctrl_i2c3: i2c3grp { |
| 99 | fsl,pins = < | 99 | fsl,pins = < |
| 100 | MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f | 100 | MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f |
| 101 | MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f | 101 | MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f |
| 102 | >; | 102 | >; |
| 103 | }; | 103 | }; |
| 104 | 104 | ||
| 105 | pinctrl_i2c4: i2c4grp { | 105 | pinctrl_i2c4: i2c4grp { |
| 106 | fsl,pins = < | 106 | fsl,pins = < |
| 107 | MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f | 107 | MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f |
| 108 | MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f | 108 | MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f |
| 109 | >; | 109 | >; |
| 110 | }; | 110 | }; |
| 111 | 111 | ||
| 112 | 112 | ||
| 113 | pinctrl_pcie0: pcie0grp { | 113 | pinctrl_pcie0: pcie0grp { |
| 114 | fsl,pins = < | 114 | fsl,pins = < |
| 115 | MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x16 | 115 | MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x16 |
| 116 | >; | 116 | >; |
| 117 | }; | 117 | }; |
| 118 | 118 | ||
| 119 | pinctrl_pcie1: pcie1grp { | 119 | pinctrl_pcie1: pcie1grp { |
| 120 | fsl,pins = < | 120 | fsl,pins = < |
| 121 | MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x16 | 121 | MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x16 |
| 122 | >; | 122 | >; |
| 123 | }; | 123 | }; |
| 124 | 124 | ||
| 125 | pinctrl_pwm1: pwm1grp { | 125 | pinctrl_pwm1: pwm1grp { |
| 126 | fsl,pins = < | 126 | fsl,pins = < |
| 127 | MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16 | 127 | MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16 |
| 128 | >; | 128 | >; |
| 129 | }; | 129 | }; |
| 130 | 130 | ||
| 131 | pinctrl_qspi: qspigrp { | 131 | pinctrl_qspi: qspigrp { |
| 132 | fsl,pins = < | 132 | fsl,pins = < |
| 133 | MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 | 133 | MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 |
| 134 | MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 | 134 | MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 |
| 135 | MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 | 135 | MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 |
| 136 | MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 | 136 | MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 |
| 137 | MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 | 137 | MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 |
| 138 | MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 | 138 | MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 |
| 139 | MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 | 139 | MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 |
| 140 | 140 | ||
| 141 | >; | 141 | >; |
| 142 | }; | 142 | }; |
| 143 | 143 | ||
| 144 | pinctrl_uart1: uart1grp { | 144 | pinctrl_uart1: uart1grp { |
| 145 | fsl,pins = < | 145 | fsl,pins = < |
| 146 | MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 | 146 | MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 |
| 147 | MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 | 147 | MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 |
| 148 | >; | 148 | >; |
| 149 | }; | 149 | }; |
| 150 | 150 | ||
| 151 | pinctrl_uart2: uart2grp { | 151 | pinctrl_uart2: uart2grp { |
| 152 | fsl,pins = < | 152 | fsl,pins = < |
| 153 | MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79 | 153 | MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x79 |
| 154 | MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79 | 154 | MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x79 |
| 155 | MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x19 /* RTS */ | 155 | MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x79 /* RTS */ |
| 156 | MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x19 /* CTS */ | 156 | MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x79 /* CTS */ |
| 157 | 157 | ||
| 158 | >; | 158 | >; |
| 159 | }; | 159 | }; |
| 160 | 160 | ||
| 161 | pinctrl_uart3: uart3grp { | 161 | pinctrl_uart3: uart3grp { |
| 162 | fsl,pins = < | 162 | fsl,pins = < |
| 163 | MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79 | 163 | MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79 |
| 164 | MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79 | 164 | MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79 |
| 165 | >; | 165 | >; |
| 166 | }; | 166 | }; |
| 167 | 167 | ||
| 168 | pinctrl_uart4: uart4grp { | 168 | pinctrl_uart4: uart4grp { |
| 169 | fsl,pins = < | 169 | fsl,pins = < |
| 170 | MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x79 | 170 | MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x79 |
| 171 | MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x79 | 171 | MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x79 |
| 172 | MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x79 /* RTS */ | ||
| 173 | MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x79 /* CTS */ | ||
| 172 | >; | 174 | >; |
| 173 | }; | 175 | }; |
| 174 | 176 | ||
| 175 | pinctrl_usdhc1: usdhc1grp { | 177 | pinctrl_usdhc1: usdhc1grp { |
| 176 | fsl,pins = < | 178 | fsl,pins = < |
| 177 | MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 | 179 | MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 |
| 178 | MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 | 180 | MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 |
| 179 | MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 | 181 | MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 |
| 180 | MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 | 182 | MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 |
| 181 | MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 | 183 | MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 |
| 182 | MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 | 184 | MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 |
| 183 | MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 | 185 | MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 |
| 184 | MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 | 186 | MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 |
| 185 | MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 | 187 | MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 |
| 186 | MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 | 188 | MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 |
| 187 | MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 | 189 | MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 |
| 188 | MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 | 190 | MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 |
| 189 | >; | 191 | >; |
| 190 | }; | 192 | }; |
| 191 | 193 | ||
| 192 | pinctrl_usdhc1_100mhz: usdhc1grp100mhz { | 194 | pinctrl_usdhc1_100mhz: usdhc1grp100mhz { |
| 193 | fsl,pins = < | 195 | fsl,pins = < |
| 194 | MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d | 196 | MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d |
| 195 | MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd | 197 | MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd |
| 196 | MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd | 198 | MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd |
| 197 | MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd | 199 | MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd |
| 198 | MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd | 200 | MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd |
| 199 | MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd | 201 | MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd |
| 200 | MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd | 202 | MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd |
| 201 | MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd | 203 | MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd |
| 202 | MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd | 204 | MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd |
| 203 | MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd | 205 | MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd |
| 204 | MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d | 206 | MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d |
| 205 | MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 | 207 | MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 |
| 206 | >; | 208 | >; |
| 207 | }; | 209 | }; |
| 208 | 210 | ||
| 209 | pinctrl_usdhc1_200mhz: usdhc1grp200mhz { | 211 | pinctrl_usdhc1_200mhz: usdhc1grp200mhz { |
| 210 | fsl,pins = < | 212 | fsl,pins = < |
| 211 | MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f | 213 | MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f |
| 212 | MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf | 214 | MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf |
| 213 | MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf | 215 | MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf |
| 214 | MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf | 216 | MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf |
| 215 | MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf | 217 | MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf |
| 216 | MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf | 218 | MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf |
| 217 | MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf | 219 | MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf |
| 218 | MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf | 220 | MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf |
| 219 | MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf | 221 | MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf |
| 220 | MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf | 222 | MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf |
| 221 | MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f | 223 | MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f |
| 222 | MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 | 224 | MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 |
| 223 | >; | 225 | >; |
| 224 | }; | 226 | }; |
| 225 | 227 | ||
| 226 | pinctrl_usdhc2_gpio: usdhc2grpgpio { | 228 | pinctrl_usdhc2_gpio: usdhc2grpgpio { |
| 227 | fsl,pins = < | 229 | fsl,pins = < |
| 228 | MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41 | 230 | MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x41 |
| 229 | MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 | 231 | MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 |
| 230 | MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 | 232 | MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 |
| 231 | >; | 233 | >; |
| 232 | }; | 234 | }; |
| 233 | 235 | ||
| 234 | pinctrl_usdhc2: usdhc2grp { | 236 | pinctrl_usdhc2: usdhc2grp { |
| 235 | fsl,pins = < | 237 | fsl,pins = < |
| 236 | MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 | 238 | MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 |
| 237 | MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 | 239 | MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 |
| 238 | MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 | 240 | MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 |
| 239 | MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 | 241 | MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 |
| 240 | MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 | 242 | MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 |
| 241 | MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 | 243 | MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 |
| 244 | MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 | ||
| 242 | >; | 245 | >; |
| 243 | }; | 246 | }; |
| 244 | 247 | ||
| 245 | pinctrl_usdhc2_100mhz: usdhc2grp100mhz { | 248 | pinctrl_usdhc2_100mhz: usdhc2grp100mhz { |
| 246 | fsl,pins = < | 249 | fsl,pins = < |
| 247 | MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d | 250 | MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d |
| 248 | MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd | 251 | MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd |
| 249 | MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd | 252 | MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd |
| 250 | MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd | 253 | MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd |
| 251 | MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd | 254 | MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd |
| 252 | MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd | 255 | MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd |
| 256 | MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 | ||
| 253 | >; | 257 | >; |
| 254 | }; | 258 | }; |
| 255 | 259 | ||
| 256 | pinctrl_usdhc2_200mhz: usdhc2grp200mhz { | 260 | pinctrl_usdhc2_200mhz: usdhc2grp200mhz { |
| 257 | fsl,pins = < | 261 | fsl,pins = < |
| 258 | MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f | 262 | MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f |
| 259 | MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf | 263 | MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf |
| 260 | MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf | 264 | MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf |
| 261 | MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf | 265 | MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf |
| 262 | MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf | 266 | MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf |
| 263 | MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf | 267 | MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf |
| 268 | MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 | ||
| 264 | >; | 269 | >; |
| 265 | }; | 270 | }; |
| 266 | 271 | ||
| 267 | pinctrl_sai2: sai2grp { | 272 | pinctrl_sai2: sai2grp { |
| 268 | fsl,pins = < | 273 | fsl,pins = < |
| 269 | MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 | 274 | MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 |
| 270 | MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 | 275 | MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 |
| 271 | MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 | 276 | MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 |
| 272 | MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 | 277 | MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 |
| 273 | MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 | 278 | MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 |
| 274 | >; | 279 | >; |
| 275 | }; | 280 | }; |
| 276 | 281 | ||
| 277 | pinctrl_wdog: wdoggrp { | 282 | pinctrl_wdog: wdoggrp { |
| 278 | fsl,pins = < | 283 | fsl,pins = < |
| 279 | MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 | 284 | MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 |
| 280 | >; | 285 | >; |
| 281 | }; | 286 | }; |
| 282 | }; | 287 | }; |
| 283 | }; | 288 | }; |
| 284 | 289 | ||
| 285 | &fec1 { | 290 | &fec1 { |
| 286 | pinctrl-names = "default"; | 291 | pinctrl-names = "default"; |
| 287 | pinctrl-0 = <&pinctrl_fec1>; | 292 | pinctrl-0 = <&pinctrl_fec1>; |
| 288 | phy-mode = "rgmii-id"; | 293 | phy-mode = "rgmii-id"; |
| 289 | phy-handle = <ðphy0>; | 294 | phy-handle = <ðphy0>; |
| 290 | fsl,magic-packet; | 295 | fsl,magic-packet; |
| 291 | interrupt-parent = <&gpio1>; | 296 | interrupt-parent = <&gpio1>; |
| 292 | interrupts = <11 IRQ_TYPE_EDGE_FALLING>; | 297 | interrupts = <11 IRQ_TYPE_EDGE_FALLING>; |
| 293 | status = "okay"; | 298 | status = "okay"; |
| 294 | 299 | ||
| 295 | mdio { | 300 | mdio { |
| 296 | #address-cells = <1>; | 301 | #address-cells = <1>; |
| 297 | #size-cells = <0>; | 302 | #size-cells = <0>; |
| 298 | 303 | ||
| 299 | ethphy0: ethernet-phy@0 { | 304 | ethphy0: ethernet-phy@0 { |
| 300 | compatible = "ethernet-phy-ieee802.3-c22"; | 305 | compatible = "ethernet-phy-ieee802.3-c22"; |
| 301 | reg = <6>; | 306 | reg = <6>; |
| 302 | at803x,led-act-blind-workaround; | 307 | at803x,led-act-blind-workaround; |
| 303 | at803x,eee-disabled; | 308 | at803x,eee-disabled; |
| 304 | }; | 309 | }; |
| 305 | }; | 310 | }; |
| 306 | }; | 311 | }; |
| 307 | 312 | ||
| 308 | &i2c1 { | 313 | &i2c1 { |
| 309 | clock-frequency = <100000>; | 314 | clock-frequency = <100000>; |
| 310 | pinctrl-names = "default"; | 315 | pinctrl-names = "default"; |
| 311 | pinctrl-0 = <&pinctrl_i2c1>; | 316 | pinctrl-0 = <&pinctrl_i2c1>; |
| 312 | status = "okay"; | 317 | status = "okay"; |
| 313 | 318 | ||
| 314 | pmic: pfuze100@08 { | 319 | pmic: pfuze100@08 { |
| 315 | compatible = "fsl,pfuze100"; | 320 | compatible = "fsl,pfuze100"; |
| 316 | reg = <0x08>; | 321 | reg = <0x08>; |
| 317 | 322 | ||
| 318 | regulators { | 323 | regulators { |
| 319 | sw1a_reg: sw1ab { | 324 | sw1a_reg: sw1ab { |
| 320 | regulator-min-microvolt = <300000>; | 325 | regulator-min-microvolt = <300000>; |
| 321 | regulator-max-microvolt = <1875000>; | 326 | regulator-max-microvolt = <1875000>; |
| 322 | regulator-always-on; | 327 | regulator-always-on; |
| 323 | }; | 328 | }; |
| 324 | 329 | ||
| 325 | sw1c_reg: sw1c { | 330 | sw1c_reg: sw1c { |
| 326 | regulator-min-microvolt = <300000>; | 331 | regulator-min-microvolt = <300000>; |
| 327 | regulator-max-microvolt = <1875000>; | 332 | regulator-max-microvolt = <1875000>; |
| 328 | regulator-always-on; | 333 | regulator-always-on; |
| 329 | }; | 334 | }; |
| 330 | 335 | ||
| 331 | sw2_reg: sw2 { | 336 | sw2_reg: sw2 { |
| 332 | regulator-min-microvolt = <800000>; | 337 | regulator-min-microvolt = <800000>; |
| 333 | regulator-max-microvolt = <3300000>; | 338 | regulator-max-microvolt = <3300000>; |
| 334 | regulator-always-on; | 339 | regulator-always-on; |
| 335 | }; | 340 | }; |
| 336 | 341 | ||
| 337 | sw3a_reg: sw3ab { | 342 | sw3a_reg: sw3ab { |
| 338 | regulator-min-microvolt = <400000>; | 343 | regulator-min-microvolt = <400000>; |
| 339 | regulator-max-microvolt = <1975000>; | 344 | regulator-max-microvolt = <1975000>; |
| 340 | regulator-always-on; | 345 | regulator-always-on; |
| 341 | }; | 346 | }; |
| 342 | 347 | ||
| 343 | sw4_reg: sw4 { | 348 | sw4_reg: sw4 { |
| 344 | regulator-min-microvolt = <800000>; | 349 | regulator-min-microvolt = <800000>; |
| 345 | regulator-max-microvolt = <3300000>; | 350 | regulator-max-microvolt = <3300000>; |
| 346 | regulator-always-on; | 351 | regulator-always-on; |
| 347 | }; | 352 | }; |
| 348 | 353 | ||
| 349 | swbst_reg: swbst { | 354 | swbst_reg: swbst { |
| 350 | regulator-min-microvolt = <5000000>; | 355 | regulator-min-microvolt = <5000000>; |
| 351 | regulator-max-microvolt = <5150000>; | 356 | regulator-max-microvolt = <5150000>; |
| 352 | }; | 357 | }; |
| 353 | 358 | ||
| 354 | snvs_reg: vsnvs { | 359 | snvs_reg: vsnvs { |
| 355 | regulator-min-microvolt = <1000000>; | 360 | regulator-min-microvolt = <1000000>; |
| 356 | regulator-max-microvolt = <3000000>; | 361 | regulator-max-microvolt = <3000000>; |
| 357 | regulator-always-on; | 362 | regulator-always-on; |
| 358 | }; | 363 | }; |
| 359 | 364 | ||
| 360 | vref_reg: vrefddr { | 365 | vref_reg: vrefddr { |
| 361 | regulator-always-on; | 366 | regulator-always-on; |
| 362 | }; | 367 | }; |
| 363 | 368 | ||
| 364 | vgen1_reg: vgen1 { | 369 | vgen1_reg: vgen1 { |
| 365 | regulator-min-microvolt = <800000>; | 370 | regulator-min-microvolt = <800000>; |
| 366 | regulator-max-microvolt = <1550000>; | 371 | regulator-max-microvolt = <1550000>; |
| 367 | }; | 372 | }; |
| 368 | 373 | ||
| 369 | vgen2_reg: vgen2 { | 374 | vgen2_reg: vgen2 { |
| 370 | regulator-min-microvolt = <800000>; | 375 | regulator-min-microvolt = <800000>; |
| 371 | regulator-max-microvolt = <1550000>; | 376 | regulator-max-microvolt = <1550000>; |
| 372 | regulator-always-on; | 377 | regulator-always-on; |
| 373 | }; | 378 | }; |
| 374 | 379 | ||
| 375 | vgen3_reg: vgen3 { | 380 | vgen3_reg: vgen3 { |
| 376 | regulator-min-microvolt = <1800000>; | 381 | regulator-min-microvolt = <1800000>; |
| 377 | regulator-max-microvolt = <3300000>; | 382 | regulator-max-microvolt = <3300000>; |
| 378 | regulator-always-on; | 383 | regulator-always-on; |
| 379 | }; | 384 | }; |
| 380 | 385 | ||
| 381 | vgen4_reg: vgen4 { | 386 | vgen4_reg: vgen4 { |
| 382 | regulator-min-microvolt = <1800000>; | 387 | regulator-min-microvolt = <1800000>; |
| 383 | regulator-max-microvolt = <3300000>; | 388 | regulator-max-microvolt = <3300000>; |
| 384 | regulator-always-on; | 389 | regulator-always-on; |
| 385 | }; | 390 | }; |
| 386 | 391 | ||
| 387 | vgen5_reg: vgen5 { | 392 | vgen5_reg: vgen5 { |
| 388 | regulator-min-microvolt = <1800000>; | 393 | regulator-min-microvolt = <1800000>; |
| 389 | regulator-max-microvolt = <3300000>; | 394 | regulator-max-microvolt = <3300000>; |
| 390 | regulator-always-on; | 395 | regulator-always-on; |
| 391 | }; | 396 | }; |
| 392 | 397 | ||
| 393 | vgen6_reg: vgen6 { | 398 | vgen6_reg: vgen6 { |
| 394 | regulator-min-microvolt = <1800000>; | 399 | regulator-min-microvolt = <1800000>; |
| 395 | regulator-max-microvolt = <3300000>; | 400 | regulator-max-microvolt = <3300000>; |
| 396 | regulator-always-on; | ||
| 397 | }; | 401 | }; |
| 398 | }; | 402 | }; |
| 399 | }; | 403 | }; |
| 400 | 404 | ||
| 401 | s35390a: s35390a@30 { | 405 | s35390a: s35390a@30 { |
| 402 | compatible = "s35390a"; | 406 | compatible = "s35390a"; |
| 403 | reg = <0x30>; | 407 | reg = <0x30>; |
| 404 | }; | 408 | }; |
| 405 | 409 | ||
| 406 | cape_eeprom0: cape_eeprom@57 { | 410 | cape_eeprom0: cape_eeprom@57 { |
| 407 | compatible = "at,24c256"; | 411 | compatible = "at,24c256"; |
| 408 | reg = <0x57>; | 412 | reg = <0x57>; |
| 409 | }; | 413 | }; |
| 410 | }; | 414 | }; |
| 411 | 415 | ||
| 412 | &i2c2 { | 416 | &i2c2 { |
| 413 | clock-frequency = <100000>; | 417 | clock-frequency = <100000>; |
| 414 | pinctrl-names = "default"; | 418 | pinctrl-names = "default"; |
| 415 | pinctrl-0 = <&pinctrl_i2c2>; | 419 | pinctrl-0 = <&pinctrl_i2c2>; |
| 416 | status = "okay"; | 420 | status = "okay"; |
| 417 | 421 | ||
| 418 | baseboard_eeprom: baseboard_eeprom@50 { | 422 | baseboard_eeprom: baseboard_eeprom@50 { |
| 419 | compatible = "at,24c256"; | 423 | compatible = "at,24c256"; |
| 420 | reg = <0x50>; | 424 | reg = <0x50>; |
| 421 | }; | 425 | }; |
| 422 | 426 | ||
| 423 | dsi_lvds_bridge: sn65dsi84@2c { | 427 | dsi_lvds_bridge: sn65dsi84@2c { |
| 424 | status = "disabled"; | 428 | status = "disabled"; |
| 425 | reg = <0x2c>; | 429 | reg = <0x2c>; |
| 426 | compatible = "ti,sn65dsi84"; | 430 | compatible = "ti,sn65dsi84"; |
| 427 | enable-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; | 431 | enable-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; |
| 428 | interrupt-parent = <&gpio4>; | 432 | interrupt-parent = <&gpio4>; |
| 429 | interrupts = <4 IRQ_TYPE_EDGE_FALLING>; | 433 | interrupts = <4 IRQ_TYPE_EDGE_FALLING>; |
| 430 | 434 | ||
| 431 | /* AUO G070VW01 7-inch 800x480 LVDS Display */ | 435 | /* AUO G070VW01 7-inch 800x480 LVDS Display */ |
| 432 | sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 | 436 | sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 |
| 433 | 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 | 437 | 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 |
| 434 | 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B | 438 | 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B |
| 435 | 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 | 439 | 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 |
| 436 | 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B | 440 | 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B |
| 437 | 0x3C 0x3D 0x3E 0xE0 0x0D>; | 441 | 0x3C 0x3D 0x3E 0xE0 0x0D>; |
| 438 | 442 | ||
| 439 | sn65dsi84,values = < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00 | 443 | sn65dsi84,values = < 0x00 0x01 0x10 0x00 0x26 0x00 0x13 0x00 |
| 440 | 0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00 | 444 | 0x78 0x00 0x03 0x00 0x20 0x03 0x00 0x00 |
| 441 | 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00 | 445 | 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00 |
| 442 | 0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00 | 446 | 0x80 0x00 0x00 0x00 0x0e 0x00 0x00 0x00 |
| 443 | 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | 447 | 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 |
| 444 | 0x00 0x00 0x00 0x01 0x01>; | 448 | 0x00 0x00 0x00 0x01 0x01>; |
| 445 | 449 | ||
| 446 | /* AUO G185XW01 18.5-inch 1366x768 LVDS Display */ | 450 | /* AUO G185XW01 18.5-inch 1366x768 LVDS Display */ |
| 447 | /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 | 451 | /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 |
| 448 | 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 | 452 | 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 |
| 449 | 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B | 453 | 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B |
| 450 | 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 | 454 | 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 |
| 451 | 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B | 455 | 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B |
| 452 | 0x3C 0x3D 0x3E 0xE0 0x0D>; | 456 | 0x3C 0x3D 0x3E 0xE0 0x0D>; |
| 453 | 457 | ||
| 454 | sn65dsi84,values = < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00 | 458 | sn65dsi84,values = < 0x00 0x05 0x10 0x00 0x26 0x00 0x2E 0x00 |
| 455 | 0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00 | 459 | 0x78 0x00 0x03 0x00 0x56 0x05 0x00 0x00 |
| 456 | 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00 | 460 | 0x00 0x00 0x00 0x00 0x21 0x00 0x00 0x00 |
| 457 | 0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00 | 461 | 0x78 0x00 0x00 0x00 0x12 0x00 0x00 0x00 |
| 458 | 0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | 462 | 0x3C 0x00 0x00 0x00 0x00 0x00 0x00 0x00 |
| 459 | 0x00 0x00 0x00 0x01 0x01>;*/ | 463 | 0x00 0x00 0x00 0x01 0x01>;*/ |
| 460 | 464 | ||
| 461 | /* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */ | 465 | /* AUO G240HW01 V0 24-inch 1920x1080 LVDS Display */ |
| 462 | /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 | 466 | /*sn65dsi84,addresses = < 0x09 0x0A 0x0B 0x0D 0x10 0x11 0x12 0x13 |
| 463 | 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 | 467 | 0x18 0x19 0x1A 0x1B 0x20 0x21 0x22 0x23 |
| 464 | 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B | 468 | 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B |
| 465 | 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 | 469 | 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 |
| 466 | 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B | 470 | 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B |
| 467 | 0x3C 0x3D 0x3E 0xE0 0x0D>; | 471 | 0x3C 0x3D 0x3E 0xE0 0x0D>; |
| 468 | 472 | ||
| 469 | sn65dsi84,values = < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00 | 473 | sn65dsi84,values = < 0x00 0x05 0x20 0x00 0x26 0x00 0x4E 0x00 |
| 470 | 0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00 | 474 | 0x6C 0x00 0x03 0x00 0x80 0x07 0x00 0x00 |
| 471 | 0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00 | 475 | 0x00 0x00 0x00 0x00 0xC3 0x00 0x00 0x00 |
| 472 | 0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00 | 476 | 0x32 0x00 0x00 0x00 0x14 0x00 0x00 0x00 |
| 473 | 0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00 | 477 | 0x19 0x00 0x00 0x00 0x00 0x00 0x00 0x00 |
| 474 | 0x00 0x00 0x00 0x01 0x01>;*/ | 478 | 0x00 0x00 0x00 0x01 0x01>;*/ |
| 475 | }; | 479 | }; |
| 476 | }; | 480 | }; |
| 477 | 481 | ||
| 478 | &i2c3 { | 482 | &i2c3 { |
| 479 | clock-frequency = <100000>; | 483 | clock-frequency = <100000>; |
| 480 | pinctrl-names = "default"; | 484 | pinctrl-names = "default"; |
| 481 | pinctrl-0 = <&pinctrl_i2c3>; | 485 | pinctrl-0 = <&pinctrl_i2c3>; |
| 482 | status = "okay"; | 486 | status = "okay"; |
| 483 | }; | 487 | }; |
| 484 | 488 | ||
| 485 | &i2c4 { | 489 | &i2c4 { |
| 486 | clock-frequency = <100000>; | 490 | clock-frequency = <100000>; |
| 487 | pinctrl-names = "default"; | 491 | pinctrl-names = "default"; |
| 488 | pinctrl-0 = <&pinctrl_i2c4>; | 492 | pinctrl-0 = <&pinctrl_i2c4>; |
| 489 | status = "okay"; | 493 | status = "okay"; |
| 490 | }; | 494 | }; |
| 491 | 495 | ||
| 492 | &pcie0{ | 496 | &pcie0{ |
| 493 | pinctrl-names = "default"; | 497 | pinctrl-names = "default"; |
| 494 | pinctrl-0 = <&pinctrl_pcie0>; | 498 | pinctrl-0 = <&pinctrl_pcie0>; |
| 495 | reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; | 499 | reset-gpio = <&gpio3 3 GPIO_ACTIVE_LOW>; |
| 496 | status = "okay"; | 500 | status = "okay"; |
| 497 | }; | 501 | }; |
| 498 | 502 | ||
| 499 | &pcie1{ | 503 | &pcie1{ |
| 500 | pinctrl-names = "default"; | 504 | pinctrl-names = "default"; |
| 501 | pinctrl-0 = <&pinctrl_pcie1>; | 505 | pinctrl-0 = <&pinctrl_pcie1>; |
| 502 | reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; | 506 | reset-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; |
| 503 | status = "okay"; | 507 | status = "okay"; |
| 504 | }; | 508 | }; |
| 505 | 509 | ||
| 506 | &pwm1 { | 510 | &pwm1 { |
| 507 | pinctrl-names = "default"; | 511 | pinctrl-names = "default"; |
| 508 | pinctrl-0 = <&pinctrl_pwm1>; | 512 | pinctrl-0 = <&pinctrl_pwm1>; |
| 509 | status = "okay"; | 513 | status = "okay"; |
| 510 | }; | 514 | }; |
| 511 | 515 | ||
| 512 | &uart1 { /* console */ | 516 | &uart1 { /* console */ |
| 513 | pinctrl-names = "default"; | 517 | pinctrl-names = "default"; |
| 514 | pinctrl-0 = <&pinctrl_uart1>; | 518 | pinctrl-0 = <&pinctrl_uart1>; |
| 515 | assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; | 519 | assigned-clocks = <&clk IMX8MQ_CLK_UART1_SRC>; |
| 516 | assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; | 520 | assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; |
| 517 | status = "okay"; | 521 | status = "okay"; |
| 518 | }; | 522 | }; |
| 519 | 523 | ||
| 520 | &lcdif { | 524 | &lcdif { |
| 521 | status = "okay"; | 525 | status = "okay"; |
| 522 | disp-dev = "mipi_dsi_northwest"; | 526 | disp-dev = "mipi_dsi_northwest"; |
| 523 | display = <&display0>; | 527 | display = <&display0>; |
| 524 | 528 | ||
| 525 | display0: display@0 { | 529 | display0: display@0 { |
| 526 | bits-per-pixel = <24>; | 530 | bits-per-pixel = <24>; |
| 527 | bus-width = <24>; | 531 | bus-width = <24>; |
| 528 | 532 | ||
| 529 | display-timings { | 533 | display-timings { |
| 530 | native-mode = <&timing0>; | 534 | native-mode = <&timing0>; |
| 531 | timing0: timing0 { | 535 | timing0: timing0 { |
| 532 | clock-frequency = <9200000>; | 536 | clock-frequency = <9200000>; |
| 533 | hactive = <480>; | 537 | hactive = <480>; |
| 534 | vactive = <272>; | 538 | vactive = <272>; |
| 535 | hfront-porch = <8>; | 539 | hfront-porch = <8>; |
| 536 | hback-porch = <4>; | 540 | hback-porch = <4>; |
| 537 | hsync-len = <41>; | 541 | hsync-len = <41>; |
| 538 | vback-porch = <2>; | 542 | vback-porch = <2>; |
| 539 | vfront-porch = <4>; | 543 | vfront-porch = <4>; |
| 540 | vsync-len = <10>; | 544 | vsync-len = <10>; |
| 541 | 545 | ||
| 542 | hsync-active = <0>; | 546 | hsync-active = <0>; |
| 543 | vsync-active = <0>; | 547 | vsync-active = <0>; |
| 544 | de-active = <1>; | 548 | de-active = <1>; |
| 545 | pixelclk-active = <0>; | 549 | pixelclk-active = <0>; |
| 546 | }; | 550 | }; |
| 547 | }; | 551 | }; |
| 548 | }; | 552 | }; |
| 549 | port@0 { | 553 | port@0 { |
| 550 | lcdif_mipi_dsi: mipi-dsi-endpoint { | 554 | lcdif_mipi_dsi: mipi-dsi-endpoint { |
| 551 | remote-endpoint = <&mipi_dsi_in>; | 555 | remote-endpoint = <&mipi_dsi_in>; |
| 552 | }; | 556 | }; |
| 553 | }; | 557 | }; |
| 554 | }; | 558 | }; |
| 555 | 559 | ||
| 556 | &qspi { | 560 | &qspi { |
| 557 | pinctrl-names = "default"; | 561 | pinctrl-names = "default"; |
| 558 | pinctrl-0 = <&pinctrl_qspi>; | 562 | pinctrl-0 = <&pinctrl_qspi>; |
| 559 | status = "okay"; | 563 | status = "okay"; |
| 560 | }; | 564 | }; |
| 561 | 565 | ||
| 562 | &mipi_dsi { | 566 | &mipi_dsi { |
| 563 | reset = <&src>; | 567 | reset = <&src>; |
| 564 | mux-sel = <&gpr>; /* lcdif or dcss */ | 568 | mux-sel = <&gpr>; /* lcdif or dcss */ |
| 565 | status = "okay"; | 569 | status = "okay"; |
| 566 | 570 | ||
| 567 | port@1 { | 571 | port@1 { |
| 568 | mipi_dsi_in: endpoint { | 572 | mipi_dsi_in: endpoint { |
| 569 | remote-endpoint = <&lcdif_mipi_dsi>; | 573 | remote-endpoint = <&lcdif_mipi_dsi>; |
| 570 | }; | 574 | }; |
| 571 | }; | 575 | }; |
| 572 | }; | 576 | }; |
| 573 | 577 | ||
| 574 | &uart2 { | 578 | &uart2 { |
| 575 | pinctrl-names = "default"; | 579 | pinctrl-names = "default"; |
| 576 | pinctrl-0 = <&pinctrl_uart2>; | 580 | pinctrl-0 = <&pinctrl_uart2>; |
| 577 | assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>; | 581 | assigned-clocks = <&clk IMX8MQ_CLK_UART2_SRC>; |
| 578 | assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; | 582 | assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; |
| 579 | fsl,uart-has-rtscts; | 583 | fsl,uart-has-rtscts; |
| 580 | status = "okay"; | 584 | status = "okay"; |
| 581 | }; | 585 | }; |
| 582 | 586 | ||
| 583 | &uart3 { | 587 | &uart3 { |
| 584 | pinctrl-names = "default"; | 588 | pinctrl-names = "default"; |
| 585 | pinctrl-0 = <&pinctrl_uart3>; | 589 | pinctrl-0 = <&pinctrl_uart3>; |
| 586 | assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; | 590 | assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>; |
| 587 | assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; | 591 | assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; |
| 588 | status = "okay"; | 592 | status = "okay"; |
| 589 | }; | 593 | }; |
| 590 | 594 | ||
| 591 | &uart4 { | 595 | &uart4 { |
| 592 | pinctrl-names = "default"; | 596 | pinctrl-names = "default"; |
| 593 | pinctrl-0 = <&pinctrl_uart4>; | 597 | pinctrl-0 = <&pinctrl_uart4>; |
| 594 | assigned-clocks = <&clk IMX8MQ_CLK_UART4_SRC>; | 598 | assigned-clocks = <&clk IMX8MQ_CLK_UART4_SRC>; |
| 595 | assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; | 599 | assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; |
| 596 | fsl,uart-has-rtscts; | 600 | fsl,uart-has-rtscts; |
| 597 | status = "okay"; | 601 | status = "okay"; |
| 598 | }; | 602 | }; |
| 599 | 603 | ||
| 600 | &usdhc1 { | 604 | &usdhc1 { |
| 601 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; | 605 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| 602 | pinctrl-0 = <&pinctrl_usdhc1>; | 606 | pinctrl-0 = <&pinctrl_usdhc1>; |
| 603 | pinctrl-1 = <&pinctrl_usdhc1_100mhz>; | 607 | pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| 604 | pinctrl-2 = <&pinctrl_usdhc1_200mhz>; | 608 | pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
| 605 | bus-width = <8>; | 609 | bus-width = <8>; |
| 606 | non-removable; | 610 | non-removable; |
| 607 | status = "okay"; | 611 | status = "okay"; |
| 608 | }; | 612 | }; |
| 609 | 613 | ||
| 610 | &usdhc2 { | 614 | &usdhc2 { |
| 611 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; | 615 | pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| 612 | pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; | 616 | pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| 613 | pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; | 617 | pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; |
| 614 | pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; | 618 | pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; |
| 615 | bus-width = <4>; | 619 | bus-width = <4>; |
| 616 | cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; | 620 | cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; |
| 617 | vmmc-supply = <®_usdhc2_vmmc>; | 621 | vmmc-supply = <®_usdhc2_vmmc>; |
| 618 | status = "okay"; | 622 | status = "okay"; |
| 619 | }; | 623 | }; |
| 620 | 624 | ||
| 621 | &usb3_phy0 { | 625 | &usb3_phy0 { |
| 622 | status = "okay"; | 626 | status = "okay"; |
| 623 | }; | 627 | }; |
| 624 | 628 | ||
| 625 | &usb3_0 { | 629 | &usb3_0 { |
| 626 | status = "okay"; | 630 | status = "okay"; |
| 627 | }; | 631 | }; |
| 628 | 632 | ||
| 629 | &usb_dwc3_0 { | 633 | &usb_dwc3_0 { |
| 630 | status = "okay"; | 634 | status = "okay"; |
| 631 | dr_mode = "peripheral"; | 635 | dr_mode = "peripheral"; |
| 632 | }; | 636 | }; |
| 633 | 637 | ||
| 634 | &usb3_phy1 { | 638 | &usb3_phy1 { |
| 635 | status = "okay"; | 639 | status = "okay"; |
| 636 | }; | 640 | }; |
| 637 | 641 | ||
| 638 | &usb3_1 { | 642 | &usb3_1 { |
| 639 | status = "disabled"; | 643 | status = "disabled"; |
| 640 | }; | 644 | }; |
| 641 | 645 | ||
| 642 | &usb_dwc3_1 { | 646 | &usb_dwc3_1 { |
| 643 | status = "okay"; | 647 | status = "okay"; |
| 644 | dr_mode = "host"; | 648 | dr_mode = "host"; |
| 645 | }; | 649 | }; |
| 646 | 650 | ||
| 647 | &sai2 { | 651 | &sai2 { |
| 648 | pinctrl-names = "default"; | 652 | pinctrl-names = "default"; |
| 649 | pinctrl-0 = <&pinctrl_sai2>; | 653 | pinctrl-0 = <&pinctrl_sai2>; |
| 650 | assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>, | 654 | assigned-clocks = <&clk IMX8MQ_CLK_SAI2_SRC>, |
| 651 | <&clk IMX8MQ_AUDIO_PLL1>, | 655 | <&clk IMX8MQ_AUDIO_PLL1>, |
| 652 | <&clk IMX8MQ_CLK_SAI2_PRE_DIV>, | 656 | <&clk IMX8MQ_CLK_SAI2_PRE_DIV>, |
| 653 | <&clk IMX8MQ_CLK_SAI2_DIV>; | 657 | <&clk IMX8MQ_CLK_SAI2_DIV>; |
| 654 | assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; | 658 | assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; |
| 655 | assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>; | 659 | assigned-clock-rates = <0>, <786432000>, <98306000>, <24576000>; |
| 656 | status = "okay"; | 660 | status = "okay"; |
| 657 | }; | 661 | }; |
| 658 | 662 | ||
| 659 | &gpu { | 663 | &gpu { |
| 660 | status = "okay"; | 664 | status = "okay"; |
| 661 | }; | 665 | }; |
| 662 | 666 | ||
| 663 | &vpu { | 667 | &vpu { |
| 664 | status = "okay"; | 668 | status = "okay"; |
| 665 | }; | 669 | }; |
| 666 | 670 | ||
| 667 | &wdog1 { | 671 | &wdog1 { |
| 668 | pinctrl-names = "default"; | 672 | pinctrl-names = "default"; |
| 669 | pinctrl-0 = <&pinctrl_wdog>; | 673 | pinctrl-0 = <&pinctrl_wdog>; |
| 670 | fsl,ext-reset-output; | 674 | fsl,ext-reset-output; |
| 671 | status = "okay"; | 675 | status = "okay"; |
| 672 | }; | 676 | }; |
board/embedian/smarcimx8mq/smarcimx8mq.c
| 1 | /* | 1 | /* |
| 2 | * Copyright 2016 Freescale Semiconductor, Inc. | 2 | * Copyright 2016 Freescale Semiconductor, Inc. |
| 3 | * Copyright 2017-2018 NXP | 3 | * Copyright 2017-2018 NXP |
| 4 | * | 4 | * |
| 5 | * SPDX-License-Identifier: GPL-2.0+ | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 6 | */ | 6 | */ |
| 7 | 7 | ||
| 8 | #include <common.h> | 8 | #include <common.h> |
| 9 | #include <malloc.h> | 9 | #include <malloc.h> |
| 10 | #include <errno.h> | 10 | #include <errno.h> |
| 11 | #include <asm/io.h> | 11 | #include <asm/io.h> |
| 12 | #include <miiphy.h> | 12 | #include <miiphy.h> |
| 13 | #include <netdev.h> | 13 | #include <netdev.h> |
| 14 | #include <asm/mach-imx/iomux-v3.h> | 14 | #include <asm/mach-imx/iomux-v3.h> |
| 15 | #include <asm-generic/gpio.h> | 15 | #include <asm-generic/gpio.h> |
| 16 | #include <fsl_esdhc.h> | 16 | #include <fsl_esdhc.h> |
| 17 | #include <mmc.h> | 17 | #include <mmc.h> |
| 18 | #include <asm/arch/imx8mq_pins.h> | 18 | #include <asm/arch/imx8mq_pins.h> |
| 19 | #include <asm/arch/sys_proto.h> | 19 | #include <asm/arch/sys_proto.h> |
| 20 | #include <asm/mach-imx/gpio.h> | 20 | #include <asm/mach-imx/gpio.h> |
| 21 | #include <asm/mach-imx/mxc_i2c.h> | 21 | #include <asm/mach-imx/mxc_i2c.h> |
| 22 | #include <asm/arch/clock.h> | 22 | #include <asm/arch/clock.h> |
| 23 | #include <asm/mach-imx/video.h> | 23 | #include <asm/mach-imx/video.h> |
| 24 | #include <asm/arch/video_common.h> | 24 | #include <asm/arch/video_common.h> |
| 25 | #include <spl.h> | 25 | #include <spl.h> |
| 26 | #include <power/pmic.h> | 26 | #include <power/pmic.h> |
| 27 | #include <power/pfuze100_pmic.h> | 27 | #include <power/pfuze100_pmic.h> |
| 28 | #include <dm.h> | 28 | #include <dm.h> |
| 29 | #include "../../freescale/common/tcpc.h" | 29 | #include "../../freescale/common/tcpc.h" |
| 30 | #include "../../freescale/common/pfuze.h" | 30 | #include "../../freescale/common/pfuze.h" |
| 31 | #include "../../freescale/common/mmc.c" | 31 | #include "../../freescale/common/mmc.c" |
| 32 | #include <usb.h> | 32 | #include <usb.h> |
| 33 | #include <dwc3-uboot.h> | 33 | #include <dwc3-uboot.h> |
| 34 | 34 | ||
| 35 | DECLARE_GLOBAL_DATA_PTR; | 35 | DECLARE_GLOBAL_DATA_PTR; |
| 36 | 36 | ||
| 37 | #define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) | 37 | #define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) |
| 38 | 38 | ||
| 39 | #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) | 39 | #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) |
| 40 | 40 | ||
| 41 | #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) | 41 | #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) |
| 42 | 42 | ||
| 43 | #define WEAK_PULLUP (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) | 43 | #define WEAK_PULLUP (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) |
| 44 | 44 | ||
| 45 | #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) | 45 | #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) |
| 46 | 46 | ||
| 47 | static iomux_v3_cfg_t const wdog_pads[] = { | 47 | static iomux_v3_cfg_t const wdog_pads[] = { |
| 48 | IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), | 48 | IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), |
| 49 | }; | 49 | }; |
| 50 | 50 | ||
| 51 | #ifdef CONFIG_FSL_QSPI | 51 | #ifdef CONFIG_FSL_QSPI |
| 52 | static iomux_v3_cfg_t const qspi_pads[] = { | 52 | static iomux_v3_cfg_t const qspi_pads[] = { |
| 53 | IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), | 53 | IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), |
| 54 | IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), | 54 | IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), |
| 55 | 55 | ||
| 56 | IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), | 56 | IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), |
| 57 | IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), | 57 | IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), |
| 58 | IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), | 58 | IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), |
| 59 | IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), | 59 | IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), |
| 60 | }; | 60 | }; |
| 61 | 61 | ||
| 62 | int board_qspi_init(void) | 62 | int board_qspi_init(void) |
| 63 | { | 63 | { |
| 64 | imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads)); | 64 | imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads)); |
| 65 | 65 | ||
| 66 | set_clk_qspi(); | 66 | set_clk_qspi(); |
| 67 | 67 | ||
| 68 | return 0; | 68 | return 0; |
| 69 | } | 69 | } |
| 70 | #endif | 70 | #endif |
| 71 | 71 | ||
| 72 | #ifdef CONFIG_CONSOLE_SER3 | 72 | #ifdef CONFIG_CONSOLE_SER3 |
| 73 | static iomux_v3_cfg_t const uart1_pads[] = { | 73 | static iomux_v3_cfg_t const uart1_pads[] = { |
| 74 | IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | 74 | IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 75 | IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | 75 | IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 76 | }; | 76 | }; |
| 77 | #endif | 77 | #endif |
| 78 | 78 | ||
| 79 | #ifdef CONFIG_CONSOLE_SER2 | 79 | #ifdef CONFIG_CONSOLE_SER2 |
| 80 | static iomux_v3_cfg_t const uart2_pads[] = { | 80 | static iomux_v3_cfg_t const uart2_pads[] = { |
| 81 | IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | 81 | IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 82 | IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | 82 | IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 83 | IMX8MQ_PAD_UART4_TXD__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | ||
| 84 | IMX8MQ_PAD_UART4_RXD__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | ||
| 85 | |||
| 83 | }; | 86 | }; |
| 84 | #endif | 87 | #endif |
| 85 | 88 | ||
| 86 | #ifdef CONFIG_CONSOLE_SER1 | 89 | #ifdef CONFIG_CONSOLE_SER1 |
| 87 | static iomux_v3_cfg_t const uart3_pads[] = { | 90 | static iomux_v3_cfg_t const uart3_pads[] = { |
| 88 | IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | 91 | IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 89 | IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | 92 | IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 90 | }; | 93 | }; |
| 91 | #endif | 94 | #endif |
| 92 | 95 | ||
| 93 | #ifdef CONFIG_CONSOLE_SER0 | 96 | #ifdef CONFIG_CONSOLE_SER0 |
| 94 | static iomux_v3_cfg_t const uart4_pads[] = { | 97 | static iomux_v3_cfg_t const uart4_pads[] = { |
| 95 | IMX8MQ_PAD_UART4_RXD__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | 98 | IMX8MQ_PAD_ECSPI2_SCLK__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 96 | IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | 99 | IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 97 | IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | 100 | IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 98 | IMX8MQ_PAD_UART4_TXD__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | 101 | IMX8MQ_PAD_ECSPI2_MOSI__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 99 | }; | 102 | }; |
| 100 | #endif | 103 | #endif |
| 101 | 104 | ||
| 102 | /* SPI0*/ | 105 | /* SPI0*/ |
| 103 | static iomux_v3_cfg_t const ecspi1_pads[] = { | 106 | static iomux_v3_cfg_t const ecspi1_pads[] = { |
| 104 | IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(QSPI_PAD_CTRL), | 107 | IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(QSPI_PAD_CTRL), |
| 105 | IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(QSPI_PAD_CTRL), | 108 | IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(QSPI_PAD_CTRL), |
| 106 | IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), | 109 | IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), |
| 107 | 110 | ||
| 108 | IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ | 111 | IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ |
| 109 | IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/ | 112 | IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/ |
| 110 | IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/ | 113 | IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/ |
| 111 | IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/ | 114 | IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/ |
| 112 | }; | 115 | }; |
| 113 | 116 | ||
| 114 | /* MISC PINs */ | 117 | /* MISC PINs */ |
| 115 | static iomux_v3_cfg_t const misc_pads[] = { | 118 | static iomux_v3_cfg_t const misc_pads[] = { |
| 116 | IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 | MUX_PAD_CTRL(WEAK_PULLUP), /*S146, PCIE_WAKE*/ | 119 | IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 | MUX_PAD_CTRL(WEAK_PULLUP), /*S146, PCIE_WAKE*/ |
| 117 | IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP), /*S148, LID#*/ | 120 | IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP), /*S148, LID#*/ |
| 118 | IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), /*S149, SLEEP#*/ | 121 | IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), /*S149, SLEEP#*/ |
| 119 | IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /*S151, CHARGING#*/ | 122 | IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /*S151, CHARGING#*/ |
| 120 | IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(WEAK_PULLUP), /*S152, CHARGER_PRSNT#*/ | 123 | IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(WEAK_PULLUP), /*S152, CHARGER_PRSNT#*/ |
| 121 | IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(WEAK_PULLUP), /*S153, CARRIER_STBY#*/ | 124 | IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(WEAK_PULLUP), /*S153, CARRIER_STBY#*/ |
| 122 | IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), /*S156, BATLOW#*/ | 125 | IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), /*S156, BATLOW#*/ |
| 123 | IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), /*CAN0_INT#*/ | 126 | IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), /*CAN0_INT#*/ |
| 124 | IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), /*CAN1_INT#*/ | 127 | IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), /*CAN1_INT#*/ |
| 125 | }; | 128 | }; |
| 126 | 129 | ||
| 127 | static void setup_iomux_misc(void) | 130 | static void setup_iomux_misc(void) |
| 128 | { | 131 | { |
| 129 | imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); | 132 | imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); |
| 130 | 133 | ||
| 131 | /* Set CARRIER_LID# as Input*/ | 134 | /* Set CARRIER_LID# as Input*/ |
| 132 | gpio_request(IMX_GPIO_NR(1, 9), "LID#"); | 135 | gpio_request(IMX_GPIO_NR(1, 9), "LID#"); |
| 133 | gpio_direction_input(IMX_GPIO_NR(1, 9)); | 136 | gpio_direction_input(IMX_GPIO_NR(1, 9)); |
| 134 | /* Set CARRIER_SLEEP# as Input*/ | 137 | /* Set CARRIER_SLEEP# as Input*/ |
| 135 | gpio_request(IMX_GPIO_NR(1, 12), "SLEEP#"); | 138 | gpio_request(IMX_GPIO_NR(1, 12), "SLEEP#"); |
| 136 | gpio_direction_input(IMX_GPIO_NR(1, 12)); | 139 | gpio_direction_input(IMX_GPIO_NR(1, 12)); |
| 137 | /* Set CARRIER_CHARGING# as Input*/ | 140 | /* Set CARRIER_CHARGING# as Input*/ |
| 138 | gpio_request(IMX_GPIO_NR(1, 01), "CHARGING#"); | 141 | gpio_request(IMX_GPIO_NR(1, 01), "CHARGING#"); |
| 139 | gpio_direction_input(IMX_GPIO_NR(1, 01)); | 142 | gpio_direction_input(IMX_GPIO_NR(1, 01)); |
| 140 | /* Set CARRIER_CHARGER_PRSNT# as Input*/ | 143 | /* Set CARRIER_CHARGER_PRSNT# as Input*/ |
| 141 | gpio_request(IMX_GPIO_NR(4, 22), "CHARGER_PRSNT#"); | 144 | gpio_request(IMX_GPIO_NR(4, 22), "CHARGER_PRSNT#"); |
| 142 | gpio_direction_input(IMX_GPIO_NR(4, 22)); | 145 | gpio_direction_input(IMX_GPIO_NR(4, 22)); |
| 143 | /* Set CARRIER_STBY# as Output High*/ | 146 | /* Set CARRIER_STBY# as Output High*/ |
| 144 | gpio_request(IMX_GPIO_NR(5, 02), "CARRIER_STBY#"); | 147 | gpio_request(IMX_GPIO_NR(5, 02), "CARRIER_STBY#"); |
| 145 | gpio_direction_output(IMX_GPIO_NR(5, 02) , 1); | 148 | gpio_direction_output(IMX_GPIO_NR(5, 02) , 1); |
| 146 | /* Set CARRIER_BATLOW# as Input*/ | 149 | /* Set CARRIER_BATLOW# as Input*/ |
| 147 | gpio_request(IMX_GPIO_NR(4, 21), "BATLOW#"); | 150 | gpio_request(IMX_GPIO_NR(4, 21), "BATLOW#"); |
| 148 | gpio_direction_input(IMX_GPIO_NR(4, 21)); | 151 | gpio_direction_input(IMX_GPIO_NR(4, 21)); |
| 149 | /* Set PCIE_WAKE# as Input*/ | 152 | /* Set PCIE_WAKE# as Input*/ |
| 150 | gpio_request(IMX_GPIO_NR(3, 5), "PCIE_WAKE#"); | 153 | gpio_request(IMX_GPIO_NR(3, 5), "PCIE_WAKE#"); |
| 151 | gpio_direction_input(IMX_GPIO_NR(3, 5)); | 154 | gpio_direction_input(IMX_GPIO_NR(3, 5)); |
| 152 | /* Set CAN0_INT# as Input*/ | 155 | /* Set CAN0_INT# as Input*/ |
| 153 | gpio_request(IMX_GPIO_NR(3, 18), "CAN0_INT#"); | 156 | gpio_request(IMX_GPIO_NR(3, 18), "CAN0_INT#"); |
| 154 | gpio_direction_input(IMX_GPIO_NR(3, 18)); | 157 | gpio_direction_input(IMX_GPIO_NR(3, 18)); |
| 155 | /* Set CAN1_INT# as Input*/ | 158 | /* Set CAN1_INT# as Input*/ |
| 156 | gpio_request(IMX_GPIO_NR(3, 16), "CAN1_INT#"); | 159 | gpio_request(IMX_GPIO_NR(3, 16), "CAN1_INT#"); |
| 157 | gpio_direction_input(IMX_GPIO_NR(3, 16)); | 160 | gpio_direction_input(IMX_GPIO_NR(3, 16)); |
| 158 | } | 161 | } |
| 159 | 162 | ||
| 160 | /* GPIO PINs, By SMARC specification, GPIO0~GPIO5 are recommended set as Output Low by default and GPIO6~GPIO11 are recommended set as Input*/ | 163 | /* GPIO PINs, By SMARC specification, GPIO0~GPIO5 are recommended set as Output Low by default and GPIO6~GPIO11 are recommended set as Input*/ |
| 161 | static iomux_v3_cfg_t const gpio_pads[] = { | 164 | static iomux_v3_cfg_t const gpio_pads[] = { |
| 162 | IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 | MUX_PAD_CTRL(WEAK_PULLUP), /*P108, GPIO0*/ | 165 | IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 | MUX_PAD_CTRL(WEAK_PULLUP), /*P108, GPIO0*/ |
| 163 | IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), /*P109, GPIO1*/ | 166 | IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), /*P109, GPIO1*/ |
| 164 | IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), /*P110, GPIO2*/ | 167 | IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), /*P110, GPIO2*/ |
| 165 | IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), /*P111, GPIO3*/ | 168 | IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), /*P111, GPIO3*/ |
| 166 | IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 | MUX_PAD_CTRL(WEAK_PULLUP), /*P112, GPIO4*/ | 169 | IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 | MUX_PAD_CTRL(WEAK_PULLUP), /*P112, GPIO4*/ |
| 167 | IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 | MUX_PAD_CTRL(WEAK_PULLUP), /*P113, GPIO5*/ | 170 | IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 | MUX_PAD_CTRL(WEAK_PULLUP), /*P113, GPIO5*/ |
| 168 | IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 | MUX_PAD_CTRL(WEAK_PULLUP), /*P114, GPIO6*/ | 171 | IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 | MUX_PAD_CTRL(WEAK_PULLUP), /*P114, GPIO6*/ |
| 169 | IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 | MUX_PAD_CTRL(WEAK_PULLUP), /*P115, GPIO7*/ | 172 | IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 | MUX_PAD_CTRL(WEAK_PULLUP), /*P115, GPIO7*/ |
| 170 | IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 | MUX_PAD_CTRL(WEAK_PULLUP), /*P116, GPIO8*/ | 173 | IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 | MUX_PAD_CTRL(WEAK_PULLUP), /*P116, GPIO8*/ |
| 171 | IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /*P114, GPIO9*/ | 174 | IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /*P114, GPIO9*/ |
| 172 | IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), /*P115, GPIO10*/ | 175 | IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), /*P115, GPIO10*/ |
| 173 | IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), /*P116, GPIO11*/ | 176 | IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), /*P116, GPIO11*/ |
| 174 | }; | 177 | }; |
| 175 | 178 | ||
| 176 | static void setup_iomux_gpio(void) | 179 | static void setup_iomux_gpio(void) |
| 177 | { | 180 | { |
| 178 | imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); | 181 | imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); |
| 179 | 182 | ||
| 180 | /* Set GPIO0 as Output Low*/ | 183 | /* Set GPIO0 as Output Low*/ |
| 181 | gpio_request(IMX_GPIO_NR(3, 25), "GPIO0"); | 184 | gpio_request(IMX_GPIO_NR(3, 25), "GPIO0"); |
| 182 | gpio_direction_output(IMX_GPIO_NR(3, 25), 0); | 185 | gpio_direction_output(IMX_GPIO_NR(3, 25), 0); |
| 183 | /* Set GPIO1 as Output Low*/ | 186 | /* Set GPIO1 as Output Low*/ |
| 184 | gpio_request(IMX_GPIO_NR(3, 19), "GPIO1"); | 187 | gpio_request(IMX_GPIO_NR(3, 19), "GPIO1"); |
| 185 | gpio_direction_output(IMX_GPIO_NR(3, 19), 0); | 188 | gpio_direction_output(IMX_GPIO_NR(3, 19), 0); |
| 186 | /* Set GPIO2 as Output Low*/ | 189 | /* Set GPIO2 as Output Low*/ |
| 187 | gpio_request(IMX_GPIO_NR(3, 20), "GPIO2"); | 190 | gpio_request(IMX_GPIO_NR(3, 20), "GPIO2"); |
| 188 | gpio_direction_output(IMX_GPIO_NR(3, 20), 0); | 191 | gpio_direction_output(IMX_GPIO_NR(3, 20), 0); |
| 189 | /* Set GPIO3 as Output Low*/ | 192 | /* Set GPIO3 as Output Low*/ |
| 190 | gpio_request(IMX_GPIO_NR(3, 21), "GPIO3"); | 193 | gpio_request(IMX_GPIO_NR(3, 21), "GPIO3"); |
| 191 | gpio_direction_output(IMX_GPIO_NR(3, 21), 0); | 194 | gpio_direction_output(IMX_GPIO_NR(3, 21), 0); |
| 192 | /* Set GPIO4 as Output Low*/ | 195 | /* Set GPIO4 as Output Low*/ |
| 193 | gpio_request(IMX_GPIO_NR(3, 22), "GPIO4"); | 196 | gpio_request(IMX_GPIO_NR(3, 22), "GPIO4"); |
| 194 | gpio_direction_output(IMX_GPIO_NR(3, 22), 0); | 197 | gpio_direction_output(IMX_GPIO_NR(3, 22), 0); |
| 195 | /* Set GPIO5 as Output Low*/ | 198 | /* Set GPIO5 as Output Low*/ |
| 196 | gpio_request(IMX_GPIO_NR(5, 3), "GPIO5"); | 199 | gpio_request(IMX_GPIO_NR(5, 3), "GPIO5"); |
| 197 | gpio_direction_output(IMX_GPIO_NR(5, 3), 0); | 200 | gpio_direction_output(IMX_GPIO_NR(5, 3), 0); |
| 198 | /* Set GPIO6 as Input*/ | 201 | /* Set GPIO6 as Input*/ |
| 199 | gpio_request(IMX_GPIO_NR(5, 4), "GPIO6"); | 202 | gpio_request(IMX_GPIO_NR(5, 4), "GPIO6"); |
| 200 | gpio_direction_input(IMX_GPIO_NR(5, 4)); | 203 | gpio_direction_input(IMX_GPIO_NR(5, 4)); |
| 201 | /* Set GPIO7 as Input*/ | 204 | /* Set GPIO7 as Input*/ |
| 202 | gpio_request(IMX_GPIO_NR(3, 23), "GPIO7"); | 205 | gpio_request(IMX_GPIO_NR(3, 23), "GPIO7"); |
| 203 | gpio_direction_input(IMX_GPIO_NR(3, 23)); | 206 | gpio_direction_input(IMX_GPIO_NR(3, 23)); |
| 204 | /* Set GPIO8 as Input*/ | 207 | /* Set GPIO8 as Input*/ |
| 205 | gpio_request(IMX_GPIO_NR(3, 24), "GPIO8"); | 208 | gpio_request(IMX_GPIO_NR(3, 24), "GPIO8"); |
| 206 | gpio_direction_input(IMX_GPIO_NR(3, 24)); | 209 | gpio_direction_input(IMX_GPIO_NR(3, 24)); |
| 207 | /* Set GPIO9 as Input*/ | 210 | /* Set GPIO9 as Input*/ |
| 208 | gpio_request(IMX_GPIO_NR(4, 11), "GPIO9"); | 211 | gpio_request(IMX_GPIO_NR(4, 11), "GPIO9"); |
| 209 | gpio_direction_input(IMX_GPIO_NR(4, 11)); | 212 | gpio_direction_input(IMX_GPIO_NR(4, 11)); |
| 210 | /* Set GPIO10 as Input*/ | 213 | /* Set GPIO10 as Input*/ |
| 211 | gpio_request(IMX_GPIO_NR(4, 10), "GPIO10"); | 214 | gpio_request(IMX_GPIO_NR(4, 10), "GPIO10"); |
| 212 | gpio_direction_input(IMX_GPIO_NR(4, 10)); | 215 | gpio_direction_input(IMX_GPIO_NR(4, 10)); |
| 213 | /* Set GPIO11 as Input*/ | 216 | /* Set GPIO11 as Input*/ |
| 214 | gpio_request(IMX_GPIO_NR(4, 20), "GPIO11"); | 217 | gpio_request(IMX_GPIO_NR(4, 20), "GPIO11"); |
| 215 | gpio_direction_input(IMX_GPIO_NR(4, 20)); | 218 | gpio_direction_input(IMX_GPIO_NR(4, 20)); |
| 216 | } | 219 | } |
| 217 | 220 | ||
| 218 | 221 | ||
| 219 | int board_early_init_f(void) | 222 | int board_early_init_f(void) |
| 220 | { | 223 | { |
| 221 | struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; | 224 | struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; |
| 222 | 225 | ||
| 223 | imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); | 226 | imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); |
| 224 | 227 | ||
| 225 | set_wdog_reset(wdog); | 228 | set_wdog_reset(wdog); |
| 226 | 229 | ||
| 227 | #ifdef CONFIG_CONSOLE_SER0 | 230 | #ifdef CONFIG_CONSOLE_SER0 |
| 228 | imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); | 231 | imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); |
| 229 | #endif | 232 | #endif |
| 230 | #ifdef CONFIG_CONSOLE_SER1 | 233 | #ifdef CONFIG_CONSOLE_SER1 |
| 231 | imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); | 234 | imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); |
| 232 | #endif | 235 | #endif |
| 233 | #ifdef CONFIG_CONSOLE_SER2 | 236 | #ifdef CONFIG_CONSOLE_SER2 |
| 234 | imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); | 237 | imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); |
| 235 | #endif | 238 | #endif |
| 236 | #ifdef CONFIG_CONSOLE_SER3 | 239 | #ifdef CONFIG_CONSOLE_SER3 |
| 237 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); | 240 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| 238 | #endif | 241 | #endif |
| 239 | 242 | ||
| 240 | return 0; | 243 | return 0; |
| 241 | } | 244 | } |
| 242 | 245 | ||
| 243 | #ifdef CONFIG_BOARD_POSTCLK_INIT | 246 | #ifdef CONFIG_BOARD_POSTCLK_INIT |
| 244 | int board_postclk_init(void) | 247 | int board_postclk_init(void) |
| 245 | { | 248 | { |
| 246 | /* TODO */ | 249 | /* TODO */ |
| 247 | return 0; | 250 | return 0; |
| 248 | } | 251 | } |
| 249 | #endif | 252 | #endif |
| 250 | 253 | ||
| 251 | int dram_init(void) | 254 | int dram_init(void) |
| 252 | { | 255 | { |
| 253 | /* rom_pointer[1] contains the size of TEE occupies */ | 256 | /* rom_pointer[1] contains the size of TEE occupies */ |
| 254 | if (rom_pointer[1]) | 257 | if (rom_pointer[1]) |
| 255 | gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; | 258 | gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; |
| 256 | else | 259 | else |
| 257 | gd->ram_size = PHYS_SDRAM_SIZE; | 260 | gd->ram_size = PHYS_SDRAM_SIZE; |
| 258 | 261 | ||
| 259 | return 0; | 262 | return 0; |
| 260 | } | 263 | } |
| 261 | 264 | ||
| 262 | #ifdef CONFIG_SYS_I2C | 265 | #ifdef CONFIG_SYS_I2C |
| 263 | /*I2C2, I2C_CAM0 and I2C_LCD*/ | 266 | /*I2C2, I2C_CAM0 and I2C_LCD*/ |
| 264 | struct i2c_pads_info i2c_pad_info2 = { | 267 | struct i2c_pads_info i2c_pad_info2 = { |
| 265 | .scl = { | 268 | .scl = { |
| 266 | .i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | I2C_PAD_CTRL, | 269 | .i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | I2C_PAD_CTRL, |
| 267 | .gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | I2C_PAD_CTRL, | 270 | .gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | I2C_PAD_CTRL, |
| 268 | .gp = IMX_GPIO_NR(5, 16), | 271 | .gp = IMX_GPIO_NR(5, 16), |
| 269 | }, | 272 | }, |
| 270 | .sda = { | 273 | .sda = { |
| 271 | .i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | I2C_PAD_CTRL, | 274 | .i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | I2C_PAD_CTRL, |
| 272 | .gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | I2C_PAD_CTRL, | 275 | .gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | I2C_PAD_CTRL, |
| 273 | .gp = IMX_GPIO_NR(5, 17), | 276 | .gp = IMX_GPIO_NR(5, 17), |
| 274 | }, | 277 | }, |
| 275 | }; | 278 | }; |
| 276 | 279 | ||
| 277 | /*I2C3, I2C_GP*/ | 280 | /*I2C3, I2C_GP*/ |
| 278 | struct i2c_pads_info i2c_pad_info3 = { | 281 | struct i2c_pads_info i2c_pad_info3 = { |
| 279 | .scl = { | 282 | .scl = { |
| 280 | .i2c_mode = IMX8MQ_PAD_I2C3_SCL__I2C3_SCL | I2C_PAD_CTRL, | 283 | .i2c_mode = IMX8MQ_PAD_I2C3_SCL__I2C3_SCL | I2C_PAD_CTRL, |
| 281 | .gpio_mode = IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 | I2C_PAD_CTRL, | 284 | .gpio_mode = IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 | I2C_PAD_CTRL, |
| 282 | .gp = IMX_GPIO_NR(5, 18), | 285 | .gp = IMX_GPIO_NR(5, 18), |
| 283 | }, | 286 | }, |
| 284 | .sda = { | 287 | .sda = { |
| 285 | .i2c_mode = IMX8MQ_PAD_I2C3_SDA__I2C3_SDA | I2C_PAD_CTRL, | 288 | .i2c_mode = IMX8MQ_PAD_I2C3_SDA__I2C3_SDA | I2C_PAD_CTRL, |
| 286 | .gpio_mode = IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 | I2C_PAD_CTRL, | 289 | .gpio_mode = IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 | I2C_PAD_CTRL, |
| 287 | .gp = IMX_GPIO_NR(5, 19), | 290 | .gp = IMX_GPIO_NR(5, 19), |
| 288 | }, | 291 | }, |
| 289 | }; | 292 | }; |
| 290 | 293 | ||
| 291 | /*I2C4, I2C_CAM1*/ | 294 | /*I2C4, I2C_CAM1*/ |
| 292 | struct i2c_pads_info i2c_pad_info4 = { | 295 | struct i2c_pads_info i2c_pad_info4 = { |
| 293 | .scl = { | 296 | .scl = { |
| 294 | .i2c_mode = IMX8MQ_PAD_I2C4_SCL__I2C4_SCL | I2C_PAD_CTRL, | 297 | .i2c_mode = IMX8MQ_PAD_I2C4_SCL__I2C4_SCL | I2C_PAD_CTRL, |
| 295 | .gpio_mode = IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 | I2C_PAD_CTRL, | 298 | .gpio_mode = IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 | I2C_PAD_CTRL, |
| 296 | .gp = IMX_GPIO_NR(5, 20), | 299 | .gp = IMX_GPIO_NR(5, 20), |
| 297 | }, | 300 | }, |
| 298 | .sda = { | 301 | .sda = { |
| 299 | .i2c_mode = IMX8MQ_PAD_I2C4_SDA__I2C4_SDA | I2C_PAD_CTRL, | 302 | .i2c_mode = IMX8MQ_PAD_I2C4_SDA__I2C4_SDA | I2C_PAD_CTRL, |
| 300 | .gpio_mode = IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 | I2C_PAD_CTRL, | 303 | .gpio_mode = IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 | I2C_PAD_CTRL, |
| 301 | .gp = IMX_GPIO_NR(5, 21), | 304 | .gp = IMX_GPIO_NR(5, 21), |
| 302 | }, | 305 | }, |
| 303 | }; | 306 | }; |
| 304 | #endif | 307 | #endif |
| 305 | 308 | ||
| 306 | #ifdef CONFIG_OF_BOARD_SETUP | 309 | #ifdef CONFIG_OF_BOARD_SETUP |
| 307 | int ft_board_setup(void *blob, bd_t *bd) | 310 | int ft_board_setup(void *blob, bd_t *bd) |
| 308 | { | 311 | { |
| 309 | return 0; | 312 | return 0; |
| 310 | } | 313 | } |
| 311 | #endif | 314 | #endif |
| 312 | 315 | ||
| 313 | /* Get the top of usable RAM */ | 316 | /* Get the top of usable RAM */ |
| 314 | ulong board_get_usable_ram_top(ulong total_size) | 317 | ulong board_get_usable_ram_top(ulong total_size) |
| 315 | { | 318 | { |
| 316 | 319 | ||
| 317 | //printf("board_get_usable_ram_top total_size is 0x%lx \n", total_size); | 320 | //printf("board_get_usable_ram_top total_size is 0x%lx \n", total_size); |
| 318 | 321 | ||
| 319 | if(gd->ram_top > 0x100000000) | 322 | if(gd->ram_top > 0x100000000) |
| 320 | gd->ram_top = 0x100000000; | 323 | gd->ram_top = 0x100000000; |
| 321 | 324 | ||
| 322 | return gd->ram_top; | 325 | return gd->ram_top; |
| 323 | } | 326 | } |
| 324 | 327 | ||
| 325 | #ifdef CONFIG_FEC_MXC | 328 | #ifdef CONFIG_FEC_MXC |
| 326 | #define FEC_RST_PAD IMX_GPIO_NR(1, 11) | 329 | #define FEC_RST_PAD IMX_GPIO_NR(1, 11) |
| 327 | static iomux_v3_cfg_t const fec1_irq_pads[] = { | 330 | static iomux_v3_cfg_t const fec1_irq_pads[] = { |
| 328 | IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), | 331 | IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), |
| 329 | }; | 332 | }; |
| 330 | 333 | ||
| 331 | static void setup_iomux_fec(void) | 334 | static void setup_iomux_fec(void) |
| 332 | { | 335 | { |
| 333 | imx_iomux_v3_setup_multiple_pads(fec1_irq_pads, | 336 | imx_iomux_v3_setup_multiple_pads(fec1_irq_pads, |
| 334 | ARRAY_SIZE(fec1_irq_pads)); | 337 | ARRAY_SIZE(fec1_irq_pads)); |
| 335 | 338 | ||
| 336 | gpio_request(IMX_GPIO_NR(1, 11), "fec1_irq"); | 339 | gpio_request(IMX_GPIO_NR(1, 11), "fec1_irq"); |
| 337 | gpio_direction_input(IMX_GPIO_NR(1, 11)); | 340 | gpio_direction_input(IMX_GPIO_NR(1, 11)); |
| 338 | } | 341 | } |
| 339 | 342 | ||
| 340 | static int setup_fec(void) | 343 | static int setup_fec(void) |
| 341 | { | 344 | { |
| 342 | struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs | 345 | struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs |
| 343 | = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; | 346 | = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; |
| 344 | 347 | ||
| 345 | setup_iomux_fec(); | 348 | setup_iomux_fec(); |
| 346 | 349 | ||
| 347 | /* Use 125M anatop REF_CLK1 for ENET1, not from external */ | 350 | /* Use 125M anatop REF_CLK1 for ENET1, not from external */ |
| 348 | clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], | 351 | clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], |
| 349 | IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0); | 352 | IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0); |
| 350 | return set_clk_enet(ENET_125MHZ); | 353 | return set_clk_enet(ENET_125MHZ); |
| 351 | } | 354 | } |
| 352 | 355 | ||
| 353 | 356 | ||
| 354 | int board_phy_config(struct phy_device *phydev) | 357 | int board_phy_config(struct phy_device *phydev) |
| 355 | { | 358 | { |
| 356 | /* enable rgmii rxc skew and phy mode select to RGMII copper */ | 359 | /* enable rgmii rxc skew and phy mode select to RGMII copper */ |
| 357 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); | 360 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); |
| 358 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); | 361 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); |
| 359 | 362 | ||
| 360 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); | 363 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); |
| 361 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); | 364 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); |
| 362 | 365 | ||
| 363 | if (phydev->drv->config) | 366 | if (phydev->drv->config) |
| 364 | phydev->drv->config(phydev); | 367 | phydev->drv->config(phydev); |
| 365 | return 0; | 368 | return 0; |
| 366 | } | 369 | } |
| 367 | #endif | 370 | #endif |
| 368 | 371 | ||
| 369 | static void setup_iomux_ecspi1(void) | 372 | static void setup_iomux_ecspi1(void) |
| 370 | { | 373 | { |
| 371 | imx_iomux_v3_setup_multiple_pads(ecspi1_pads, | 374 | imx_iomux_v3_setup_multiple_pads(ecspi1_pads, |
| 372 | ARRAY_SIZE(ecspi1_pads)); | 375 | ARRAY_SIZE(ecspi1_pads)); |
| 373 | } | 376 | } |
| 374 | 377 | ||
| 375 | int board_spi_cs_gpio(unsigned bus, unsigned cs) | 378 | int board_spi_cs_gpio(unsigned bus, unsigned cs) |
| 376 | { | 379 | { |
| 377 | gpio_request(IMX_GPIO_NR(5, 9), "espi1_cs0"); | 380 | gpio_request(IMX_GPIO_NR(5, 9), "espi1_cs0"); |
| 378 | return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(5, 9)) : -1; | 381 | return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(5, 9)) : -1; |
| 379 | gpio_request(IMX_GPIO_NR(1, 0), "espi1_cs1"); | 382 | gpio_request(IMX_GPIO_NR(1, 0), "espi1_cs1"); |
| 380 | return (bus == 0 && cs == 1) ? (IMX_GPIO_NR(1, 0)) : -1; | 383 | return (bus == 0 && cs == 1) ? (IMX_GPIO_NR(1, 0)) : -1; |
| 381 | gpio_request(IMX_GPIO_NR(3, 15), "espi1_cs2"); | 384 | gpio_request(IMX_GPIO_NR(3, 15), "espi1_cs2"); |
| 382 | return (bus == 0 && cs == 2) ? (IMX_GPIO_NR(3, 15)) : -1; | 385 | return (bus == 0 && cs == 2) ? (IMX_GPIO_NR(3, 15)) : -1; |
| 383 | gpio_request(IMX_GPIO_NR(3, 17), "espi1_cs3"); | 386 | gpio_request(IMX_GPIO_NR(3, 17), "espi1_cs3"); |
| 384 | return (bus == 0 && cs == 3) ? (IMX_GPIO_NR(3, 17)) : -1; | 387 | return (bus == 0 && cs == 3) ? (IMX_GPIO_NR(3, 17)) : -1; |
| 385 | } | 388 | } |
| 386 | 389 | ||
| 387 | #ifdef CONFIG_USB_DWC3 | 390 | #ifdef CONFIG_USB_DWC3 |
| 388 | 391 | ||
| 389 | #define USB_PHY_CTRL0 0xF0040 | 392 | #define USB_PHY_CTRL0 0xF0040 |
| 390 | #define USB_PHY_CTRL0_REF_SSP_EN BIT(2) | 393 | #define USB_PHY_CTRL0_REF_SSP_EN BIT(2) |
| 391 | 394 | ||
| 392 | #define USB_PHY_CTRL1 0xF0044 | 395 | #define USB_PHY_CTRL1 0xF0044 |
| 393 | #define USB_PHY_CTRL1_RESET BIT(0) | 396 | #define USB_PHY_CTRL1_RESET BIT(0) |
| 394 | #define USB_PHY_CTRL1_COMMONONN BIT(1) | 397 | #define USB_PHY_CTRL1_COMMONONN BIT(1) |
| 395 | #define USB_PHY_CTRL1_ATERESET BIT(3) | 398 | #define USB_PHY_CTRL1_ATERESET BIT(3) |
| 396 | #define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) | 399 | #define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) |
| 397 | #define USB_PHY_CTRL1_VDATDETENB0 BIT(20) | 400 | #define USB_PHY_CTRL1_VDATDETENB0 BIT(20) |
| 398 | 401 | ||
| 399 | #define USB_PHY_CTRL2 0xF0048 | 402 | #define USB_PHY_CTRL2 0xF0048 |
| 400 | #define USB_PHY_CTRL2_TXENABLEN0 BIT(8) | 403 | #define USB_PHY_CTRL2_TXENABLEN0 BIT(8) |
| 401 | 404 | ||
| 402 | static struct dwc3_device dwc3_device_data = { | 405 | static struct dwc3_device dwc3_device_data = { |
| 403 | #ifdef CONFIG_SPL_BUILD | 406 | #ifdef CONFIG_SPL_BUILD |
| 404 | .maximum_speed = USB_SPEED_HIGH, | 407 | .maximum_speed = USB_SPEED_HIGH, |
| 405 | #else | 408 | #else |
| 406 | .maximum_speed = USB_SPEED_SUPER, | 409 | .maximum_speed = USB_SPEED_SUPER, |
| 407 | #endif | 410 | #endif |
| 408 | .base = USB1_BASE_ADDR, | 411 | .base = USB1_BASE_ADDR, |
| 409 | .dr_mode = USB_DR_MODE_PERIPHERAL, | 412 | .dr_mode = USB_DR_MODE_PERIPHERAL, |
| 410 | .index = 0, | 413 | .index = 0, |
| 411 | .power_down_scale = 2, | 414 | .power_down_scale = 2, |
| 412 | }; | 415 | }; |
| 413 | 416 | ||
| 414 | int usb_gadget_handle_interrupts(void) | 417 | int usb_gadget_handle_interrupts(void) |
| 415 | { | 418 | { |
| 416 | dwc3_uboot_handle_interrupt(0); | 419 | dwc3_uboot_handle_interrupt(0); |
| 417 | return 0; | 420 | return 0; |
| 418 | } | 421 | } |
| 419 | 422 | ||
| 420 | static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) | 423 | static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) |
| 421 | { | 424 | { |
| 422 | u32 RegData; | 425 | u32 RegData; |
| 423 | 426 | ||
| 424 | RegData = readl(dwc3->base + USB_PHY_CTRL1); | 427 | RegData = readl(dwc3->base + USB_PHY_CTRL1); |
| 425 | RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | | 428 | RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | |
| 426 | USB_PHY_CTRL1_COMMONONN); | 429 | USB_PHY_CTRL1_COMMONONN); |
| 427 | RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; | 430 | RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; |
| 428 | writel(RegData, dwc3->base + USB_PHY_CTRL1); | 431 | writel(RegData, dwc3->base + USB_PHY_CTRL1); |
| 429 | 432 | ||
| 430 | RegData = readl(dwc3->base + USB_PHY_CTRL0); | 433 | RegData = readl(dwc3->base + USB_PHY_CTRL0); |
| 431 | RegData |= USB_PHY_CTRL0_REF_SSP_EN; | 434 | RegData |= USB_PHY_CTRL0_REF_SSP_EN; |
| 432 | writel(RegData, dwc3->base + USB_PHY_CTRL0); | 435 | writel(RegData, dwc3->base + USB_PHY_CTRL0); |
| 433 | 436 | ||
| 434 | RegData = readl(dwc3->base + USB_PHY_CTRL2); | 437 | RegData = readl(dwc3->base + USB_PHY_CTRL2); |
| 435 | RegData |= USB_PHY_CTRL2_TXENABLEN0; | 438 | RegData |= USB_PHY_CTRL2_TXENABLEN0; |
| 436 | writel(RegData, dwc3->base + USB_PHY_CTRL2); | 439 | writel(RegData, dwc3->base + USB_PHY_CTRL2); |
| 437 | 440 | ||
| 438 | RegData = readl(dwc3->base + USB_PHY_CTRL1); | 441 | RegData = readl(dwc3->base + USB_PHY_CTRL1); |
| 439 | RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); | 442 | RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); |
| 440 | writel(RegData, dwc3->base + USB_PHY_CTRL1); | 443 | writel(RegData, dwc3->base + USB_PHY_CTRL1); |
| 441 | } | 444 | } |
| 442 | #endif | 445 | #endif |
| 443 | 446 | ||
| 444 | /*USB Enable Over-Current Pin Setting*/ | 447 | /*USB Enable Over-Current Pin Setting*/ |
| 445 | static iomux_v3_cfg_t const usb_en_oc_pads[] = { | 448 | static iomux_v3_cfg_t const usb_en_oc_pads[] = { |
| 446 | IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), | 449 | IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), |
| 447 | IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), | 450 | IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), |
| 448 | IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), | 451 | IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), |
| 449 | }; | 452 | }; |
| 450 | 453 | ||
| 451 | static void setup_iomux_usb_en_oc(void) | 454 | static void setup_iomux_usb_en_oc(void) |
| 452 | { | 455 | { |
| 453 | imx_iomux_v3_setup_multiple_pads(usb_en_oc_pads, | 456 | imx_iomux_v3_setup_multiple_pads(usb_en_oc_pads, |
| 454 | ARRAY_SIZE(usb_en_oc_pads)); | 457 | ARRAY_SIZE(usb_en_oc_pads)); |
| 455 | 458 | ||
| 456 | gpio_request(IMX_GPIO_NR(3, 10), "usb0_en_oc#"); | 459 | gpio_request(IMX_GPIO_NR(3, 10), "usb0_en_oc#"); |
| 457 | gpio_direction_input(IMX_GPIO_NR(3, 10)); | 460 | gpio_direction_input(IMX_GPIO_NR(3, 10)); |
| 458 | gpio_request(IMX_GPIO_NR(3, 12), "usb2_en_oc#"); | 461 | gpio_request(IMX_GPIO_NR(3, 12), "usb2_en_oc#"); |
| 459 | gpio_direction_input(IMX_GPIO_NR(3, 12)); | 462 | gpio_direction_input(IMX_GPIO_NR(3, 12)); |
| 460 | gpio_request(IMX_GPIO_NR(3, 13), "usb3_en_oc#"); | 463 | gpio_request(IMX_GPIO_NR(3, 13), "usb3_en_oc#"); |
| 461 | gpio_direction_input(IMX_GPIO_NR(3, 13)); | 464 | gpio_direction_input(IMX_GPIO_NR(3, 13)); |
| 462 | } | 465 | } |
| 463 | 466 | ||
| 464 | #ifdef CONFIG_USB_TCPC | 467 | #ifdef CONFIG_USB_TCPC |
| 465 | struct tcpc_port port; | 468 | struct tcpc_port port; |
| 466 | struct tcpc_port_config port_config = { | 469 | struct tcpc_port_config port_config = { |
| 467 | .i2c_bus = 0, | 470 | .i2c_bus = 0, |
| 468 | .addr = 0x50, | 471 | .addr = 0x50, |
| 469 | .port_type = TYPEC_PORT_UFP, | 472 | .port_type = TYPEC_PORT_UFP, |
| 470 | .max_snk_mv = 20000, | 473 | .max_snk_mv = 20000, |
| 471 | .max_snk_ma = 3000, | 474 | .max_snk_ma = 3000, |
| 472 | .max_snk_mw = 15000, | 475 | .max_snk_mw = 15000, |
| 473 | .op_snk_mv = 9000, | 476 | .op_snk_mv = 9000, |
| 474 | }; | 477 | }; |
| 475 | 478 | ||
| 476 | #define USB_TYPEC_SEL IMX_GPIO_NR(3, 15) | 479 | #define USB_TYPEC_SEL IMX_GPIO_NR(3, 15) |
| 477 | 480 | ||
| 478 | static iomux_v3_cfg_t ss_mux_gpio[] = { | 481 | static iomux_v3_cfg_t ss_mux_gpio[] = { |
| 479 | IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), | 482 | IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 480 | }; | 483 | }; |
| 481 | 484 | ||
| 482 | void ss_mux_select(enum typec_cc_polarity pol) | 485 | void ss_mux_select(enum typec_cc_polarity pol) |
| 483 | { | 486 | { |
| 484 | if (pol == TYPEC_POLARITY_CC1) | 487 | if (pol == TYPEC_POLARITY_CC1) |
| 485 | gpio_direction_output(USB_TYPEC_SEL, 1); | 488 | gpio_direction_output(USB_TYPEC_SEL, 1); |
| 486 | else | 489 | else |
| 487 | gpio_direction_output(USB_TYPEC_SEL, 0); | 490 | gpio_direction_output(USB_TYPEC_SEL, 0); |
| 488 | } | 491 | } |
| 489 | 492 | ||
| 490 | static int setup_typec(void) | 493 | static int setup_typec(void) |
| 491 | { | 494 | { |
| 492 | int ret; | 495 | int ret; |
| 493 | 496 | ||
| 494 | imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); | 497 | imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); |
| 495 | gpio_request(USB_TYPEC_SEL, "typec_sel"); | 498 | gpio_request(USB_TYPEC_SEL, "typec_sel"); |
| 496 | 499 | ||
| 497 | ret = tcpc_init(&port, port_config, &ss_mux_select); | 500 | ret = tcpc_init(&port, port_config, &ss_mux_select); |
| 498 | if (ret) { | 501 | if (ret) { |
| 499 | printf("%s: tcpc init failed, err=%d\n", | 502 | printf("%s: tcpc init failed, err=%d\n", |
| 500 | __func__, ret); | 503 | __func__, ret); |
| 501 | } | 504 | } |
| 502 | 505 | ||
| 503 | return ret; | 506 | return ret; |
| 504 | } | 507 | } |
| 505 | #endif | 508 | #endif |
| 506 | 509 | ||
| 507 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) | 510 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) |
| 508 | int board_usb_init(int index, enum usb_init_type init) | 511 | int board_usb_init(int index, enum usb_init_type init) |
| 509 | { | 512 | { |
| 510 | int ret = 0; | 513 | int ret = 0; |
| 511 | imx8m_usb_power(index, true); | 514 | imx8m_usb_power(index, true); |
| 512 | 515 | ||
| 513 | if (index == 0 && init == USB_INIT_DEVICE) { | 516 | if (index == 0 && init == USB_INIT_DEVICE) { |
| 514 | #ifdef CONFIG_USB_TCPC | 517 | #ifdef CONFIG_USB_TCPC |
| 515 | ret = tcpc_setup_ufp_mode(&port); | 518 | ret = tcpc_setup_ufp_mode(&port); |
| 516 | #endif | 519 | #endif |
| 517 | dwc3_nxp_usb_phy_init(&dwc3_device_data); | 520 | dwc3_nxp_usb_phy_init(&dwc3_device_data); |
| 518 | return dwc3_uboot_init(&dwc3_device_data); | 521 | return dwc3_uboot_init(&dwc3_device_data); |
| 519 | } else if (index == 0 && init == USB_INIT_HOST) { | 522 | } else if (index == 0 && init == USB_INIT_HOST) { |
| 520 | #ifdef CONFIG_USB_TCPC | 523 | #ifdef CONFIG_USB_TCPC |
| 521 | ret = tcpc_setup_dfp_mode(&port); | 524 | ret = tcpc_setup_dfp_mode(&port); |
| 522 | #endif | 525 | #endif |
| 523 | return ret; | 526 | return ret; |
| 524 | } | 527 | } |
| 525 | 528 | ||
| 526 | return 0; | 529 | return 0; |
| 527 | } | 530 | } |
| 528 | 531 | ||
| 529 | int board_usb_cleanup(int index, enum usb_init_type init) | 532 | int board_usb_cleanup(int index, enum usb_init_type init) |
| 530 | { | 533 | { |
| 531 | int ret = 0; | 534 | int ret = 0; |
| 532 | if (index == 0 && init == USB_INIT_DEVICE) { | 535 | if (index == 0 && init == USB_INIT_DEVICE) { |
| 533 | dwc3_uboot_exit(index); | 536 | dwc3_uboot_exit(index); |
| 534 | } else if (index == 0 && init == USB_INIT_HOST) { | 537 | } else if (index == 0 && init == USB_INIT_HOST) { |
| 535 | #ifdef CONFIG_USB_TCPC | 538 | #ifdef CONFIG_USB_TCPC |
| 536 | ret = tcpc_disable_src_vbus(&port); | 539 | ret = tcpc_disable_src_vbus(&port); |
| 537 | #endif | 540 | #endif |
| 538 | } | 541 | } |
| 539 | 542 | ||
| 540 | imx8m_usb_power(index, false); | 543 | imx8m_usb_power(index, false); |
| 541 | 544 | ||
| 542 | return ret; | 545 | return ret; |
| 543 | } | 546 | } |
| 544 | #endif | 547 | #endif |
| 545 | 548 | ||
| 546 | int board_init(void) | 549 | int board_init(void) |
| 547 | { | 550 | { |
| 548 | board_qspi_init(); | 551 | board_qspi_init(); |
| 549 | setup_iomux_usb_en_oc(); | 552 | setup_iomux_usb_en_oc(); |
| 550 | setup_iomux_misc(); | 553 | setup_iomux_misc(); |
| 551 | setup_iomux_gpio(); | 554 | setup_iomux_gpio(); |
| 552 | 555 | ||
| 553 | #ifdef CONFIG_FEC_MXC | 556 | #ifdef CONFIG_FEC_MXC |
| 554 | setup_fec(); | 557 | setup_fec(); |
| 555 | #endif | 558 | #endif |
| 556 | 559 | ||
| 557 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) | 560 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) |
| 558 | init_usb_clk(); | 561 | init_usb_clk(); |
| 559 | #endif | 562 | #endif |
| 560 | 563 | ||
| 561 | #ifdef CONFIG_USB_TCPC | 564 | #ifdef CONFIG_USB_TCPC |
| 562 | setup_typec(); | 565 | setup_typec(); |
| 563 | #endif | 566 | #endif |
| 564 | return 0; | 567 | return 0; |
| 565 | } | 568 | } |
| 566 | 569 | ||
| 567 | int board_mmc_get_env_dev(int devno) | 570 | int board_mmc_get_env_dev(int devno) |
| 568 | { | 571 | { |
| 569 | return devno; | 572 | return devno; |
| 570 | } | 573 | } |
| 571 | 574 | ||
| 572 | int board_late_init(void) | 575 | int board_late_init(void) |
| 573 | { | 576 | { |
| 574 | setup_iomux_ecspi1(); | 577 | setup_iomux_ecspi1(); |
| 575 | 578 | ||
| 576 | /* Read Module Information from on module EEPROM and pass | 579 | /* Read Module Information from on module EEPROM and pass |
| 577 | * mac address to kernel | 580 | * mac address to kernel |
| 578 | */ | 581 | */ |
| 579 | struct udevice *dev; | 582 | struct udevice *dev; |
| 580 | int ret; | 583 | int ret; |
| 581 | u8 name[8]; | 584 | u8 name[8]; |
| 582 | u8 serial[12]; | 585 | u8 serial[12]; |
| 583 | u8 revision[4]; | 586 | u8 revision[4]; |
| 584 | u8 mac[6]; | 587 | u8 mac[6]; |
| 585 | 588 | ||
| 586 | ret = i2c_get_chip_for_busnum(2, 0x50, 2, &dev); | 589 | ret = i2c_get_chip_for_busnum(2, 0x50, 2, &dev); |
| 587 | if (ret) { | 590 | if (ret) { |
| 588 | debug("failed to get eeprom\n"); | 591 | debug("failed to get eeprom\n"); |
| 589 | return 0; | 592 | return 0; |
| 590 | } | 593 | } |
| 591 | 594 | ||
| 592 | /* Board ID */ | 595 | /* Board ID */ |
| 593 | ret = dm_i2c_read(dev, 0x4, name, 8); | 596 | ret = dm_i2c_read(dev, 0x4, name, 8); |
| 594 | if (ret) { | 597 | if (ret) { |
| 595 | debug("failed to read board ID from EEPROM\n"); | 598 | debug("failed to read board ID from EEPROM\n"); |
| 596 | return 0; | 599 | return 0; |
| 597 | } | 600 | } |
| 598 | puts("---------Embedian SMARC-iMX8M------------\n"); | 601 | puts("---------Embedian SMARC-iMX8M------------\n"); |
| 599 | printf(" Board ID: %c%c%c%c%c%c%c%c\n", | 602 | printf(" Board ID: %c%c%c%c%c%c%c%c\n", |
| 600 | name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]); | 603 | name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]); |
| 601 | 604 | ||
| 602 | /* Board Hardware Revision */ | 605 | /* Board Hardware Revision */ |
| 603 | ret = dm_i2c_read(dev, 0xc, revision, 4); | 606 | ret = dm_i2c_read(dev, 0xc, revision, 4); |
| 604 | if (ret) { | 607 | if (ret) { |
| 605 | debug("failed to read hardware revison from EEPROM\n"); | 608 | debug("failed to read hardware revison from EEPROM\n"); |
| 606 | return 0; | 609 | return 0; |
| 607 | } | 610 | } |
| 608 | printf(" Hardware Revision: %c%c%c%c\n", | 611 | printf(" Hardware Revision: %c%c%c%c\n", |
| 609 | revision[0], revision[1], revision[2], revision[3]); | 612 | revision[0], revision[1], revision[2], revision[3]); |
| 610 | 613 | ||
| 611 | /* Serial number */ | 614 | /* Serial number */ |
| 612 | ret = dm_i2c_read(dev, 0x10, serial, 12); | 615 | ret = dm_i2c_read(dev, 0x10, serial, 12); |
| 613 | if (ret) { | 616 | if (ret) { |
| 614 | debug("failed to read srial number from EEPROM\n"); | 617 | debug("failed to read srial number from EEPROM\n"); |
| 615 | return 0; | 618 | return 0; |
| 616 | } | 619 | } |
| 617 | printf(" Serial Number#: %c%c%c%c%c%c%c%c%c%c%c%c\n", | 620 | printf(" Serial Number#: %c%c%c%c%c%c%c%c%c%c%c%c\n", |
| 618 | serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]); | 621 | serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]); |
| 619 | 622 | ||
| 620 | /*MAC address */ | 623 | /*MAC address */ |
| 621 | ret = dm_i2c_read(dev, 0x3c, mac, 6); | 624 | ret = dm_i2c_read(dev, 0x3c, mac, 6); |
| 622 | if (ret) { | 625 | if (ret) { |
| 623 | debug("failed to read eth0 mac address from EEPROM\n"); | 626 | debug("failed to read eth0 mac address from EEPROM\n"); |
| 624 | return 0; | 627 | return 0; |
| 625 | } | 628 | } |
| 626 | 629 | ||
| 627 | if (is_valid_ethaddr(mac)) | 630 | if (is_valid_ethaddr(mac)) |
| 628 | printf(" MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n", | 631 | printf(" MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n", |
| 629 | mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); | 632 | mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); |
| 630 | eth_env_set_enetaddr("ethaddr", mac); | 633 | eth_env_set_enetaddr("ethaddr", mac); |
| 631 | puts("-----------------------------------------\n"); | 634 | puts("-----------------------------------------\n"); |
| 632 | 635 | ||
| 633 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | 636 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| 634 | env_set("board_name", "SMARC-iMX8M"); | 637 | env_set("board_name", "SMARC-iMX8M"); |
| 635 | env_set("board_rev", "iMX8MQ"); | 638 | env_set("board_rev", "iMX8MQ"); |
| 636 | #endif | 639 | #endif |
| 637 | 640 | ||
| 638 | #ifdef CONFIG_ENV_IS_IN_MMC | 641 | #ifdef CONFIG_ENV_IS_IN_MMC |
| 639 | board_late_mmc_env_init(); | 642 | board_late_mmc_env_init(); |
| 640 | #endif | 643 | #endif |
| 641 | 644 | ||
| 642 | /* SMARC BOOT_SEL*/ | 645 | /* SMARC BOOT_SEL*/ |
| 643 | gpio_request(IMX_GPIO_NR(1, 8), "BOOT_SEL_1"); | 646 | gpio_request(IMX_GPIO_NR(1, 8), "BOOT_SEL_1"); |
| 644 | gpio_request(IMX_GPIO_NR(1, 5), "BOOT_SEL_2"); | 647 | gpio_request(IMX_GPIO_NR(1, 5), "BOOT_SEL_2"); |
| 645 | gpio_request(IMX_GPIO_NR(1, 6), "BOOT_SEL_3"); | 648 | gpio_request(IMX_GPIO_NR(1, 6), "BOOT_SEL_3"); |
| 646 | if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 649 | if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 647 | puts("BOOT_SEL Detected: OFF OFF OFF, Boot from Carrier SATA is not supported...\n"); | 650 | puts("BOOT_SEL Detected: OFF OFF OFF, Boot from Carrier SATA is not supported...\n"); |
| 648 | hang(); | 651 | hang(); |
| 649 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | 652 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { |
| 650 | puts("BOOT_SEL Detected: OFF OFF ON, Load Image from USB0...\n"); | 653 | puts("BOOT_SEL Detected: OFF OFF ON, Load Image from USB0...\n"); |
| 651 | env_set_ulong("usb dev", 1); | 654 | env_set_ulong("usb dev", 1); |
| 652 | env_set("bootcmd", "usb start; run loadusbbootenv; run importusbbootenv; run uenvcmd; loadusbimage; run usbboot;"); | 655 | env_set("bootcmd", "usb start; run loadusbbootenv; run importusbbootenv; run uenvcmd; loadusbimage; run usbboot;"); |
| 653 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 656 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 654 | puts("BOOT_SEL Detected: OFF ON OFF, Boot from Carrier eSPI is not supported...\n"); | 657 | puts("BOOT_SEL Detected: OFF ON OFF, Boot from Carrier eSPI is not supported...\n"); |
| 655 | hang(); | 658 | hang(); |
| 656 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 659 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 657 | puts("BOOT_SEL Detected: ON OFF OFF, Load Image from Carrier SD Card...\n"); | 660 | puts("BOOT_SEL Detected: ON OFF OFF, Load Image from Carrier SD Card...\n"); |
| 658 | env_set_ulong("mmcdev", 1); | 661 | env_set_ulong("mmcdev", 1); |
| 659 | env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;"); | 662 | env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;"); |
| 660 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | 663 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { |
| 661 | puts("BOOT_SEL Detected: OFF ON ON, Load Image from Module eMMC Flash...\n"); | 664 | puts("BOOT_SEL Detected: OFF ON ON, Load Image from Module eMMC Flash...\n"); |
| 662 | env_set_ulong("mmcdev", 0); | 665 | env_set_ulong("mmcdev", 0); |
| 663 | env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;"); | 666 | env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;"); |
| 664 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | 667 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { |
| 665 | puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); | 668 | puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); |
| 666 | env_set("bootcmd", "run netboot;"); | 669 | env_set("bootcmd", "run netboot;"); |
| 667 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | 670 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { |
| 668 | puts("Carrier SPI Boot is not supported...\n"); | 671 | puts("Carrier SPI Boot is not supported...\n"); |
| 669 | hang(); | 672 | hang(); |
| 670 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | 673 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { |
| 671 | puts("BOOT_SEL Detected: ON ON ON, Boot from Module SPI is not supported...\n"); | 674 | puts("BOOT_SEL Detected: ON ON ON, Boot from Module SPI is not supported...\n"); |
| 672 | hang(); | 675 | hang(); |
| 673 | } else { | 676 | } else { |
| 674 | puts("unsupported boot devices\n"); | 677 | puts("unsupported boot devices\n"); |
| 675 | hang(); | 678 | hang(); |
| 676 | } | 679 | } |
| 677 | 680 | ||
| 678 | return 0; | 681 | return 0; |
| 679 | } | 682 | } |
| 680 | 683 | ||
| 681 | #ifdef CONFIG_FSL_FASTBOOT | 684 | #ifdef CONFIG_FSL_FASTBOOT |
| 682 | #ifdef CONFIG_ANDROID_RECOVERY | 685 | #ifdef CONFIG_ANDROID_RECOVERY |
| 683 | #define LID_KEY IMX_GPIO_NR(1, 9) | 686 | #define LID_KEY IMX_GPIO_NR(1, 9) |
| 684 | #define LID_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) | 687 | #define LID_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) |
| 685 | 688 | ||
| 686 | static iomux_v3_cfg_t const lid_pads[] = { | 689 | static iomux_v3_cfg_t const lid_pads[] = { |
| 687 | IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(LID_PAD_CTRL), | 690 | IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(LID_PAD_CTRL), |
| 688 | }; | 691 | }; |
| 689 | 692 | ||
| 690 | int is_recovery_key_pressing(void) | 693 | int is_recovery_key_pressing(void) |
| 691 | { | 694 | { |
| 692 | imx_iomux_v3_setup_multiple_pads(lid_pads, ARRAY_SIZE(lid_pads)); | 695 | imx_iomux_v3_setup_multiple_pads(lid_pads, ARRAY_SIZE(lid_pads)); |
| 693 | gpio_request(LID_KEY, "LID"); | 696 | gpio_request(LID_KEY, "LID"); |
| 694 | gpio_direction_input(LID_KEY); | 697 | gpio_direction_input(LID_KEY); |
| 695 | if (gpio_get_value(LID_KEY) == 0) { /* LID key is low assert */ | 698 | if (gpio_get_value(LID_KEY) == 0) { /* LID key is low assert */ |
| 696 | printf("Recovery key pressed\n"); | 699 | printf("Recovery key pressed\n"); |
| 697 | return 1; | 700 | return 1; |
| 698 | } | 701 | } |
| 699 | return 0; | 702 | return 0; |
| 700 | } | 703 | } |
| 701 | #endif /*CONFIG_ANDROID_RECOVERY*/ | 704 | #endif /*CONFIG_ANDROID_RECOVERY*/ |
| 702 | #endif /*CONFIG_FSL_FASTBOOT*/ | 705 | #endif /*CONFIG_FSL_FASTBOOT*/ |
| 703 | 706 | ||
| 704 | #if defined(CONFIG_VIDEO_IMXDCSS) | 707 | #if defined(CONFIG_VIDEO_IMXDCSS) |
| 705 | 708 | ||
| 706 | struct display_info_t const displays[] = {{ | 709 | struct display_info_t const displays[] = {{ |
| 707 | .bus = 0, /* Unused */ | 710 | .bus = 0, /* Unused */ |
| 708 | .addr = 0, /* Unused */ | 711 | .addr = 0, /* Unused */ |
| 709 | .pixfmt = GDF_32BIT_X888RGB, | 712 | .pixfmt = GDF_32BIT_X888RGB, |
| 710 | .detect = NULL, | 713 | .detect = NULL, |
| 711 | .enable = NULL, | 714 | .enable = NULL, |
| 712 | #ifndef CONFIG_VIDEO_IMXDCSS_1080P | 715 | #ifndef CONFIG_VIDEO_IMXDCSS_1080P |
| 713 | .mode = { | 716 | .mode = { |
| 714 | .name = "HDMI", /* 720P60 */ | 717 | .name = "HDMI", /* 720P60 */ |
| 715 | .refresh = 60, | 718 | .refresh = 60, |
| 716 | .xres = 1280, | 719 | .xres = 1280, |
| 717 | .yres = 720, | 720 | .yres = 720, |
| 718 | .pixclock = 13468, /* 74250 kHz */ | 721 | .pixclock = 13468, /* 74250 kHz */ |
| 719 | .left_margin = 110, | 722 | .left_margin = 110, |
| 720 | .right_margin = 220, | 723 | .right_margin = 220, |
| 721 | .upper_margin = 5, | 724 | .upper_margin = 5, |
| 722 | .lower_margin = 20, | 725 | .lower_margin = 20, |
| 723 | .hsync_len = 40, | 726 | .hsync_len = 40, |
| 724 | .vsync_len = 5, | 727 | .vsync_len = 5, |
| 725 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | 728 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
| 726 | .vmode = FB_VMODE_NONINTERLACED | 729 | .vmode = FB_VMODE_NONINTERLACED |
| 727 | } | 730 | } |
| 728 | #else | 731 | #else |
| 729 | .mode = { | 732 | .mode = { |
| 730 | .name = "HDMI", /* 1080P60 */ | 733 | .name = "HDMI", /* 1080P60 */ |
| 731 | .refresh = 60, | 734 | .refresh = 60, |
| 732 | .xres = 1920, | 735 | .xres = 1920, |
| 733 | .yres = 1080, | 736 | .yres = 1080, |
| 734 | .pixclock = 6734, /* 148500 kHz */ | 737 | .pixclock = 6734, /* 148500 kHz */ |
| 735 | .left_margin = 148, | 738 | .left_margin = 148, |
| 736 | .right_margin = 88, | 739 | .right_margin = 88, |
| 737 | .upper_margin = 36, | 740 | .upper_margin = 36, |
| 738 | .lower_margin = 4, | 741 | .lower_margin = 4, |
| 739 | .hsync_len = 44, | 742 | .hsync_len = 44, |
| 740 | .vsync_len = 5, | 743 | .vsync_len = 5, |
| 741 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | 744 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, |
| 742 | .vmode = FB_VMODE_NONINTERLACED | 745 | .vmode = FB_VMODE_NONINTERLACED |
| 743 | } | 746 | } |
| 744 | #endif | 747 | #endif |
| 745 | } }; | 748 | } }; |
| 746 | size_t display_count = ARRAY_SIZE(displays); | 749 | size_t display_count = ARRAY_SIZE(displays); |
| 747 | 750 | ||
| 748 | #endif /* CONFIG_VIDEO_IMXDCSS */ | 751 | #endif /* CONFIG_VIDEO_IMXDCSS */ |
| 749 | 752 | ||
| 750 | /* return hard code board id for imx8m_ref */ | 753 | /* return hard code board id for imx8m_ref */ |
| 751 | #if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M) | 754 | #if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M) |
| 752 | int get_imx8m_baseboard_id(void) | 755 | int get_imx8m_baseboard_id(void) |
| 753 | { | 756 | { |
| 754 | return IMX8M_REF_3G; | 757 | return IMX8M_REF_3G; |
| 755 | } | 758 | } |
| 756 | #endif | 759 | #endif |
| 757 | 760 |