Commit 4f106bc8becc194057cd306f9188b1393b7df558
1 parent
79d4eb627c
Exists in
v2017.01-smarct4x
and in
30 other branches
x86: pch9: Implement get_io_base op
IO_BASE is only seen on PCH9 device, implement the get_io_base op. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
Showing 1 changed file with 17 additions and 0 deletions Side-by-side Diff
drivers/pch/pch9.c
... | ... | @@ -9,6 +9,7 @@ |
9 | 9 | #include <pch.h> |
10 | 10 | |
11 | 11 | #define GPIO_BASE 0x48 |
12 | +#define IO_BASE 0x4c | |
12 | 13 | #define SBASE_ADDR 0x54 |
13 | 14 | |
14 | 15 | static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep) |
15 | 16 | |
... | ... | @@ -52,9 +53,25 @@ |
52 | 53 | return 0; |
53 | 54 | } |
54 | 55 | |
56 | +static int pch9_get_io_base(struct udevice *dev, u32 *iobasep) | |
57 | +{ | |
58 | + u32 base; | |
59 | + | |
60 | + dm_pci_read_config32(dev, IO_BASE, &base); | |
61 | + if (base == 0x00000000 || base == 0xffffffff) { | |
62 | + debug("%s: unexpected BASE value\n", __func__); | |
63 | + return -ENODEV; | |
64 | + } | |
65 | + | |
66 | + *iobasep = base & 1 ? base & ~3 : base & ~15; | |
67 | + | |
68 | + return 0; | |
69 | +} | |
70 | + | |
55 | 71 | static const struct pch_ops pch9_ops = { |
56 | 72 | .get_spi_base = pch9_get_spi_base, |
57 | 73 | .get_gpio_base = pch9_get_gpio_base, |
74 | + .get_io_base = pch9_get_io_base, | |
58 | 75 | }; |
59 | 76 | |
60 | 77 | static const struct udevice_id pch9_ids[] = { |