Eric Lee / smarc-uboot

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Commit 5043045dede0ad4ffb4c5ec21da81956ca3c8362

Authored by Masahiro Yamada
Committed by Tom Rini
1 parent 41eb4e5c31
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc: ppc4xx: remove korat board support 

This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Larry Johnson <lrj@acm.org>

Showing 13 changed files with 1 additions and 1514 deletions Side-by-side Diff

arch/powerpc/cpu/ppc4xx/Kconfig
Diff comments   View file @ 5043045
... ... @@ -13,9 +13,6 @@
13 13 config TARGET_CSB472
14 14 bool "Support csb472"
15 15  
16   -config TARGET_KORAT
17   - bool "Support korat"
18   -
19 16 config TARGET_LWMON5
20 17 bool "Support lwmon5"
21 18 select SUPPORT_SPL
... ... @@ -195,7 +192,6 @@
195 192 source "board/gdsys/dlvision/Kconfig"
196 193 source "board/gdsys/gdppc440etx/Kconfig"
197 194 source "board/gdsys/intip/Kconfig"
198   -source "board/korat/Kconfig"
199 195 source "board/lwmon5/Kconfig"
200 196 source "board/mosaixtech/icon/Kconfig"
201 197 source "board/mpl/mip405/Kconfig"
board/korat/Kconfig
View file @ 5043045
1   -if TARGET_KORAT
2   -
3   -config SYS_BOARD
4   - default "korat"
5   -
6   -config SYS_CONFIG_NAME
7   - default "korat"
8   -
9   -endif
board/korat/MAINTAINERS
View file @ 5043045
1   -KORAT BOARD
2   -M: Larry Johnson <lrj@acm.org>
3   -S: Maintained
4   -F: board/korat/
5   -F: include/configs/korat.h
6   -F: configs/korat_defconfig
7   -F: configs/korat_perm_defconfig
board/korat/Makefile
View file @ 5043045
1   -#
2   -# (C) Copyright 2002-2007
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = korat.o
9   -extra-y += init.o
board/korat/README
View file @ 5043045
1   -The Korat board has two NOR flashes, FLASH0 and FLASH1, which are connected to
2   -chip select 0 and 1, respectively. FLASH0 contains 16 MiB, and is mapped to
3   -addresses 0xFF000000 - 0xFFFFFFFF as U-Boot Flash Bank #2. FLASH1 contains
4   -from 16 to 128 MiB, and is mapped to 0xF?000000 - 0xF7FFFFFF as U-Boot Flash
5   -Bank #1 (with the starting address depending on the flash size detected at
6   -runtime). The write-enable pin on FLASH0 is disabled, so the contents of FLASH0
7   -cannot be modified in the field. This also prevents FLASH0 from executing
8   -commands to return chip information, so its configuration is hard-coded in
9   -U-Boot.
10   -
11   -There are two versions of U-Boot for Korat: "permanent" and "upgradable". The
12   -permanent U-Boot is pre-programmed at the top of FLASH0, e.g., at addresses
13   -0xFFFA0000 - 0xFFFFFFFF for the current 384 KiB size. The upgradable U-Boot is
14   -located 256 KiB from the top of FLASH1, e.g. at addresses 0xF7F6000 - 0xF7FC0000
15   -for the current 384 KiB size. FLASH1 addresses 0xF7FE0000 - 0xF7FF0000 are
16   -used for the U-Boot environmental parameters, and addresses 0xF7FC0000 -
17   -0xF7FDFFFF are used for the redundant copy of the parameters. These locations
18   -are used by both versions of U-Boot.
19   -
20   -On booting, the permanent U-Boot in FLASH0 begins executing. After performing
21   -minimal setup, it monitors the state of the board's Reset switch (GPIO47). If
22   -the switch is sensed as open before a timeout period, then U-Boot branches to
23   -address 0xF7FBFFFC. This causes the upgradable U-Boot to execute from the
24   -beginning. If the switch remains closed thoughout the timeout period, the
25   -permanent U-Boot activates the on-board buzzer until the switch is sensed as
26   -opened. It then continues to execute without branching to FLASH1. The effect
27   -of this is that normally the Korat board boots its upgradable U-Boot, but, if
28   -this has been corrupted, the user can boot the permanent U-Boot, which can then
29   -be used to erase and reload FLASH1 as needed.
30   -
31   -Note that it is not necessary for the permanent U-Boot to have all the latest
32   -features, but only that it have sufficient functionality (working "tftp",
33   -"erase", "cp.b", etc.) to repair FLASH1. Also, the permanent U-Boot makes no
34   -assumptions about the size of FLASH1 or the size of the upgradable U-Boot: it is
35   -sufficient that the upgradable U-Boot can be started by a branch to 0xF7FBFFFC.
36   -
37   -The build sequence:
38   -
39   - make korat_perm_config
40   - make all
41   -
42   -builds the permanent U-Boot by selecting loader file "u-boot.lds" and defining
43   -preprocessor symbol "CONFIG_KORAT_PERMANENT". The default build:
44   -
45   - make korat_config
46   - make all
47   -
48   -creates the upgradable U-Boot by selecting loader file "u-boot-F7FC.lds" and
49   -leaving preprocessor symbol "CONFIG_KORAT_PERMANENT" undefined.
50   -
51   -2008-02-22, Larry Johnson <lrj@acm.org>
52   -
53   -
54   -The CompactFlash(R) controller on the Korat board provides a hi-speed USB
55   -interface. This may be connected to either a dedicated port on the on-board
56   -USB controller, or to a USB port on the PowerPC 440EPx processor. The U-Boot
57   -environment variable "korat_usbcf" can be used to specify which of these two
58   -USB host ports is used for CompactFlash. The valid setting for the variable are
59   -the strings "pci" and "ppc". If the variable defined and set to "ppc", then the
60   -PowerPC USB port is used. In all other cases the on-board USB controller is
61   -used, but if "korat_usbcf" is defined but is set to a string other than the two
62   -valid options, a warning is also issued.
63   -
64   -2009-01-28, Larry Johnson <lrj@acm.org>
board/korat/config.mk
View file @ 5043045
1   -#
2   -# (C) Copyright 2002
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -#
8   -# Korat (PPC440EPx) board
9   -#
10   -
11   -PLATFORM_CPPFLAGS += -DCONFIG_440=1
12   -
13   -ifeq ($(debug),1)
14   -PLATFORM_CPPFLAGS += -DDEBUG
15   -endif
16   -
17   -ifeq ($(emul),1)
18   -PLATFORM_CPPFLAGS += -fno-schedule-insns -fno-schedule-insns2
19   -endif
20   -
21   -ifeq ($(dbcr),1)
22   -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8CFF0000
23   -endif
24   -
25   -ifndef CONFIG_KORAT_PERMANENT
26   -LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-F7FC.lds
27   -endif
board/korat/init.S
View file @ 5043045
1   -/*
2   - *
3   - * SPDX-License-Identifier: GPL-2.0+
4   - */
5   -
6   -#include <asm-offsets.h>
7   -#include <ppc_asm.tmpl>
8   -#include <asm/mmu.h>
9   -#include <config.h>
10   -
11   -/**************************************************************************
12   - * TLB TABLE
13   - *
14   - * This table is used by the cpu boot code to setup the initial tlb
15   - * entries. Rather than make broad assumptions in the cpu source tree,
16   - * this table lets each board set things up however they like.
17   - *
18   - * Pointer to the table is returned in r1
19   - *
20   - *************************************************************************/
21   - .section .bootpg,"ax"
22   - .globl tlbtab
23   -
24   -tlbtab:
25   - tlbtab_start
26   -
27   - /*
28   - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
29   - * speed up boot process. It is patched after relocation to enable SA_I
30   - */
31   - tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G )
32   -
33   - /*
34   - * TLB entries for SDRAM are not needed on this platform. They are
35   - * generated dynamically in the SPD DDR2 detection routine.
36   - */
37   -
38   -#ifdef CONFIG_SYS_INIT_RAM_DCACHE
39   - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
40   - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0,
41   - AC_RWX | SA_G )
42   -#endif
43   -
44   - /* TLB-entry for PCI Memory */
45   - tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M,
46   - CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG )
47   -
48   - tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M,
49   - CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG )
50   -
51   - tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M,
52   - CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG )
53   -
54   - tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M,
55   - CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG )
56   -
57   - /* TLB-entry for EBC */
58   - tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG )
59   -
60   - /* TLB-entry for Internal Registers & OCM */
61   - /* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
62   - tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I )
63   -
64   - /*TLB-entry PCI registers*/
65   - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG )
66   -
67   - /* TLB-entry for peripherals */
68   - tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG)
69   -
70   - /* TLB-entry PCI IO Space - from sr@denx.de */
71   - tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG)
72   -
73   - tlbtab_end
74   -
75   -#if defined(CONFIG_KORAT_PERMANENT)
76   - .globl korat_branch_absolute
77   -korat_branch_absolute:
78   - mtlr r3
79   - blr
80   -#endif
board/korat/korat.c
View file @ 5043045
1   -/*
2   - * (C) Copyright 2007-2010
3   - * Larry Johnson, lrj@acm.org
4   - *
5   - * (C) Copyright 2006-2007
6   - * Stefan Roese, DENX Software Engineering, sr@denx.de.
7   - *
8   - * (C) Copyright 2006
9   - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
10   - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
11   - *
12   - * SPDX-License-Identifier: GPL-2.0+
13   - */
14   -
15   -#include <common.h>
16   -#include <fdt_support.h>
17   -#include <i2c.h>
18   -#include <libfdt.h>
19   -#include <asm/ppc440.h>
20   -#include <asm/bitops.h>
21   -#include <asm/ppc4xx-gpio.h>
22   -#include <asm/io.h>
23   -#include <asm/ppc4xx-uic.h>
24   -#include <asm/processor.h>
25   -#include <asm/4xx_pci.h>
26   -
27   -DECLARE_GLOBAL_DATA_PTR;
28   -
29   -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
30   -
31   -ulong flash_get_size(ulong base, int banknum);
32   -
33   -#if defined(CONFIG_KORAT_PERMANENT)
34   -void korat_buzzer(int const on)
35   -{
36   - if (on) {
37   - out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
38   - in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) | 0x80);
39   - } else {
40   - out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
41   - in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) & ~0x80);
42   - }
43   -}
44   -#endif
45   -
46   -int board_early_init_f(void)
47   -{
48   - uint32_t sdr0_pfc1, sdr0_pfc2;
49   - uint32_t reg;
50   - int eth;
51   -
52   -#if defined(CONFIG_KORAT_PERMANENT)
53   - unsigned mscount;
54   -
55   - extern void korat_branch_absolute(uint32_t addr);
56   -
57   - for (mscount = 0; mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) {
58   - udelay(1000);
59   - if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) {
60   - /* This call does not return. */
61   - korat_branch_absolute(
62   - CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4);
63   - }
64   - }
65   - korat_buzzer(1);
66   - while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_))
67   - udelay(1000);
68   -
69   - korat_buzzer(0);
70   -#endif
71   -
72   - mtdcr(EBC0_CFGADDR, EBC0_CFG);
73   - mtdcr(EBC0_CFGDATA, 0xb8400000);
74   -
75   - /*
76   - * Setup the interrupt controller polarities, triggers, etc.
77   - */
78   - mtdcr(UIC0SR, 0xffffffff); /* clear all */
79   - mtdcr(UIC0ER, 0x00000000); /* disable all */
80   - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
81   - mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
82   - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
83   - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
84   - mtdcr(UIC0SR, 0xffffffff); /* clear all */
85   -
86   - mtdcr(UIC1SR, 0xffffffff); /* clear all */
87   - mtdcr(UIC1ER, 0x00000000); /* disable all */
88   - mtdcr(UIC1CR, 0x00000000); /* all non-critical */
89   - mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
90   - mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
91   - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
92   - mtdcr(UIC1SR, 0xffffffff); /* clear all */
93   -
94   - mtdcr(UIC2SR, 0xffffffff); /* clear all */
95   - mtdcr(UIC2ER, 0x00000000); /* disable all */
96   - mtdcr(UIC2CR, 0x00000000); /* all non-critical */
97   - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
98   - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
99   - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
100   - mtdcr(UIC2SR, 0xffffffff); /* clear all */
101   -
102   - /*
103   - * Take sim card reader and CF controller out of reset. Also enable PHY
104   - * auto-detect until board-specific PHY resets are available.
105   - */
106   - out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0);
107   -
108   - /* Configure the two Ethernet PHYs. For each PHY, configure for fiber
109   - * if the SFP module is present, and for copper if it is not present.
110   - */
111   - for (eth = 0; eth < 2; ++eth) {
112   - if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) {
113   - /* SFP module not present: configure PHY for copper. */
114   - /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
115   - out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
116   - in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) |
117   - 0x06 << (4 * eth));
118   - } else {
119   - /* SFP module present: configure PHY for fiber and
120   - enable output */
121   - gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1);
122   - gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0);
123   - }
124   - }
125   - /* enable Ethernet: set GPIO45 and GPIO46 to 1 */
126   - gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1);
127   - gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1);
128   -
129   - /* Wait 1 ms, then enable Fiber signal detect to PHYs. */
130   - udelay(1000);
131   - out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
132   - in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88);
133   -
134   - /* select Ethernet (and optionally IIC1) pins */
135   - mfsdr(SDR0_PFC1, sdr0_pfc1);
136   - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
137   - SDR0_PFC1_SELECT_CONFIG_4;
138   -#ifdef CONFIG_I2C_MULTI_BUS
139   - sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
140   -#endif
141   - mfsdr(SDR0_PFC2, sdr0_pfc2);
142   - sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
143   - SDR0_PFC2_SELECT_CONFIG_4;
144   - mtsdr(SDR0_PFC2, sdr0_pfc2);
145   - mtsdr(SDR0_PFC1, sdr0_pfc1);
146   -
147   - /* PCI arbiter enabled */
148   - mfsdr(SDR0_PCI0, reg);
149   - mtsdr(SDR0_PCI0, 0x80000000 | reg);
150   -
151   - return 0;
152   -}
153   -
154   -/*
155   - * The boot flash on CS0 normally has its write-enable pin disabled, and so will
156   - * not respond to CFI commands. This routine therefore fills in the flash
157   - * information for the boot flash. (The flash at CS1 operates normally.)
158   - */
159   -ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
160   -{
161   - uint32_t addr;
162   - int i;
163   -
164   - if (1 != banknum)
165   - return 0;
166   -
167   - info->size = CONFIG_SYS_FLASH0_SIZE;
168   - info->sector_count = CONFIG_SYS_FLASH0_SIZE / 0x20000;
169   - info->flash_id = 0x01000000;
170   - info->portwidth = 2;
171   - info->chipwidth = 2;
172   - info->buffer_size = 32;
173   - info->erase_blk_tout = 16384;
174   - info->write_tout = 2;
175   - info->buffer_write_tout = 5;
176   - info->vendor = 2;
177   - info->cmd_reset = 0x00F0;
178   - info->interface = 2;
179   - info->legacy_unlock = 0;
180   - info->manufacturer_id = 1;
181   - info->device_id = 0x007E;
182   -
183   -#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
184   - info->device_id2 = 0x2101;
185   -#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
186   - info->device_id2 = 0x2301;
187   -#else
188   -#error Unable to set device_id2 for current CONFIG_SYS_FLASH0_SIZE
189   -#endif
190   -
191   - info->ext_addr = 0x0040;
192   - info->cfi_version = 0x3133;
193   - info->cfi_offset = 0x0055;
194   - info->addr_unlock1 = 0x00000555;
195   - info->addr_unlock2 = 0x000002AA;
196   - info->name = "CFI conformant";
197   - for (i = 0, addr = -info->size;
198   - i < info->sector_count;
199   - ++i, addr += 0x20000) {
200   - info->start[i] = addr;
201   - info->protect[i] = 0x00;
202   - }
203   - return 1;
204   -}
205   -
206   -static int man_data_read(unsigned int addr)
207   -{
208   - /*
209   - * Read an octet of data from address "addr" in the manufacturer's
210   - * information serial EEPROM, or -1 on error.
211   - */
212   - u8 data[2];
213   -
214   - if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) ||
215   - 0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) {
216   - debug("man_data_read(0x%02X) failed\n", addr);
217   - return -1;
218   - }
219   - debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]);
220   - return data[0];
221   -}
222   -
223   -static unsigned int man_data_field_addr(unsigned int const field)
224   -{
225   - /*
226   - * The manufacturer's information serial EEPROM contains a sequence of
227   - * zero-delimited fields. Return the starting address of field "field",
228   - * or 0 on error.
229   - */
230   - unsigned addr, i;
231   -
232   - if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1))
233   - /* Only format "A" is currently supported */
234   - return 0;
235   -
236   - for (addr = 2, i = 1; i < field && addr < 256; ++addr) {
237   - if ('\0' == man_data_read(addr))
238   - ++i;
239   - }
240   - return (addr < 256) ? addr : 0;
241   -}
242   -
243   -static char *man_data_read_field(char s[], unsigned const field,
244   - unsigned const length)
245   -{
246   - /*
247   - * Place the null-terminated contents of field "field" of length
248   - * "length" from the manufacturer's information serial EEPROM into
249   - * string "s[length + 1]" and return a pointer to s, or return 0 on
250   - * error. In either case the original contents of s[] is not preserved.
251   - */
252   - unsigned addr, i;
253   -
254   - addr = man_data_field_addr(field);
255   - if (0 == addr || addr + length >= 255)
256   - return 0;
257   -
258   - for (i = 0; i < length; ++i) {
259   - int const c = man_data_read(addr++);
260   -
261   - if (c <= 0)
262   - return 0;
263   -
264   - s[i] = (char)c;
265   - }
266   - if (0 != man_data_read(addr))
267   - return 0;
268   -
269   - s[i] = '\0';
270   - return s;
271   -}
272   -
273   -static void set_serial_number(void)
274   -{
275   - /*
276   - * If the environmental variable "serial#" is not set, try to set it
277   - * from the manufacturer's information serial EEPROM.
278   - */
279   - char s[MAN_INFO_LENGTH + MAN_MAC_ADDR_LENGTH + 2];
280   -
281   - if (getenv("serial#"))
282   - return;
283   -
284   - if (!man_data_read_field(s, MAN_INFO_FIELD, MAN_INFO_LENGTH))
285   - return;
286   -
287   - s[MAN_INFO_LENGTH] = '-';
288   - if (!man_data_read_field(s + MAN_INFO_LENGTH + 1, MAN_MAC_ADDR_FIELD,
289   - MAN_MAC_ADDR_LENGTH))
290   - return;
291   -
292   - setenv("serial#", s);
293   -}
294   -
295   -static void set_mac_addresses(void)
296   -{
297   - /*
298   - * If the environmental variables "ethaddr" and/or "eth1addr" are not
299   - * set, try to set them from the manufacturer's information serial
300   - * EEPROM.
301   - */
302   -
303   -#if MAN_MAC_ADDR_LENGTH % 2 != 0
304   -#error MAN_MAC_ADDR_LENGTH must be an even number
305   -#endif
306   -
307   - char s[(3 * MAN_MAC_ADDR_LENGTH) / 2];
308   - char *src;
309   - char *dst;
310   -
311   - if (0 != getenv("ethaddr") && 0 != getenv("eth1addr"))
312   - return;
313   -
314   - if (0 == man_data_read_field(s + (MAN_MAC_ADDR_LENGTH / 2) - 1,
315   - MAN_MAC_ADDR_FIELD, MAN_MAC_ADDR_LENGTH))
316   - return;
317   -
318   - for (src = s + (MAN_MAC_ADDR_LENGTH / 2) - 1, dst = s; src != dst;) {
319   - *dst++ = *src++;
320   - *dst++ = *src++;
321   - *dst++ = ':';
322   - }
323   - if (0 == getenv("ethaddr"))
324   - setenv("ethaddr", s);
325   -
326   - if (0 == getenv("eth1addr")) {
327   - ++s[((3 * MAN_MAC_ADDR_LENGTH) / 2) - 2];
328   - setenv("eth1addr", s);
329   - }
330   -}
331   -
332   -int misc_init_r(void)
333   -{
334   - uint32_t pbcr;
335   - int size_val;
336   - uint32_t reg;
337   - unsigned long usb2d0cr = 0;
338   - unsigned long usb2phy0cr, usb2h0cr = 0;
339   - unsigned long sdr0_pfc1;
340   - uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
341   - char const *const act = getenv("usbact");
342   - char const *const usbcf = getenv("korat_usbcf");
343   -
344   - /*
345   - * Re-do FLASH1 sizing and adjust flash start and offset.
346   - */
347   - gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size;
348   - gd->bd->bi_flashoffset = 0;
349   -
350   - mtdcr(EBC0_CFGADDR, PB1CR);
351   - pbcr = mfdcr(EBC0_CFGDATA);
352   - size_val = ffs(flash1_size) - 21;
353   - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
354   - mtdcr(EBC0_CFGADDR, PB1CR);
355   - mtdcr(EBC0_CFGDATA, pbcr);
356   -
357   - /*
358   - * Re-check to get correct base address
359   - */
360   - flash_get_size(gd->bd->bi_flashstart, 0);
361   -
362   - /*
363   - * Re-do FLASH1 sizing and adjust flash offset to reserve space for
364   - * environment
365   - */
366   - gd->bd->bi_flashoffset =
367   - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR;
368   -
369   - mtdcr(EBC0_CFGADDR, PB1CR);
370   - pbcr = mfdcr(EBC0_CFGDATA);
371   - size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21;
372   - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
373   - mtdcr(EBC0_CFGADDR, PB1CR);
374   - mtdcr(EBC0_CFGDATA, pbcr);
375   -
376   - /* Monitor protection ON by default */
377   -#if defined(CONFIG_KORAT_PERMANENT)
378   - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
379   - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
380   - flash_info + 1);
381   -#else
382   - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
383   - CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
384   - flash_info);
385   -#endif
386   - /* Env protection ON by default */
387   - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
388   - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
389   - flash_info);
390   - (void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
391   - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
392   - flash_info);
393   -
394   - /*
395   - * USB suff...
396   - */
397   - /*
398   - * Select the USB controller on the 440EPx ("ppc") or on the PCI bus
399   - * ("pci") for the CompactFlash.
400   - */
401   - if (usbcf != NULL && (strcmp(usbcf, "ppc") == 0)) {
402   - /*
403   - * If environment variable "usbcf" is defined and set to "ppc",
404   - * then connect the CompactFlash controller to the PowerPC USB
405   - * port.
406   - */
407   - printf("Attaching CompactFlash controller to PPC USB\n");
408   - out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02,
409   - in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02) | 0x10);
410   - } else {
411   - if (usbcf != NULL && (strcmp(usbcf, "pci") != 0))
412   - printf("Warning: \"korat_usbcf\" is not set to a legal "
413   - "value (\"ppc\" or \"pci\")\n");
414   -
415   - printf("Attaching CompactFlash controller to PCI USB\n");
416   - }
417   - if (act == NULL || strcmp(act, "hostdev") == 0) {
418   - /* SDR Setting */
419   - mfsdr(SDR0_PFC1, sdr0_pfc1);
420   - mfsdr(SDR0_USB2D0CR, usb2d0cr);
421   - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
422   - mfsdr(SDR0_USB2H0CR, usb2h0cr);
423   -
424   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
425   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
426   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
427   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
428   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
429   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
430   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
431   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
432   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
433   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
434   -
435   - /*
436   - * An 8-bit/60MHz interface is the only possible alternative
437   - * when connecting the Device to the PHY
438   - */
439   - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
440   - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
441   -
442   - /*
443   - * To enable the USB 2.0 Device function
444   - * through the UTMI interface
445   - */
446   - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
447   - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
448   -
449   - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
450   - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
451   -
452   - mtsdr(SDR0_PFC1, sdr0_pfc1);
453   - mtsdr(SDR0_USB2D0CR, usb2d0cr);
454   - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
455   - mtsdr(SDR0_USB2H0CR, usb2h0cr);
456   -
457   - /* clear resets */
458   - udelay(1000);
459   - mtsdr(SDR0_SRST1, 0x00000000);
460   - udelay(1000);
461   - mtsdr(SDR0_SRST0, 0x00000000);
462   -
463   - printf("USB: Host(int phy) Device(ext phy)\n");
464   -
465   - } else if (strcmp(act, "dev") == 0) {
466   - /*-------------------PATCH-------------------------------*/
467   - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
468   -
469   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
470   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
471   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
472   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
473   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
474   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
475   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
476   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
477   - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
478   -
479   - udelay(1000);
480   - mtsdr(SDR0_SRST1, 0x672c6000);
481   -
482   - udelay(1000);
483   - mtsdr(SDR0_SRST0, 0x00000080);
484   -
485   - udelay(1000);
486   - mtsdr(SDR0_SRST1, 0x60206000);
487   -
488   - *(unsigned int *)(0xe0000350) = 0x00000001;
489   -
490   - udelay(1000);
491   - mtsdr(SDR0_SRST1, 0x60306000);
492   - /*-------------------PATCH-------------------------------*/
493   -
494   - /* SDR Setting */
495   - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
496   - mfsdr(SDR0_USB2H0CR, usb2h0cr);
497   - mfsdr(SDR0_USB2D0CR, usb2d0cr);
498   - mfsdr(SDR0_PFC1, sdr0_pfc1);
499   -
500   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
501   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
502   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
503   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
504   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
505   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
506   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
507   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
508   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
509   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
510   -
511   - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
512   - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
513   -
514   - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
515   - usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
516   -
517   - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
518   - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
519   -
520   - mtsdr(SDR0_USB2H0CR, usb2h0cr);
521   - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
522   - mtsdr(SDR0_USB2D0CR, usb2d0cr);
523   - mtsdr(SDR0_PFC1, sdr0_pfc1);
524   -
525   - /* clear resets */
526   - udelay(1000);
527   - mtsdr(SDR0_SRST1, 0x00000000);
528   - udelay(1000);
529   - mtsdr(SDR0_SRST0, 0x00000000);
530   -
531   - printf("USB: Device(int phy)\n");
532   - }
533   -
534   - mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */
535   - reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
536   - mtsdr(SDR0_SRST1, reg);
537   -
538   - /*
539   - * Clear PLB4A0_ACR[WRP]
540   - * This fix will make the MAL burst disabling patch for the Linux
541   - * EMAC driver obsolete.
542   - */
543   - reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
544   - mtdcr(PLB4A0_ACR, reg);
545   -
546   - set_serial_number();
547   - set_mac_addresses();
548   - gpio_write_bit(CONFIG_SYS_GPIO_ATMEGA_RESET_, 1);
549   -
550   - return 0;
551   -}
552   -
553   -int checkboard(void)
554   -{
555   - char const *const s = getenv("serial#");
556   - u8 const rev = in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0);
557   -
558   - printf("Board: Korat, Rev. %X", rev);
559   - if (s)
560   - printf(", serial# %s", s);
561   -
562   - printf(".\n Ethernet PHY 0: ");
563   - if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL))
564   - printf("fiber");
565   - else
566   - printf("copper");
567   -
568   - printf(", PHY 1: ");
569   - if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY1_FIBER_SEL))
570   - printf("fiber");
571   - else
572   - printf("copper");
573   -
574   - printf(".\n");
575   -#if defined(CONFIG_KORAT_PERMANENT)
576   - printf(" Executing permanent copy of U-Boot.\n");
577   -#endif
578   - return 0;
579   -}
580   -
581   -#if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
582   -/*
583   - * Assign interrupts to PCI devices.
584   - */
585   -void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
586   -{
587   - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
588   -}
589   -#endif
590   -
591   -/*
592   - * pci_target_init
593   - *
594   - * The bootstrap configuration provides default settings for the pci
595   - * inbound map (PIM). But the bootstrap config choices are limited and
596   - * may not be sufficient for a given board.
597   - */
598   -#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
599   -void pci_target_init(struct pci_controller *hose)
600   -{
601   - /* First do 440EP(x) common setup */
602   - __pci_target_init(hose);
603   -
604   - /*
605   - * Set up Configuration registers for on-board NEC uPD720101 USB
606   - * controller.
607   - */
608   - pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
609   -}
610   -#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
611   -
612   -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
613   -int ft_board_setup(void *blob, bd_t *bd)
614   -{
615   - u32 val[4];
616   - int rc;
617   -
618   - ft_cpu_setup(blob, bd);
619   -
620   - /* Fixup NOR mapping */
621   - val[0] = 1; /* chip select number */
622   - val[1] = 0; /* always 0 */
623   - val[2] = gd->bd->bi_flashstart;
624   - val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
625   - rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
626   - val, sizeof(val), 1);
627   - if (rc)
628   - printf("Unable to update property NOR mapping, err=%s\n",
629   - fdt_strerror(rc));
630   -
631   - return 0;
632   -}
633   -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
board/korat/u-boot-F7FC.lds
View file @ 5043045
1   -/*
2   - * (C) Copyright 2002
3   - * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -OUTPUT_ARCH(powerpc)
9   -/* Do we need any of these for elf?
10   - __DYNAMIC = 0; */
11   -SECTIONS
12   -{
13   - .resetvec 0xF7FBFFFC :
14   - {
15   - *(.resetvec)
16   - } = 0xffff
17   -
18   - .bootpg 0xF7FBF000 :
19   - {
20   - arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
21   - } = 0xffff
22   -
23   - /* Read-only sections, merged into text segment: */
24   - . = + SIZEOF_HEADERS;
25   - .interp : { *(.interp) }
26   - .hash : { *(.hash) }
27   - .dynsym : { *(.dynsym) }
28   - .dynstr : { *(.dynstr) }
29   - .rel.text : { *(.rel.text) }
30   - .rela.text : { *(.rela.text) }
31   - .rel.data : { *(.rel.data) }
32   - .rela.data : { *(.rela.data) }
33   - .rel.rodata : { *(.rel.rodata) }
34   - .rela.rodata : { *(.rela.rodata) }
35   - .rel.got : { *(.rel.got) }
36   - .rela.got : { *(.rela.got) }
37   - .rel.ctors : { *(.rel.ctors) }
38   - .rela.ctors : { *(.rela.ctors) }
39   - .rel.dtors : { *(.rel.dtors) }
40   - .rela.dtors : { *(.rela.dtors) }
41   - .rel.bss : { *(.rel.bss) }
42   - .rela.bss : { *(.rela.bss) }
43   - .rel.plt : { *(.rel.plt) }
44   - .rela.plt : { *(.rela.plt) }
45   - .init : { *(.init) }
46   - .plt : { *(.plt) }
47   - .text :
48   - {
49   - /* WARNING - the following is hand-optimized to fit within */
50   - /* the sector layout of our flash chips! XXX FIXME XXX */
51   -
52   - arch/powerpc/cpu/ppc4xx/start.o (.text)
53   -
54   - *(.text)
55   - *(.got1)
56   - }
57   - _etext = .;
58   - PROVIDE (etext = .);
59   - .rodata :
60   - {
61   - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
62   - }
63   - .fini : { *(.fini) } =0
64   - .ctors : { *(.ctors) }
65   - .dtors : { *(.dtors) }
66   -
67   - /* Read-write section, merged into data segment: */
68   - . = (. + 0x00FF) & 0xFFFFFF00;
69   - _erotext = .;
70   - PROVIDE (erotext = .);
71   - .reloc :
72   - {
73   - *(.got)
74   - _GOT2_TABLE_ = .;
75   - *(.got2)
76   - _FIXUP_TABLE_ = .;
77   - *(.fixup)
78   - }
79   - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
80   - __fixup_entries = (. - _FIXUP_TABLE_)>>2;
81   -
82   - .data :
83   - {
84   - *(.data)
85   - *(.data1)
86   - *(.sdata)
87   - *(.sdata2)
88   - *(.dynamic)
89   - CONSTRUCTORS
90   - }
91   - _edata = .;
92   - PROVIDE (edata = .);
93   -
94   - . = .;
95   -
96   - .u_boot_list : {
97   - KEEP(*(SORT(.u_boot_list*)));
98   - }
99   -
100   - . = .;
101   - __start___ex_table = .;
102   - __ex_table : { *(__ex_table) }
103   - __stop___ex_table = .;
104   -
105   - . = ALIGN(256);
106   - __init_begin = .;
107   - .text.init : { *(.text.init) }
108   - .data.init : { *(.data.init) }
109   - . = ALIGN(256);
110   - __init_end = .;
111   -
112   - __bss_start = .;
113   - .bss (NOLOAD) :
114   - {
115   - *(.sbss) *(.scommon)
116   - *(.dynbss)
117   - *(.bss)
118   - *(COMMON)
119   - . = ALIGN(4);
120   - }
121   -
122   - __bss_end = . ;
123   - PROVIDE (end = .);
124   -}
configs/korat_defconfig
View file @ 5043045
1   -CONFIG_PPC=y
2   -CONFIG_4xx=y
3   -CONFIG_TARGET_KORAT=y
configs/korat_perm_defconfig
View file @ 5043045
1   -CONFIG_SYS_EXTRA_OPTIONS="KORAT_PERMANENT"
2   -CONFIG_PPC=y
3   -CONFIG_4xx=y
4   -CONFIG_TARGET_KORAT=y
doc/README.scrapyard
Diff comments   View file @ 5043045
... ... @@ -12,6 +12,7 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +korat powerpc ppc4xx - - Larry Johnson <lrj@acm.org>
15 16 galaxy5200 powerpc mpc5xxx - - Eric Millbrandt <emillbrandt@dekaresearch.com>
16 17 W7OLMC powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
17 18 W7OLMG powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
include/configs/korat.h
View file @ 5043045
1   -/*
2   - * (C) Copyright 2007-2009
3   - * Larry Johnson, lrj@acm.org
4   - *
5   - * (C) Copyright 2006-2007
6   - * Stefan Roese, DENX Software Engineering, sr@denx.de.
7   - *
8   - * (C) Copyright 2006
9   - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
10   - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
11   - *
12   - * SPDX-License-Identifier: GPL-2.0+
13   - */
14   -
15   -/*
16   - * korat.h - configuration for Korat board
17   - */
18   -#ifndef __CONFIG_H
19   -#define __CONFIG_H
20   -
21   -/*
22   - * High Level Configuration Options
23   - */
24   -#define CONFIG_440EPX 1 /* Specific PPC440EPx */
25   -#define CONFIG_SYS_CLK_FREQ 33333333
26   -
27   -#ifdef CONFIG_KORAT_PERMANENT
28   -#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
29   -#else
30   -#define CONFIG_SYS_TEXT_BASE 0xF7F60000
31   -#endif
32   -
33   -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
34   -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
35   -
36   -/*
37   - * Manufacturer's information serial EEPROM parameters
38   - */
39   -#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
40   -#define MAN_INFO_FIELD 2
41   -#define MAN_INFO_LENGTH 9
42   -#define MAN_MAC_ADDR_FIELD 3
43   -#define MAN_MAC_ADDR_LENGTH 12
44   -
45   -/*
46   - * Base addresses -- Note these are effective addresses where the actual
47   - * resources get mapped (not physical addresses).
48   - */
49   -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
50   -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
51   -
52   -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
53   -#define CONFIG_SYS_FLASH0_SIZE 0x01000000
54   -#define CONFIG_SYS_FLASH0_ADDR (-CONFIG_SYS_FLASH0_SIZE)
55   -#define CONFIG_SYS_FLASH1_TOP 0xF8000000
56   -#define CONFIG_SYS_FLASH1_MAX_SIZE 0x08000000
57   -#define CONFIG_SYS_FLASH1_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
58   -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH1_ADDR /* start of FLASH */
59   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
60   -#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
61   -#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_OCM_BASE
62   -#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
63   -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
64   -#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000)
65   -
66   -#define CONFIG_SYS_USB2D0_BASE 0xe0000100
67   -#define CONFIG_SYS_USB_DEVICE 0xe0000000
68   -#define CONFIG_SYS_USB_HOST 0xe0000400
69   -#define CONFIG_SYS_CPLD_BASE 0xc0000000
70   -
71   -/*
72   - * Initial RAM & stack pointer
73   - */
74   -/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
75   -#undef CONFIG_SYS_INIT_RAM_DCACHE
76   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
77   -#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
78   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
79   -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
80   -
81   -/*
82   - * Serial Port
83   - */
84   -#define CONFIG_CONS_INDEX 1 /* Use UART0 */
85   -#define CONFIG_SYS_NS16550
86   -#define CONFIG_SYS_NS16550_SERIAL
87   -#define CONFIG_SYS_NS16550_REG_SIZE 1
88   -#define CONFIG_SYS_NS16550_CLK get_serial_clock()
89   -#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
90   -#define CONFIG_BAUDRATE 115200
91   -
92   -#define CONFIG_SYS_BAUDRATE_TABLE \
93   - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
94   -
95   -/*
96   - * Environment
97   - */
98   -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
99   -
100   -/*
101   - * FLASH related
102   - */
103   -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
104   -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
105   -#define CONFIG_FLASH_CFI_LEGACY /* Allow hard-coded config for FLASH0 */
106   -
107   -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
108   -
109   -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
110   -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */
111   -
112   -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
113   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
114   -
115   -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
116   -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
117   -
118   -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
119   -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
120   -
121   -#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
122   -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
123   -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
124   -
125   -/* Address and size of Redundant Environment Sector */
126   -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
127   -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
128   -
129   -/*
130   - * DDR SDRAM
131   - */
132   -#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
133   -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
134   -#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
135   -#define CONFIG_DDR_ECC /* Use ECC when available */
136   -#define SPD_EEPROM_ADDRESS {0x50}
137   -#define CONFIG_PROG_SDRAM_TLB
138   -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4 KiB as */
139   - /* per 440EPx Errata CHIP_11 */
140   -
141   -/*
142   - * I2C
143   - */
144   -#define CONFIG_SYS_I2C
145   -#define CONFIG_SYS_I2C_PPC4XX
146   -#define CONFIG_SYS_I2C_PPC4XX_CH0
147   -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
148   -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
149   -
150   -#define CONFIG_SYS_I2C_MULTI_EEPROMS
151   -#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
152   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
153   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
154   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
155   -
156   -/* I2C RTC */
157   -#define CONFIG_RTC_M41T60 1
158   -#define CONFIG_SYS_I2C_RTC_ADDR 0x68
159   -
160   -/* I2C SYSMON (LM73) */
161   -#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
162   -#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
163   -#define CONFIG_SYS_DTT_MAX_TEMP 70
164   -#define CONFIG_SYS_DTT_MIN_TEMP -30
165   -
166   -#define CONFIG_PREBOOT "echo;" \
167   - "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
168   - "echo"
169   -
170   -#undef CONFIG_BOOTARGS
171   -
172   -/* Setup some board specific values for the default environment variables */
173   -#define CONFIG_HOSTNAME korat
174   -
175   -/* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
176   -#define CONFIG_EXTRA_ENV_SETTINGS \
177   - "u_boot=korat/u-boot.bin\0" \
178   - "load=tftp 200000 ${u_boot}\0" \
179   - "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \
180   - "cp.b ${fileaddr} F7F60000 ${filesize};protect on " \
181   - "F7F60000 F7FBFFFF\0" \
182   - "upd=run load update\0" \
183   - "bootfile=korat/uImage\0" \
184   - "dtb=korat/korat.dtb\0" \
185   - "kernel_addr=F4000000\0" \
186   - "ramdisk_addr=F4400000\0" \
187   - "dtb_addr=F41E0000\0" \
188   - "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; " \
189   - "cp.b ${fileaddr} F4000000 ${filesize}\0" \
190   - "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; " \
191   - "cp.b ${fileaddr} F41E0000 ${filesize}\0" \
192   - "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; " \
193   - "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} " \
194   - "${dtb}\0" \
195   - "rd_size=73728\0" \
196   - "ramargs=setenv bootargs root=/dev/ram rw " \
197   - "ramdisk_size=${rd_size}\0" \
198   - "usbdev=sda1\0" \
199   - "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \
200   - "rootpath=/opt/eldk/ppc_4xxFP\0" \
201   - "netdev=eth0\0" \
202   - "nfsargs=setenv bootargs root=/dev/nfs rw " \
203   - "nfsroot=${serverip}:${rootpath}\0" \
204   - "pciclk=33\0" \
205   - "addide=setenv bootargs ${bootargs} ide=reverse " \
206   - "idebus=${pciclk}\0" \
207   - "addip=setenv bootargs ${bootargs} " \
208   - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
209   - ":${hostname}:${netdev}:off panic=1\0" \
210   - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
211   - "flash_cf=run usbargs addide addip addtty; " \
212   - "bootm ${kernel_addr} - ${dtb_addr}\0" \
213   - "flash_nfs=run nfsargs addide addip addtty; " \
214   - "bootm ${kernel_addr} - ${dtb_addr}\0" \
215   - "flash_self=run ramargs addip addtty; " \
216   - "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0" \
217   - ""
218   -
219   -#define CONFIG_BOOTCOMMAND "run flash_cf"
220   -
221   -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
222   -
223   -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
224   -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
225   -
226   -#define CONFIG_PPC4xx_EMAC
227   -#define CONFIG_IBM_EMAC4_V4 1
228   -#define CONFIG_MII 1 /* MII PHY management */
229   -#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
230   -#define CONFIG_PHY_DYNAMIC_ANEG 1
231   -
232   -#undef CONFIG_PHY_RESET /* Don't do software PHY reset */
233   -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
234   -
235   -#define CONFIG_HAS_ETH0
236   -#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx */
237   - /* buffers & descriptors */
238   -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
239   -#define CONFIG_PHY1_ADDR 3
240   -
241   -/* USB */
242   -#define CONFIG_USB_OHCI
243   -#define CONFIG_USB_STORAGE
244   -
245   -/* Comment this out to enable USB 1.1 device */
246   -#define USB_2_0_DEVICE
247   -
248   -/* Partitions */
249   -#define CONFIG_MAC_PARTITION
250   -#define CONFIG_DOS_PARTITION
251   -#define CONFIG_ISO_PARTITION
252   -
253   -/*
254   - * BOOTP options
255   - */
256   -#define CONFIG_BOOTP_BOOTFILESIZE
257   -#define CONFIG_BOOTP_BOOTPATH
258   -#define CONFIG_BOOTP_GATEWAY
259   -#define CONFIG_BOOTP_HOSTNAME
260   -#define CONFIG_BOOTP_SUBNETMASK
261   -
262   -/*
263   - * Command line configuration.
264   - */
265   -#include <config_cmd_default.h>
266   -
267   -#define CONFIG_CMD_ASKENV
268   -#define CONFIG_CMD_DATE
269   -#define CONFIG_CMD_DHCP
270   -#define CONFIG_CMD_DTT
271   -#define CONFIG_CMD_DIAG
272   -#define CONFIG_CMD_EEPROM
273   -#define CONFIG_CMD_ELF
274   -#define CONFIG_CMD_FAT
275   -#define CONFIG_CMD_I2C
276   -#define CONFIG_CMD_IRQ
277   -#define CONFIG_CMD_MII
278   -#define CONFIG_CMD_NET
279   -#define CONFIG_CMD_NFS
280   -#define CONFIG_CMD_PCI
281   -#define CONFIG_CMD_PING
282   -#define CONFIG_CMD_REGINFO
283   -#define CONFIG_CMD_SDRAM
284   -#define CONFIG_CMD_USB
285   -
286   -/* POST support */
287   -#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
288   - CONFIG_SYS_POST_CPU | \
289   - CONFIG_SYS_POST_ECC | \
290   - CONFIG_SYS_POST_ETHER | \
291   - CONFIG_SYS_POST_FPU | \
292   - CONFIG_SYS_POST_I2C | \
293   - CONFIG_SYS_POST_MEMORY | \
294   - CONFIG_SYS_POST_RTC | \
295   - CONFIG_SYS_POST_SPR | \
296   - CONFIG_SYS_POST_UART)
297   -
298   -#define CONFIG_LOGBUFFER
299   -#define CONFIG_SYS_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
300   -
301   -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
302   -
303   -#define CONFIG_SUPPORT_VFAT
304   -
305   -/*
306   - * Miscellaneous configurable options
307   - */
308   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
309   -#if defined(CONFIG_CMD_KGDB)
310   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
311   -#else
312   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
313   -#endif
314   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
315   - /* Print Buffer Size */
316   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
317   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
318   -
319   -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
320   -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
321   -
322   -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
323   -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
324   -
325   -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
326   -#define CONFIG_LOOPW 1 /* enable loopw command */
327   -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
328   -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
329   -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
330   -
331   -/*
332   - * Korat-specific options
333   - */
334   -#define CONFIG_SYS_KORAT_MAN_RESET_MS 10000 /* timeout for manufacturer reset */
335   -
336   -/*
337   - * PCI stuff
338   - */
339   -/* General PCI */
340   -#define CONFIG_PCI /* include pci support */
341   -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
342   -#define CONFIG_PCI_PNP /* do pci plug-and-play */
343   -#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
344   -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
345   -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
346   - /* CONFIG_SYS_PCI_MEMBASE */
347   -/* Board-specific PCI */
348   -#define CONFIG_SYS_PCI_TARGET_INIT
349   -#define CONFIG_SYS_PCI_MASTER_INIT
350   -#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
351   -
352   -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
353   -#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
354   -
355   -/*
356   - * For booting Linux, the board info and command line data have to be in the
357   - * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
358   - * during initialization.
359   - */
360   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
361   -
362   -/*
363   - * External Bus Controller (EBC) Setup
364   - */
365   -
366   -/* Memory Bank 0 (NOR-FLASH) initialization */
367   -#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
368   -#define CONFIG_SYS_EBC_PB0AP 0x04017300
369   -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
370   -#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
371   -#define CONFIG_SYS_EBC_PB0AP 0x04017300
372   -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
373   -#else
374   -#error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
375   -#endif
376   -
377   -/* Memory Bank 1 (NOR-FLASH) initialization */
378   -#if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
379   -#define CONFIG_SYS_EBC_PB1AP 0x04017300
380   -#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
381   -#else
382   -#error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
383   -#endif
384   -
385   -/* Memory Bank 2 (CPLD) initialization */
386   -#define CONFIG_SYS_EBC_PB2AP 0x04017300
387   -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_CPLD_BASE | 0x00038000)
388   -
389   -/*
390   - * GPIO Setup
391   - *
392   - * Korat GPIO usage:
393   - *
394   - * Init.
395   - * Pin Source I/O value Function
396   - * ------ ------ --- ----- ---------------------------------
397   - * GPIO00 Alt1 I/O x PerAddr07
398   - * GPIO01 Alt1 I/O x PerAddr06
399   - * GPIO02 Alt1 I/O x PerAddr05
400   - * GPIO03 GPIO x x GPIO03 to expansion bus connector
401   - * GPIO04 GPIO x x GPIO04 to expansion bus connector
402   - * GPIO05 GPIO x x GPIO05 to expansion bus connector
403   - * GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
404   - * GPIO07 Alt1 O x PerCS2 (CPLD)
405   - * GPIO08 Alt1 O x PerCS3 to expansion bus connector
406   - * GPIO09 Alt1 O x PerCS4 to expansion bus connector
407   - * GPIO10 Alt1 O x PerCS5 to expansion bus connector
408   - * GPIO11 Alt1 I x PerErr
409   - * GPIO12 GPIO O 0 ATMega !Reset
410   - * GPIO13 GPIO x x Test Point 2 (TP2)
411   - * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
412   - * GPIO15 GPIO O 0 CPU Run LED !On
413   - * GPIO16 Alt1 O x GMC1TxD0
414   - * GPIO17 Alt1 O x GMC1TxD1
415   - * GPIO18 Alt1 O x GMC1TxD2
416   - * GPIO19 Alt1 O x GMC1TxD3
417   - * GPIO20 Alt1 I x RejectPkt0
418   - * GPIO21 Alt1 I x RejectPkt1
419   - * GPIO22 GPIO I x PGOOD_DDR
420   - * GPIO23 Alt1 O x SCPD0
421   - * GPIO24 Alt1 O x GMC0TxD2
422   - * GPIO25 Alt1 O x GMC0TxD3
423   - * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
424   - * GPIO27 GPIO O 0 PHY #0 1000BASE-X select
425   - * GPIO28 GPIO O 0 PHY #1 1000BASE-X select
426   - * GPIO29 GPIO I x Test jumper !Present
427   - * GPIO30 GPIO I x SFP module #0 !Present
428   - * GPIO31 GPIO I x SFP module #1 !Present
429   - *
430   - * GPIO32 GPIO O 1 SFP module #0 Tx !Enable
431   - * GPIO33 GPIO O 1 SFP module #1 Tx !Enable
432   - * GPIO34 Alt2 I x !UART1_CTS
433   - * GPIO35 Alt2 O x !UART1_RTS
434   - * GPIO36 Alt1 I x !UART0_CTS
435   - * GPIO37 Alt1 O x !UART0_RTS
436   - * GPIO38 Alt2 O x UART1_Tx
437   - * GPIO39 Alt2 I x UART1_Rx
438   - * GPIO40 Alt1 I x IRQ0 (Ethernet 0)
439   - * GPIO41 Alt1 I x IRQ1 (Ethernet 1)
440   - * GPIO42 Alt1 I x IRQ2 (PCI interrupt)
441   - * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
442   - * GPIO44 xxxx x x (grounded through pulldown)
443   - * GPIO45 GPIO O 0 PHY #0 Enable
444   - * GPIO46 GPIO O 0 PHY #1 Enable
445   - * GPIO47 GPIO I x Reset switch !Pressed
446   - * GPIO48 GPIO I x Shutdown switch !Pressed
447   - * GPIO49 xxxx x x (reserved for trace port)
448   - * . . . . .
449   - * . . . . .
450   - * . . . . .
451   - * GPIO63 xxxx x x (reserved for trace port)
452   - */
453   -
454   -#define CONFIG_SYS_GPIO_ATMEGA_RESET_ 12
455   -#define CONFIG_SYS_GPIO_ATMEGA_SS_ 13
456   -#define CONFIG_SYS_GPIO_PHY0_FIBER_SEL 27
457   -#define CONFIG_SYS_GPIO_PHY1_FIBER_SEL 28
458   -#define CONFIG_SYS_GPIO_SFP0_PRESENT_ 30
459   -#define CONFIG_SYS_GPIO_SFP1_PRESENT_ 31
460   -#define CONFIG_SYS_GPIO_SFP0_TX_EN_ 32
461   -#define CONFIG_SYS_GPIO_SFP1_TX_EN_ 33
462   -#define CONFIG_SYS_GPIO_PHY0_EN 45
463   -#define CONFIG_SYS_GPIO_PHY1_EN 46
464   -#define CONFIG_SYS_GPIO_RESET_PRESSED_ 47
465   -
466   -/*
467   - * PPC440 GPIO Configuration
468   - */
469   -#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
470   -{ \
471   -/* GPIO Core 0 */ \
472   -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
473   -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
474   -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
475   -{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
476   -{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
477   -{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
478   -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
479   -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
480   -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
481   -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
482   -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
483   -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
484   -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
485   -{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
486   -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
487   -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
488   -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
489   -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
490   -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
491   -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
492   -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
493   -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
494   -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
495   -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
496   -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
497   -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
498   -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
499   -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
500   -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
501   -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
502   -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
503   -{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
504   -}, \
505   -{ \
506   -/* GPIO Core 1 */ \
507   -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
508   -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
509   -{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
510   -{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
511   -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
512   -{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
513   -{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
514   -{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
515   -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
516   -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
517   -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
518   -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
519   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
520   -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
521   -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
522   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
523   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
524   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
525   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
526   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
527   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
528   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
529   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
530   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
531   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
532   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
533   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
534   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
535   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
536   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
537   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
538   -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
539   -} \
540   -}
541   -
542   -#if defined(CONFIG_CMD_KGDB)
543   -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
544   -#endif
545   -
546   -/* Pass open firmware flat tree */
547   -#define CONFIG_OF_LIBFDT 1
548   -#define CONFIG_OF_BOARD_SETUP 1
549   -
550   -#endif /* __CONFIG_H */