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Commit 508f412125c417623880b98fa860471c7000fbca

Authored by Bhuvanchandra DV
Committed by Stefano Babic
1 parent 098d85840e
Exists in v2017.01-smarct4x and in 34 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: vf610: Add iomux support for DSPI 

Add iomux definitions for DSPI second instance.

Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>

Showing 2 changed files with 30 additions and 0 deletions Side-by-side Diff

arch/arm/include/asm/arch-vf610/iomux-vf610.h
Diff comments   View file @ 508f412
... ... @@ -35,6 +35,11 @@
35 35 #define VF610_GPIO_PAD_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_DSE_50ohm | \
36 36 PAD_CTL_PUS_47K_UP | PAD_CTL_IBE_ENABLE)
37 37  
  38 +#define VF610_DSPI_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_DSE_20ohm | \
  39 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
  40 +#define VF610_DSPI_SIN_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_DSE_20ohm | \
  41 + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH)
  42 +
38 43 enum {
39 44 VF610_PAD_PTA6__RMII0_CLKIN = IOMUX_PAD(0x0000, 0x0000, 2, __NA_, 0, VF610_ENET_PAD_CTRL),
40 45 VF610_PAD_PTA6__RMII0_CLKOUT = IOMUX_PAD(0x0000, 0x0000, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
... ... @@ -91,6 +96,10 @@
91 96 VF610_PAD_PTC15__RMII1_TD1 = IOMUX_PAD(0x00f0, 0x00f0, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
92 97 VF610_PAD_PTC16__RMII1_TD0 = IOMUX_PAD(0x00f4, 0x00f4, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
93 98 VF610_PAD_PTC17__RMII1_TXEN = IOMUX_PAD(0x00f8, 0x00f8, 1, __NA_, 0, VF610_ENET_PAD_CTRL),
  99 + VF610_PAD_PTD5__DSPI1_CS0 = IOMUX_PAD(0x0150, 0x0150, 3, 0x300, 1, VF610_DSPI_PAD_CTRL),
  100 + VF610_PAD_PTD6__DSPI1_SIN = IOMUX_PAD(0x0154, 0x0154, 3, 0x2fc, 1, VF610_DSPI_SIN_PAD_CTRL),
  101 + VF610_PAD_PTD7__DSPI1_SOUT = IOMUX_PAD(0x0158, 0x0158, 3, __NA_, 0, VF610_DSPI_PAD_CTRL),
  102 + VF610_PAD_PTD8__DSPI1_SCK = IOMUX_PAD(0x015c, 0x015c, 3, 0x2f8, 1, VF610_DSPI_PAD_CTRL),
94 103 VF610_PAD_PTC29__GPIO_102 = IOMUX_PAD(0x0198, 0x0198, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
95 104 VF610_PAD_PTC30__GPIO_103 = IOMUX_PAD(0x019c, 0x019c, 0, __NA_, 0, VF610_GPIO_PAD_CTRL),
96 105 VF610_PAD_PTA24__ESDHC1_CLK = IOMUX_PAD(0x0038, 0x0038, 5, __NA_, 0, VF610_SDHC_PAD_CTRL),
board/toradex/colibri_vf/colibri_vf.c
Diff comments   View file @ 508f412
... ... @@ -146,6 +146,20 @@
146 146 }
147 147 #endif
148 148  
  149 +#ifdef CONFIG_FSL_DSPI
  150 +static void setup_iomux_dspi(void)
  151 +{
  152 + static const iomux_v3_cfg_t dspi1_pads[] = {
  153 + VF610_PAD_PTD5__DSPI1_CS0,
  154 + VF610_PAD_PTD6__DSPI1_SIN,
  155 + VF610_PAD_PTD7__DSPI1_SOUT,
  156 + VF610_PAD_PTD8__DSPI1_SCK,
  157 + };
  158 +
  159 + imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads));
  160 +}
  161 +#endif
  162 +
149 163 #ifdef CONFIG_VYBRID_GPIO
150 164 static void setup_iomux_gpio(void)
151 165 {
... ... @@ -252,6 +266,9 @@
252 266  
253 267 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
254 268 CCM_CCGR0_UART0_CTRL_MASK);
  269 +#ifdef CONFIG_FSL_DSPI
  270 + setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
  271 +#endif
255 272 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
256 273 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
257 274 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
... ... @@ -362,6 +379,10 @@
362 379  
363 380 #ifdef CONFIG_VYBRID_GPIO
364 381 setup_iomux_gpio();
  382 +#endif
  383 +
  384 +#ifdef CONFIG_FSL_DSPI
  385 + setup_iomux_dspi();
365 386 #endif
366 387  
367 388 return 0;