Eric Lee / smarc-uboot

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Commit 537440da909cbdec68d036dad93a9df2eaf4fbb7

Authored by Eric Lee
1 parent e29075cdf5
Exists in smarc-imx_v2014.04_3.14.28_1.0.0_ga and in 1 other branch smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga

Update to imx_v2014.04_3.14.28_1.0.0_ga and bug fixed

Showing 20 changed files with 600 additions and 51 deletions Side-by-side Diff

... ... @@ -568,6 +568,7 @@
568 568 CONFIG_ARM_ERRATA_751472
569 569 CONFIG_ARM_ERRATA_794072
570 570 CONFIG_ARM_ERRATA_761320
  571 + CONFIG_ARM_ERRATA_845369
571 572  
572 573 If set, the workarounds for these ARM errata are applied early
573 574 during U-Boot startup. Note that these options force the
arch/arm/cpu/armv7/mx6/soc.c
Diff comments   View file @ 537440d
... ... @@ -1029,7 +1029,7 @@
1029 1029 void v7_outer_cache_enable(void)
1030 1030 {
1031 1031 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
1032   - unsigned int val;
  1032 + unsigned int val, cache_id;
1033 1033  
1034 1034 #if defined CONFIG_MX6SL
1035 1035 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
1036 1036  
1037 1037  
... ... @@ -1049,22 +1049,23 @@
1049 1049  
1050 1050 val = readl(&pl310->pl310_prefetch_ctrl);
1051 1051  
1052   - /* Turn on the L2 I/D prefetch */
1053   - val |= 0x30000000;
  1052 + /* Turn on the L2 I/D prefetch, double linefill */
  1053 + /* Set prefetch offset with any value except 23 as per errata 765569 */
  1054 + val |= 0x7000000f;
1054 1055  
1055 1056 /*
1056   - * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
1057   - * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
  1057 + * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL/SX
  1058 + * is r3p2.
1058 1059 * But according to ARM PL310 errata: 752271
1059 1060 * ID: 752271: Double linefill feature can cause data corruption
1060 1061 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
1061 1062 * Workaround: The only workaround to this erratum is to disable the
1062 1063 * double linefill feature. This is the default behavior.
1063 1064 */
1064   -
1065   -#ifndef CONFIG_MX6Q
1066   - val |= 0x40800000;
1067   -#endif
  1065 + cache_id = readl(&pl310->pl310_cache_id);
  1066 + if (((cache_id & L2X0_CACHE_ID_PART_MASK) == L2X0_CACHE_ID_PART_L310)
  1067 + && ((cache_id & L2X0_CACHE_ID_RTL_MASK) < L2X0_CACHE_ID_RTL_R3P2))
  1068 + val &= ~(1 << 30);
1068 1069 writel(val, &pl310->pl310_prefetch_ctrl);
1069 1070  
1070 1071 val = readl(&pl310->pl310_power_ctrl);
arch/arm/cpu/armv7/start.S
Diff comments   View file @ 537440d
... ... @@ -227,6 +227,11 @@
227 227 orr r0, r0, #1 << 21 @ set bit #21
228 228 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
229 229 #endif
  230 +#ifdef CONFIG_ARM_ERRATA_845369
  231 + mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
  232 + orr r0, r0, #1 << 22 @ set bit #22
  233 + mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
  234 +#endif
230 235  
231 236 mov pc, lr @ back to my caller
232 237 ENDPROC(cpu_init_cp15)
arch/arm/include/asm/arch-mx6/mx6sl_pins.h
Diff comments   View file @ 537440d
... ... @@ -57,7 +57,8 @@
57 57 MX6_PAD_I2C1_SDA__GPIO_3_13 = IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0),
58 58 MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0),
59 59 MX6_PAD_I2C1_SCL__GPIO_3_12 = IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0),
60   -
  60 + MX6_PAD_EPDC_PWRCTRL2__GPIO_2_9 = IOMUX_PAD(0x03DC, 0x00EC, 5, 0x0000, 0, 0),
  61 + MX6_PAD_EPDC_PWRCTRL3__GPIO_2_10 = IOMUX_PAD(0x03E0, 0x00F0, 5, 0x0000, 0, 0),
61 62 MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 = IOMUX_PAD(0x03E8, 0x00F8, 5, 0x0000, 0, 0),
62 63 MX6_PAD_EPDC_VCOM0__GPIO_2_3 = IOMUX_PAD(0x0410, 0x0120, 5, 0x0000, 0, 0),
63 64 MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 = IOMUX_PAD(0x03EC, 0x00FC, 5, 0x0000, 0, 0),
... ... @@ -115,7 +116,7 @@
115 116  
116 117 MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0),
117 118 MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0),
118   -
  119 + MX6_PAD_KEY_COL6__GPIO_4_4 = IOMUX_PAD(0x048C, 0x0184, 5, 0x0000, 0, 0),
119 120 MX6_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0358, 0x0068, 0, 0x0684, 0, 0),
120 121 MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x035C, 0x006C, 0, 0x0688, 0, 0),
121 122 MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x0360, 0x0070, 0, 0x067C, 0, 0),
arch/arm/include/asm/imx-common/regs-bch.h
Diff comments   View file @ 537440d
... ... @@ -5,7 +5,7 @@
5 5 * on behalf of DENX Software Engineering GmbH
6 6 *
7 7 * Based on code from LTIB:
8   - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  8 + * Copyright 2008-2014 Freescale Semiconductor, Inc. All Rights Reserved.
9 9 *
10 10 * SPDX-License-Identifier: GPL-2.0+
11 11 */
... ... @@ -148,6 +148,7 @@
148 148 #define BCH_FLASHLAYOUT0_ECC0_ECC30 (0xf << 12)
149 149 #define BCH_FLASHLAYOUT0_ECC0_ECC32 (0x10 << 12)
150 150 #define BCH_FLASHLAYOUT0_GF13_0_GF14_1 (1 << 10)
  151 +#define BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET 10
151 152 #define BCH_FLASHLAYOUT0_DATA0_SIZE_MASK 0xfff
152 153 #define BCH_FLASHLAYOUT0_DATA0_SIZE_OFFSET 0
153 154  
... ... @@ -178,6 +179,7 @@
178 179 #define BCH_FLASHLAYOUT1_ECCN_ECC30 (0xf << 12)
179 180 #define BCH_FLASHLAYOUT1_ECCN_ECC32 (0x10 << 12)
180 181 #define BCH_FLASHLAYOUT1_GF13_0_GF14_1 (1 << 10)
  182 +#define BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET 10
181 183 #define BCH_FLASHLAYOUT1_DATAN_SIZE_MASK 0xfff
182 184 #define BCH_FLASHLAYOUT1_DATAN_SIZE_OFFSET 0
183 185  
arch/arm/include/asm/pl310.h
Diff comments   View file @ 537440d
... ... @@ -75,5 +75,10 @@
75 75 void pl310_inval_range(u32 start, u32 end);
76 76 void pl310_clean_inval_range(u32 start, u32 end);
77 77  
  78 +#define L2X0_CACHE_ID_PART_MASK (0xf << 6)
  79 +#define L2X0_CACHE_ID_PART_L310 (3 << 6)
  80 +#define L2X0_CACHE_ID_RTL_MASK 0x3f
  81 +#define L2X0_CACHE_ID_RTL_R3P2 0x8
  82 +
78 83 #endif
board/embedian/smarcfimx6/smarcfimx6.c
Diff comments   View file @ 537440d
... ... @@ -28,7 +28,6 @@
28 28 #include <mxc_epdc_fb.h>
29 29 #endif
30 30 #include <asm/arch/mxc_hdmi.h>
31   -#include <asm/arch/crm_regs.h>
32 31 #include <linux/fb.h>
33 32 #include <ipu_pixfmt.h>
34 33 #include <asm/io.h>
... ... @@ -78,6 +77,9 @@
78 77  
79 78 #ifdef CONFIG_SYS_I2C_MXC
80 79 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  80 +
  81 +#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  82 +
81 83 /*I2C1 I2C_PM*/
82 84 struct i2c_pads_info i2c_pad_info1 = {
83 85 .scl = {
... ... @@ -161,6 +163,10 @@
161 163 MX6_PAD_EIM_D16__GPIO3_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
162 164 };
163 165  
  166 +iomux_v3_cfg_t const reset_out_pads[] = {
  167 + MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
  168 +};
  169 +
164 170 iomux_v3_cfg_t const enet_pads[] = {
165 171 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
166 172 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
167 173  
... ... @@ -230,16 +236,13 @@
230 236 MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
231 237 MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
232 238 MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/
233   - MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/
234   - MX6_PAD_EIM_D25__GPIO3_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/
  239 + MX6_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/
  240 + MX6_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/
235 241 };
236 242  
237 243 static void setup_spinor(void)
238 244 {
239 245 imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
240   - gpio_direction_output(IMX_GPIO_NR(5, 29), 0);
241   - gpio_direction_output(IMX_GPIO_NR(3, 24), 0);
242   - gpio_direction_output(IMX_GPIO_NR(3, 25), 0);
243 246 }
244 247 #endif
245 248  
... ... @@ -248,8 +251,8 @@
248 251 MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
249 252 MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
250 253 MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
251   - MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/
252   - MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/
  254 + MX6_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/
  255 + MX6_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/
253 256 };
254 257  
255 258 iomux_v3_cfg_t const pcie_pads[] = {
... ... @@ -264,7 +267,6 @@
264 267 gpio_direction_input(IMX_GPIO_NR(1, 16));
265 268 gpio_direction_input(IMX_GPIO_NR(1, 17));
266 269 gpio_direction_input(IMX_GPIO_NR(1, 19));
267   - gpio_direction_output(IMX_GPIO_NR(1, 20), 0);
268 270 }
269 271  
270 272 /* CAN0/FLEXCAN1 */
... ... @@ -370,6 +372,14 @@
370 372 gpio_direction_output(IMX_GPIO_NR(3, 16) , 1);
371 373 }
372 374  
  375 +static void setup_iomux_reset_out(void)
  376 +{
  377 + imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));
  378 +
  379 + /* Set CPU RESET_OUT as Output */
  380 + gpio_direction_output(IMX_GPIO_NR(6, 16) , 0);
  381 +}
  382 +
373 383 static void setup_spi1(void)
374 384 {
375 385 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
... ... @@ -1141,6 +1151,7 @@
1141 1151 int board_early_init_f(void)
1142 1152 {
1143 1153 setup_iomux_wdt();
  1154 + setup_iomux_reset_out();
1144 1155 setup_iomux_uart1();
1145 1156 setup_iomux_uart2();
1146 1157 setup_iomux_uart4();
... ... @@ -1346,7 +1357,7 @@
1346 1357  
1347 1358 #ifdef CONFIG_IMX_UDC
1348 1359 iomux_v3_cfg_t const otg_udc_pads[] = {
1349   - (MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
  1360 + (MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP)),
1350 1361 };
1351 1362 void udc_pins_setting(void)
1352 1363 {
1353 1364  
... ... @@ -1360,12 +1371,16 @@
1360 1371  
1361 1372 #ifdef CONFIG_USB_EHCI_MX6
1362 1373 iomux_v3_cfg_t const usb_otg_pads[] = {
1363   - MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
1364   - MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
  1374 + MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),
  1375 + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
  1376 + /* OTG Power enable */
  1377 + MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(OUTPUT_40OHM),
1365 1378 };
1366 1379  
1367 1380 iomux_v3_cfg_t const usb_hc1_pads[] = {
1368   - MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  1381 + MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(WEAK_PULLUP),
  1382 + /* USB1 Power enable */
  1383 + MX6_PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(OUTPUT_40OHM),
1369 1384 };
1370 1385  
1371 1386 int board_ehci_hcd_init(int port)
1372 1387  
1373 1388  
... ... @@ -1393,14 +1408,20 @@
1393 1408 {
1394 1409 switch (port) {
1395 1410 case 0:
  1411 + /* Set USB OTG Over Current */
  1412 + gpio_direction_input(IMX_GPIO_NR(1, 30));
  1413 + /* Trun On USB OTG Power */
  1414 + gpio_direction_output(IMX_GPIO_NR(1, 29),1);
1396 1415 break;
1397 1416 case 1:
1398 1417 if (on){
1399   - gpio_direction_output(IMX_GPIO_NR(1, 29), 1);
1400   - gpio_direction_input(IMX_GPIO_NR(1, 30));
  1418 + /* Set USB1 Over Current */
  1419 + gpio_direction_input(IMX_GPIO_NR(1, 27));
  1420 + /* Trun On USB1 Power */
  1421 + gpio_direction_output(IMX_GPIO_NR(1, 26),1);
1401 1422 }
1402 1423 else
1403   - gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
  1424 + gpio_direction_output(IMX_GPIO_NR(1, 26), 0);
1404 1425 break;
1405 1426 default:
1406 1427 printf("MXC USB port %d not yet supported\n", port);
board/freescale/common/recovery.c
Diff comments   View file @ 537440d
... ... @@ -70,7 +70,7 @@
70 70 puts("Fastboot: Recovery key pressing got!\n");
71 71 setup_recovery_env();
72 72 } else if (check_recovery_cmd_file()) {
73   - puts("Fastboot: Recovery command file founded!\n");
  73 + puts("Fastboot: Recovery command file found!\n");
74 74 setup_recovery_env();
75 75 } else {
76 76 puts("Fastboot: Normal\n");
board/freescale/mx6qarm2/imximage.cfg
Diff comments   View file @ 537440d
1 1 /*
2   - * Copyright (C) 2011-2014 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc.
3 3 * Jason Liu <r64343@freescale.com>
4 4 *
5 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -44,7 +44,213 @@
44 44 * Address absolute address of the register
45 45 * value value to be stored in the register
46 46 */
47   -#ifdef CONFIG_MX6DQ_LPDDR2
  47 +#ifdef CONFIG_MX6DQ_POP_LPDDR2
  48 +
  49 +DATA 4 0x020c4068 0xffffffff
  50 +DATA 4 0x020c406c 0xffffffff
  51 +DATA 4 0x020c4070 0xffffffff
  52 +DATA 4 0x020c4074 0xffffffff
  53 +DATA 4 0x020c4078 0xffffffff
  54 +DATA 4 0x020c407c 0xffffffff
  55 +DATA 4 0x020c4080 0xffffffff
  56 +DATA 4 0x020c4084 0xffffffff
  57 +
  58 +/* DCD */
  59 +DATA 4 0x020e0798 0x00080000
  60 +DATA 4 0x020e0758 0x00000000
  61 +
  62 +DATA 4 0x020e0588 0x00000030
  63 +DATA 4 0x020e0594 0x00000030
  64 +
  65 +DATA 4 0x020e056c 0x00000030
  66 +DATA 4 0x020e0578 0x00000030
  67 +DATA 4 0x020e074c 0x00000030
  68 +
  69 +DATA 4 0x020e057c 0x00000030
  70 +DATA 4 0x020e058c 0x00000000
  71 +DATA 4 0x020e059c 0x00000030
  72 +DATA 4 0x020e05a0 0x00000030
  73 +DATA 4 0x020e078c 0x00000030
  74 +
  75 +DATA 4 0x020e0750 0x00020000
  76 +DATA 4 0x020e05a8 0x00003030
  77 +DATA 4 0x020e05b0 0x00003030
  78 +DATA 4 0x020e0524 0x00003030
  79 +DATA 4 0x020e051c 0x00003030
  80 +DATA 4 0x020e0518 0x00003030
  81 +DATA 4 0x020e050c 0x00003030
  82 +DATA 4 0x020e05b8 0x00003030
  83 +DATA 4 0x020e05c0 0x00003030
  84 +
  85 +DATA 4 0x020e0774 0x00020000
  86 +DATA 4 0x020e0784 0x00000030
  87 +DATA 4 0x020e0788 0x00000030
  88 +DATA 4 0x020e0794 0x00000030
  89 +DATA 4 0x020e079c 0x00000030
  90 +DATA 4 0x020e07a0 0x00000030
  91 +DATA 4 0x020e07a4 0x00000030
  92 +DATA 4 0x020e07a8 0x00000030
  93 +DATA 4 0x020e0748 0x00000030
  94 +
  95 +DATA 4 0x020e05ac 0x00000030
  96 +DATA 4 0x020e05b4 0x00000030
  97 +DATA 4 0x020e0528 0x00000030
  98 +DATA 4 0x020e0520 0x00000030
  99 +DATA 4 0x020e0514 0x00000030
  100 +DATA 4 0x020e0510 0x00000030
  101 +DATA 4 0x020e05bc 0x00000030
  102 +DATA 4 0x020e05c4 0x00000030
  103 +
  104 +DATA 4 0x021b001c 0x00008000
  105 +DATA 4 0x021b401c 0x00008000
  106 +
  107 +DATA 4 0x021b085c 0x1B5F0107
  108 +DATA 4 0x021b485c 0x1B5F0107
  109 +
  110 +DATA 4 0x021b0800 0xA1390003
  111 +
  112 +DATA 4 0x021b0890 0x00400000
  113 +DATA 4 0x021b4890 0x00400000
  114 +
  115 +DATA 4 0x021b0848 0x3C3A3A44
  116 +DATA 4 0x021b4848 0x3C3A3A44
  117 +
  118 +DATA 4 0x021b0850 0x4238423A
  119 +DATA 4 0x021b4850 0x4238423A
  120 +
  121 +DATA 4 0x021b083c 0x20000000
  122 +DATA 4 0x021b0840 0x00000000
  123 +DATA 4 0x021b483c 0x20000000
  124 +DATA 4 0x021b4840 0x00000000
  125 +
  126 +DATA 4 0x020e0774 0x00020000
  127 +DATA 4 0x020e0784 0x00000030
  128 +DATA 4 0x020e0788 0x00000030
  129 +DATA 4 0x020e0794 0x00000030
  130 +DATA 4 0x020e079c 0x00000030
  131 +DATA 4 0x020e07a0 0x00000030
  132 +DATA 4 0x020e07a4 0x00000030
  133 +DATA 4 0x020e07a8 0x00000030
  134 +DATA 4 0x020e0748 0x00000030
  135 +
  136 +DATA 4 0x020e05ac 0x00000030
  137 +DATA 4 0x020e05b4 0x00000030
  138 +DATA 4 0x020e0528 0x00000030
  139 +DATA 4 0x020e0520 0x00000030
  140 +DATA 4 0x020e0514 0x00000030
  141 +DATA 4 0x020e0510 0x00000030
  142 +DATA 4 0x020e05bc 0x00000030
  143 +DATA 4 0x020e05c4 0x00000030
  144 +
  145 +DATA 4 0x021b001c 0x00008000
  146 +DATA 4 0x021b401c 0x00008000
  147 +
  148 +DATA 4 0x021b085c 0x1B5F0107
  149 +DATA 4 0x021b485c 0x1B5F0107
  150 +
  151 +DATA 4 0x021b0800 0xA1390003
  152 +
  153 +DATA 4 0x021b0890 0x00400000
  154 +DATA 4 0x021b4890 0x00400000
  155 +
  156 +DATA 4 0x021b0848 0x3C3A3A44
  157 +DATA 4 0x021b4848 0x3C3A3A44
  158 +
  159 +DATA 4 0x021b0850 0x4238423A
  160 +DATA 4 0x021b4850 0x4238423A
  161 +
  162 +DATA 4 0x021b083c 0x20000000
  163 +DATA 4 0x021b0840 0x00000000
  164 +DATA 4 0x021b483c 0x20000000
  165 +DATA 4 0x021b4840 0x00000000
  166 +
  167 +DATA 4 0x021b081c 0x33333333
  168 +DATA 4 0x021b0820 0x33333333
  169 +DATA 4 0x021b0824 0x33333333
  170 +DATA 4 0x021b0828 0x33333333
  171 +DATA 4 0x021b481c 0x33333333
  172 +DATA 4 0x021b4820 0x33333333
  173 +DATA 4 0x021b4824 0x33333333
  174 +DATA 4 0x021b4828 0x33333333
  175 +
  176 +DATA 4 0x021b082c 0xf3333333
  177 +DATA 4 0x021b0830 0xf3333333
  178 +DATA 4 0x021b0834 0xf3333333
  179 +DATA 4 0x021b0838 0xf3333333
  180 +DATA 4 0x021b482c 0xf3333333
  181 +DATA 4 0x021b4830 0xf3333333
  182 +DATA 4 0x021b4834 0xf3333333
  183 +DATA 4 0x021b4838 0xf3333333
  184 +
  185 +DATA 4 0x021b08b8 0x00000800
  186 +DATA 4 0x021b48b8 0x00000800
  187 +
  188 +DATA 4 0x021b0004 0x00020036
  189 +DATA 4 0x021b0008 0x00000000
  190 +DATA 4 0x021b000c 0x444961A5
  191 +DATA 4 0x021b0010 0x00160E83
  192 +DATA 4 0x021b0014 0x000000DD
  193 +
  194 +DATA 4 0x021b0018 0x0000174C
  195 +DATA 4 0x021b001c 0x00008000
  196 +DATA 4 0x021b002c 0x149F26D2
  197 +DATA 4 0x021b0030 0x00000010
  198 +DATA 4 0x021b0038 0x0021099B
  199 +DATA 4 0x021b0040 0x0000004F
  200 +DATA 4 0x021b0400 0x11420000
  201 +DATA 4 0x021b0000 0x83110000
  202 +
  203 +DATA 4 0x021b4004 0x00020036
  204 +DATA 4 0x021b4008 0x00000000
  205 +DATA 4 0x021b400c 0x444961A5
  206 +DATA 4 0x021b4010 0x00160E83
  207 +DATA 4 0x021b4014 0x000000DD
  208 +
  209 +DATA 4 0x021b4018 0x0000174C
  210 +DATA 4 0x021b401c 0x00008000
  211 +DATA 4 0x021b402c 0x149F26D2
  212 +DATA 4 0x021b4030 0x00000010
  213 +DATA 4 0x021b4038 0x0021099B
  214 +DATA 4 0x021b4040 0x00000017
  215 +DATA 4 0x021b4400 0x11420000
  216 +DATA 4 0x021b4000 0x83110000
  217 +
  218 +DATA 4 0x021b001c 0x003F8030
  219 +DATA 4 0x021b001c 0xFF0A8030
  220 +DATA 4 0x021b001c 0xC2018030
  221 +DATA 4 0x021b001c 0x06028030
  222 +DATA 4 0x021b001c 0x02038030
  223 +
  224 +DATA 4 0x021b401c 0x003F8030
  225 +DATA 4 0x021b401c 0xFF0A8030
  226 +DATA 4 0x021b401c 0xC2018030
  227 +DATA 4 0x021b401c 0x06028030
  228 +DATA 4 0x021b401c 0x02038030
  229 +
  230 +DATA 4 0x021b0800 0xA1390003
  231 +
  232 +DATA 4 0x021b0020 0x00001800
  233 +DATA 4 0x021b4020 0x00001800
  234 +
  235 +DATA 4 0x021b0818 0x00000000
  236 +DATA 4 0x021b4818 0x00000000
  237 +
  238 +DATA 4 0x021b0004 0x00025576
  239 +DATA 4 0x021b4004 0x00025576
  240 +
  241 +DATA 4 0x021b0404 0x00011006
  242 +DATA 4 0x021b4404 0x00011006
  243 +
  244 +DATA 4 0x021b001c 0x00000000
  245 +DATA 4 0x021b401c 0x00000000
  246 +
  247 +/* enable AXI cache for VDOA/VPU/IPU */
  248 +DATA 4, 0x020e0010, 0xF00000CF
  249 +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  250 +DATA 4, 0x020e0018, 0x007F007F
  251 +DATA 4, 0x020e001c, 0x007F007F
  252 +
  253 +#elif defined(CONFIG_MX6DQ_LPDDR2)
48 254 /* DCD */
49 255 DATA 4 0x020C4018 0x60324
50 256  
board/freescale/mx6qarm2/plugin.S
Diff comments   View file @ 537440d
1 1 /*
2   - * Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
  2 + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc.
3 3 *
4 4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 5 *
6 6  
... ... @@ -919,8 +919,241 @@
919 919 str r1, [r0, #0x1c]
920 920 .endm
921 921  
  922 +.macro imx6dq_pop_arm2_lpddr2_setting
  923 + ldr r0, =CCM_BASE_ADDR
  924 + ldr r1, =0xffffffff
  925 + str r1, [r0, #0x068]
  926 + ldr r1, =0xffffffff
  927 + str r1, [r0, #0x06c]
  928 + ldr r1, =0xffffffff
  929 + str r1, [r0, #0x070]
  930 + ldr r1, =0xffffffff
  931 + str r1, [r0, #0x074]
  932 + ldr r1, =0xffffffff
  933 + str r1, [r0, #0x078]
  934 + ldr r1, =0xffffffff
  935 + str r1, [r0, #0x07c]
  936 + ldr r1, =0xffffffff
  937 + str r1, [r0, #0x080]
  938 + ldr r1, =0xffffffff
  939 + str r1, [r0, #0x084]
  940 +
  941 + ldr r0, =IOMUXC_BASE_ADDR
  942 + ldr r1, =0x00080000
  943 + str r1, [r0, #0x798]
  944 + ldr r1, =0x00000000
  945 + str r1, [r0, #0x758]
  946 + ldr r1, =0x00000030
  947 + str r1, [r0, #0x588]
  948 + str r1, [r0, #0x594]
  949 + str r1, [r0, #0x56c]
  950 + str r1, [r0, #0x578]
  951 + str r1, [r0, #0x74c]
  952 + str r1, [r0, #0x57c]
  953 + str r1, [r0, #0x58c]
  954 + str r1, [r0, #0x59c]
  955 + str r1, [r0, #0x5a0]
  956 + str r1, [r0, #0x78c]
  957 +
  958 + ldr r1, =0x00020000
  959 + str r1, [r0, #0x750]
  960 + ldr r1, =0x00003030
  961 + str r1, [r0, #0x5a8]
  962 + str r1, [r0, #0x5b0]
  963 + str r1, [r0, #0x524]
  964 + str r1, [r0, #0x51c]
  965 + str r1, [r0, #0x518]
  966 + str r1, [r0, #0x50c]
  967 + str r1, [r0, #0x5b8]
  968 + str r1, [r0, #0x5c0]
  969 +
  970 + ldr r1, =0x00020000
  971 + str r1, [r0, #0x774]
  972 + ldr r1, =0x00000030
  973 + str r1, [r0, #0x784]
  974 + str r1, [r0, #0x788]
  975 + str r1, [r0, #0x794]
  976 + str r1, [r0, #0x79c]
  977 + str r1, [r0, #0x7a0]
  978 + str r1, [r0, #0x7a4]
  979 + str r1, [r0, #0x7a8]
  980 + str r1, [r0, #0x748]
  981 + str r1, [r0, #0x5ac]
  982 + str r1, [r0, #0x5b4]
  983 + str r1, [r0, #0x528]
  984 + str r1, [r0, #0x520]
  985 + str r1, [r0, #0x514]
  986 + str r1, [r0, #0x510]
  987 + str r1, [r0, #0x5bc]
  988 + str r1, [r0, #0x5c4]
  989 +
  990 + ldr r0, =MMDC_P0_BASE_ADDR
  991 + ldr r1, =MMDC_P1_BASE_ADDR
  992 + ldr r2, =0x00008000
  993 + str r2, [r0, #0x1c]
  994 + str r2, [r1, #0x1c]
  995 + ldr r2, =0x1B5F0107
  996 + str r2, [r0, #0x85c]
  997 + str r2, [r1, #0x85c]
  998 + ldr r2, =0xA1390003
  999 + str r2, [r0, #0x800]
  1000 + ldr r2, =0x00400000
  1001 + str r2, [r0, #0x890]
  1002 + str r2, [r1, #0x890]
  1003 + ldr r2, =0x3C3A3A44
  1004 + str r2, [r0, #0x848]
  1005 + str r2, [r1, #0x848]
  1006 + ldr r2, =0x4238423A
  1007 + str r2, [r0, #0x850]
  1008 + str r2, [r1, #0x850]
  1009 +
  1010 + ldr r2, =0x20000000
  1011 + str r2, [r0, #0x83c]
  1012 + ldr r2, =0x00000000
  1013 + str r2, [r0, #0x840]
  1014 + ldr r2, =0x20000000
  1015 + str r2, [r1, #0x83c]
  1016 + ldr r2, =0x00000000
  1017 + str r2, [r1, #0x840]
  1018 +
  1019 + ldr r2, =0x33333333
  1020 + str r2, [r0, #0x81c]
  1021 + str r2, [r0, #0x820]
  1022 + str r2, [r0, #0x824]
  1023 + str r2, [r0, #0x828]
  1024 + str r2, [r1, #0x81c]
  1025 + str r2, [r1, #0x820]
  1026 + str r2, [r1, #0x824]
  1027 + str r2, [r1, #0x828]
  1028 +
  1029 + ldr r2, =0xf3333333
  1030 + str r2, [r0, #0x82c]
  1031 + str r2, [r0, #0x830]
  1032 + str r2, [r0, #0x834]
  1033 + str r2, [r0, #0x838]
  1034 + str r2, [r1, #0x82c]
  1035 + str r2, [r1, #0x830]
  1036 + str r2, [r1, #0x834]
  1037 + str r2, [r1, #0x838]
  1038 +
  1039 + ldr r2, =0x00000800
  1040 + str r2, [r0, #0x8b8]
  1041 + str r2, [r1, #0x8b8]
  1042 +
  1043 + ldr r2, =0x00020036
  1044 + str r2, [r0, #0x4]
  1045 + ldr r2, =0x00000000
  1046 + str r2, [r0, #0x8]
  1047 + ldr r2, =0x444961A5
  1048 + str r2, [r0, #0xc]
  1049 + ldr r2, =0x00160E83
  1050 + str r2, [r0, #0x10]
  1051 + ldr r2, =0x000000DD
  1052 + str r2, [r0, #0x14]
  1053 +
  1054 + ldr r2, =0x0000174C
  1055 + str r2, [r0, #0x18]
  1056 + ldr r2, =0x00008000
  1057 + str r2, [r0, #0x1c]
  1058 + ldr r2, =0x149F26D2
  1059 + str r2, [r0, #0x2c]
  1060 + ldr r2, =0x00000010
  1061 + str r2, [r0, #0x30]
  1062 + ldr r2, =0x0021099B
  1063 + str r2, [r0, #0x38]
  1064 + ldr r2, =0x0000004F
  1065 + str r2, [r0, #0x40]
  1066 + ldr r2, =0x11420000
  1067 + str r2, [r0, #0x400]
  1068 + ldr r2, =0x83110000
  1069 + str r2, [r0, #0x0]
  1070 +
  1071 + ldr r2, =0x00020036
  1072 + str r2, [r1, #0x4]
  1073 + ldr r2, =0x00000000
  1074 + str r2, [r1, #0x8]
  1075 + ldr r2, =0x444961A5
  1076 + str r2, [r1, #0xc]
  1077 + ldr r2, =0x00160E83
  1078 + str r2, [r1, #0x10]
  1079 + ldr r2, =0x000000DD
  1080 + str r2, [r1, #0x14]
  1081 +
  1082 + ldr r2, =0x0000174C
  1083 + str r2, [r1, #0x18]
  1084 + ldr r2, =0x00008000
  1085 + str r2, [r1, #0x1c]
  1086 + ldr r2, =0x149F26D2
  1087 + str r2, [r1, #0x2c]
  1088 + ldr r2, =0x00000010
  1089 + str r2, [r1, #0x30]
  1090 + ldr r2, =0x0021099B
  1091 + str r2, [r1, #0x38]
  1092 + ldr r2, =0x00000017
  1093 + str r2, [r1, #0x40]
  1094 + ldr r2, =0x11420000
  1095 + str r2, [r1, #0x400]
  1096 + ldr r2, =0x83110000
  1097 + str r2, [r1, #0x0]
  1098 +
  1099 + ldr r2, =0x003F8030
  1100 + str r2, [r0, #0x1c]
  1101 + ldr r2, =0xFF0A8030
  1102 + str r2, [r0, #0x1c]
  1103 + ldr r2, =0xC2018030
  1104 + str r2, [r0, #0x1c]
  1105 + ldr r2, =0x06028030
  1106 + str r2, [r0, #0x1c]
  1107 + ldr r2, =0x02038030
  1108 + str r2, [r0, #0x1c]
  1109 +
  1110 + ldr r2, =0x003F8030
  1111 + str r2, [r1, #0x1c]
  1112 + ldr r2, =0xFF0A8030
  1113 + str r2, [r1, #0x1c]
  1114 + ldr r2, =0xC2018030
  1115 + str r2, [r1, #0x1c]
  1116 + ldr r2, =0x06028030
  1117 + str r2, [r1, #0x1c]
  1118 + ldr r2, =0x02038030
  1119 + str r2, [r1, #0x1c]
  1120 +
  1121 + ldr r2, =0xA1390003
  1122 + str r2, [r0, #0x800]
  1123 +
  1124 + ldr r2, =0x00001800
  1125 + str r2, [r0, #0x20]
  1126 + str r2, [r1, #0x20]
  1127 +
  1128 + ldr r2, =0x00000000
  1129 + str r2, [r0, #0x818]
  1130 + str r2, [r1, #0x818]
  1131 +
  1132 + ldr r2, =0x00025576
  1133 + str r2, [r0, #0x4]
  1134 + str r2, [r1, #0x4]
  1135 +
  1136 + ldr r2, =0x00011006
  1137 + str r2, [r0, #0x404]
  1138 + str r2, [r1, #0x404]
  1139 +
  1140 + ldr r2, =0x00000000
  1141 + str r2, [r0, #0x1c]
  1142 + str r2, [r1, #0x1c]
  1143 +
  1144 + ldr r0, =IOMUXC_BASE_ADDR
  1145 + ldr r1, =0xF00000CF
  1146 + str r1, [r0, #0x10]
  1147 + ldr r1, =0x007F007F
  1148 + str r1, [r0, #0x18]
  1149 + ldr r1, =0x007F007F
  1150 + str r1, [r0, #0x1c]
  1151 +.endm
  1152 +
922 1153 .macro imx6_ddr_setting
923   - #if defined (CONFIG_MX6DQ_LPDDR2)
  1154 + #if defined (CONFIG_MX6DQ_POP_LPDDR2)
  1155 + imx6dq_pop_arm2_lpddr2_setting
  1156 + #elif defined (CONFIG_MX6DQ_LPDDR2)
924 1157 imx6dqarm2_lpddr2_setting
925 1158 #elif defined (CONFIG_MX6Q)
926 1159 imx6dqarm2_ddr_setting
board/freescale/mx6slevk/mx6slevk.c
Diff comments   View file @ 537440d
... ... @@ -60,6 +60,8 @@
60 60 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
61 61 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
62 62  
  63 +#define ELAN_INTR_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_HYS)
  64 +
63 65 #define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
64 66 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
65 67  
... ... @@ -149,6 +151,12 @@
149 151 MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
150 152 };
151 153  
  154 +static iomux_v3_cfg_t const elan_pads[] = {
  155 + MX6_PAD_EPDC_PWRCTRL2__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL),
  156 + MX6_PAD_EPDC_PWRCTRL3__GPIO_2_10 | MUX_PAD_CTRL(ELAN_INTR_PAD_CTRL),
  157 + MX6_PAD_KEY_COL6__GPIO_4_4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
  158 +};
  159 +
152 160 static iomux_v3_cfg_t const epdc_enable_pads[] = {
153 161 MX6_PAD_EPDC_D0__EPDC_SDDO_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
154 162 MX6_PAD_EPDC_D1__EPDC_SDDO_1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
... ... @@ -853,6 +861,36 @@
853 861 return 0;
854 862 }
855 863  
  864 +void setup_elan_pads(void)
  865 +{
  866 +#define TOUCH_CS IMX_GPIO_NR(2, 9)
  867 +#define TOUCH_INT IMX_GPIO_NR(2, 10)
  868 +#define TOUCH_RST IMX_GPIO_NR(4, 4)
  869 + imx_iomux_v3_setup_multiple_pads(elan_pads, ARRAY_SIZE(elan_pads));
  870 +}
  871 +
  872 +void elan_init(void)
  873 +{
  874 + gpio_direction_input(TOUCH_INT);
  875 + gpio_direction_output(TOUCH_CS , 1);
  876 + gpio_set_value(TOUCH_CS, 0);
  877 + gpio_direction_output(TOUCH_RST , 1);
  878 + gpio_set_value(TOUCH_RST, 0);
  879 + mdelay(10);
  880 + gpio_set_value(TOUCH_RST, 1);
  881 + gpio_set_value(TOUCH_CS, 1);
  882 + mdelay(100);
  883 +}
  884 +
  885 +/*
  886 + * This function overwrite the function defined in
  887 + * drivers/i2c/mxc_i2c.c, which is a weak symbol
  888 + */
  889 +void i2c_force_reset_slave(void)
  890 +{
  891 + elan_init();
  892 +}
  893 +
856 894 int board_late_init(void)
857 895 {
858 896 int ret = 0;
... ... @@ -860,6 +898,7 @@
860 898 #ifdef CONFIG_SYS_I2C_MXC
861 899 setup_i2c(0, CONFIG_SYS_I2C_SPEED,
862 900 0x7f, &i2c_pad_info0);
  901 + setup_elan_pads();
863 902 ret = setup_pmic_voltages();
864 903 if (ret)
865 904 return -1;
... ... @@ -321,6 +321,7 @@
321 321 Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2_lpddr2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_LPDDR2,DDR_MB=512 Jason Liu <r64343@freescale.com>
322 322 Active arm armv7 mx6 freescale mx6qarm2 mx6dlarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,DDR_MB=2048 Jason Liu <r64343@freescale.com>
323 323 Active arm armv7 mx6 freescale mx6qarm2 mx6dlarm2_lpddr2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL,MX6DL_LPDDR2,DDR_MB=512 Jason Liu <r64343@freescale.com>
  324 +Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2_pop_lpddr2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6Q,MX6DQ_POP_LPDDR2,DDR_MB=1024
324 325 Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/mx6q.cfg,MX6Q,DEFAULT_FDT_FILE="imx6q-sabreauto.dtb",DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com>
325 326 Active arm armv7 mx6 freescale mx6qsabreauto mx6dlsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL,DEFAULT_FDT_FILE="imx6dl-sabreauto.dtb",DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com>
326 327 Active arm armv7 mx6 freescale mx6qsabreauto mx6solosabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/mx6solo.cfg,MX6SOLO,DEFAULT_FDT_FILE="imx6dl-sabreauto.dtb",DDR_MB=1024,SYS_NOSMP="nosmp" Fabio Estevam <fabio.estevam@freescale.com>
... ... @@ -44,6 +44,7 @@
44 44 U-Boot_CSF.bin U-Boot_CSF_pad.bin
45 45 cat u-boot.imx U-Boot_CSF_pad.bin > u-boot-signed.imx
46 46  
47   -NOTE: U-Boot_CSF.bin needs to be padded to the value specified in
48   -the imximage.cfg file.
  47 +NOTE: When booting from NAND, the u-boot image must be padded to the
  48 +size indicated in the Boot Data size field. The padding must be
  49 +added to the end of the file, after any U-Boot_CSF.bin.
drivers/i2c/mxc_i2c.c
Diff comments   View file @ 537440d
... ... @@ -238,6 +238,17 @@
238 238 }
239 239  
240 240 /*
  241 + * Stub implementations for outer i2c slave operations
  242 + * Any board has special requirement (i.mx6slevk) can
  243 + * overwrite the function
  244 + */
  245 +void __i2c_force_reset_slave(void)
  246 +{
  247 +}
  248 +void i2c_force_reset_slave(void)
  249 + __attribute__((weak, alias("__i2c_force_reset_slave")));
  250 +
  251 +/*
241 252 * Send start signal, chip address and
242 253 * write register address
243 254 */
... ... @@ -246,6 +257,9 @@
246 257 {
247 258 unsigned int temp;
248 259 int ret;
  260 +
  261 + /* Reset i2c slave */
  262 + i2c_force_reset_slave();
249 263  
250 264 /* Enable I2C controller */
251 265 #ifdef I2C_QUIRK_REG
drivers/mtd/nand/mxs_nand.c
Diff comments   View file @ 537440d
... ... @@ -41,6 +41,9 @@
41 41  
42 42 #define MXS_NAND_BCH_TIMEOUT 10000
43 43  
  44 +int chunk_data_chunk_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
  45 +int galois_field = 13;
  46 +
44 47 struct mxs_nand_info {
45 48 int cur_chip;
46 49  
47 50  
... ... @@ -130,12 +133,12 @@
130 133  
131 134 static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
132 135 {
133   - return page_data_size / MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
  136 + return page_data_size / chunk_data_chunk_size;
134 137 }
135 138  
136 139 static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
137 140 {
138   - return ecc_strength * 13;
  141 + return ecc_strength * galois_field;
139 142 }
140 143  
141 144 static uint32_t mxs_nand_aux_status_offset(void)
... ... @@ -149,7 +152,7 @@
149 152 int ecc_strength;
150 153  
151 154 ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
152   - / (13 * mxs_nand_ecc_chunk_cnt(page_data_size));
  155 + /(galois_field * mxs_nand_ecc_chunk_cnt(page_data_size));
153 156  
154 157 /* We need the minor even number. */
155 158 ecc_strength -= ecc_strength & 1;
... ... @@ -166,7 +169,7 @@
166 169 uint32_t block_mark_chunk_bit_offset;
167 170 uint32_t block_mark_bit_offset;
168 171  
169   - chunk_data_size_in_bits = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 8;
  172 + chunk_data_size_in_bits = chunk_data_chunk_size * 8;
170 173 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
171 174  
172 175 chunk_total_size_in_bits =
... ... @@ -966,9 +969,8 @@
966 969 uint32_t tmp;
967 970  
968 971 if (mtd->oobsize > MXS_NAND_CHUNK_DATA_CHUNK_SIZE) {
969   - printf("we do not support the NAND whose OOB size is"
970   - "larger then 512 bytes!\n");
971   - return -EINVAL;
  972 + chunk_data_chunk_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 2;
  973 + galois_field = 14;
972 974 }
973 975  
974 976 /* Configure BCH and set NFC geometry */
975 977  
976 978  
977 979  
... ... @@ -980,16 +982,20 @@
980 982 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
981 983 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
982 984 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
983   - tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
  985 + tmp |= chunk_data_chunk_size
984 986 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
  987 + tmp |= (14 == galois_field ? 1 : 0)
  988 + << BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
985 989 writel(tmp, &bch_regs->hw_bch_flash0layout0);
986 990  
987 991 tmp = (mtd->writesize + mtd->oobsize)
988 992 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
989 993 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
990 994 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
991   - tmp |= MXS_NAND_CHUNK_DATA_CHUNK_SIZE
  995 + tmp |= chunk_data_chunk_size
992 996 >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
  997 + tmp |= (14 == galois_field ? 1 : 0)
  998 + << BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
993 999 writel(tmp, &bch_regs->hw_bch_flash0layout1);
994 1000  
995 1001 /* Set *all* chip selects to use layout 0 */
drivers/mtd/nand/nand_base.c
Diff comments   View file @ 537440d
... ... @@ -2629,9 +2629,20 @@
2629 2629 if (!mtd->name)
2630 2630 mtd->name = p->model;
2631 2631 mtd->writesize = le32_to_cpu(p->byte_per_page);
2632   - mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
  2632 +
  2633 + /*
  2634 + * pages_per_block and blocks_per_lun may not be a power-of-2 size
  2635 + * (don't ask me who thought of this...). MTD assumes that these
  2636 + * dimensions will be power-of-2, so just truncate the remaining area.
  2637 + */
  2638 + mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
  2639 + mtd->erasesize *= mtd->writesize;
  2640 +
2633 2641 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2634   - chip->chipsize = le32_to_cpu(p->blocks_per_lun);
  2642 +
  2643 + /* See erasesize comment */
  2644 + chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
  2645 +
2635 2646 chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2636 2647 *busw = 0;
2637 2648 if (le16_to_cpu(p->features) & 1)
include/configs/mx6_common.h
Diff comments   View file @ 537440d
... ... @@ -17,11 +17,14 @@
17 17 #ifndef __MX6_COMMON_H
18 18 #define __MX6_COMMON_H
19 19  
20   -#define CONFIG_ARM_ERRATA_742230
21 20 #define CONFIG_ARM_ERRATA_743622
  21 +#if (defined(CONFIG_MX6QP) || defined(CONFIG_MX6Q) ||\
  22 +defined(CONFIG_MX6DL)) && !defined(CONFIG_MX6SOLO)
22 23 #define CONFIG_ARM_ERRATA_751472
23 24 #define CONFIG_ARM_ERRATA_794072
24 25 #define CONFIG_ARM_ERRATA_761320
  26 +#define CONFIG_ARM_ERRATA_845369
  27 +#endif
25 28 #define CONFIG_BOARD_POSTCLK_INIT
26 29 #define CONFIG_LDO_BYPASS_CHECK
27 30 #define CONFIG_MXC_GPT_HCLK
include/configs/smarcfimx6.h
Diff comments   View file @ 537440d
... ... @@ -50,7 +50,7 @@
50 50 #define CONFIG_USB_ETHER_ASIX
51 51 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
52 52 #define CONFIG_MXC_USB_FLAGS 0
53   -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */
  53 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
54 54  
55 55 #define CONFIG_SYS_FSL_USDHC_NUM 3
56 56 #define CONFIG_SYS_MMC_ENV_DEV 0 /* 0 SDHC, 1 SDMMC, 2 eMMC */
... ... @@ -78,7 +78,6 @@
78 78 #define CONFIG_PCI_SCAN_SHOW
79 79 #define CONFIG_PCIE_IMX
80 80 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(1, 20)
81   -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 17)
82 81 #endif
83 82  
84 83 /*#define CONFIG_SPLASH_SCREEN*/
include/configs/smarcfimx6_common.h
Diff comments   View file @ 537440d
... ... @@ -353,7 +353,7 @@
353 353 #define CONFIG_SPI_FLASH_MACRONIX
354 354 #define CONFIG_MXC_SPI
355 355 #define CONFIG_SF_DEFAULT_BUS 1
356   -#define CONFIG_SF_DEFAULT_SPEED 12000000
  356 +#define CONFIG_SF_DEFAULT_SPEED 16000000
357 357 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
358 358 #endif
359 359  
include/linux/mtd/nand.h
Diff comments   View file @ 537440d
... ... @@ -46,7 +46,7 @@
46 46 * is supported now. If you add a chip with bigger oobsize/page
47 47 * adjust this accordingly.
48 48 */
49   -#define NAND_MAX_OOBSIZE 640
  49 +#define NAND_MAX_OOBSIZE 744
50 50 #define NAND_MAX_PAGESIZE 8192
51 51  
52 52 /*