mx6: add weim registers

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

mx6: add weim registers
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam · Stefano Babic
1 parent 32c81ea65c
Showing 1 changed file with 37 additions and 0 deletions Side-by-side Diff
arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -332,6 +332,43 @@
 #define SRC_SCR_CORE_3_ENABLE_OFFSET    24
 #define SRC_SCR_CORE_3_ENABLE_MASK      (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
  
+/* WEIM registers */
+struct weim {
+	u32 cs0gcr1;
+	u32 cs0gcr2;
+	u32 cs0rcr1;
+	u32 cs0rcr2;
+	u32 cs0wcr1;
+	u32 cs0wcr2;
+
+	u32 cs1gcr1;
+	u32 cs1gcr2;
+	u32 cs1rcr1;
+	u32 cs1rcr2;
+	u32 cs1wcr1;
+	u32 cs1wcr2;
+
+	u32 cs2gcr1;
+	u32 cs2gcr2;
+	u32 cs2rcr1;
+	u32 cs2rcr2;
+	u32 cs2wcr1;
+	u32 cs2wcr2;
+
+	u32 cs3gcr1;
+	u32 cs3gcr2;
+	u32 cs3rcr1;
+	u32 cs3rcr2;
+	u32 cs3wcr1;
+	u32 cs3wcr2;
+
+	u32 unused[12];
+
+	u32 wcr;
+	u32 wiar;
+	u32 ear;
+};
+
 /* System Reset Controller (SRC) */
 struct src {
 	u32	scr;
...	...	@@ -332,6 +332,43 @@
332	332	#define SRC_SCR_CORE_3_ENABLE_OFFSET 24
333	333	#define SRC_SCR_CORE_3_ENABLE_MASK (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
334	334
	335	+/* WEIM registers */
	336	+struct weim {
	337	+ u32 cs0gcr1;
	338	+ u32 cs0gcr2;
	339	+ u32 cs0rcr1;
	340	+ u32 cs0rcr2;
	341	+ u32 cs0wcr1;
	342	+ u32 cs0wcr2;
	343	+
	344	+ u32 cs1gcr1;
	345	+ u32 cs1gcr2;
	346	+ u32 cs1rcr1;
	347	+ u32 cs1rcr2;
	348	+ u32 cs1wcr1;
	349	+ u32 cs1wcr2;
	350	+
	351	+ u32 cs2gcr1;
	352	+ u32 cs2gcr2;
	353	+ u32 cs2rcr1;
	354	+ u32 cs2rcr2;
	355	+ u32 cs2wcr1;
	356	+ u32 cs2wcr2;
	357	+
	358	+ u32 cs3gcr1;
	359	+ u32 cs3gcr2;
	360	+ u32 cs3rcr1;
	361	+ u32 cs3rcr2;
	362	+ u32 cs3wcr1;
	363	+ u32 cs3wcr2;
	364	+
	365	+ u32 unused[12];
	366	+
	367	+ u32 wcr;
	368	+ u32 wiar;
	369	+ u32 ear;
	370	+};
	371	+
335	372	/* System Reset Controller (SRC) */
336	373	struct src {
337	374	u32 scr;