Commit 5902f4ce0f2bd1411e40dc0ece3598a0fc19b2ae
Committed by
Tom Rini
1 parent
b45c48a7c3
Exists in
v2017.01-smarct4x
and in
37 other branches
ARM: Introduce erratum workaround for 430973
430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Showing 2 changed files with 14 additions and 0 deletions Side-by-side Diff
README
... | ... | @@ -693,6 +693,7 @@ |
693 | 693 | NOTE: The following can be machine specific errata. These |
694 | 694 | do have ability to provide rudimentary version and machine |
695 | 695 | specific checks, but expect no product checks. |
696 | + CONFIG_ARM_ERRATA_430973 | |
696 | 697 | CONFIG_ARM_ERRATA_454179 |
697 | 698 | CONFIG_ARM_ERRATA_798870 |
698 | 699 |
arch/arm/cpu/armv7/start.S
... | ... | @@ -202,6 +202,19 @@ |
202 | 202 | skip_errata_454179: |
203 | 203 | #endif |
204 | 204 | |
205 | +#ifdef CONFIG_ARM_ERRATA_430973 | |
206 | + cmp r2, #0x21 @ Only on < r2p1 | |
207 | + bge skip_errata_430973 | |
208 | + | |
209 | + mrc p15, 0, r0, c1, c0, 1 @ Read ACR | |
210 | + orr r0, r0, #(0x1 << 6) @ Set IBE bit | |
211 | + push {r1-r5} @ Save the cpu info registers | |
212 | + bl v7_arch_cp15_set_acr | |
213 | + pop {r1-r5} @ Restore the cpu info - fall through | |
214 | + | |
215 | +skip_errata_430973: | |
216 | +#endif | |
217 | + | |
205 | 218 | mov pc, r5 @ back to my caller |
206 | 219 | ENDPROC(cpu_init_cp15) |
207 | 220 |