Eric Lee / smarc-uboot

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Commit 5ed28948a3ffe6c735386e59c132989869beaa3e

Authored by Albert ARIBAUD
2 parents e6607cffef 83bad1026b
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

Showing 51 changed files Side-by-side Diff

arch/arm/cpu/armv7/am33xx/board.c
Diff comments   View file @ 5ed2894
... ... @@ -144,6 +144,19 @@
144 144  
145 145 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
146 146 /*
  147 + * In the case of non-SPL based booting we'll want to call these
  148 + * functions a tiny bit later as it will require gd to be set and cleared
  149 + * and that's not true in s_init in this case so we cannot do it there.
  150 + */
  151 +int board_early_init_f(void)
  152 +{
  153 + prcm_init();
  154 + set_mux_conf_regs();
  155 +
  156 + return 0;
  157 +}
  158 +
  159 +/*
147 160 * This function is the place to do per-board things such as ramp up the
148 161 * MPU clock frequency.
149 162 */
... ... @@ -224,7 +237,7 @@
224 237 set_uart_mux_conf();
225 238 setup_clocks_for_console();
226 239 uart_soft_reset();
227   -#ifdef CONFIG_NOR_BOOT
  240 +#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
228 241 gd->baudrate = CONFIG_BAUDRATE;
229 242 serial_init();
230 243 gd->have_console = 1;
231 244  
232 245  
... ... @@ -232,13 +245,14 @@
232 245 gd = &gdata;
233 246 preloader_console_init();
234 247 #endif
235   - prcm_init();
236   - set_mux_conf_regs();
237 248 #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
238 249 /* Enable RTC32K clock */
239 250 rtc32k_enable();
240 251 #endif
  252 +#ifdef CONFIG_SPL_BUILD
  253 + board_early_init_f();
241 254 sdram_init();
  255 +#endif
242 256 }
243 257 #endif
244 258  
arch/arm/cpu/armv7/am33xx/clock.c
Diff comments   View file @ 5ed2894
... ... @@ -170,9 +170,20 @@
170 170 };
171 171 }
172 172  
  173 +/*
  174 + * Before scaling up the clocks we need to have the PMIC scale up the
  175 + * voltages first. This will be dependent on which PMIC is in use
  176 + * and in some cases we may not be scaling things up at all and thus not
  177 + * need to do anything here.
  178 + */
  179 +__weak void scale_vcores(void)
  180 +{
  181 +}
  182 +
173 183 void prcm_init()
174 184 {
175 185 enable_basic_clocks();
  186 + scale_vcores();
176 187 setup_dplls();
177 188 }
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
Diff comments   View file @ 5ed2894
... ... @@ -53,6 +53,8 @@
53 53  
54 54 void setup_clocks_for_console(void)
55 55 {
  56 + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
  57 +
56 58 /* Do not add any spl_debug prints in this function */
57 59 clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
58 60 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
... ... @@ -63,6 +65,13 @@
63 65 MODULE_CLKCTRL_MODULEMODE_MASK,
64 66 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
65 67 MODULE_CLKCTRL_MODULEMODE_SHIFT);
  68 +
  69 + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
  70 + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
  71 + clkctrl = readl(&cmwkup->wkup_uart0ctrl);
  72 + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
  73 + MODULE_CLKCTRL_IDLEST_SHIFT;
  74 + }
66 75 }
67 76  
68 77 void enable_basic_clocks(void)
arch/arm/cpu/armv7/am33xx/emif4.c
Diff comments   View file @ 5ed2894
... ... @@ -21,6 +21,10 @@
21 21  
22 22 int dram_init(void)
23 23 {
  24 +#ifndef CONFIG_SKIP_LOWLEVEL_INIT
  25 + sdram_init();
  26 +#endif
  27 +
24 28 /* dram_init must store complete ramsize in gd->ram_size */
25 29 gd->ram_size = get_ram_size(
26 30 (void *)CONFIG_SYS_SDRAM_BASE,
arch/arm/cpu/armv7/keystone/init.c
Diff comments   View file @ 5ed2894
... ... @@ -8,6 +8,7 @@
8 8 */
9 9  
10 10 #include <common.h>
  11 +#include <ns16550.h>
11 12 #include <asm/io.h>
12 13 #include <asm/arch/clock.h>
13 14 #include <asm/arch/hardware.h>
... ... @@ -29,6 +30,14 @@
29 30 share_all_segments(10); /* QM PDSP */
30 31 share_all_segments(11); /* PCIE */
31 32 #endif
  33 +
  34 + /*
  35 + * just initialise the COM2 port so that TI specific
  36 + * UART register PWREMU_MGMT is initialized. Linux UART
  37 + * driver doesn't handle this.
  38 + */
  39 + NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM2),
  40 + CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
32 41  
33 42 return 0;
34 43 }
arch/arm/cpu/armv7/omap3/mem.c
Diff comments   View file @ 5ed2894
... ... @@ -21,18 +21,7 @@
21 21 struct gpmc *gpmc_cfg;
22 22  
23 23 #if defined(CONFIG_CMD_NAND)
24   -#if defined(GPMC_NAND_ECC_SP_x8_LAYOUT) || defined(GPMC_NAND_ECC_LP_x8_LAYOUT)
25 24 static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
26   - SMNAND_GPMC_CONFIG1,
27   - SMNAND_GPMC_CONFIG2,
28   - SMNAND_GPMC_CONFIG3,
29   - SMNAND_GPMC_CONFIG4,
30   - SMNAND_GPMC_CONFIG5,
31   - SMNAND_GPMC_CONFIG6,
32   - 0,
33   -};
34   -#else
35   -static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
36 25 M_NAND_GPMC_CONFIG1,
37 26 M_NAND_GPMC_CONFIG2,
38 27 M_NAND_GPMC_CONFIG3,
... ... @@ -40,7 +29,6 @@
40 29 M_NAND_GPMC_CONFIG5,
41 30 M_NAND_GPMC_CONFIG6, 0
42 31 };
43   -#endif
44 32 #endif /* CONFIG_CMD_NAND */
45 33  
46 34 #if defined(CONFIG_CMD_ONENAND)
arch/arm/include/asm/arch-am33xx/clock.h
Diff comments   View file @ 5ed2894
... ... @@ -107,6 +107,7 @@
107 107 const struct dpll_params *get_dpll_core_params(void);
108 108 const struct dpll_params *get_dpll_per_params(void);
109 109 const struct dpll_params *get_dpll_ddr_params(void);
  110 +void scale_vcores(void);
110 111 void do_setup_dpll(const struct dpll_regs *, const struct dpll_params *);
111 112 void prcm_init(void);
112 113 void enable_basic_clocks(void);
arch/arm/include/asm/arch-am33xx/cpu.h
Diff comments   View file @ 5ed2894
... ... @@ -26,7 +26,17 @@
26 26 #define TCLR_PRE BIT(5) /* Pre-scaler enable */
27 27 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
28 28 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
  29 +#define TCLR_CE BIT(6) /* compare mode enable */
  30 +#define TCLR_SCPWM BIT(7) /* pwm outpin behaviour */
  31 +#define TCLR_TCM BIT(8) /* edge detection of input pin*/
  32 +#define TCLR_TRG_SHIFT (10) /* trigmode on pwm outpin */
  33 +#define TCLR_PT BIT(12) /* pulse/toggle mode of outpin*/
  34 +#define TCLR_CAPTMODE BIT(13) /* capture mode */
  35 +#define TCLR_GPOCFG BIT(14) /* 0=output,1=input */
29 36  
  37 +#define TCFG_RESET BIT(0) /* software reset */
  38 +#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
  39 +#define TCFG_IDLEMOD_SHIFT (2) /* power management */
30 40 /* device type */
31 41 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
32 42 #define TST_DEVICE 0x0
... ... @@ -87,7 +97,8 @@
87 97 unsigned int wkctrlclkctrl; /* offset 0x04 */
88 98 unsigned int wkgpio0clkctrl; /* offset 0x08 */
89 99 unsigned int wkl4wkclkctrl; /* offset 0x0c */
90   - unsigned int resv2[4];
  100 + unsigned int timer0clkctrl; /* offset 0x10 */
  101 + unsigned int resv2[3];
91 102 unsigned int idlestdpllmpu; /* offset 0x20 */
92 103 unsigned int resv3[2];
93 104 unsigned int clkseldpllmpu; /* offset 0x2c */
... ... @@ -121,7 +132,9 @@
121 132 unsigned int wkup_uart0ctrl; /* offset 0xB4 */
122 133 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
123 134 unsigned int wkup_adctscctrl; /* offset 0xBC */
124   - unsigned int resv12[6];
  135 + unsigned int resv12;
  136 + unsigned int timer1clkctrl; /* offset 0xC4 */
  137 + unsigned int resv13[4];
125 138 unsigned int divm6dpllcore; /* offset 0xD8 */
126 139 };
127 140  
... ... @@ -178,7 +191,9 @@
178 191 unsigned int epwmss2clkctrl; /* offset 0xD8 */
179 192 unsigned int l3instrclkctrl; /* offset 0xDC */
180 193 unsigned int l3clkctrl; /* Offset 0xE0 */
181   - unsigned int resv8[4];
  194 + unsigned int resv8[2];
  195 + unsigned int timer5clkctrl; /* offset 0xEC */
  196 + unsigned int timer6clkctrl; /* offset 0xF0 */
182 197 unsigned int mmc1clkctrl; /* offset 0xF4 */
183 198 unsigned int mmc2clkctrl; /* offset 0xF8 */
184 199 unsigned int resv9[8];
185 200  
... ... @@ -191,9 +206,17 @@
191 206  
192 207 /* Encapsulating Display pll registers */
193 208 struct cm_dpll {
194   - unsigned int resv1[2];
  209 + unsigned int resv1;
  210 + unsigned int clktimer7clk; /* offset 0x04 */
195 211 unsigned int clktimer2clk; /* offset 0x08 */
196   - unsigned int resv2[10];
  212 + unsigned int clktimer3clk; /* offset 0x0C */
  213 + unsigned int clktimer4clk; /* offset 0x10 */
  214 + unsigned int resv2;
  215 + unsigned int clktimer5clk; /* offset 0x18 */
  216 + unsigned int clktimer6clk; /* offset 0x1C */
  217 + unsigned int resv3[2];
  218 + unsigned int clktimer1clk; /* offset 0x28 */
  219 + unsigned int resv4[2];
197 220 unsigned int clklcdcpixelclk; /* offset 0x34 */
198 221 };
199 222 #else
arch/arm/include/asm/arch-keystone/hardware-k2hk.h
Diff comments   View file @ 5ed2894
... ... @@ -115,8 +115,6 @@
115 115 #define K2HK_LPSC_ARM_SREFLEX 51
116 116 #define K2HK_LPSC_TETRIS 52
117 117  
118   -#define K2HK_UART0_BASE 0x02530c00
119   -
120 118 /* DDR3A definitions */
121 119 #define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000
122 120 #define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000
arch/arm/include/asm/arch-keystone/hardware.h
Diff comments   View file @ 5ed2894
... ... @@ -142,6 +142,9 @@
142 142 #define KS2_DDR3_PMCTL_OFFSET 0x38
143 143 #define KS2_DDR3_ZQCFG_OFFSET 0xC8
144 144  
  145 +#define KS2_UART0_BASE 0x02530c00
  146 +#define KS2_UART1_BASE 0x02531000
  147 +
145 148 #ifdef CONFIG_SOC_K2HK
146 149 #include <asm/arch/hardware-k2hk.h>
147 150 #endif
arch/arm/include/asm/arch-omap3/mem.h
Diff comments   View file @ 5ed2894
... ... @@ -354,14 +354,6 @@
354 354  
355 355 #define GPMC_CS_ENABLE 0x1
356 356  
357   -#define SMNAND_GPMC_CONFIG1 0x00000800
358   -#define SMNAND_GPMC_CONFIG2 0x00141400
359   -#define SMNAND_GPMC_CONFIG3 0x00141400
360   -#define SMNAND_GPMC_CONFIG4 0x0F010F01
361   -#define SMNAND_GPMC_CONFIG5 0x010C1414
362   -#define SMNAND_GPMC_CONFIG6 0x1F0F0A80
363   -#define SMNAND_GPMC_CONFIG7 0x00000C44
364   -
365 357 #define M_NAND_GPMC_CONFIG1 0x00001800
366 358 #define M_NAND_GPMC_CONFIG2 0x00141400
367 359 #define M_NAND_GPMC_CONFIG3 0x00141400
board/BuR/tseries/board.c
Diff comments   View file @ 5ed2894
... ... @@ -117,7 +117,9 @@
117 117 int board_init(void)
118 118 {
119 119 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  120 +#ifdef CONFIG_NAND
120 121 gpmc_init();
  122 +#endif
121 123 return 0;
122 124 }
123 125  
board/BuR/tseries/mux.c
Diff comments   View file @ 5ed2894
... ... @@ -27,6 +27,11 @@
27 27 };
28 28 #ifdef CONFIG_MMC
29 29 static struct module_pin_mux mmc1_pin_mux[] = {
  30 + {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
  31 + {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
  32 + {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
  33 + {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
  34 +
30 35 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
31 36 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
32 37 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
... ... @@ -125,7 +130,7 @@
125 130 {OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
126 131 /* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */
127 132 {OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)},
128   - /* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
  133 + /* GPIO2_27 (MMC0_DAT1) - MII_nNAND */
129 134 {OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
130 135 /* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
131 136 {OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
... ... @@ -148,7 +153,7 @@
148 153 * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
149 154 */
150 155 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
151   - /* GPIO0_19 (DMA_INTR0) - ISPLAY_MODE (CPLD) */
  156 + /* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
152 157 {OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
153 158 /* GPIO0_20 (DMA_INTR1) - REP-Switch */
154 159 {OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
board/compulab/cm_t35/cm_t35.c
Diff comments   View file @ 5ed2894
... ... @@ -54,12 +54,12 @@
54 54 };
55 55  
56 56 static u32 gpmc_nand_config[GPMC_MAX_REG] = {
57   - SMNAND_GPMC_CONFIG1,
58   - SMNAND_GPMC_CONFIG2,
59   - SMNAND_GPMC_CONFIG3,
60   - SMNAND_GPMC_CONFIG4,
61   - SMNAND_GPMC_CONFIG5,
62   - SMNAND_GPMC_CONFIG6,
  57 + M_NAND_GPMC_CONFIG1,
  58 + M_NAND_GPMC_CONFIG2,
  59 + M_NAND_GPMC_CONFIG3,
  60 + M_NAND_GPMC_CONFIG4,
  61 + M_NAND_GPMC_CONFIG5,
  62 + M_NAND_GPMC_CONFIG6,
63 63 0,
64 64 };
65 65  
board/ti/am43xx/Makefile
Diff comments   View file @ 5ed2894
... ... @@ -6,7 +6,7 @@
6 6 # SPDX-License-Identifier: GPL-2.0+
7 7 #
8 8  
9   -ifdef CONFIG_SPL_BUILD
  9 +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
10 10 obj-y := mux.o
11 11 endif
12 12  
board/ti/am43xx/board.c
Diff comments   View file @ 5ed2894
... ... @@ -19,6 +19,7 @@
19 19 #include <asm/arch/gpio.h>
20 20 #include <asm/emif.h>
21 21 #include "board.h"
  22 +#include <power/tps65218.h>
22 23 #include <miiphy.h>
23 24 #include <cpsw.h>
24 25  
... ... @@ -70,7 +71,7 @@
70 71 return 0;
71 72 }
72 73  
73   -#ifdef CONFIG_SPL_BUILD
  74 +#ifndef CONFIG_SKIP_LOWLEVEL_INIT
74 75  
75 76 #define NUM_OPPS 6
76 77  
... ... @@ -254,13 +255,6 @@
254 255  
255 256 const struct dpll_params *get_dpll_ddr_params(void)
256 257 {
257   - struct am43xx_board_id header;
258   -
259   - enable_i2c0_pin_mux();
260   - i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
261   - if (read_eeprom(&header) < 0)
262   - puts("Could not get board ID.\n");
263   -
264 258 if (board_is_eposevm())
265 259 return &epos_evm_dpll_ddr;
266 260 else if (board_is_gpevm())
267 261  
... ... @@ -302,8 +296,11 @@
302 296 static int get_opp_offset(int max_off, int min_off)
303 297 {
304 298 struct ctrl_stat *ctrl = (struct ctrl_stat *)CTRL_BASE;
305   - int opp = readl(&ctrl->dev_attr), offset, i;
  299 + int opp, offset, i;
306 300  
  301 + /* Bits 0:11 are defined to be the MPU_MAX_FREQ */
  302 + opp = readl(&ctrl->dev_attr) & ~0xFFFFF000;
  303 +
307 304 for (i = max_off; i >= min_off; i--) {
308 305 offset = opp & (1 << i);
309 306 if (!offset)
... ... @@ -333,6 +330,46 @@
333 330 int ind = get_sys_clk_index();
334 331  
335 332 return &dpll_per[ind];
  333 +}
  334 +
  335 +void scale_vcores(void)
  336 +{
  337 + const struct dpll_params *mpu_params;
  338 + int mpu_vdd;
  339 + struct am43xx_board_id header;
  340 +
  341 + enable_i2c0_pin_mux();
  342 + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  343 + if (read_eeprom(&header) < 0)
  344 + puts("Could not get board ID.\n");
  345 +
  346 + /* Get the frequency */
  347 + mpu_params = get_dpll_mpu_params();
  348 +
  349 + if (i2c_probe(TPS65218_CHIP_PM))
  350 + return;
  351 +
  352 + if (mpu_params->m == 1000) {
  353 + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1330MV;
  354 + } else if (mpu_params->m == 600) {
  355 + mpu_vdd = TPS65218_DCDC_VOLT_SEL_1100MV;
  356 + } else {
  357 + puts("Unknown MPU clock, not scaling\n");
  358 + return;
  359 + }
  360 +
  361 + /* Set DCDC1 (CORE) voltage to 1.1V */
  362 + if (tps65218_voltage_update(TPS65218_DCDC1,
  363 + TPS65218_DCDC_VOLT_SEL_1100MV)) {
  364 + puts("tps65218_voltage_update failure\n");
  365 + return;
  366 + }
  367 +
  368 + /* Set DCDC2 (MPU) voltage */
  369 + if (tps65218_voltage_update(TPS65218_DCDC2, mpu_vdd)) {
  370 + puts("tps65218_voltage_update failure\n");
  371 + return;
  372 + }
336 373 }
337 374  
338 375 void set_uart_mux_conf(void)
... ... @@ -279,6 +279,7 @@
279 279 Active arm armv7 am33xx ti am335x am335x_evm_uart5 am335x_evm:SERIAL6,CONS_INDEX=6,NAND Tom Rini <trini@ti.com>
280 280 Active arm armv7 am33xx ti am335x am335x_evm_usbspl am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT Tom Rini <trini@ti.com>
281 281 Active arm armv7 am33xx ti am43xx am43xx_evm am43xx_evm:SERIAL1,CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com>
  282 +Active arm armv7 am33xx ti am43xx am43xx_evm_qspiboot am43xx_evm:SERIAL1,CONS_INDEX=1,QSPI,QSPI_BOOT Lokesh Vutla <lokeshvutla@ti.com>
282 283 Active arm armv7 am33xx ti ti814x ti814x_evm - Matt Porter <matt.porter@linaro.org>
283 284 Active arm armv7 am33xx ti ti816x ti816x_evm - -
284 285 Active arm armv7 at91 atmel sama5d3_xplained sama5d3_xplained_mmc sama5d3_xplained:SAMA5D3,SYS_USE_MMC Bo Shen <voice.shen@atmel.com>
... ... @@ -190,7 +190,25 @@
190 190 This is used by SoC platforms which do not have built-in ELM
191 191 hardware engine required for BCH ECC correction.
192 192  
  193 + CONFIG_SYS_NAND_BUSWIDTH_16BIT
  194 + Indicates that NAND device has 16-bit wide data-bus. In absence of this
  195 + config, bus-width of NAND device is assumed to be either 8-bit and later
  196 + determined by reading ONFI params.
  197 + Above config is useful when NAND device's bus-width information cannot
  198 + be determined from on-chip ONFI params, like in following scenarios:
  199 + - SPL boot does not support reading of ONFI parameters. This is done to
  200 + keep SPL code foot-print small.
  201 + - In current U-Boot flow using nand_init(), driver initialization
  202 + happens in board_nand_init() which is called before any device probe
  203 + (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
  204 + not available while configuring controller. So a static CONFIG_NAND_xx
  205 + is needed to know the device's bus-width in advance.
  206 + Some drivers using above config are:
  207 + drivers/mtd/nand/mxc_nand.c
  208 + drivers/mtd/nand/ndfc.c
  209 + drivers/mtd/nand/omap_gpmc.c
193 210  
  211 +
194 212 Platform specific options
195 213 =========================
196 214 CONFIG_NAND_OMAP_GPMC
... ... @@ -231,6 +249,48 @@
231 249 8-bit BCH code with
232 250 - ecc calculation using GPMC hardware engine,
233 251 - error detection using ELM hardware engine.
  252 + OMAP_ECC_BCH16_CODE_HW
  253 + 16-bit BCH code with
  254 + - ecc calculation using GPMC hardware engine,
  255 + - error detection using ELM hardware engine.
  256 +
  257 + How to select ECC scheme on OMAP and AMxx platforms ?
  258 + -----------------------------------------------------
  259 + Though higher ECC schemes have more capability to detect and correct
  260 + bit-flips, but still selection of ECC scheme is dependent on following
  261 + - hardware engines present in SoC.
  262 + Some legacy OMAP SoC do not have ELM h/w engine thus such
  263 + SoC cannot support BCHx_HW ECC schemes.
  264 + - size of OOB/Spare region
  265 + With higher ECC schemes, more OOB/Spare area is required to
  266 + store ECC. So choice of ECC scheme is limited by NAND oobsize.
  267 +
  268 + In general following expression can help:
  269 + NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
  270 + where
  271 + NAND_OOBSIZE = number of bytes available in
  272 + OOB/spare area per NAND page.
  273 + NAND_PAGESIZE = bytes in main-area of NAND page.
  274 + ECC_BYTES = number of ECC bytes generated to
  275 + protect 512 bytes of data, which is:
  276 + 3 for HAM1_xx ecc schemes
  277 + 7 for BCH4_xx ecc schemes
  278 + 14 for BCH8_xx ecc schemes
  279 + 26 for BCH16_xx ecc schemes
  280 +
  281 + example to check for BCH16 on 2K page NAND
  282 + NAND_PAGESIZE = 2048
  283 + NAND_OOBSIZE = 64
  284 + 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
  285 + Thus BCH16 cannot be supported on 2K page NAND.
  286 +
  287 + However, for 4K pagesize NAND
  288 + NAND_PAGESIZE = 4096
  289 + NAND_OOBSIZE = 64
  290 + ECC_BYTES = 26
  291 + 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
  292 + Thus BCH16 can be supported on 4K page NAND.
  293 +
234 294  
235 295 NOTE:
236 296 =====
drivers/mtd/nand/am335x_spl_bch.c
Diff comments   View file @ 5ed2894
... ... @@ -55,7 +55,7 @@
55 55 }
56 56  
57 57 /* Shift the offset from byte addressing to word addressing. */
58   - if (this->options & NAND_BUSWIDTH_16)
  58 + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
59 59 offs >>= 1;
60 60  
61 61 /* Set ALE and clear CLE to start address cycle */
drivers/mtd/nand/atmel_nand.c
Diff comments   View file @ 5ed2894
... ... @@ -1195,7 +1195,7 @@
1195 1195  
1196 1196 hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
1197 1197  
1198   - if (this->options & NAND_BUSWIDTH_16)
  1198 + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
1199 1199 offs >>= 1;
1200 1200  
1201 1201 hwctrl(&mtd, offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
drivers/mtd/nand/nand_base.c
Diff comments   View file @ 5ed2894
... ... @@ -575,7 +575,8 @@
575 575 /* Serially input address */
576 576 if (column != -1) {
577 577 /* Adjust columns for 16 bit buswidth */
578   - if (chip->options & NAND_BUSWIDTH_16)
  578 + if ((chip->options & NAND_BUSWIDTH_16) &&
  579 + !nand_opcode_8bits(command))
579 580 column >>= 1;
580 581 chip->cmd_ctrl(mtd, column, ctrl);
581 582 ctrl &= ~NAND_CTRL_CHANGE;
... ... @@ -668,7 +669,8 @@
668 669 /* Serially input address */
669 670 if (column != -1) {
670 671 /* Adjust columns for 16 bit buswidth */
671   - if (chip->options & NAND_BUSWIDTH_16)
  672 + if ((chip->options & NAND_BUSWIDTH_16) &&
  673 + !nand_opcode_8bits(command))
672 674 column >>= 1;
673 675 chip->cmd_ctrl(mtd, column, ctrl);
674 676 ctrl &= ~NAND_CTRL_CHANGE;
... ... @@ -2582,7 +2584,7 @@
2582 2584 int *busw)
2583 2585 {
2584 2586 struct nand_onfi_params *p = &chip->onfi_params;
2585   - int i;
  2587 + int i, j;
2586 2588 int val;
2587 2589  
2588 2590 /* Try ONFI for unknown chip or LP */
... ... @@ -2593,7 +2595,8 @@
2593 2595  
2594 2596 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2595 2597 for (i = 0; i < 3; i++) {
2596   - chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
  2598 + for (j = 0; j < sizeof(*p); j++)
  2599 + ((uint8_t *)p)[j] = chip->read_byte(mtd);
2597 2600 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2598 2601 le16_to_cpu(p->crc)) {
2599 2602 pr_info("ONFI param page %d valid\n", i);
drivers/mtd/nand/nand_spl_simple.c
Diff comments   View file @ 5ed2894
... ... @@ -78,7 +78,7 @@
78 78 }
79 79  
80 80 /* Shift the offset from byte addressing to word addressing. */
81   - if (this->options & NAND_BUSWIDTH_16)
  81 + if ((this->options & NAND_BUSWIDTH_16) && !nand_opcode_8bits(cmd))
82 82 offs >>= 1;
83 83  
84 84 /* Begin command latch cycle */
drivers/mtd/nand/omap_elm.c
Diff comments   View file @ 5ed2894
... ... @@ -16,23 +16,21 @@
16 16 #include <common.h>
17 17 #include <asm/io.h>
18 18 #include <asm/errno.h>
19   -#include <linux/mtd/omap_gpmc.h>
20 19 #include <linux/mtd/omap_elm.h>
21 20 #include <asm/arch/hardware.h>
22 21  
  22 +#define DRIVER_NAME "omap-elm"
23 23 #define ELM_DEFAULT_POLY (0)
24 24  
25 25 struct elm *elm_cfg;
26 26  
27 27 /**
28   - * elm_load_syndromes - Load BCH syndromes based on nibble selection
  28 + * elm_load_syndromes - Load BCH syndromes based on bch_type selection
29 29 * @syndrome: BCH syndrome
30   - * @nibbles:
  30 + * @bch_type: BCH4/BCH8/BCH16
31 31 * @poly: Syndrome Polynomial set to use
32   - *
33   - * Load BCH syndromes based on nibble selection
34 32 */
35   -static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly)
  33 +static void elm_load_syndromes(u8 *syndrome, enum bch_level bch_type, u8 poly)
36 34 {
37 35 u32 *ptr;
38 36 u32 val;
... ... @@ -48,8 +46,7 @@
48 46 (syndrome[7] << 24);
49 47 writel(val, ptr);
50 48  
51   - /* BCH 8-bit with 26 nibbles (4*8=32) */
52   - if (nibbles > 13) {
  49 + if (bch_type == BCH_8_BIT || bch_type == BCH_16_BIT) {
53 50 /* reg 2 */
54 51 ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2];
55 52 val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) |
... ... @@ -62,8 +59,7 @@
62 59 writel(val, ptr);
63 60 }
64 61  
65   - /* BCH 16-bit with 52 nibbles (7*8=56) */
66   - if (nibbles > 26) {
  62 + if (bch_type == BCH_16_BIT) {
67 63 /* reg 4 */
68 64 ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4];
69 65 val = syndrome[16] | (syndrome[17] << 8) |
... ... @@ -87,7 +83,7 @@
87 83 /**
88 84 * elm_check_errors - Check for BCH errors and return error locations
89 85 * @syndrome: BCH syndrome
90   - * @nibbles:
  86 + * @bch_type: BCH4/BCH8/BCH16
91 87 * @error_count: Returns number of errrors in the syndrome
92 88 * @error_locations: Returns error locations (in decimal) in this array
93 89 *
94 90  
... ... @@ -95,14 +91,14 @@
95 91 * and locations in the array passed. Returns -1 if error is not correctable,
96 92 * else returns 0
97 93 */
98   -int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
  94 +int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count,
99 95 u32 *error_locations)
100 96 {
101 97 u8 poly = ELM_DEFAULT_POLY;
102 98 s8 i;
103 99 u32 location_status;
104 100  
105   - elm_load_syndromes(syndrome, nibbles, poly);
  101 + elm_load_syndromes(syndrome, bch_type, poly);
106 102  
107 103 /* start processing */
108 104 writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6])
... ... @@ -118,8 +114,10 @@
118 114  
119 115 /* check if correctable */
120 116 location_status = readl(&elm_cfg->error_location[poly].location_status);
121   - if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK))
122   - return -1;
  117 + if (!(location_status & ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK)) {
  118 + printf("%s: uncorrectable ECC errors\n", DRIVER_NAME);
  119 + return -EBADMSG;
  120 + }
123 121  
124 122 /* get error count */
125 123 *error_count = readl(&elm_cfg->error_location[poly].location_status) &
drivers/mtd/nand/omap_gpmc.c
Diff comments   View file @ 5ed2894
... ... @@ -148,35 +148,20 @@
148 148 }
149 149  
150 150 /*
151   - * Generic BCH interface
  151 + * Driver configurations
152 152 */
153   -struct nand_bch_priv {
154   - uint8_t mode;
155   - uint8_t type;
156   - uint8_t nibbles;
  153 +struct omap_nand_info {
157 154 struct bch_control *control;
158 155 enum omap_ecc ecc_scheme;
159 156 };
160 157  
161   -/* bch types */
162   -#define ECC_BCH4 0
163   -#define ECC_BCH8 1
164   -#define ECC_BCH16 2
165   -
166   -/* BCH nibbles for diff bch levels */
167   -#define ECC_BCH4_NIBBLES 13
168   -#define ECC_BCH8_NIBBLES 26
169   -#define ECC_BCH16_NIBBLES 52
170   -
171 158 /*
172 159 * This can be a single instance cause all current users have only one NAND
173 160 * with nearly the same setup (BCH8, some with ELM and others with sw BCH
174 161 * library).
175 162 * When some users with other BCH strength will exists this have to change!
176 163 */
177   -static __maybe_unused struct nand_bch_priv bch_priv = {
178   - .type = ECC_BCH8,
179   - .nibbles = ECC_BCH8_NIBBLES,
  164 +static __maybe_unused struct omap_nand_info omap_nand_info = {
180 165 .control = NULL
181 166 };
182 167  
... ... @@ -206,7 +191,7 @@
206 191 static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode)
207 192 {
208 193 struct nand_chip *nand = mtd->priv;
209   - struct nand_bch_priv *bch = nand->priv;
  194 + struct omap_nand_info *info = nand->priv;
210 195 unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0;
211 196 unsigned int ecc_algo = 0;
212 197 unsigned int bch_type = 0;
... ... @@ -215,7 +200,7 @@
215 200 u32 ecc_config_val = 0;
216 201  
217 202 /* configure GPMC for specific ecc-scheme */
218   - switch (bch->ecc_scheme) {
  203 + switch (info->ecc_scheme) {
219 204 case OMAP_ECC_HAM1_CODE_SW:
220 205 return;
221 206 case OMAP_ECC_HAM1_CODE_HW:
... ... @@ -239,6 +224,19 @@
239 224 eccsize1 = 2; /* non-ECC bits in nibbles per sector */
240 225 }
241 226 break;
  227 + case OMAP_ECC_BCH16_CODE_HW:
  228 + ecc_algo = 0x1;
  229 + bch_type = 0x2;
  230 + if (mode == NAND_ECC_WRITE) {
  231 + bch_wrapmode = 0x01;
  232 + eccsize0 = 0; /* extra bits in nibbles per sector */
  233 + eccsize1 = 52; /* OOB bits in nibbles per sector */
  234 + } else {
  235 + bch_wrapmode = 0x01;
  236 + eccsize0 = 52; /* ECC bits in nibbles per sector */
  237 + eccsize1 = 0; /* non-ECC bits in nibbles per sector */
  238 + }
  239 + break;
242 240 default:
243 241 return;
244 242 }
245 243  
... ... @@ -277,11 +275,11 @@
277 275 uint8_t *ecc_code)
278 276 {
279 277 struct nand_chip *chip = mtd->priv;
280   - struct nand_bch_priv *bch = chip->priv;
  278 + struct omap_nand_info *info = chip->priv;
281 279 uint32_t *ptr, val = 0;
282 280 int8_t i = 0, j;
283 281  
284   - switch (bch->ecc_scheme) {
  282 + switch (info->ecc_scheme) {
285 283 case OMAP_ECC_HAM1_CODE_HW:
286 284 val = readl(&gpmc_cfg->ecc1_result);
287 285 ecc_code[0] = val & 0xFF;
288 286  
... ... @@ -305,11 +303,34 @@
305 303 ptr--;
306 304 }
307 305 break;
  306 + case OMAP_ECC_BCH16_CODE_HW:
  307 + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[2]);
  308 + ecc_code[i++] = (val >> 8) & 0xFF;
  309 + ecc_code[i++] = (val >> 0) & 0xFF;
  310 + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[1]);
  311 + ecc_code[i++] = (val >> 24) & 0xFF;
  312 + ecc_code[i++] = (val >> 16) & 0xFF;
  313 + ecc_code[i++] = (val >> 8) & 0xFF;
  314 + ecc_code[i++] = (val >> 0) & 0xFF;
  315 + val = readl(&gpmc_cfg->bch_result_4_6[0].bch_result_x[0]);
  316 + ecc_code[i++] = (val >> 24) & 0xFF;
  317 + ecc_code[i++] = (val >> 16) & 0xFF;
  318 + ecc_code[i++] = (val >> 8) & 0xFF;
  319 + ecc_code[i++] = (val >> 0) & 0xFF;
  320 + for (j = 3; j >= 0; j--) {
  321 + val = readl(&gpmc_cfg->bch_result_0_3[0].bch_result_x[j]
  322 + );
  323 + ecc_code[i++] = (val >> 24) & 0xFF;
  324 + ecc_code[i++] = (val >> 16) & 0xFF;
  325 + ecc_code[i++] = (val >> 8) & 0xFF;
  326 + ecc_code[i++] = (val >> 0) & 0xFF;
  327 + }
  328 + break;
308 329 default:
309 330 return -EINVAL;
310 331 }
311 332 /* ECC scheme specific syndrome customizations */
312   - switch (bch->ecc_scheme) {
  333 + switch (info->ecc_scheme) {
313 334 case OMAP_ECC_HAM1_CODE_HW:
314 335 break;
315 336 #ifdef CONFIG_BCH
... ... @@ -323,6 +344,8 @@
323 344 case OMAP_ECC_BCH8_CODE_HW:
324 345 ecc_code[chip->ecc.bytes - 1] = 0x00;
325 346 break;
  347 + case OMAP_ECC_BCH16_CODE_HW:
  348 + break;
326 349 default:
327 350 return -EINVAL;
328 351 }
329 352  
330 353  
... ... @@ -345,16 +368,17 @@
345 368 uint8_t *read_ecc, uint8_t *calc_ecc)
346 369 {
347 370 struct nand_chip *chip = mtd->priv;
348   - struct nand_bch_priv *bch = chip->priv;
349   - uint32_t eccbytes = chip->ecc.bytes;
  371 + struct omap_nand_info *info = chip->priv;
  372 + struct nand_ecc_ctrl *ecc = &chip->ecc;
350 373 uint32_t error_count = 0, error_max;
351   - uint32_t error_loc[8];
  374 + uint32_t error_loc[ELM_MAX_ERROR_COUNT];
  375 + enum bch_level bch_type;
352 376 uint32_t i, ecc_flag = 0;
353 377 uint8_t count, err = 0;
354 378 uint32_t byte_pos, bit_pos;
355 379  
356 380 /* check calculated ecc */
357   - for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
  381 + for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
358 382 if (calc_ecc[i] != 0x00)
359 383 ecc_flag = 1;
360 384 }
... ... @@ -363,7 +387,7 @@
363 387  
364 388 /* check for whether its a erased-page */
365 389 ecc_flag = 0;
366   - for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) {
  390 + for (i = 0; i < ecc->bytes && !ecc_flag; i++) {
367 391 if (read_ecc[i] != 0xff)
368 392 ecc_flag = 1;
369 393 }
370 394  
371 395  
372 396  
373 397  
374 398  
375 399  
... ... @@ -374,26 +398,34 @@
374 398 * while reading ECC result we read it in big endian.
375 399 * Hence while loading to ELM we have rotate to get the right endian.
376 400 */
377   - switch (bch->ecc_scheme) {
  401 + switch (info->ecc_scheme) {
378 402 case OMAP_ECC_BCH8_CODE_HW:
379   - omap_reverse_list(calc_ecc, eccbytes - 1);
  403 + bch_type = BCH_8_BIT;
  404 + omap_reverse_list(calc_ecc, ecc->bytes - 1);
380 405 break;
  406 + case OMAP_ECC_BCH16_CODE_HW:
  407 + bch_type = BCH_16_BIT;
  408 + omap_reverse_list(calc_ecc, ecc->bytes);
  409 + break;
381 410 default:
382 411 return -EINVAL;
383 412 }
384 413 /* use elm module to check for errors */
385   - elm_config((enum bch_level)(bch->type));
386   - if (elm_check_error(calc_ecc, bch->nibbles, &error_count, error_loc)) {
387   - printf("nand: error: uncorrectable ECC errors\n");
388   - return -EINVAL;
389   - }
  414 + elm_config(bch_type);
  415 + err = elm_check_error(calc_ecc, bch_type, &error_count, error_loc);
  416 + if (err)
  417 + return err;
  418 +
390 419 /* correct bch error */
391 420 for (count = 0; count < error_count; count++) {
392   - switch (bch->type) {
393   - case ECC_BCH8:
  421 + switch (info->ecc_scheme) {
  422 + case OMAP_ECC_BCH8_CODE_HW:
394 423 /* 14th byte in ECC is reserved to match ROM layout */
395   - error_max = SECTOR_BYTES + (eccbytes - 1);
  424 + error_max = SECTOR_BYTES + (ecc->bytes - 1);
396 425 break;
  426 + case OMAP_ECC_BCH16_CODE_HW:
  427 + error_max = SECTOR_BYTES + ecc->bytes;
  428 + break;
397 429 default:
398 430 return -EINVAL;
399 431 }
400 432  
... ... @@ -496,10 +528,10 @@
496 528 /* cannot correct more than 8 errors */
497 529 unsigned int errloc[8];
498 530 struct nand_chip *chip = mtd->priv;
499   - struct nand_bch_priv *chip_priv = chip->priv;
500   - struct bch_control *bch = chip_priv->control;
  531 + struct omap_nand_info *info = chip->priv;
501 532  
502   - count = decode_bch(bch, NULL, 512, read_ecc, calc_ecc, NULL, errloc);
  533 + count = decode_bch(info->control, NULL, 512, read_ecc, calc_ecc,
  534 + NULL, errloc);
503 535 if (count > 0) {
504 536 /* correct errors */
505 537 for (i = 0; i < count; i++) {
506 538  
... ... @@ -535,15 +567,11 @@
535 567 static void __maybe_unused omap_free_bch(struct mtd_info *mtd)
536 568 {
537 569 struct nand_chip *chip = mtd->priv;
538   - struct nand_bch_priv *chip_priv = chip->priv;
539   - struct bch_control *bch = NULL;
  570 + struct omap_nand_info *info = chip->priv;
540 571  
541   - if (chip_priv)
542   - bch = chip_priv->control;
543   -
544   - if (bch) {
545   - free_bch(bch);
546   - chip_priv->control = NULL;
  572 + if (info->control) {
  573 + free_bch(info->control);
  574 + info->control = NULL;
547 575 }
548 576 }
549 577 #endif /* CONFIG_BCH */
... ... @@ -557,7 +585,7 @@
557 585 */
558 586 static int omap_select_ecc_scheme(struct nand_chip *nand,
559 587 enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) {
560   - struct nand_bch_priv *bch = nand->priv;
  588 + struct omap_nand_info *info = nand->priv;
561 589 struct nand_ecclayout *ecclayout = &omap_ecclayout;
562 590 int eccsteps = pagesize / SECTOR_BYTES;
563 591 int i;
564 592  
... ... @@ -567,12 +595,10 @@
567 595 debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n");
568 596 /* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
569 597 * initialized in nand_scan_tail(), so just set ecc.mode */
570   - bch_priv.control = NULL;
571   - bch_priv.type = 0;
  598 + info->control = NULL;
572 599 nand->ecc.mode = NAND_ECC_SOFT;
573 600 nand->ecc.layout = NULL;
574 601 nand->ecc.size = 0;
575   - bch->ecc_scheme = OMAP_ECC_HAM1_CODE_SW;
576 602 break;
577 603  
578 604 case OMAP_ECC_HAM1_CODE_HW:
... ... @@ -583,8 +609,7 @@
583 609 (3 * eccsteps) + BADBLOCK_MARKER_LENGTH));
584 610 return -EINVAL;
585 611 }
586   - bch_priv.control = NULL;
587   - bch_priv.type = 0;
  612 + info->control = NULL;
588 613 /* populate ecc specific fields */
589 614 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
590 615 nand->ecc.mode = NAND_ECC_HW;
... ... @@ -605,7 +630,6 @@
605 630 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
606 631 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
607 632 BADBLOCK_MARKER_LENGTH;
608   - bch->ecc_scheme = OMAP_ECC_HAM1_CODE_HW;
609 633 break;
610 634  
611 635 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW:
612 636  
... ... @@ -618,12 +642,11 @@
618 642 return -EINVAL;
619 643 }
620 644 /* check if BCH S/W library can be used for error detection */
621   - bch_priv.control = init_bch(13, 8, 0x201b);
622   - if (!bch_priv.control) {
  645 + info->control = init_bch(13, 8, 0x201b);
  646 + if (!info->control) {
623 647 printf("nand: error: could not init_bch()\n");
624 648 return -ENODEV;
625 649 }
626   - bch_priv.type = ECC_BCH8;
627 650 /* populate ecc specific fields */
628 651 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
629 652 nand->ecc.mode = NAND_ECC_HW;
... ... @@ -647,7 +670,6 @@
647 670 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
648 671 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
649 672 BADBLOCK_MARKER_LENGTH;
650   - bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
651 673 break;
652 674 #else
653 675 printf("nand: error: CONFIG_BCH required for ECC\n");
... ... @@ -665,7 +687,7 @@
665 687 }
666 688 /* intialize ELM for ECC error detection */
667 689 elm_init();
668   - bch_priv.type = ECC_BCH8;
  690 + info->control = NULL;
669 691 /* populate ecc specific fields */
670 692 memset(&nand->ecc, 0, sizeof(struct nand_ecc_ctrl));
671 693 nand->ecc.mode = NAND_ECC_HW;
672 694  
... ... @@ -683,13 +705,44 @@
683 705 ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
684 706 ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes -
685 707 BADBLOCK_MARKER_LENGTH;
686   - bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW;
687 708 break;
688 709 #else
689 710 printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
690 711 return -EINVAL;
691 712 #endif
692 713  
  714 + case OMAP_ECC_BCH16_CODE_HW:
  715 +#ifdef CONFIG_NAND_OMAP_ELM
  716 + debug("nand: using OMAP_ECC_BCH16_CODE_HW\n");
  717 + /* check ecc-scheme requirements before updating ecc info */
  718 + if ((26 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) {
  719 + printf("nand: error: insufficient OOB: require=%d\n", (
  720 + (26 * eccsteps) + BADBLOCK_MARKER_LENGTH));
  721 + return -EINVAL;
  722 + }
  723 + /* intialize ELM for ECC error detection */
  724 + elm_init();
  725 + /* populate ecc specific fields */
  726 + nand->ecc.mode = NAND_ECC_HW;
  727 + nand->ecc.size = SECTOR_BYTES;
  728 + nand->ecc.bytes = 26;
  729 + nand->ecc.strength = 16;
  730 + nand->ecc.hwctl = omap_enable_hwecc;
  731 + nand->ecc.correct = omap_correct_data_bch;
  732 + nand->ecc.calculate = omap_calculate_ecc;
  733 + nand->ecc.read_page = omap_read_page_bch;
  734 + /* define ecc-layout */
  735 + ecclayout->eccbytes = nand->ecc.bytes * eccsteps;
  736 + for (i = 0; i < ecclayout->eccbytes; i++)
  737 + ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH;
  738 + ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH;
  739 + ecclayout->oobfree[0].length = oobsize - nand->ecc.bytes -
  740 + BADBLOCK_MARKER_LENGTH;
  741 + break;
  742 +#else
  743 + printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n");
  744 + return -EINVAL;
  745 +#endif
693 746 default:
694 747 debug("nand: error: ecc scheme not enabled or supported\n");
695 748 return -EINVAL;
... ... @@ -699,6 +752,7 @@
699 752 if (ecc_scheme != OMAP_ECC_HAM1_CODE_SW)
700 753 nand->ecc.layout = ecclayout;
701 754  
  755 + info->ecc_scheme = ecc_scheme;
702 756 return 0;
703 757 }
704 758  
705 759  
706 760  
... ... @@ -802,16 +856,21 @@
802 856  
803 857 nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat;
804 858 nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd;
805   - nand->priv = &bch_priv;
  859 + nand->priv = &omap_nand_info;
806 860 nand->cmd_ctrl = omap_nand_hwcontrol;
807 861 nand->options |= NAND_NO_PADDING | NAND_CACHEPRG;
808   - /* If we are 16 bit dev, our gpmc config tells us that */
809   - if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000)
810   - nand->options |= NAND_BUSWIDTH_16;
811   -
812 862 nand->chip_delay = 100;
813 863 nand->ecc.layout = &omap_ecclayout;
814 864  
  865 + /* configure driver and controller based on NAND device bus-width */
  866 + gpmc_config = readl(&gpmc_cfg->cs[cs].config1);
  867 +#if defined(CONFIG_SYS_NAND_BUSWIDTH_16BIT)
  868 + nand->options |= NAND_BUSWIDTH_16;
  869 + writel(gpmc_config | (0x1 << 12), &gpmc_cfg->cs[cs].config1);
  870 +#else
  871 + nand->options &= ~NAND_BUSWIDTH_16;
  872 + writel(gpmc_config & ~(0x1 << 12), &gpmc_cfg->cs[cs].config1);
  873 +#endif
815 874 /* select ECC scheme */
816 875 #if defined(CONFIG_NAND_OMAP_ECCSCHEME)
817 876 err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME,
drivers/power/pmic/Makefile
Diff comments   View file @ 5ed2894
... ... @@ -13,5 +13,6 @@
13 13 obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
14 14 obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o
15 15 obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
  16 +obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o
16 17 obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o
drivers/power/pmic/pmic_tps65218.c
Diff comments   View file @ 5ed2894
  1 +/*
  2 + * (C) Copyright 2011-2013
  3 + * Texas Instruments, <www.ti.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <i2c.h>
  10 +#include <power/tps65218.h>
  11 +
  12 +/**
  13 + * tps65218_reg_write() - Generic function that can write a TPS65218 PMIC
  14 + * register or bit field regardless of protection
  15 + * level.
  16 + *
  17 + * @prot_level: Register password protection. Use
  18 + * TPS65218_PROT_LEVEL_NONE,
  19 + * TPS65218_PROT_LEVEL_1 or TPS65218_PROT_LEVEL_2
  20 + * @dest_reg: Register address to write.
  21 + * @dest_val: Value to write.
  22 + * @mask: Bit mask (8 bits) to be applied. Function will only
  23 + * change bits that are set in the bit mask.
  24 + *
  25 + * @return: 0 for success, not 0 on failure, as per the i2c API
  26 + */
  27 +int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
  28 + uchar mask)
  29 +{
  30 + uchar read_val;
  31 + uchar xor_reg;
  32 + int ret;
  33 +
  34 + /*
  35 + * If we are affecting only a bit field, read dest_reg and apply the
  36 + * mask
  37 + */
  38 + if (mask != TPS65218_MASK_ALL_BITS) {
  39 + ret = i2c_read(TPS65218_CHIP_PM, dest_reg, 1, &read_val, 1);
  40 + if (ret)
  41 + return ret;
  42 + read_val &= (~mask);
  43 + read_val |= (dest_val & mask);
  44 + dest_val = read_val;
  45 + }
  46 +
  47 + if (prot_level > 0) {
  48 + xor_reg = dest_reg ^ TPS65218_PASSWORD_UNLOCK;
  49 + ret = i2c_write(TPS65218_CHIP_PM, TPS65218_PASSWORD, 1,
  50 + &xor_reg, 1);
  51 + if (ret)
  52 + return ret;
  53 + }
  54 +
  55 + ret = i2c_write(TPS65218_CHIP_PM, dest_reg, 1, &dest_val, 1);
  56 + if (ret)
  57 + return ret;
  58 +
  59 + if (prot_level == TPS65218_PROT_LEVEL_2) {
  60 + ret = i2c_write(TPS65218_CHIP_PM, TPS65218_PASSWORD, 1,
  61 + &xor_reg, 1);
  62 + if (ret)
  63 + return ret;
  64 +
  65 + ret = i2c_write(TPS65218_CHIP_PM, dest_reg, 1, &dest_val, 1);
  66 + if (ret)
  67 + return ret;
  68 + }
  69 +
  70 + return 0;
  71 +}
  72 +
  73 +/**
  74 + * tps65218_voltage_update() - Function to change a voltage level, as this
  75 + * is a multi-step process.
  76 + * @dc_cntrl_reg: DC voltage control register to change.
  77 + * @volt_sel: New value for the voltage register
  78 + * @return: 0 for success, not 0 on failure.
  79 + */
  80 +int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel)
  81 +{
  82 + if ((dc_cntrl_reg != TPS65218_DCDC1) &&
  83 + (dc_cntrl_reg != TPS65218_DCDC2))
  84 + return 1;
  85 +
  86 + /* set voltage level */
  87 + if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, dc_cntrl_reg, volt_sel,
  88 + TPS65218_MASK_ALL_BITS))
  89 + return 1;
  90 +
  91 + /* set GO bit to initiate voltage transition */
  92 + if (tps65218_reg_write(TPS65218_PROT_LEVEL_2, TPS65218_SLEW,
  93 + TPS65218_DCDC_GO, TPS65218_DCDC_GO))
  94 + return 1;
  95 +
  96 + return 0;
  97 +}
drivers/spi/ti_qspi.c
Diff comments   View file @ 5ed2894
... ... @@ -106,6 +106,7 @@
106 106 slave->memory_map = (void *)MMAP_START_ADDR_DRA;
107 107 #else
108 108 slave->memory_map = (void *)MMAP_START_ADDR_AM43x;
  109 + slave->op_mode_rx = 8;
109 110 #endif
110 111  
111 112 memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
include/configs/am3517_crane.h
Diff comments   View file @ 5ed2894
... ... @@ -329,6 +329,7 @@
329 329 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
330 330  
331 331 /* NAND boot config */
  332 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
332 333 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
333 334 #define CONFIG_SYS_NAND_PAGE_COUNT 64
334 335 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
include/configs/am43xx_evm.h
Diff comments   View file @ 5ed2894
... ... @@ -32,11 +32,15 @@
32 32 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
33 33 #define CONFIG_SYS_I2C_MULTI_EEPROMS
34 34  
  35 +/* Power */
  36 +#define CONFIG_POWER_TPS65218
  37 +
35 38 /* SPL defines. */
36 39 #define CONFIG_SPL_TEXT_BASE 0x40300350
37 40 #define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */
38 41 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \
39 42 (128 << 20))
  43 +#define CONFIG_SPL_POWER_SUPPORT
40 44 #define CONFIG_SPL_YMODEM_SUPPORT
41 45  
42 46 /* Enabling L2 Cache */
43 47  
44 48  
... ... @@ -48,15 +52,24 @@
48 52 * Since SPL did pll and ddr initialization for us,
49 53 * we don't need to do it twice.
50 54 */
51   -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
  55 +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT)
52 56 #define CONFIG_SKIP_LOWLEVEL_INIT
53 57 #endif
54 58  
  59 +/*
  60 + * When building U-Boot such that there is no previous loader
  61 + * we need to call board_early_init_f. This is taken care of in
  62 + * s_init when we have SPL used.
  63 + */
  64 +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL)
  65 +#define CONFIG_BOARD_EARLY_INIT_F
  66 +#endif
  67 +
55 68 /* Now bring in the rest of the common code. */
56 69 #include <configs/ti_armv7_common.h>
57 70  
58   -/* Always 128 KiB env size */
59   -#define CONFIG_ENV_SIZE (128 << 10)
  71 +/* Always 64 KiB env size */
  72 +#define CONFIG_ENV_SIZE (64 << 10)
60 73  
61 74 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
62 75  
... ... @@ -86,6 +99,30 @@
86 99 #define CONFIG_OMAP_USB_PHY
87 100 #define CONFIG_AM437X_USB2PHY2_HOST
88 101  
  102 +#ifdef CONFIG_QSPI_BOOT
  103 +#define CONFIG_SYS_TEXT_BASE 0x30000000
  104 +#undef CONFIG_ENV_IS_NOWHERE
  105 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  106 +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  107 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  108 +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */
  109 +#define CONFIG_ENV_OFFSET 0x110000
  110 +#define CONFIG_ENV_OFFSET_REDUND 0x120000
  111 +#ifdef MTDIDS_DEFAULT
  112 +#undef MTDIDS_DEFAULT
  113 +#endif
  114 +#ifdef MTDPARTS_DEFAULT
  115 +#undef MTDPARTS_DEFAULT
  116 +#endif
  117 +#define MTDPARTS_DEFAULT "mtdparts=qspi.0:512k(QSPI.u-boot)," \
  118 + "512k(QSPI.u-boot.backup)," \
  119 + "512k(QSPI.u-boot-spl-os)," \
  120 + "64k(QSPI.u-boot-env)," \
  121 + "64k(QSPI.u-boot-env.backup)," \
  122 + "8m(QSPI.kernel)," \
  123 + "-(QSPI.file-system)"
  124 +#endif
  125 +
89 126 /* SPI */
90 127 #undef CONFIG_OMAP3_SPI
91 128 #define CONFIG_TI_QSPI
... ... @@ -94,6 +131,7 @@
94 131 #define CONFIG_CMD_SF
95 132 #define CONFIG_CMD_SPI
96 133 #define CONFIG_TI_SPI_MMAP
  134 +#define CONFIG_SPI_FLASH_BAR
97 135 #define CONFIG_QSPI_SEL_GPIO 48
98 136 #define CONFIG_SF_DEFAULT_SPEED 48000000
99 137 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3
... ... @@ -145,6 +183,7 @@
145 183 "loadfdt=load ${devtype} ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
146 184 "mmcboot=mmc dev ${mmcdev}; " \
147 185 "setenv devnum ${mmcdev}; " \
  186 + "setenv devtype mmc; " \
148 187 "if mmc rescan; then " \
149 188 "echo SD/MMC found on device ${devnum};" \
150 189 "if run loadbootenv; then " \
include/configs/bur_am335x_common.h
Diff comments   View file @ 5ed2894
... ... @@ -12,6 +12,8 @@
12 12 #ifndef __BUR_AM335X_COMMON_H__
13 13 #define __BUR_AM335X_COMMON_H__
14 14 /* ------------------------------------------------------------------------- */
  15 +#define CONFIG_SYS_GENERIC_BOARD
  16 +
15 17 #define CONFIG_AM33XX
16 18 #define CONFIG_OMAP
17 19 #define CONFIG_OMAP_COMMON
... ... @@ -94,7 +96,7 @@
94 96 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000
95 97 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1
96 98 #define CONFIG_SYS_I2C_OMAP24XX
97   -
  99 +#define CONFIG_CMD_I2C
98 100 /* GPIO */
99 101 #define CONFIG_OMAP_GPIO
100 102 #define CONFIG_CMD_GPIO
include/configs/cm_t335.h
Diff comments   View file @ 5ed2894
... ... @@ -141,7 +141,6 @@
141 141 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
142 142  
143 143 #define CONFIG_CMD_NAND
144   -#define GPMC_NAND_ECC_LP_x8_LAYOUT
145 144 #define MTDIDS_DEFAULT "nand0=nand"
146 145 #define MTDPARTS_DEFAULT "mtdparts=nand:2m(spl)," \
147 146 "1m(u-boot),1m(u-boot-env)," \
include/configs/cm_t35.h
Diff comments   View file @ 5ed2894
... ... @@ -158,7 +158,6 @@
158 158 /* CS0 */
159 159 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
160 160 /* devices */
161   -#define GPMC_NAND_ECC_LP_x8_LAYOUT
162 161  
163 162 /* Environment information */
164 163 #define CONFIG_BOOTDELAY 3
include/configs/devkit8000.h
Diff comments   View file @ 5ed2894
... ... @@ -314,6 +314,7 @@
314 314 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
315 315  
316 316 /* NAND boot config */
  317 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
317 318 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
318 319 #define CONFIG_SYS_NAND_PAGE_COUNT 64
319 320 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
include/configs/dig297.h
Diff comments   View file @ 5ed2894
... ... @@ -138,6 +138,7 @@
138 138 * Board NAND Info.
139 139 */
140 140 #define CONFIG_NAND_OMAP_GPMC
  141 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
141 142 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
142 143 /* to access nand */
143 144 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
include/configs/k2hk_evm.h
Diff comments   View file @ 5ed2894
... ... @@ -71,7 +71,8 @@
71 71 #define CONFIG_SYS_NS16550_SERIAL
72 72 #define CONFIG_SYS_NS16550_MEM32
73 73 #define CONFIG_SYS_NS16550_REG_SIZE -4
74   -#define CONFIG_SYS_NS16550_COM1 K2HK_UART0_BASE
  74 +#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE
  75 +#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE
75 76 #define CONFIG_SYS_NS16550_CLK clk_get_rate(K2HK_CLK1_6)
76 77 #define CONFIG_CONS_INDEX 1
77 78 #define CONFIG_BAUDRATE 115200
... ... @@ -130,6 +131,7 @@
130 131  
131 132 /* NAND Configuration */
132 133 #define CONFIG_NAND_DAVINCI
  134 +#define CONFIG_CMD_NAND_ECCLAYOUT
133 135 #define CONFIG_SYS_NAND_CS 2
134 136 #define CONFIG_SYS_NAND_USE_FLASH_BBT
135 137 #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
include/configs/omap3_beagle.h
Diff comments   View file @ 5ed2894
... ... @@ -295,6 +295,7 @@
295 295 #define CONFIG_SPL_OMAP3_ID_NAND
296 296  
297 297 /* NAND boot config */
  298 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
298 299 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
299 300 #define CONFIG_SYS_NAND_PAGE_COUNT 64
300 301 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
include/configs/omap3_evm_common.h
Diff comments   View file @ 5ed2894
... ... @@ -120,7 +120,7 @@
120 120  
121 121 /* Max number of NAND devices */
122 122 #define CONFIG_SYS_MAX_NAND_DEVICE 1
123   -
  123 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
124 124 /* Timeout values (in ticks) */
125 125 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
126 126 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
include/configs/omap3_igep00x0.h
Diff comments   View file @ 5ed2894
... ... @@ -187,6 +187,7 @@
187 187  
188 188 /* NAND boot config */
189 189 #ifdef CONFIG_NAND
  190 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
190 191 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
191 192 #define CONFIG_SYS_NAND_PAGE_COUNT 64
192 193 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
include/configs/omap3_logic.h
Diff comments   View file @ 5ed2894
... ... @@ -141,6 +141,7 @@
141 141  
142 142 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
143 143 /* NAND devices */
  144 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
144 145 #define CONFIG_JFFS2_NAND
145 146 /* nand device jffs2 lives on */
146 147 #define CONFIG_JFFS2_DEV "nand0"
include/configs/omap3_overo.h
Diff comments   View file @ 5ed2894
... ... @@ -206,6 +206,7 @@
206 206 #define CONFIG_SYS_CACHELINE_SIZE 64
207 207  
208 208 /* NAND boot config */
  209 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
209 210 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
210 211 #define CONFIG_SYS_NAND_PAGE_COUNT 64
211 212 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
include/configs/omap3_zoom1.h
Diff comments   View file @ 5ed2894
... ... @@ -98,6 +98,7 @@
98 98 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
99 99 /* to access nand at */
100 100 /* CS0 */
  101 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
101 102  
102 103 /* Environment information */
103 104  
include/configs/pengwyn.h
Diff comments   View file @ 5ed2894
... ... @@ -149,7 +149,6 @@
149 149 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
150 150 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
151 151  
152   -#define GPMC_NAND_ECC_LP_x8_LAYOUT 1
153 152 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
154 153 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
155 154 "128k(SPL.backup1)," \
include/configs/tam3517-common.h
Diff comments   View file @ 5ed2894
... ... @@ -185,6 +185,7 @@
185 185 /* Configure the PISMO */
186 186 #define PISMO1_NAND_SIZE GPMC_SIZE_128M
187 187  
  188 +#define CONFIG_NAND
188 189 #define CONFIG_NAND_OMAP_GPMC
189 190 #define CONFIG_ENV_IS_IN_NAND
190 191 #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */
... ... @@ -249,6 +250,7 @@
249 250 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
250 251  
251 252 /* NAND boot config */
  253 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
252 254 #define CONFIG_SYS_NAND_PAGE_COUNT 64
253 255 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
254 256 #define CONFIG_SYS_NAND_OOBSIZE 64
include/configs/tao3530.h
Diff comments   View file @ 5ed2894
... ... @@ -137,10 +137,10 @@
137 137 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
138 138 /* to access nand at */
139 139 /* CS0 */
140   -#define GPMC_NAND_ECC_LP_x16_LAYOUT
141 140  
142 141 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
143 142 /* devices */
  143 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
144 144 /* Environment information */
145 145 #define CONFIG_BOOTDELAY 3
146 146  
include/configs/ti_am335x_common.h
Diff comments   View file @ 5ed2894
... ... @@ -75,6 +75,15 @@
75 75 #define CONFIG_SKIP_LOWLEVEL_INIT
76 76 #endif
77 77  
  78 +/*
  79 + * When building U-Boot such that there is no previous loader
  80 + * we need to call board_early_init_f. This is taken care of in
  81 + * s_init when we have SPL used.
  82 + */
  83 +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && !defined(CONFIG_SPL)
  84 +#define CONFIG_BOARD_EARLY_INIT_F
  85 +#endif
  86 +
78 87 #ifdef CONFIG_NAND
79 88 #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */
80 89 #endif
include/configs/ti_armv7_common.h
Diff comments   View file @ 5ed2894
... ... @@ -196,7 +196,8 @@
196 196 * under common/spl/. Given our generally common memory map, we set a
197 197 * number of related defaults and sizes here.
198 198 */
199   -#ifndef CONFIG_NOR_BOOT
  199 +#if !defined(CONFIG_NOR_BOOT) && \
  200 + !(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX))
200 201 #define CONFIG_SPL
201 202 #define CONFIG_SPL_FRAMEWORK
202 203 #define CONFIG_SPL_OS_BOOT
include/configs/tseries.h
Diff comments   View file @ 5ed2894
... ... @@ -157,7 +157,6 @@
157 157 /* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
158 158 #define CONFIG_NAND_OMAP_ELM
159 159 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
160   -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
161 160 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
162 161 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
163 162 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
include/linux/mtd/nand.h
Diff comments   View file @ 5ed2894
... ... @@ -719,5 +719,24 @@
719 719 }
720 720 #endif
721 721  
  722 +/**
  723 + * Check if the opcode's address should be sent only on the lower 8 bits
  724 + * @command: opcode to check
  725 + */
  726 +static inline int nand_opcode_8bits(unsigned int command)
  727 +{
  728 + switch (command) {
  729 + case NAND_CMD_READID:
  730 + case NAND_CMD_PARAM:
  731 + case NAND_CMD_GET_FEATURES:
  732 + case NAND_CMD_SET_FEATURES:
  733 + return 1;
  734 + default:
  735 + break;
  736 + }
  737 + return 0;
  738 +}
  739 +
  740 +
722 741 #endif /* __LINUX_MTD_NAND_H */
include/linux/mtd/omap_elm.h
Diff comments   View file @ 5ed2894
... ... @@ -24,6 +24,9 @@
24 24 #define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100)
25 25 #define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F)
26 26  
  27 +#define ELM_MAX_CHANNELS 8
  28 +#define ELM_MAX_ERROR_COUNT 16
  29 +
27 30 #ifndef __ASSEMBLY__
28 31  
29 32 enum bch_level {
... ... @@ -43,7 +46,7 @@
43 46 struct location {
44 47 u32 location_status; /* 0x800 */
45 48 u8 res1[124]; /* 0x804 */
46   - u32 error_location_x[16]; /* 0x880.... */
  49 + u32 error_location_x[ELM_MAX_ERROR_COUNT]; /* 0x880, 0x980, .. */
47 50 u8 res2[64]; /* 0x8c0 */
48 51 };
49 52  
50 53  
51 54  
... ... @@ -63,12 +66,12 @@
63 66 u8 res2[92]; /* 0x024 */
64 67 u32 page_ctrl; /* 0x080 */
65 68 u8 res3[892]; /* 0x084 */
66   - struct syndrome syndrome_fragments[8]; /* 0x400 */
  69 + struct syndrome syndrome_fragments[ELM_MAX_CHANNELS]; /* 0x400,0x420 */
67 70 u8 res4[512]; /* 0x600 */
68   - struct location error_location[8]; /* 0x800 */
  71 + struct location error_location[ELM_MAX_CHANNELS]; /* 0x800,0x900 ... */
69 72 };
70 73  
71   -int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count,
  74 +int elm_check_error(u8 *syndrome, enum bch_level bch_type, u32 *error_count,
72 75 u32 *error_locations);
73 76 int elm_config(enum bch_level level);
74 77 void elm_reset(void);
include/linux/mtd/omap_gpmc.h
Diff comments   View file @ 5ed2894
... ... @@ -11,6 +11,7 @@
11 11  
12 12 #define GPMC_BUF_EMPTY 0
13 13 #define GPMC_BUF_FULL 1
  14 +#define GPMC_MAX_SECTORS 8
14 15  
15 16 enum omap_ecc {
16 17 /* 1-bit ECC calculation by Software, Error detection by Software */
... ... @@ -26,6 +27,8 @@
26 27 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
27 28 /* 8-bit ECC calculation by GPMC, Error detection by ELM */
28 29 OMAP_ECC_BCH8_CODE_HW,
  30 + /* 16-bit ECC calculation by GPMC, Error detection by ELM */
  31 + OMAP_ECC_BCH16_CODE_HW,
29 32 };
30 33  
31 34 struct gpmc_cs {
... ... @@ -46,6 +49,10 @@
46 49 u32 bch_result_x[4];
47 50 };
48 51  
  52 +struct bch_res_4_6 {
  53 + u32 bch_result_x[3];
  54 +};
  55 +
49 56 struct gpmc {
50 57 u8 res1[0x10];
51 58 u32 sysconfig; /* 0x10 */
... ... @@ -75,7 +82,9 @@
75 82 u8 res7[12]; /* 0x224 */
76 83 u32 testmomde_ctrl; /* 0x230 */
77 84 u8 res8[12]; /* 0x234 */
78   - struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */
  85 + struct bch_res_0_3 bch_result_0_3[GPMC_MAX_SECTORS]; /* 0x240,0x250, */
  86 + u8 res9[16 * 4]; /* 0x2C0 - 0x2FF */
  87 + struct bch_res_4_6 bch_result_4_6[GPMC_MAX_SECTORS]; /* 0x300,0x310, */
79 88 };
80 89  
81 90 /* Used for board specific gpmc initialization */
include/power/tps65218.h
Diff comments   View file @ 5ed2894
  1 +/*
  2 + * (C) Copyright 2014
  3 + * Texas Instruments, <www.ti.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef __POWER_TPS65218_H__
  9 +#define __POWER_TPS65218_H__
  10 +
  11 +/* I2C chip address */
  12 +#define TPS65218_CHIP_PM 0x24
  13 +
  14 +/* Registers */
  15 +enum {
  16 + TPS65218_CHIPID = 0x00,
  17 + TPS65218_INT1,
  18 + TPS65218_INT2,
  19 + TPS65218_INT_MASK1,
  20 + TPS65218_INT_MASK2,
  21 + TPS65218_STATUS,
  22 + TPS65218_CONTROL,
  23 + TPS65218_FLAG,
  24 + TPS65218_PASSWORD = 0x10,
  25 + TPS65218_ENABLE1,
  26 + TPS65218_ENABLE2,
  27 + TPS65218_CONFIG1,
  28 + TPS65218_CONFIG2,
  29 + TPS65218_CONFIG3,
  30 + TPS65218_DCDC1,
  31 + TPS65218_DCDC2,
  32 + TPS65218_DCDC3,
  33 + TPS65218_DCDC4,
  34 + TPS65218_SLEW,
  35 + TPS65218_LDO1,
  36 + TPS65218_SEQ1 = 0x20,
  37 + TPS65218_SEQ2,
  38 + TPS65218_SEQ3,
  39 + TPS65218_SEQ4,
  40 + TPS65218_SEQ5,
  41 + TPS65218_SEQ6,
  42 + TPS65218_SEQ7,
  43 + TPS65218_PMIC_NUM_OF_REGS,
  44 +};
  45 +
  46 +#define TPS65218_PROT_LEVEL_NONE 0x00
  47 +#define TPS65218_PROT_LEVEL_1 0x01
  48 +#define TPS65218_PROT_LEVEL_2 0x02
  49 +
  50 +#define TPS65218_PASSWORD_LOCK_FOR_WRITE 0x00
  51 +#define TPS65218_PASSWORD_UNLOCK 0x7D
  52 +
  53 +#define TPS65218_DCDC_GO 0x80
  54 +
  55 +#define TPS65218_MASK_ALL_BITS 0xFF
  56 +
  57 +#define TPS65218_DCDC_VOLT_SEL_1100MV 0x19
  58 +#define TPS65218_DCDC_VOLT_SEL_1330MV 0x30
  59 +
  60 +int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val,
  61 + uchar mask);
  62 +int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel);
  63 +#endif /* __POWER_TPS65218_H__ */