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Commit 60d804c2f3ddd0071348c6e65999e19b4d07d16a

Authored by Marek Vasut
1 parent 7056efcc32
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: socfpga: pl310: Map SDRAM to 0x0 

Configure the PL310 address filter to make sure DRAM is mapped to 0x0.
This code also configures the "remap" register of NIC-301 and sets the
required 'mpuzero' bit.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

Showing 1 changed file with 14 additions and 0 deletions Inline Diff

arch/arm/cpu/armv7/socfpga/misc.c
Diff comments   View file @ 60d804c
1 /* 1 /*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <asm/io.h> 8 #include <asm/io.h>
9 #include <altera.h> 9 #include <altera.h>
10 #include <miiphy.h> 10 #include <miiphy.h>
11 #include <netdev.h> 11 #include <netdev.h>
12 #include <asm/arch/reset_manager.h> 12 #include <asm/arch/reset_manager.h>
13 #include <asm/arch/system_manager.h> 13 #include <asm/arch/system_manager.h>
14 #include <asm/arch/dwmmc.h> 14 #include <asm/arch/dwmmc.h>
15 #include <asm/arch/nic301.h>
16 #include <asm/pl310.h>
15 17
16 DECLARE_GLOBAL_DATA_PTR; 18 DECLARE_GLOBAL_DATA_PTR;
17 19
20 static struct pl310_regs *const pl310 =
21 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
18 static struct socfpga_system_manager *sysmgr_regs = 22 static struct socfpga_system_manager *sysmgr_regs =
19 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 23 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
24 static struct nic301_registers *nic301_regs =
25 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
20 26
21 int dram_init(void) 27 int dram_init(void)
22 { 28 {
23 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 29 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
24 return 0; 30 return 0;
25 } 31 }
26 32
27 /* 33 /*
28 * DesignWare Ethernet initialization 34 * DesignWare Ethernet initialization
29 */ 35 */
30 #ifdef CONFIG_DESIGNWARE_ETH 36 #ifdef CONFIG_DESIGNWARE_ETH
31 int cpu_eth_init(bd_t *bis) 37 int cpu_eth_init(bd_t *bis)
32 { 38 {
33 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS 39 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
34 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; 40 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
35 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS 41 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
36 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; 42 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
37 #else 43 #else
38 #error "Incorrect CONFIG_EMAC_BASE value!" 44 #error "Incorrect CONFIG_EMAC_BASE value!"
39 #endif 45 #endif
40 46
41 /* Initialize EMAC. This needs to be done at least once per boot. */ 47 /* Initialize EMAC. This needs to be done at least once per boot. */
42 48
43 /* 49 /*
44 * Putting the EMAC controller to reset when configuring the PHY 50 * Putting the EMAC controller to reset when configuring the PHY
45 * interface select at System Manager 51 * interface select at System Manager
46 */ 52 */
47 socfpga_emac_reset(1); 53 socfpga_emac_reset(1);
48 54
49 /* Clearing emac0 PHY interface select to 0 */ 55 /* Clearing emac0 PHY interface select to 0 */
50 clrbits_le32(&sysmgr_regs->emacgrp_ctrl, 56 clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
51 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); 57 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
52 58
53 /* configure to PHY interface select choosed */ 59 /* configure to PHY interface select choosed */
54 setbits_le32(&sysmgr_regs->emacgrp_ctrl, 60 setbits_le32(&sysmgr_regs->emacgrp_ctrl,
55 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); 61 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
56 62
57 /* Release the EMAC controller from reset */ 63 /* Release the EMAC controller from reset */
58 socfpga_emac_reset(0); 64 socfpga_emac_reset(0);
59 65
60 /* initialize and register the emac */ 66 /* initialize and register the emac */
61 return designware_initialize(CONFIG_EMAC_BASE, 67 return designware_initialize(CONFIG_EMAC_BASE,
62 CONFIG_PHY_INTERFACE_MODE); 68 CONFIG_PHY_INTERFACE_MODE);
63 } 69 }
64 #endif 70 #endif
65 71
66 #ifdef CONFIG_DWMMC 72 #ifdef CONFIG_DWMMC
67 /* 73 /*
68 * Initializes MMC controllers. 74 * Initializes MMC controllers.
69 * to override, implement board_mmc_init() 75 * to override, implement board_mmc_init()
70 */ 76 */
71 int cpu_mmc_init(bd_t *bis) 77 int cpu_mmc_init(bd_t *bis)
72 { 78 {
73 return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS, 79 return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
74 CONFIG_HPS_SDMMC_BUSWIDTH, 0); 80 CONFIG_HPS_SDMMC_BUSWIDTH, 0);
75 } 81 }
76 #endif 82 #endif
77 83
78 #if defined(CONFIG_DISPLAY_CPUINFO) 84 #if defined(CONFIG_DISPLAY_CPUINFO)
79 /* 85 /*
80 * Print CPU information 86 * Print CPU information
81 */ 87 */
82 int print_cpuinfo(void) 88 int print_cpuinfo(void)
83 { 89 {
84 puts("CPU: Altera SoCFPGA Platform\n"); 90 puts("CPU: Altera SoCFPGA Platform\n");
85 return 0; 91 return 0;
86 } 92 }
87 #endif 93 #endif
88 94
89 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ 95 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
90 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) 96 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
91 int overwrite_console(void) 97 int overwrite_console(void)
92 { 98 {
93 return 0; 99 return 0;
94 } 100 }
95 #endif 101 #endif
96 102
97 #ifdef CONFIG_FPGA 103 #ifdef CONFIG_FPGA
98 /* 104 /*
99 * FPGA programming support for SoC FPGA Cyclone V 105 * FPGA programming support for SoC FPGA Cyclone V
100 */ 106 */
101 static Altera_desc altera_fpga[] = { 107 static Altera_desc altera_fpga[] = {
102 { 108 {
103 /* Family */ 109 /* Family */
104 Altera_SoCFPGA, 110 Altera_SoCFPGA,
105 /* Interface type */ 111 /* Interface type */
106 fast_passive_parallel, 112 fast_passive_parallel,
107 /* No limitation as additional data will be ignored */ 113 /* No limitation as additional data will be ignored */
108 -1, 114 -1,
109 /* No device function table */ 115 /* No device function table */
110 NULL, 116 NULL,
111 /* Base interface address specified in driver */ 117 /* Base interface address specified in driver */
112 NULL, 118 NULL,
113 /* No cookie implementation */ 119 /* No cookie implementation */
114 0 120 0
115 }, 121 },
116 }; 122 };
117 123
118 /* add device descriptor to FPGA device table */ 124 /* add device descriptor to FPGA device table */
119 static void socfpga_fpga_add(void) 125 static void socfpga_fpga_add(void)
120 { 126 {
121 int i; 127 int i;
122 fpga_init(); 128 fpga_init();
123 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) 129 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
124 fpga_add(fpga_altera, &altera_fpga[i]); 130 fpga_add(fpga_altera, &altera_fpga[i]);
125 } 131 }
126 #else 132 #else
127 static inline void socfpga_fpga_add(void) {} 133 static inline void socfpga_fpga_add(void) {}
128 #endif 134 #endif
129 135
130 int arch_cpu_init(void) 136 int arch_cpu_init(void)
131 { 137 {
132 /* 138 /*
133 * If the HW watchdog is NOT enabled, make sure it is not running, 139 * If the HW watchdog is NOT enabled, make sure it is not running,
134 * for example because it was enabled in the preloader. This might 140 * for example because it was enabled in the preloader. This might
135 * trigger a watchdog-triggered reboot of Linux kernel later. 141 * trigger a watchdog-triggered reboot of Linux kernel later.
136 */ 142 */
137 #ifndef CONFIG_HW_WATCHDOG 143 #ifndef CONFIG_HW_WATCHDOG
138 socfpga_watchdog_reset(); 144 socfpga_watchdog_reset();
139 #endif 145 #endif
140 return 0; 146 return 0;
141 } 147 }
142 148
143 int misc_init_r(void) 149 int misc_init_r(void)
144 { 150 {
151 /* Configure the L2 controller to make SDRAM start at 0 */
152 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
153 writel(0x2, &nic301_regs->remap);
154 #else
155 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
156 writel(0x1, &pl310->pl310_addr_filter_start);
157 #endif
158
145 /* Add device descriptor to FPGA device table */ 159 /* Add device descriptor to FPGA device table */
146 socfpga_fpga_add(); 160 socfpga_fpga_add();
147 return 0; 161 return 0;
148 } 162 }
149 163