Commit 632de0672d3c3ab53ad798c47f5f1eb26008a0e4
Committed by
Wolfgang Denk
1 parent
0df6b8446c
Exists in
master
and in
54 other branches
Refactor code for "i2c sdram" command
Signed-off-by: Larry Johnson <lrj@acm.org>
Showing 1 changed file with 220 additions and 291 deletions Side-by-side Diff
common/cmd_i2c.c
... | ... | @@ -655,29 +655,120 @@ |
655 | 655 | * (most?) embedded boards don't use SDRAM DIMMs. |
656 | 656 | */ |
657 | 657 | #if defined(CONFIG_CMD_SDRAM) |
658 | +static void print_ddr2_tcyc (u_char const b) | |
659 | +{ | |
660 | + printf ("%d.", (b >> 4) & 0x0F); | |
661 | + switch (b & 0x0F) { | |
662 | + case 0x0: | |
663 | + case 0x1: | |
664 | + case 0x2: | |
665 | + case 0x3: | |
666 | + case 0x4: | |
667 | + case 0x5: | |
668 | + case 0x6: | |
669 | + case 0x7: | |
670 | + case 0x8: | |
671 | + case 0x9: | |
672 | + printf ("%d ns\n", b & 0x0F); | |
673 | + break; | |
674 | + case 0xA: | |
675 | + puts ("25 ns\n"); | |
676 | + break; | |
677 | + case 0xB: | |
678 | + puts ("33 ns\n"); | |
679 | + break; | |
680 | + case 0xC: | |
681 | + puts ("66 ns\n"); | |
682 | + break; | |
683 | + case 0xD: | |
684 | + puts ("75 ns\n"); | |
685 | + break; | |
686 | + default: | |
687 | + puts ("?? ns\n"); | |
688 | + break; | |
689 | + } | |
690 | +} | |
658 | 691 | |
692 | +static void decode_bits (u_char const b, char const *str[], int const do_once) | |
693 | +{ | |
694 | + u_char mask; | |
695 | + | |
696 | + for (mask = 0x80; mask != 0x00; mask >>= 1, ++str) { | |
697 | + if (b & mask) { | |
698 | + puts (*str); | |
699 | + if (do_once) | |
700 | + return; | |
701 | + } | |
702 | + } | |
703 | +} | |
704 | + | |
659 | 705 | /* |
660 | 706 | * Syntax: |
661 | 707 | * sdram {i2c_chip} |
662 | 708 | */ |
663 | -int do_sdram ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) | |
709 | +int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) | |
664 | 710 | { |
665 | - enum {unknown, EDO, SDRAM, DDR2} type; | |
711 | + enum { unknown, EDO, SDRAM, DDR2 } type; | |
712 | + | |
666 | 713 | u_char chip; |
667 | 714 | u_char data[128]; |
668 | 715 | u_char cksum; |
669 | 716 | int j; |
670 | 717 | |
718 | + static const char *decode_CAS_DDR2[] = { | |
719 | + " TBD", " 6", " 5", " 4", " 3", " 2", " TBD", " TBD" | |
720 | + }; | |
721 | + | |
722 | + static const char *decode_CAS_default[] = { | |
723 | + " TBD", " 7", " 6", " 5", " 4", " 3", " 2", " 1" | |
724 | + }; | |
725 | + | |
726 | + static const char *decode_CS_WE_default[] = { | |
727 | + " TBD", " 6", " 5", " 4", " 3", " 2", " 1", " 0" | |
728 | + }; | |
729 | + | |
730 | + static const char *decode_byte21_default[] = { | |
731 | + " TBD (bit 7)\n", | |
732 | + " Redundant row address\n", | |
733 | + " Differential clock input\n", | |
734 | + " Registerd DQMB inputs\n", | |
735 | + " Buffered DQMB inputs\n", | |
736 | + " On-card PLL\n", | |
737 | + " Registered address/control lines\n", | |
738 | + " Buffered address/control lines\n" | |
739 | + }; | |
740 | + | |
741 | + static const char *decode_byte22_DDR2[] = { | |
742 | + " TBD (bit 7)\n", | |
743 | + " TBD (bit 6)\n", | |
744 | + " TBD (bit 5)\n", | |
745 | + " TBD (bit 4)\n", | |
746 | + " TBD (bit 3)\n", | |
747 | + " Supports partial array self refresh\n", | |
748 | + " Supports 50 ohm ODT\n", | |
749 | + " Supports weak driver\n" | |
750 | + }; | |
751 | + | |
752 | + static const char *decode_row_density_DDR2[] = { | |
753 | + "512 MiB", "256 MiB", "128 MiB", "16 GiB", | |
754 | + "8 GiB", "4 GiB", "2 GiB", "1 GiB" | |
755 | + }; | |
756 | + | |
757 | + static const char *decode_row_density_default[] = { | |
758 | + "512 MiB", "256 MiB", "128 MiB", "64 MiB", | |
759 | + "32 MiB", "16 MiB", "8 MiB", "4 MiB" | |
760 | + }; | |
761 | + | |
671 | 762 | if (argc < 2) { |
672 | 763 | printf ("Usage:\n%s\n", cmdtp->usage); |
673 | 764 | return 1; |
674 | 765 | } |
675 | 766 | /* |
676 | 767 | * Chip is always specified. |
677 | - */ | |
678 | - chip = simple_strtoul(argv[1], NULL, 16); | |
768 | + */ | |
769 | + chip = simple_strtoul (argv[1], NULL, 16); | |
679 | 770 | |
680 | - if (i2c_read(chip, 0, 1, data, sizeof(data)) != 0) { | |
771 | + if (i2c_read (chip, 0, 1, data, sizeof (data)) != 0) { | |
681 | 772 | puts ("No SDRAM Serial Presence Detect found.\n"); |
682 | 773 | return 1; |
683 | 774 | } |
684 | 775 | |
685 | 776 | |
686 | 777 | |
... | ... | @@ -688,15 +779,15 @@ |
688 | 779 | } |
689 | 780 | if (cksum != data[63]) { |
690 | 781 | printf ("WARNING: Configuration data checksum failure:\n" |
691 | - " is 0x%02x, calculated 0x%02x\n", | |
692 | - data[63], cksum); | |
782 | + " is 0x%02x, calculated 0x%02x\n", data[63], cksum); | |
693 | 783 | } |
694 | - printf("SPD data revision %d.%d\n", | |
784 | + printf ("SPD data revision %d.%d\n", | |
695 | 785 | (data[62] >> 4) & 0x0F, data[62] & 0x0F); |
696 | - printf("Bytes used 0x%02X\n", data[0]); | |
697 | - printf("Serial memory size 0x%02X\n", 1 << data[1]); | |
786 | + printf ("Bytes used 0x%02X\n", data[0]); | |
787 | + printf ("Serial memory size 0x%02X\n", 1 << data[1]); | |
788 | + | |
698 | 789 | puts ("Memory type "); |
699 | - switch(data[2]) { | |
790 | + switch (data[2]) { | |
700 | 791 | case 2: |
701 | 792 | type = EDO; |
702 | 793 | puts ("EDO\n"); |
703 | 794 | |
704 | 795 | |
705 | 796 | |
706 | 797 | |
707 | 798 | |
708 | 799 | |
709 | 800 | |
710 | 801 | |
... | ... | @@ -714,34 +805,36 @@ |
714 | 805 | puts ("unknown\n"); |
715 | 806 | break; |
716 | 807 | } |
808 | + | |
717 | 809 | puts ("Row address bits "); |
718 | 810 | if ((data[3] & 0x00F0) == 0) |
719 | - printf("%d\n", data[3] & 0x0F); | |
811 | + printf ("%d\n", data[3] & 0x0F); | |
720 | 812 | else |
721 | - printf("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F); | |
813 | + printf ("%d/%d\n", data[3] & 0x0F, (data[3] >> 4) & 0x0F); | |
814 | + | |
722 | 815 | puts ("Column address bits "); |
723 | 816 | if ((data[4] & 0x00F0) == 0) |
724 | - printf("%d\n", data[4] & 0x0F); | |
817 | + printf ("%d\n", data[4] & 0x0F); | |
725 | 818 | else |
726 | - printf("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F); | |
819 | + printf ("%d/%d\n", data[4] & 0x0F, (data[4] >> 4) & 0x0F); | |
727 | 820 | |
728 | 821 | switch (type) { |
729 | 822 | case DDR2: |
730 | - printf("Number of ranks %d\n", | |
731 | - (data[5] & 0x07) + 1); | |
823 | + printf ("Number of ranks %d\n", | |
824 | + (data[5] & 0x07) + 1); | |
732 | 825 | break; |
733 | 826 | default: |
734 | - printf("Module rows %d\n", data[5]); | |
827 | + printf ("Module rows %d\n", data[5]); | |
735 | 828 | break; |
736 | 829 | } |
737 | 830 | |
738 | 831 | switch (type) { |
739 | 832 | case DDR2: |
740 | - printf("Module data width %d bits\n", data[6]); | |
833 | + printf ("Module data width %d bits\n", data[6]); | |
741 | 834 | break; |
742 | 835 | default: |
743 | - printf("Module data width %d bits\n", | |
744 | - (data[7] << 8) | data[6]); | |
836 | + printf ("Module data width %d bits\n", | |
837 | + (data[7] << 8) | data[6]); | |
745 | 838 | break; |
746 | 839 | } |
747 | 840 | |
748 | 841 | |
749 | 842 | |
750 | 843 | |
751 | 844 | |
752 | 845 | |
753 | 846 | |
754 | 847 | |
755 | 848 | |
756 | 849 | |
757 | 850 | |
... | ... | @@ -758,85 +851,58 @@ |
758 | 851 | |
759 | 852 | switch (type) { |
760 | 853 | case DDR2: |
761 | - printf("SDRAM cycle time %d.", | |
762 | - (data[9] >> 4) & 0x0F); | |
763 | - switch (data[9] & 0x0F) { | |
764 | - case 0x0: | |
765 | - case 0x1: | |
766 | - case 0x2: | |
767 | - case 0x3: | |
768 | - case 0x4: | |
769 | - case 0x5: | |
770 | - case 0x6: | |
771 | - case 0x7: | |
772 | - case 0x8: | |
773 | - case 0x9: | |
774 | - printf("%d ns\n", data[9] & 0x0F); | |
775 | - break; | |
776 | - case 0xA: | |
777 | - puts("25 ns\n"); | |
778 | - break; | |
779 | - case 0xB: | |
780 | - puts("33 ns\n"); | |
781 | - break; | |
782 | - case 0xC: | |
783 | - puts("66 ns\n"); | |
784 | - break; | |
785 | - case 0xD: | |
786 | - puts("75 ns\n"); | |
787 | - break; | |
788 | - default: | |
789 | - puts("?? ns\n"); | |
790 | - break; | |
791 | - } | |
854 | + printf ("SDRAM cycle time "); | |
855 | + print_ddr2_tcyc (data[9]); | |
792 | 856 | break; |
793 | 857 | default: |
794 | - printf("SDRAM cycle time %d.%d nS\n", | |
795 | - (data[9] >> 4) & 0x0F, data[9] & 0x0F); | |
858 | + printf ("SDRAM cycle time %d.%d ns\n", | |
859 | + (data[9] >> 4) & 0x0F, data[9] & 0x0F); | |
796 | 860 | break; |
797 | 861 | } |
798 | 862 | |
799 | 863 | switch (type) { |
800 | 864 | case DDR2: |
801 | - printf("SDRAM access time 0.%d%d ns\n", | |
802 | - (data[10] >> 4) & 0x0F, data[10] & 0x0F); | |
865 | + printf ("SDRAM access time 0.%d%d ns\n", | |
866 | + (data[10] >> 4) & 0x0F, data[10] & 0x0F); | |
803 | 867 | break; |
804 | 868 | default: |
805 | - printf("SDRAM access time %d.%d nS\n", | |
806 | - (data[10] >> 4) & 0x0F, data[10] & 0x0F); | |
869 | + printf ("SDRAM access time %d.%d ns\n", | |
870 | + (data[10] >> 4) & 0x0F, data[10] & 0x0F); | |
807 | 871 | break; |
808 | 872 | } |
809 | 873 | |
810 | 874 | puts ("EDC configuration "); |
811 | - switch(data[11]) { | |
875 | + switch (data[11]) { | |
812 | 876 | case 0: puts ("None\n"); break; |
813 | 877 | case 1: puts ("Parity\n"); break; |
814 | 878 | case 2: puts ("ECC\n"); break; |
815 | 879 | default: puts ("unknown\n"); break; |
816 | 880 | } |
881 | + | |
817 | 882 | if ((data[12] & 0x80) == 0) |
818 | 883 | puts ("No self refresh, rate "); |
819 | 884 | else |
820 | 885 | puts ("Self refresh, rate "); |
886 | + | |
821 | 887 | switch(data[12] & 0x7F) { |
822 | - case 0: puts ("15.625 uS\n"); break; | |
823 | - case 1: puts ("3.9 uS\n"); break; | |
824 | - case 2: puts ("7.8 uS \n"); break; | |
825 | - case 3: puts ("31.3 uS\n"); break; | |
826 | - case 4: puts ("62.5 uS\n"); break; | |
827 | - case 5: puts ("125 uS\n"); break; | |
888 | + case 0: puts ("15.625 us\n"); break; | |
889 | + case 1: puts ("3.9 us\n"); break; | |
890 | + case 2: puts ("7.8 us\n"); break; | |
891 | + case 3: puts ("31.3 us\n"); break; | |
892 | + case 4: puts ("62.5 us\n"); break; | |
893 | + case 5: puts ("125 us\n"); break; | |
828 | 894 | default: puts ("unknown\n"); break; |
829 | 895 | } |
830 | 896 | |
831 | 897 | switch (type) { |
832 | 898 | case DDR2: |
833 | - printf("SDRAM width (primary) %d\n", data[13]); | |
899 | + printf ("SDRAM width (primary) %d\n", data[13]); | |
834 | 900 | break; |
835 | 901 | default: |
836 | - printf("SDRAM width (primary) %d\n", data[13] & 0x7F); | |
902 | + printf ("SDRAM width (primary) %d\n", data[13] & 0x7F); | |
837 | 903 | if ((data[13] & 0x80) != 0) { |
838 | - printf(" (second bank) %d\n", | |
839 | - 2 * (data[13] & 0x7F)); | |
904 | + printf (" (second bank) %d\n", | |
905 | + 2 * (data[13] & 0x7F)); | |
840 | 906 | } |
841 | 907 | break; |
842 | 908 | } |
843 | 909 | |
844 | 910 | |
845 | 911 | |
... | ... | @@ -844,24 +910,24 @@ |
844 | 910 | switch (type) { |
845 | 911 | case DDR2: |
846 | 912 | if (data[14] != 0) |
847 | - printf("EDC width %d\n", data[14]); | |
913 | + printf ("EDC width %d\n", data[14]); | |
848 | 914 | break; |
849 | 915 | default: |
850 | 916 | if (data[14] != 0) { |
851 | - printf("EDC width %d\n", | |
852 | - data[14] & 0x7F); | |
917 | + printf ("EDC width %d\n", | |
918 | + data[14] & 0x7F); | |
853 | 919 | |
854 | 920 | if ((data[14] & 0x80) != 0) { |
855 | - printf(" (second bank) %d\n", | |
856 | - 2 * (data[14] & 0x7F)); | |
921 | + printf (" (second bank) %d\n", | |
922 | + 2 * (data[14] & 0x7F)); | |
857 | 923 | } |
858 | 924 | } |
859 | 925 | break; |
860 | 926 | } |
861 | 927 | |
862 | - if (DDR2 != type ) { | |
863 | - printf("Min clock delay, back-to-back random column addresses " | |
864 | - "%d\n", data[15]); | |
928 | + if (DDR2 != type) { | |
929 | + printf ("Min clock delay, back-to-back random column addresses " | |
930 | + "%d\n", data[15]); | |
865 | 931 | } |
866 | 932 | |
867 | 933 | puts ("Burst length(s) "); |
868 | 934 | |
869 | 935 | |
870 | 936 | |
871 | 937 | |
... | ... | @@ -871,56 +937,30 @@ |
871 | 937 | if (data[16] & 0x02) puts (" 2"); |
872 | 938 | if (data[16] & 0x01) puts (" 1"); |
873 | 939 | putc ('\n'); |
874 | - printf("Number of banks %d\n", data[17]); | |
940 | + printf ("Number of banks %d\n", data[17]); | |
875 | 941 | |
876 | 942 | switch (type) { |
877 | 943 | case DDR2: |
878 | 944 | puts ("CAS latency(s) "); |
879 | - if (data[18] & 0x83) puts (" TBD"); | |
880 | - if (data[18] & 0x40) puts (" 6"); | |
881 | - if (data[18] & 0x20) puts (" 5"); | |
882 | - if (data[18] & 0x10) puts (" 4"); | |
883 | - if (data[18] & 0x08) puts (" 3"); | |
884 | - if (data[18] & 0x04) puts (" 2"); | |
945 | + decode_bits (data[18], decode_CAS_DDR2, 0); | |
885 | 946 | putc ('\n'); |
886 | 947 | break; |
887 | 948 | default: |
888 | 949 | puts ("CAS latency(s) "); |
889 | - if (data[18] & 0x80) puts (" TBD"); | |
890 | - if (data[18] & 0x40) puts (" 7"); | |
891 | - if (data[18] & 0x20) puts (" 6"); | |
892 | - if (data[18] & 0x10) puts (" 5"); | |
893 | - if (data[18] & 0x08) puts (" 4"); | |
894 | - if (data[18] & 0x04) puts (" 3"); | |
895 | - if (data[18] & 0x02) puts (" 2"); | |
896 | - if (data[18] & 0x01) puts (" 1"); | |
950 | + decode_bits (data[18], decode_CAS_default, 0); | |
897 | 951 | putc ('\n'); |
898 | 952 | break; |
899 | 953 | } |
900 | 954 | |
901 | 955 | if (DDR2 != type) { |
902 | 956 | puts ("CS latency(s) "); |
903 | - if (data[19] & 0x80) puts (" TBD"); | |
904 | - if (data[19] & 0x40) puts (" 6"); | |
905 | - if (data[19] & 0x20) puts (" 5"); | |
906 | - if (data[19] & 0x10) puts (" 4"); | |
907 | - if (data[19] & 0x08) puts (" 3"); | |
908 | - if (data[19] & 0x04) puts (" 2"); | |
909 | - if (data[19] & 0x02) puts (" 1"); | |
910 | - if (data[19] & 0x01) puts (" 0"); | |
957 | + decode_bits (data[19], decode_CS_WE_default, 0); | |
911 | 958 | putc ('\n'); |
912 | 959 | } |
913 | 960 | |
914 | 961 | if (DDR2 != type) { |
915 | 962 | puts ("WE latency(s) "); |
916 | - if (data[20] & 0x80) puts (" TBD"); | |
917 | - if (data[20] & 0x40) puts (" 6"); | |
918 | - if (data[20] & 0x20) puts (" 5"); | |
919 | - if (data[20] & 0x10) puts (" 4"); | |
920 | - if (data[20] & 0x08) puts (" 3"); | |
921 | - if (data[20] & 0x04) puts (" 2"); | |
922 | - if (data[20] & 0x02) puts (" 1"); | |
923 | - if (data[20] & 0x01) puts (" 0"); | |
963 | + decode_bits (data[20], decode_CS_WE_default, 0); | |
924 | 964 | putc ('\n'); |
925 | 965 | } |
926 | 966 | |
927 | 967 | |
928 | 968 | |
929 | 969 | |
... | ... | @@ -935,48 +975,24 @@ |
935 | 975 | puts (" TBD (bit 5)\n"); |
936 | 976 | if (data[21] & 0x10) |
937 | 977 | puts (" FET switch external enable\n"); |
938 | - printf(" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03); | |
978 | + printf (" %d PLLs on DIMM\n", (data[21] >> 2) & 0x03); | |
939 | 979 | if (data[20] & 0x11) { |
940 | - printf(" %d active registers on DIMM\n", | |
941 | - (data[21] & 0x03) + 1); | |
980 | + printf (" %d active registers on DIMM\n", | |
981 | + (data[21] & 0x03) + 1); | |
942 | 982 | } |
943 | 983 | break; |
944 | 984 | default: |
945 | 985 | puts ("Module attributes:\n"); |
946 | 986 | if (!data[21]) |
947 | 987 | puts (" (none)\n"); |
948 | - if (data[21] & 0x80) | |
949 | - puts (" TBD (bit 7)\n"); | |
950 | - if (data[21] & 0x40) | |
951 | - puts (" Redundant row address\n"); | |
952 | - if (data[21] & 0x20) | |
953 | - puts (" Differential clock input\n"); | |
954 | - if (data[21] & 0x10) | |
955 | - puts (" Registerd DQMB inputs\n"); | |
956 | - if (data[21] & 0x08) | |
957 | - puts (" Buffered DQMB inputs\n"); | |
958 | - if (data[21] & 0x04) | |
959 | - puts (" On-card PLL\n"); | |
960 | - if (data[21] & 0x02) | |
961 | - puts (" Registered address/control lines\n"); | |
962 | - if (data[21] & 0x01) | |
963 | - puts (" Buffered address/control lines\n"); | |
988 | + else | |
989 | + decode_bits (data[21], decode_byte21_default, 0); | |
964 | 990 | break; |
965 | 991 | } |
966 | 992 | |
967 | 993 | switch (type) { |
968 | 994 | case DDR2: |
969 | - if (data[22] & 0x80) puts (" TBD (bit 7)\n"); | |
970 | - if (data[22] & 0x40) puts (" TBD (bit 6)\n"); | |
971 | - if (data[22] & 0x20) puts (" TBD (bit 5)\n"); | |
972 | - if (data[22] & 0x10) puts (" TBD (bit 4)\n"); | |
973 | - if (data[22] & 0x08) puts (" TBD (bit 3)\n"); | |
974 | - if (data[22] & 0x04) | |
975 | - puts (" Supports parital array self refresh\n"); | |
976 | - if (data[22] & 0x02) | |
977 | - puts (" Supports 50 ohm ODT\n"); | |
978 | - if (data[22] & 0x01) | |
979 | - puts (" Supports weak driver\n"); | |
995 | + decode_bits (data[22], decode_byte22_DDR2, 0); | |
980 | 996 | break; |
981 | 997 | default: |
982 | 998 | puts ("Device attributes:\n"); |
983 | 999 | |
984 | 1000 | |
985 | 1001 | |
986 | 1002 | |
987 | 1003 | |
988 | 1004 | |
989 | 1005 | |
990 | 1006 | |
991 | 1007 | |
992 | 1008 | |
993 | 1009 | |
994 | 1010 | |
995 | 1011 | |
996 | 1012 | |
997 | 1013 | |
998 | 1014 | |
999 | 1015 | |
1000 | 1016 | |
1001 | 1017 | |
1002 | 1018 | |
1003 | 1019 | |
1004 | 1020 | |
1005 | 1021 | |
1006 | 1022 | |
1007 | 1023 | |
1008 | 1024 | |
1009 | 1025 | |
1010 | 1026 | |
1011 | 1027 | |
1012 | 1028 | |
1013 | 1029 | |
1014 | 1030 | |
1015 | 1031 | |
1016 | 1032 | |
... | ... | @@ -995,259 +1011,172 @@ |
995 | 1011 | |
996 | 1012 | switch (type) { |
997 | 1013 | case DDR2: |
998 | - printf("SDRAM cycle time (2nd highest CAS latency) %d.", | |
999 | - (data[23] >> 4) & 0x0F); | |
1000 | - | |
1001 | - switch (data[23] & 0x0F) { | |
1002 | - case 0x0: | |
1003 | - case 0x1: | |
1004 | - case 0x2: | |
1005 | - case 0x3: | |
1006 | - case 0x4: | |
1007 | - case 0x5: | |
1008 | - case 0x6: | |
1009 | - case 0x7: | |
1010 | - case 0x8: | |
1011 | - case 0x9: | |
1012 | - printf("%d ns\n", data[23] & 0x0F); | |
1013 | - break; | |
1014 | - case 0xA: | |
1015 | - puts("25 ns\n"); | |
1016 | - break; | |
1017 | - case 0xB: | |
1018 | - puts("33 ns\n"); | |
1019 | - break; | |
1020 | - case 0xC: | |
1021 | - puts("66 ns\n"); | |
1022 | - break; | |
1023 | - case 0xD: | |
1024 | - puts("75 ns\n"); | |
1025 | - break; | |
1026 | - default: | |
1027 | - puts("?? ns\n"); | |
1028 | - break; | |
1029 | - } | |
1014 | + printf ("SDRAM cycle time (2nd highest CAS latency) "); | |
1015 | + print_ddr2_tcyc (data[23]); | |
1030 | 1016 | break; |
1031 | 1017 | default: |
1032 | - printf("SDRAM cycle time (2nd highest CAS latency) %d." | |
1033 | - "%d nS\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F); | |
1018 | + printf ("SDRAM cycle time (2nd highest CAS latency) %d." | |
1019 | + "%d ns\n", (data[23] >> 4) & 0x0F, data[23] & 0x0F); | |
1034 | 1020 | break; |
1035 | 1021 | } |
1036 | 1022 | |
1037 | 1023 | switch (type) { |
1038 | 1024 | case DDR2: |
1039 | - printf("SDRAM access from clock (2nd highest CAS latency) 0." | |
1040 | - "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F); | |
1025 | + printf ("SDRAM access from clock (2nd highest CAS latency) 0." | |
1026 | + "%d%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F); | |
1041 | 1027 | break; |
1042 | 1028 | default: |
1043 | - printf("SDRAM access from clock (2nd highest CAS latency) %d." | |
1044 | - "%d nS\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F); | |
1029 | + printf ("SDRAM access from clock (2nd highest CAS latency) %d." | |
1030 | + "%d ns\n", (data[24] >> 4) & 0x0F, data[24] & 0x0F); | |
1045 | 1031 | break; |
1046 | 1032 | } |
1047 | 1033 | |
1048 | 1034 | switch (type) { |
1049 | 1035 | case DDR2: |
1050 | - printf("SDRAM cycle time (3rd highest CAS latency) %d.", | |
1051 | - (data[25] >> 4) & 0x0F); | |
1052 | - | |
1053 | - switch (data[25] & 0x0F) { | |
1054 | - case 0x0: | |
1055 | - case 0x1: | |
1056 | - case 0x2: | |
1057 | - case 0x3: | |
1058 | - case 0x4: | |
1059 | - case 0x5: | |
1060 | - case 0x6: | |
1061 | - case 0x7: | |
1062 | - case 0x8: | |
1063 | - case 0x9: | |
1064 | - printf("%d ns\n", data[25] & 0x0F); | |
1065 | - break; | |
1066 | - case 0xA: | |
1067 | - puts("25 ns\n"); | |
1068 | - break; | |
1069 | - case 0xB: | |
1070 | - puts("33 ns\n"); | |
1071 | - break; | |
1072 | - case 0xC: | |
1073 | - puts("66 ns\n"); | |
1074 | - break; | |
1075 | - case 0xD: | |
1076 | - puts("75 ns\n"); | |
1077 | - break; | |
1078 | - default: | |
1079 | - puts("?? ns\n"); | |
1080 | - break; | |
1081 | - } | |
1036 | + printf ("SDRAM cycle time (3rd highest CAS latency) "); | |
1037 | + print_ddr2_tcyc (data[25]); | |
1082 | 1038 | break; |
1083 | 1039 | default: |
1084 | - printf("SDRAM cycle time (3rd highest CAS latency) %d." | |
1085 | - "%d nS\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F); | |
1040 | + printf ("SDRAM cycle time (3rd highest CAS latency) %d." | |
1041 | + "%d ns\n", (data[25] >> 4) & 0x0F, data[25] & 0x0F); | |
1086 | 1042 | break; |
1087 | 1043 | } |
1088 | 1044 | |
1089 | 1045 | switch (type) { |
1090 | 1046 | case DDR2: |
1091 | - printf("SDRAM access from clock (3rd highest CAS latency) 0." | |
1092 | - "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F); | |
1047 | + printf ("SDRAM access from clock (3rd highest CAS latency) 0." | |
1048 | + "%d%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F); | |
1093 | 1049 | break; |
1094 | 1050 | default: |
1095 | - printf("SDRAM access from clock (3rd highest CAS latency) %d." | |
1096 | - "%d nS\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F); | |
1051 | + printf ("SDRAM access from clock (3rd highest CAS latency) %d." | |
1052 | + "%d ns\n", (data[26] >> 4) & 0x0F, data[26] & 0x0F); | |
1097 | 1053 | break; |
1098 | 1054 | } |
1099 | 1055 | |
1100 | 1056 | switch (type) { |
1101 | 1057 | case DDR2: |
1102 | - printf("Minimum row precharge %d", data[27] >> 2); | |
1103 | - switch (data[27] & 0x03) { | |
1104 | - case 0x0: puts(".00 ns\n"); break; | |
1105 | - case 0x1: puts(".25 ns\n"); break; | |
1106 | - case 0x2: puts(".50 ns\n"); break; | |
1107 | - case 0x3: puts(".75 ns\n"); break; | |
1108 | - } | |
1058 | + printf ("Minimum row precharge %d.%02d ns\n", | |
1059 | + (data[27] >> 2) & 0x3F, 25 * (data[27] & 0x03)); | |
1109 | 1060 | break; |
1110 | 1061 | default: |
1111 | - printf("Minimum row precharge %d nS\n", data[27]); | |
1062 | + printf ("Minimum row precharge %d ns\n", data[27]); | |
1112 | 1063 | break; |
1113 | 1064 | } |
1114 | 1065 | |
1115 | 1066 | switch (type) { |
1116 | 1067 | case DDR2: |
1117 | - printf("Row active to row active min %d", data[28] >> 2); | |
1118 | - switch (data[28] & 0x03) { | |
1119 | - case 0x0: puts(".00 ns\n"); break; | |
1120 | - case 0x1: puts(".25 ns\n"); break; | |
1121 | - case 0x2: puts(".50 ns\n"); break; | |
1122 | - case 0x3: puts(".75 ns\n"); break; | |
1123 | - } | |
1068 | + printf ("Row active to row active min %d.%02d ns\n", | |
1069 | + (data[28] >> 2) & 0x3F, 25 * (data[28] & 0x03)); | |
1124 | 1070 | break; |
1125 | 1071 | default: |
1126 | - printf("Row active to row active min %d nS\n", data[28]); | |
1072 | + printf ("Row active to row active min %d ns\n", data[28]); | |
1127 | 1073 | break; |
1128 | 1074 | } |
1129 | 1075 | |
1130 | 1076 | switch (type) { |
1131 | 1077 | case DDR2: |
1132 | - printf("RAS to CAS delay min %d", data[29] >> 2); | |
1133 | - switch (data[29] & 0x03) { | |
1134 | - case 0x0: puts(".00 ns\n"); break; | |
1135 | - case 0x1: puts(".25 ns\n"); break; | |
1136 | - case 0x2: puts(".50 ns\n"); break; | |
1137 | - case 0x3: puts(".75 ns\n"); break; | |
1138 | - } | |
1078 | + printf ("RAS to CAS delay min %d.%02d ns\n", | |
1079 | + (data[29] >> 2) & 0x3F, 25 * (data[29] & 0x03)); | |
1139 | 1080 | break; |
1140 | 1081 | default: |
1141 | - printf("RAS to CAS delay min %d nS\n", data[29]); | |
1082 | + printf ("RAS to CAS delay min %d ns\n", data[29]); | |
1142 | 1083 | break; |
1143 | 1084 | } |
1144 | 1085 | |
1145 | - printf("Minimum RAS pulse width %d nS\n", data[30]); | |
1086 | + printf ("Minimum RAS pulse width %d ns\n", data[30]); | |
1146 | 1087 | |
1147 | 1088 | switch (type) { |
1148 | 1089 | case DDR2: |
1149 | - puts ("Density of each row "); | |
1150 | - if (data[31] & 0x80) puts (" 512 MiB\n"); | |
1151 | - if (data[31] & 0x40) puts (" 256 MiB\n"); | |
1152 | - if (data[31] & 0x20) puts (" 128 MiB\n"); | |
1153 | - if (data[31] & 0x10) puts (" 16 GiB\n"); | |
1154 | - if (data[31] & 0x08) puts (" 8 GiB\n"); | |
1155 | - if (data[31] & 0x04) puts (" 4 GiB\n"); | |
1156 | - if (data[31] & 0x02) puts (" 2 GiB\n"); | |
1157 | - if (data[31] & 0x01) puts (" 1 GiB\n"); | |
1090 | + puts ("Density of each row "); | |
1091 | + decode_bits (data[31], decode_row_density_DDR2, 1); | |
1092 | + putc ('\n'); | |
1158 | 1093 | break; |
1159 | 1094 | default: |
1160 | - puts ("Density of each row "); | |
1161 | - if (data[31] & 0x80) puts (" 512 MiB\n"); | |
1162 | - if (data[31] & 0x40) puts (" 256 MiB\n"); | |
1163 | - if (data[31] & 0x20) puts (" 128 MiB\n"); | |
1164 | - if (data[31] & 0x10) puts (" 64 MiB\n"); | |
1165 | - if (data[31] & 0x08) puts (" 32 MiB\n"); | |
1166 | - if (data[31] & 0x04) puts (" 16 MiB\n"); | |
1167 | - if (data[31] & 0x02) puts (" 8 MiB\n"); | |
1168 | - if (data[31] & 0x01) puts (" 4 MiB\n"); | |
1095 | + puts ("Density of each row "); | |
1096 | + decode_bits (data[31], decode_row_density_default, 1); | |
1097 | + putc ('\n'); | |
1169 | 1098 | break; |
1170 | 1099 | } |
1171 | 1100 | |
1172 | 1101 | switch (type) { |
1173 | 1102 | case DDR2: |
1174 | - puts("Command and Address setup "); | |
1103 | + puts ("Command and Address setup "); | |
1175 | 1104 | if (data[32] >= 0xA0) { |
1176 | - printf("1.%d%d ns\n", | |
1177 | - ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F); | |
1105 | + printf ("1.%d%d ns\n", | |
1106 | + ((data[32] >> 4) & 0x0F) - 10, data[32] & 0x0F); | |
1178 | 1107 | } else { |
1179 | - printf("0.%d%d ns\n", | |
1180 | - ((data[32] >> 4) & 0x0F), data[32] & 0x0F); | |
1108 | + printf ("0.%d%d ns\n", | |
1109 | + ((data[32] >> 4) & 0x0F), data[32] & 0x0F); | |
1181 | 1110 | } |
1182 | 1111 | break; |
1183 | 1112 | default: |
1184 | - printf("Command and Address setup %c%d.%d nS\n", | |
1185 | - (data[32] & 0x80) ? '-' : '+', | |
1186 | - (data[32] >> 4) & 0x07, data[32] & 0x0F); | |
1113 | + printf ("Command and Address setup %c%d.%d ns\n", | |
1114 | + (data[32] & 0x80) ? '-' : '+', | |
1115 | + (data[32] >> 4) & 0x07, data[32] & 0x0F); | |
1187 | 1116 | break; |
1188 | 1117 | } |
1189 | 1118 | |
1190 | 1119 | switch (type) { |
1191 | 1120 | case DDR2: |
1192 | - puts("Command and Address hold "); | |
1121 | + puts ("Command and Address hold "); | |
1193 | 1122 | if (data[33] >= 0xA0) { |
1194 | - printf("1.%d%d ns\n", | |
1195 | - ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F); | |
1123 | + printf ("1.%d%d ns\n", | |
1124 | + ((data[33] >> 4) & 0x0F) - 10, data[33] & 0x0F); | |
1196 | 1125 | } else { |
1197 | - printf("0.%d%d ns\n", | |
1198 | - ((data[33] >> 4) & 0x0F), data[33] & 0x0F); | |
1126 | + printf ("0.%d%d ns\n", | |
1127 | + ((data[33] >> 4) & 0x0F), data[33] & 0x0F); | |
1199 | 1128 | } |
1200 | 1129 | break; |
1201 | 1130 | default: |
1202 | - printf("Command and Address hold %c%d.%d nS\n", | |
1203 | - (data[33] & 0x80) ? '-' : '+', | |
1204 | - (data[33] >> 4) & 0x07, data[33] & 0x0F); | |
1131 | + printf ("Command and Address hold %c%d.%d ns\n", | |
1132 | + (data[33] & 0x80) ? '-' : '+', | |
1133 | + (data[33] >> 4) & 0x07, data[33] & 0x0F); | |
1205 | 1134 | break; |
1206 | 1135 | } |
1207 | 1136 | |
1208 | 1137 | switch (type) { |
1209 | 1138 | case DDR2: |
1210 | - printf("Data signal input setup 0.%d%d ns\n", | |
1211 | - (data[34] >> 4) & 0x0F, data[34] & 0x0F); | |
1139 | + printf ("Data signal input setup 0.%d%d ns\n", | |
1140 | + (data[34] >> 4) & 0x0F, data[34] & 0x0F); | |
1212 | 1141 | break; |
1213 | 1142 | default: |
1214 | - printf("Data signal input setup %c%d.%d nS\n", | |
1215 | - (data[34] & 0x80) ? '-' : '+', | |
1216 | - (data[34] >> 4) & 0x07, data[34] & 0x0F); | |
1143 | + printf ("Data signal input setup %c%d.%d ns\n", | |
1144 | + (data[34] & 0x80) ? '-' : '+', | |
1145 | + (data[34] >> 4) & 0x07, data[34] & 0x0F); | |
1217 | 1146 | break; |
1218 | 1147 | } |
1219 | 1148 | |
1220 | 1149 | switch (type) { |
1221 | 1150 | case DDR2: |
1222 | - printf("Data signal input hold 0.%d%d ns\n", | |
1223 | - (data[35] >> 4) & 0x0F, data[35] & 0x0F); | |
1151 | + printf ("Data signal input hold 0.%d%d ns\n", | |
1152 | + (data[35] >> 4) & 0x0F, data[35] & 0x0F); | |
1224 | 1153 | break; |
1225 | 1154 | default: |
1226 | - printf("Data signal input hold %c%d.%d nS\n", | |
1227 | - (data[35] & 0x80) ? '-' : '+', | |
1228 | - (data[35] >> 4) & 0x07, data[35] & 0x0F); | |
1155 | + printf ("Data signal input hold %c%d.%d ns\n", | |
1156 | + (data[35] & 0x80) ? '-' : '+', | |
1157 | + (data[35] >> 4) & 0x07, data[35] & 0x0F); | |
1229 | 1158 | break; |
1230 | 1159 | } |
1231 | 1160 | |
1232 | 1161 | puts ("Manufacturer's JEDEC ID "); |
1233 | 1162 | for (j = 64; j <= 71; j++) |
1234 | - printf("%02X ", data[j]); | |
1163 | + printf ("%02X ", data[j]); | |
1235 | 1164 | putc ('\n'); |
1236 | - printf("Manufacturing Location %02X\n", data[72]); | |
1165 | + printf ("Manufacturing Location %02X\n", data[72]); | |
1237 | 1166 | puts ("Manufacturer's Part Number "); |
1238 | 1167 | for (j = 73; j <= 90; j++) |
1239 | - printf("%02X ", data[j]); | |
1168 | + printf ("%02X ", data[j]); | |
1240 | 1169 | putc ('\n'); |
1241 | - printf("Revision Code %02X %02X\n", data[91], data[92]); | |
1242 | - printf("Manufacturing Date %02X %02X\n", data[93], data[94]); | |
1170 | + printf ("Revision Code %02X %02X\n", data[91], data[92]); | |
1171 | + printf ("Manufacturing Date %02X %02X\n", data[93], data[94]); | |
1243 | 1172 | puts ("Assembly Serial Number "); |
1244 | 1173 | for (j = 95; j <= 98; j++) |
1245 | - printf("%02X ", data[j]); | |
1174 | + printf ("%02X ", data[j]); | |
1246 | 1175 | putc ('\n'); |
1247 | 1176 | |
1248 | 1177 | if (DDR2 != type) { |
1249 | - printf("Speed rating PC%d\n", | |
1250 | - data[126] == 0x66 ? 66 : data[126]); | |
1178 | + printf ("Speed rating PC%d\n", | |
1179 | + data[126] == 0x66 ? 66 : data[126]); | |
1251 | 1180 | } |
1252 | 1181 | return 0; |
1253 | 1182 | } |